Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2542

1

T1

1

T2

1

T3

1

auto[UartRx]

2542

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4511	1			T1	2		T2	2		T3	2
values[1]	47	1			T29	1		T391	1		T461	1
values[2]	50	1			T483	1		T163	1		T219	1
values[3]	39	1			T29	2		T455	1		T464	1
values[4]	58	1			T25	1		T29	1		T387	1
values[5]	50	1			T84	2		T29	2		T62	1
values[6]	39	1			T25	1		T84	1		T428	1
values[7]	58	1			T25	1		T84	1		T29	4
values[8]	68	1			T29	1		T455	2		T387	1
values[9]	61	1			T84	1		T448	1		T391	1
values[10]	71	1			T25	2		T84	1		T29	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2359	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	14	1			T29	1		T391	1		T465	1
auto[UartTx]	values[2]	16	1			T63	2		T484	1		T485	1
auto[UartTx]	values[3]	14	1			T163	1		T131	1		T472	1
auto[UartTx]	values[4]	16	1			T29	1		T483	1		T63	1
auto[UartTx]	values[5]	19	1			T62	1		T486	1		T472	1
auto[UartTx]	values[6]	12	1			T483	1		T486	1		T487	1
auto[UartTx]	values[7]	23	1			T25	1		T29	3		T455	1
auto[UartTx]	values[8]	22	1			T455	1		T465	1		T163	1
auto[UartTx]	values[9]	17	1			T455	1		T465	1		T486	1
auto[UartTx]	values[10]	22	1			T25	1		T455	1		T465	1
auto[UartRx]	values[0]	2152	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	33	1			T461	1		T483	1		T62	1
auto[UartRx]	values[2]	34	1			T483	1		T163	1		T219	1
auto[UartRx]	values[3]	25	1			T29	2		T455	1		T464	1
auto[UartRx]	values[4]	42	1			T25	1		T387	1		T62	1
auto[UartRx]	values[5]	31	1			T84	2		T29	2		T163	1
auto[UartRx]	values[6]	27	1			T25	1		T84	1		T428	1
auto[UartRx]	values[7]	35	1			T84	1		T29	1		T425	2
auto[UartRx]	values[8]	46	1			T29	1		T455	1		T387	1
auto[UartRx]	values[9]	44	1			T84	1		T448	1		T391	1
auto[UartRx]	values[10]	49	1			T25	1		T84	1		T29	1