Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1934	1			T11	2		T12	2		T13	9
auto[BaudRate115200]	2179	1			T11	4		T13	12		T14	3
auto[BaudRate230400]	1888	1			T11	2		T13	6		T14	2
auto[BaudRate128Kbps]	1945	1			T11	1		T13	3		T14	4
auto[BaudRate256Kbps]	2175	1			T11	1		T13	19		T14	3
auto[BaudRate1Mbps]	1806	1			T13	21		T14	3		T16	1
auto[BaudRate1p5Mbps]	1261	1			T11	1		T14	2		T15	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1256	1			T20	6		T441	2		T120	9
freqs[25]	1443	1			T11	11		T18	9		T21	2
freqs[48]	414	1			T115	10		T84	22		T359	5
freqs[50]	415	1			T14	21		T482	1		T40	9
freqs[100]	1077	1			T12	2		T25	37		T488	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	190	1			T20	2		T441	1		T120	2
auto[BaudRate9600]	freqs[25]	204	1			T11	2		T18	5		T113	2
auto[BaudRate9600]	freqs[48]	63	1			T115	4		T84	5		T489	2
auto[BaudRate9600]	freqs[50]	67	1			T14	4		T482	1		T40	1
auto[BaudRate9600]	freqs[100]	158	1			T12	2		T25	6		T488	4
auto[BaudRate115200]	freqs[24]	189	1			T20	4		T120	2		T216	1
auto[BaudRate115200]	freqs[25]	240	1			T11	4		T18	4		T21	1
auto[BaudRate115200]	freqs[48]	65	1			T115	1		T84	4		T489	3
auto[BaudRate115200]	freqs[50]	67	1			T14	3		T40	1		T490	2
auto[BaudRate115200]	freqs[100]	174	1			T25	5		T488	5		T134	1
auto[BaudRate230400]	freqs[24]	201	1			T120	1		T135	3		T118	2
auto[BaudRate230400]	freqs[25]	208	1			T11	2		T113	2		T121	2
auto[BaudRate230400]	freqs[48]	53	1			T115	1		T84	2		T359	1
auto[BaudRate230400]	freqs[50]	49	1			T14	2		T40	3		T119	1
auto[BaudRate230400]	freqs[100]	138	1			T25	6		T134	3		T427	1
auto[BaudRate128Kbps]	freqs[24]	173	1			T120	1		T135	3		T216	2
auto[BaudRate128Kbps]	freqs[25]	193	1			T11	1		T113	2		T442	1
auto[BaudRate128Kbps]	freqs[48]	61	1			T115	1		T84	5		T369	2
auto[BaudRate128Kbps]	freqs[50]	47	1			T14	4		T40	2		T119	1
auto[BaudRate128Kbps]	freqs[100]	144	1			T25	10		T134	1		T427	2
auto[BaudRate256Kbps]	freqs[24]	203	1			T120	2		T216	2		T118	2
auto[BaudRate256Kbps]	freqs[25]	252	1			T11	1		T113	1		T114	3
auto[BaudRate256Kbps]	freqs[48]	61	1			T115	1		T84	3		T359	3
auto[BaudRate256Kbps]	freqs[50]	69	1			T14	3		T40	2		T119	2
auto[BaudRate256Kbps]	freqs[100]	148	1			T25	7		T134	1		T427	5
auto[BaudRate1Mbps]	freqs[24]	194	1			T441	1		T135	3		T216	1
auto[BaudRate1Mbps]	freqs[25]	231	1			T113	2		T114	2		T26	3
auto[BaudRate1Mbps]	freqs[48]	54	1			T84	1		T489	3		T369	2
auto[BaudRate1Mbps]	freqs[50]	70	1			T14	3		T119	3		T355	3
auto[BaudRate1Mbps]	freqs[100]	158	1			T25	2		T134	3		T427	4
auto[BaudRate1p5Mbps]	freqs[25]	115	1			T11	1		T21	1		T114	5
auto[BaudRate1p5Mbps]	freqs[48]	57	1			T115	2		T84	2		T359	1
auto[BaudRate1p5Mbps]	freqs[50]	46	1			T14	2		T119	1		T366	1
auto[BaudRate1p5Mbps]	freqs[100]	157	1			T25	1		T134	2		T427	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded