Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2231 1 T2 3 T3 6 T5 3
all_levels[1] 481 1 T13 1 T24 7 T115 1
all_levels[2] 405 1 T13 1 T22 1 T25 1
all_levels[3] 369 1 T13 16 T14 4 T19 24
all_levels[4] 418 1 T11 1 T14 3 T113 1
all_levels[5] 580 1 T11 4 T13 1 T23 1
all_levels[6] 359 1 T14 137 T120 2 T135 1
all_levels[7] 442 1 T14 3 T114 1 T135 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%