Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	121024	1			T2	5		T3	8		T5	5
all_pins[1]	121024	1			T2	5		T3	8		T5	5
all_pins[2]	121024	1			T2	5		T3	8		T5	5
all_pins[3]	121024	1			T2	5		T3	8		T5	5
all_pins[4]	121024	1			T2	5		T3	8		T5	5
all_pins[5]	121024	1			T2	5		T3	8		T5	5
all_pins[6]	121024	1			T2	5		T3	8		T5	5
all_pins[7]	121024	1			T2	5		T3	8		T5	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	958608	1			T2	29		T3	54		T5	33
values[0x1]	9584	1			T2	11		T3	10		T5	7
transitions[0x0=>0x1]	8788	1			T2	8		T3	9		T5	4
transitions[0x1=>0x0]	8795	1			T2	8		T3	9		T5	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118582	1			T2	2		T3	8		T5	5
all_pins[0]	values[0x1]	2442	1			T2	3		T38	4		T96	2
all_pins[0]	transitions[0x0=>0x1]	2166	1			T38	4		T97	1		T111	2
all_pins[0]	transitions[0x1=>0x0]	2447	1			T3	4		T38	1		T96	1
all_pins[1]	values[0x0]	118301	1			T2	2		T3	4		T5	5
all_pins[1]	values[0x1]	2723	1			T2	3		T3	4		T38	1
all_pins[1]	transitions[0x0=>0x1]	2465	1			T2	3		T3	4		T38	1
all_pins[1]	transitions[0x1=>0x0]	2129	1			T3	1		T5	2		T111	2
all_pins[2]	values[0x0]	118637	1			T2	5		T3	7		T5	3
all_pins[2]	values[0x1]	2387	1			T3	1		T5	2		T111	2
all_pins[2]	transitions[0x0=>0x1]	2344	1			T3	1		T5	2		T111	2
all_pins[2]	transitions[0x1=>0x0]	166	1			T3	3		T5	2		T38	2
all_pins[3]	values[0x0]	120815	1			T2	5		T3	5		T5	3
all_pins[3]	values[0x1]	209	1			T3	3		T5	2		T38	2
all_pins[3]	transitions[0x0=>0x1]	169	1			T3	3		T5	1		T38	1
all_pins[3]	transitions[0x1=>0x0]	391	1			T2	1		T3	1		T38	3
all_pins[4]	values[0x0]	120593	1			T2	4		T3	7		T5	4
all_pins[4]	values[0x1]	431	1			T2	1		T3	1		T5	1
all_pins[4]	transitions[0x0=>0x1]	366	1			T2	1		T38	4		T96	2
all_pins[4]	transitions[0x1=>0x0]	153	1			T2	3		T49	2		T97	1
all_pins[5]	values[0x0]	120806	1			T2	2		T3	7		T5	4
all_pins[5]	values[0x1]	218	1			T2	3		T3	1		T5	1
all_pins[5]	transitions[0x0=>0x1]	182	1			T2	3		T3	1		T97	1
all_pins[5]	transitions[0x1=>0x0]	772	1			T2	1		T38	2		T97	2
all_pins[6]	values[0x0]	120216	1			T2	4		T3	8		T5	4
all_pins[6]	values[0x1]	808	1			T2	1		T5	1		T38	2
all_pins[6]	transitions[0x0=>0x1]	770	1			T2	1		T5	1		T38	2
all_pins[6]	transitions[0x1=>0x0]	328	1			T38	1		T96	2		T97	1
all_pins[7]	values[0x0]	120658	1			T2	5		T3	8		T5	5
all_pins[7]	values[0x1]	366	1			T38	1		T96	2		T97	1
all_pins[7]	transitions[0x0=>0x1]	326	1			T38	1		T96	1		T112	2
all_pins[7]	transitions[0x1=>0x0]	2409	1			T2	3		T38	4		T96	1