Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	634	1			T2	4		T3	7		T5	4
all_values[1]	634	1			T2	4		T3	7		T5	4
all_values[2]	634	1			T2	4		T3	7		T5	4
all_values[3]	634	1			T2	4		T3	7		T5	4
all_values[4]	634	1			T2	4		T3	7		T5	4
all_values[5]	634	1			T2	4		T3	7		T5	4
all_values[6]	634	1			T2	4		T3	7		T5	4
all_values[7]	634	1			T2	4		T3	7		T5	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2841

1

T2

20

T3

31

T5

20

auto[1]

2231

1

T2

12

T3

25

T5

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2037

1

T2

7

T3

20

T5

15

auto[1]

3035

1

T2

25

T3

36

T5

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3036

1

T2

16

T3

33

T5

20

auto[1]

2036

1

T2

16

T3

23

T5

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	146	1			T3	2		T5	1		T38	2
all_values[0]	auto[0]	auto[0]	auto[1]	55	1			T111	1		T417	1		T418	3
all_values[0]	auto[0]	auto[1]	auto[0]	131	1			T2	1		T3	2		T5	3
all_values[0]	auto[0]	auto[1]	auto[1]	53	1			T2	1		T38	1		T96	1
all_values[0]	auto[1]	auto[0]	auto[1]	142	1			T3	3		T38	1		T49	2
all_values[0]	auto[1]	auto[1]	auto[1]	107	1			T2	2		T38	3		T111	2
all_values[1]	auto[0]	auto[0]	auto[0]	133	1			T5	1		T38	1		T49	1
all_values[1]	auto[0]	auto[0]	auto[1]	65	1			T3	2		T5	1		T38	1
all_values[1]	auto[0]	auto[1]	auto[0]	96	1			T38	2		T419	1		T420	1
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T2	1		T3	2		T96	1
all_values[1]	auto[1]	auto[0]	auto[1]	156	1			T2	2		T3	1		T5	1
all_values[1]	auto[1]	auto[1]	auto[1]	105	1			T2	1		T3	2		T5	1
all_values[2]	auto[0]	auto[0]	auto[0]	150	1			T3	3		T5	1		T38	6
all_values[2]	auto[0]	auto[0]	auto[1]	67	1			T2	1		T96	1		T419	1
all_values[2]	auto[0]	auto[1]	auto[0]	106	1			T5	1		T49	1		T111	1
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T3	2		T5	1		T49	1
all_values[2]	auto[1]	auto[0]	auto[1]	140	1			T2	3		T3	2		T38	1
all_values[2]	auto[1]	auto[1]	auto[1]	110	1			T5	1		T111	3		T417	1
all_values[3]	auto[0]	auto[0]	auto[0]	143	1			T2	1		T5	1		T38	4
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T2	1		T3	1		T112	1
all_values[3]	auto[0]	auto[1]	auto[0]	100	1			T96	1		T419	1		T417	1
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T3	1		T112	2		T421	1
all_values[3]	auto[1]	auto[0]	auto[1]	143	1			T2	2		T3	3		T5	2
all_values[3]	auto[1]	auto[1]	auto[1]	117	1			T3	2		T5	1		T38	2
all_values[4]	auto[0]	auto[0]	auto[0]	159	1			T3	1		T5	1		T38	1
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T2	1		T3	1		T5	1
all_values[4]	auto[0]	auto[1]	auto[0]	85	1			T2	1		T96	1		T97	2
all_values[4]	auto[0]	auto[1]	auto[1]	71	1			T3	1		T38	2		T96	1
all_values[4]	auto[1]	auto[0]	auto[1]	140	1			T2	1		T3	2		T5	1
all_values[4]	auto[1]	auto[1]	auto[1]	113	1			T2	1		T3	2		T5	1
all_values[5]	auto[0]	auto[0]	auto[0]	150	1			T5	2		T38	3		T49	2
all_values[5]	auto[0]	auto[0]	auto[1]	59	1			T3	1		T38	1		T96	2
all_values[5]	auto[0]	auto[1]	auto[0]	107	1			T3	4		T97	1		T419	1
all_values[5]	auto[0]	auto[1]	auto[1]	59	1			T2	2		T49	1		T111	1
all_values[5]	auto[1]	auto[0]	auto[1]	138	1			T3	1		T5	1		T38	3
all_values[5]	auto[1]	auto[1]	auto[1]	121	1			T2	2		T3	1		T5	1
all_values[6]	auto[0]	auto[0]	auto[0]	148	1			T2	1		T3	1		T38	1
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T2	2		T5	1		T96	1
all_values[6]	auto[0]	auto[1]	auto[0]	135	1			T3	5		T38	2		T96	2
all_values[6]	auto[0]	auto[1]	auto[1]	54	1			T5	1		T38	1		T49	1
all_values[6]	auto[1]	auto[0]	auto[1]	126	1			T2	1		T3	1		T5	2
all_values[6]	auto[1]	auto[1]	auto[1]	108	1			T38	1		T49	1		T96	1
all_values[7]	auto[0]	auto[0]	auto[0]	151	1			T2	3		T3	1		T5	3
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T3	2		T38	1		T49	1
all_values[7]	auto[0]	auto[1]	auto[0]	97	1			T3	1		T5	1		T417	3
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T96	1		T112	1		T421	1
all_values[7]	auto[1]	auto[0]	auto[1]	176	1			T2	1		T3	3		T38	2
all_values[7]	auto[1]	auto[1]	auto[1]	94	1			T38	2		T112	1		T417	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal