Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.31 99.79 98.45 100.00 99.76 100.00 97.86


Total test records in report: 1299
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T1258 /workspace/coverage/cover_reg_top/15.uart_intr_test.1813961082 Dec 31 12:46:34 PM PST 23 Dec 31 12:46:38 PM PST 23 52015513 ps
T80 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3216875886 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:29 PM PST 23 16729027 ps
T1259 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1299958101 Dec 31 12:46:59 PM PST 23 Dec 31 12:47:02 PM PST 23 68613962 ps
T1260 /workspace/coverage/cover_reg_top/21.uart_intr_test.1786592993 Dec 31 12:46:45 PM PST 23 Dec 31 12:46:47 PM PST 23 19066799 ps
T1261 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2905910721 Dec 31 12:46:21 PM PST 23 Dec 31 12:46:24 PM PST 23 42106391 ps
T1262 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3075673885 Dec 31 12:46:35 PM PST 23 Dec 31 12:46:38 PM PST 23 11354848 ps
T1263 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1330827383 Dec 31 12:46:20 PM PST 23 Dec 31 12:46:23 PM PST 23 176235466 ps
T69 /workspace/coverage/cover_reg_top/3.uart_csr_rw.996070506 Dec 31 12:46:17 PM PST 23 Dec 31 12:46:18 PM PST 23 28519510 ps
T1264 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2426053861 Dec 31 12:46:49 PM PST 23 Dec 31 12:46:52 PM PST 23 37589506 ps
T1265 /workspace/coverage/cover_reg_top/30.uart_intr_test.590799710 Dec 31 12:46:36 PM PST 23 Dec 31 12:46:39 PM PST 23 80609178 ps
T1266 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3553184218 Dec 31 12:46:51 PM PST 23 Dec 31 12:46:53 PM PST 23 15746242 ps
T70 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2776204048 Dec 31 12:46:20 PM PST 23 Dec 31 12:46:23 PM PST 23 27531498 ps
T1267 /workspace/coverage/cover_reg_top/25.uart_intr_test.3097923584 Dec 31 12:46:44 PM PST 23 Dec 31 12:46:46 PM PST 23 12660431 ps
T1268 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3539784957 Dec 31 12:46:55 PM PST 23 Dec 31 12:46:56 PM PST 23 63381574 ps
T1269 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2692633070 Dec 31 12:46:46 PM PST 23 Dec 31 12:46:49 PM PST 23 17829706 ps
T1270 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3966689072 Dec 31 12:46:42 PM PST 23 Dec 31 12:46:45 PM PST 23 11613370 ps
T1271 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2638806849 Dec 31 12:46:29 PM PST 23 Dec 31 12:46:32 PM PST 23 15192900 ps
T1272 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3886766105 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:34 PM PST 23 46688015 ps
T1273 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1072248047 Dec 31 12:47:04 PM PST 23 Dec 31 12:47:09 PM PST 23 65994296 ps
T1274 /workspace/coverage/cover_reg_top/10.uart_intr_test.3912391492 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:37 PM PST 23 11997268 ps
T1275 /workspace/coverage/cover_reg_top/5.uart_intr_test.2251944509 Dec 31 12:46:31 PM PST 23 Dec 31 12:46:36 PM PST 23 52606722 ps
T1276 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.499105060 Dec 31 12:46:28 PM PST 23 Dec 31 12:46:40 PM PST 23 114688388 ps
T416 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.736896003 Dec 31 12:47:03 PM PST 23 Dec 31 12:47:09 PM PST 23 176874189 ps
T1277 /workspace/coverage/cover_reg_top/37.uart_intr_test.2534066273 Dec 31 12:47:12 PM PST 23 Dec 31 12:47:15 PM PST 23 12137747 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_intr_test.784716018 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:34 PM PST 23 17288684 ps
T1279 /workspace/coverage/cover_reg_top/49.uart_intr_test.2197572018 Dec 31 12:46:58 PM PST 23 Dec 31 12:46:59 PM PST 23 15248000 ps
T71 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2279544497 Dec 31 12:46:32 PM PST 23 Dec 31 12:46:37 PM PST 23 18995282 ps
T1280 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2716440135 Dec 31 12:46:41 PM PST 23 Dec 31 12:46:45 PM PST 23 416049413 ps
T1281 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.586275123 Dec 31 12:46:59 PM PST 23 Dec 31 12:47:01 PM PST 23 104972323 ps
T1282 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1511089251 Dec 31 12:46:31 PM PST 23 Dec 31 12:46:37 PM PST 23 54534426 ps
T1283 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3385810319 Dec 31 12:46:38 PM PST 23 Dec 31 12:46:41 PM PST 23 52297840 ps
T1284 /workspace/coverage/cover_reg_top/5.uart_tl_errors.929488249 Dec 31 12:46:41 PM PST 23 Dec 31 12:46:45 PM PST 23 32336842 ps
T1285 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2921195025 Dec 31 12:46:21 PM PST 23 Dec 31 12:46:25 PM PST 23 69379443 ps
T414 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.951409994 Dec 31 12:46:28 PM PST 23 Dec 31 12:46:32 PM PST 23 654901796 ps
T1286 /workspace/coverage/cover_reg_top/48.uart_intr_test.1419020819 Dec 31 12:46:56 PM PST 23 Dec 31 12:46:57 PM PST 23 11059620 ps
T1287 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.904283425 Dec 31 12:46:37 PM PST 23 Dec 31 12:46:40 PM PST 23 13683628 ps
T72 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3333392526 Dec 31 12:46:15 PM PST 23 Dec 31 12:46:16 PM PST 23 14050637 ps
T1288 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1742344916 Dec 31 12:46:45 PM PST 23 Dec 31 12:46:48 PM PST 23 110517265 ps
T1289 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3158061686 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:29 PM PST 23 379153532 ps
T1290 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3849313076 Dec 31 12:46:18 PM PST 23 Dec 31 12:46:20 PM PST 23 15487646 ps
T1291 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.306849172 Dec 31 12:46:23 PM PST 23 Dec 31 12:46:27 PM PST 23 3124133203 ps
T1292 /workspace/coverage/cover_reg_top/14.uart_tl_errors.4214647192 Dec 31 12:46:58 PM PST 23 Dec 31 12:47:01 PM PST 23 269382859 ps
T1293 /workspace/coverage/cover_reg_top/9.uart_intr_test.3321036450 Dec 31 12:46:52 PM PST 23 Dec 31 12:46:54 PM PST 23 23524316 ps
T1294 /workspace/coverage/cover_reg_top/41.uart_intr_test.3253088668 Dec 31 12:46:45 PM PST 23 Dec 31 12:46:48 PM PST 23 48693891 ps
T1295 /workspace/coverage/cover_reg_top/33.uart_intr_test.2479505315 Dec 31 12:46:53 PM PST 23 Dec 31 12:46:55 PM PST 23 43495824 ps
T1296 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1777915079 Dec 31 12:47:21 PM PST 23 Dec 31 12:47:23 PM PST 23 110519155 ps
T1297 /workspace/coverage/cover_reg_top/11.uart_intr_test.1110908481 Dec 31 12:46:49 PM PST 23 Dec 31 12:46:53 PM PST 23 21565625 ps
T1298 /workspace/coverage/cover_reg_top/20.uart_intr_test.3887290216 Dec 31 12:46:35 PM PST 23 Dec 31 12:46:39 PM PST 23 28539250 ps
T1299 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.13137514 Dec 31 12:46:30 PM PST 23 Dec 31 12:46:33 PM PST 23 100061315 ps

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2823868135
Short name T1
Test name
Test status
Simulation time 222620947 ps
CPU time 1.37 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:44 PM PST 23
Peak memory 197408 kb
Host smart-1a689e5a-c8bb-4e3a-8743-e5f27c84f647
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823868135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2823868135
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/default/33.uart_stress_all.1486764154
Short name T13
Test name
Test status
Simulation time 894949332178 ps
CPU time 787.35 seconds
Started Dec 31 01:13:46 PM PST 23
Finished Dec 31 01:26:55 PM PST 23
Peak memory 216692 kb
Host smart-9198683f-0226-4fff-987e-91fb149f7141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486764154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1486764154
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3136419906
Short name T114
Test name
Test status
Simulation time 129979259952 ps
CPU time 311.64 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:20:20 PM PST 23
Peak memory 200148 kb
Host smart-73c880d4-d215-44bb-b5a2-3ff8e9e75830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136419906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3136419906
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1748948002
Short name T34
Test name
Test status
Simulation time 78529189 ps
CPU time 1.21 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 199992 kb
Host smart-f6b3d957-18be-47f1-917d-00cba2df0135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748948002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1748948002
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1970799733
Short name T29
Test name
Test status
Simulation time 107879136390 ps
CPU time 920.5 seconds
Started Dec 31 01:15:14 PM PST 23
Finished Dec 31 01:30:35 PM PST 23
Peak memory 224860 kb
Host smart-03dcbf41-1d1b-4fab-bb42-8be60f9d92d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970799733 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1970799733
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2953109085
Short name T38
Test name
Test status
Simulation time 27547079 ps
CPU time 0.65 seconds
Started Dec 31 12:46:59 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 194328 kb
Host smart-abd3ffdb-8469-4c98-a855-a63d426966de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953109085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2953109085
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/default/7.uart_stress_all.2750186898
Short name T14
Test name
Test status
Simulation time 988992688054 ps
CPU time 930.42 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:28:02 PM PST 23
Peak memory 200232 kb
Host smart-416801e1-c33d-470b-b77e-244a01993042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750186898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2750186898
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all.626544541
Short name T123
Test name
Test status
Simulation time 1561995809446 ps
CPU time 2231.82 seconds
Started Dec 31 01:13:35 PM PST 23
Finished Dec 31 01:50:54 PM PST 23
Peak memory 210348 kb
Host smart-43f266c2-7efd-4aa5-8e67-c3d738386a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626544541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.626544541
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3653970600
Short name T429
Test name
Test status
Simulation time 63891461642 ps
CPU time 103.3 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:14:07 PM PST 23
Peak memory 200184 kb
Host smart-e843fb73-fce9-4389-a9d7-12dc6d47a844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653970600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3653970600
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_stress_all.3836550264
Short name T344
Test name
Test status
Simulation time 1607239842847 ps
CPU time 904.89 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:30:09 PM PST 23
Peak memory 200124 kb
Host smart-3f613254-cd5e-4207-9d91-26220b83f2f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836550264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3836550264
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.742880193
Short name T425
Test name
Test status
Simulation time 194942208624 ps
CPU time 535.92 seconds
Started Dec 31 01:12:34 PM PST 23
Finished Dec 31 01:21:33 PM PST 23
Peak memory 216660 kb
Host smart-d5951346-0006-43f8-b837-91b1b815ed31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742880193 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.742880193
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3675408376
Short name T31
Test name
Test status
Simulation time 170846705 ps
CPU time 0.96 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 198840 kb
Host smart-5a43ef03-8014-450a-ae14-99fdd2680440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675408376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3675408376
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2989481154
Short name T36
Test name
Test status
Simulation time 17107096 ps
CPU time 0.61 seconds
Started Dec 31 12:46:48 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 195400 kb
Host smart-b39f4e09-512f-4141-8498-7a0ff88dfc47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989481154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2989481154
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3491832279
Short name T130
Test name
Test status
Simulation time 82340458676 ps
CPU time 31.67 seconds
Started Dec 31 01:15:54 PM PST 23
Finished Dec 31 01:16:27 PM PST 23
Peak memory 199104 kb
Host smart-2221b18a-bc6c-407e-b5e9-d228438a50eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491832279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3491832279
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.2901699155
Short name T250
Test name
Test status
Simulation time 485640367763 ps
CPU time 568.56 seconds
Started Dec 31 01:13:36 PM PST 23
Finished Dec 31 01:23:11 PM PST 23
Peak memory 200188 kb
Host smart-3ac7b0c5-cd69-44cc-aa0f-b5afa7c9c545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901699155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2901699155
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_intr.4009016729
Short name T124
Test name
Test status
Simulation time 1082365751795 ps
CPU time 1356.29 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:36:10 PM PST 23
Peak memory 199936 kb
Host smart-99334a32-3cbe-4434-a4ce-191fd3402dc5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009016729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4009016729
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.589300345
Short name T340
Test name
Test status
Simulation time 237473621819 ps
CPU time 1136.83 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:34:28 PM PST 23
Peak memory 225068 kb
Host smart-9265e60b-2ebd-4113-9f48-e3ffd139314e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589300345 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.589300345
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.3567486765
Short name T27
Test name
Test status
Simulation time 175412548034 ps
CPU time 239.32 seconds
Started Dec 31 01:13:01 PM PST 23
Finished Dec 31 01:17:14 PM PST 23
Peak memory 200192 kb
Host smart-89045e95-60bf-4a30-90d6-15bceb78d381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567486765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3567486765
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3235784667
Short name T87
Test name
Test status
Simulation time 205968423 ps
CPU time 0.84 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 217768 kb
Host smart-bee11fcd-886a-440e-9f73-013de8f61b2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235784667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3235784667
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1122889567
Short name T112
Test name
Test status
Simulation time 19428762 ps
CPU time 0.56 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 185128 kb
Host smart-0fdfe20a-60f8-481b-8155-dc12705d3fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122889567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1122889567
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.4146508769
Short name T312
Test name
Test status
Simulation time 439152669709 ps
CPU time 1117.95 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:31:14 PM PST 23
Peak memory 224812 kb
Host smart-3f9db37e-4053-41ba-a717-a2d7ce8d70bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146508769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.4146508769
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2210569531
Short name T119
Test name
Test status
Simulation time 101730426066 ps
CPU time 92.44 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:17:19 PM PST 23
Peak memory 200224 kb
Host smart-cfb37294-191c-43b5-a082-01c97e2d216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210569531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2210569531
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.4082907512
Short name T143
Test name
Test status
Simulation time 565237009539 ps
CPU time 356.43 seconds
Started Dec 31 01:15:07 PM PST 23
Finished Dec 31 01:21:08 PM PST 23
Peak memory 200260 kb
Host smart-6a146c9f-eabe-4aef-9781-6a511a14ae0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082907512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.4082907512
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.520671128
Short name T91
Test name
Test status
Simulation time 67978207 ps
CPU time 1.19 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 199076 kb
Host smart-aab19b60-412c-48b9-8556-5581c819e845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520671128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.520671128
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/16.uart_alert_test.3718414218
Short name T93
Test name
Test status
Simulation time 11964337 ps
CPU time 0.55 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:23 PM PST 23
Peak memory 195652 kb
Host smart-67c14f20-8289-42c2-81a1-9cc43d24fe03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718414218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3718414218
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3194105650
Short name T131
Test name
Test status
Simulation time 487168823313 ps
CPU time 1315.57 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:37:23 PM PST 23
Peak memory 230616 kb
Host smart-de72cd36-e10a-46b6-8839-f72f714e3bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194105650 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3194105650
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.4037071358
Short name T84
Test name
Test status
Simulation time 63616759659 ps
CPU time 315.76 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:18:43 PM PST 23
Peak memory 214780 kb
Host smart-0f8f1c33-87cb-4de6-b3f3-386bc3475ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037071358 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.4037071358
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1768701685
Short name T4
Test name
Test status
Simulation time 18122096 ps
CPU time 0.68 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 197020 kb
Host smart-872944d1-6c21-42dc-a179-890863001662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768701685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1768701685
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1321793297
Short name T256
Test name
Test status
Simulation time 68043181776 ps
CPU time 117.6 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:15:23 PM PST 23
Peak memory 200176 kb
Host smart-72d71897-4f6a-4ac0-8c20-ab97bf158277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321793297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1321793297
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.2899211983
Short name T202
Test name
Test status
Simulation time 274249074113 ps
CPU time 234.5 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:17:25 PM PST 23
Peak memory 200216 kb
Host smart-a210b0a3-c9a7-4fb8-bef1-e1bf03a5ee98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899211983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2899211983
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1588009266
Short name T120
Test name
Test status
Simulation time 164305187462 ps
CPU time 74.56 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:16:41 PM PST 23
Peak memory 199856 kb
Host smart-a95754ab-24e0-4fb8-906a-561d3467b186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588009266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1588009266
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2649992576
Short name T257
Test name
Test status
Simulation time 167329475096 ps
CPU time 18.19 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 199500 kb
Host smart-5d96cb5d-111d-4b00-a5dd-15e0177e0def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649992576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2649992576
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1645576235
Short name T128
Test name
Test status
Simulation time 163872524157 ps
CPU time 74.32 seconds
Started Dec 31 01:15:54 PM PST 23
Finished Dec 31 01:17:10 PM PST 23
Peak memory 200176 kb
Host smart-cc6425cb-ad41-4ccc-9c6e-5041535da00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645576235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1645576235
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.2724736966
Short name T396
Test name
Test status
Simulation time 703573839375 ps
CPU time 296.24 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:17:20 PM PST 23
Peak memory 200156 kb
Host smart-3c9d9538-e84c-4efc-935f-35ac7a7acd9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724736966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2724736966
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2710759104
Short name T383
Test name
Test status
Simulation time 195189084040 ps
CPU time 85.6 seconds
Started Dec 31 01:13:48 PM PST 23
Finished Dec 31 01:15:15 PM PST 23
Peak memory 200220 kb
Host smart-5a531ad2-05a1-44e2-a759-c30520532a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710759104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2710759104
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2012906650
Short name T368
Test name
Test status
Simulation time 315136391508 ps
CPU time 1375.95 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:38:34 PM PST 23
Peak memory 225420 kb
Host smart-8dfcc75c-0cb5-4562-acea-bc9703bdbbbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012906650 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2012906650
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1784216437
Short name T163
Test name
Test status
Simulation time 79664177087 ps
CPU time 466.67 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:22:51 PM PST 23
Peak memory 216692 kb
Host smart-80cc5dd4-042a-4062-83bb-5d9da78ca0cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784216437 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1784216437
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2711667699
Short name T421
Test name
Test status
Simulation time 13510718 ps
CPU time 0.56 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 194352 kb
Host smart-1ac01aa5-c182-41bf-9ea0-3b5592683fed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711667699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2711667699
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1450610044
Short name T242
Test name
Test status
Simulation time 90506481313 ps
CPU time 71.08 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:16:49 PM PST 23
Peak memory 200136 kb
Host smart-c9bd6220-dad9-4822-9eec-8d32b460d154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450610044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1450610044
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.856966286
Short name T261
Test name
Test status
Simulation time 135759978627 ps
CPU time 53.64 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:16:32 PM PST 23
Peak memory 200208 kb
Host smart-f2022207-44ac-4907-9bc8-83de537e1a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856966286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.856966286
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1125168004
Short name T514
Test name
Test status
Simulation time 32464368 ps
CPU time 1.54 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:46:51 PM PST 23
Peak memory 199976 kb
Host smart-269f0686-5f2f-40a3-bd3d-8232bc110892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125168004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1125168004
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.586275123
Short name T1281
Test name
Test status
Simulation time 104972323 ps
CPU time 0.9 seconds
Started Dec 31 12:46:59 PM PST 23
Finished Dec 31 12:47:01 PM PST 23
Peak memory 198628 kb
Host smart-e0a33055-c98c-45eb-ba42-0f204c0b96e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586275123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.586275123
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3446794144
Short name T231
Test name
Test status
Simulation time 109040650484 ps
CPU time 43.31 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:16:13 PM PST 23
Peak memory 200116 kb
Host smart-efd09736-8cea-4ac7-930a-00797ca751f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446794144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3446794144
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3061996448
Short name T175
Test name
Test status
Simulation time 145898252361 ps
CPU time 200.99 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:18:57 PM PST 23
Peak memory 200236 kb
Host smart-9a326e0a-ae88-4118-a14d-3f8df0ec6b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061996448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3061996448
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.40308831
Short name T199
Test name
Test status
Simulation time 59951198856 ps
CPU time 29.96 seconds
Started Dec 31 01:15:38 PM PST 23
Finished Dec 31 01:16:09 PM PST 23
Peak memory 200048 kb
Host smart-e8b440be-6df9-4498-aa9f-ab542eea5d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40308831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.40308831
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_stress_all.1742694956
Short name T342
Test name
Test status
Simulation time 519338802564 ps
CPU time 258.72 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:19:49 PM PST 23
Peak memory 200152 kb
Host smart-ae747334-d95e-4bf6-86b5-cd027e97da68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742694956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1742694956
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.4283459295
Short name T287
Test name
Test status
Simulation time 46698719371 ps
CPU time 110.87 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:17:41 PM PST 23
Peak memory 200196 kb
Host smart-a1b4fc69-2600-4bdb-8a3c-efe683e20f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283459295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.4283459295
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2764461487
Short name T149
Test name
Test status
Simulation time 105917175755 ps
CPU time 111.53 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:17:29 PM PST 23
Peak memory 200144 kb
Host smart-7d581ea1-477a-42c8-ad21-7a2af7d012b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764461487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2764461487
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1802505785
Short name T174
Test name
Test status
Simulation time 42318584198 ps
CPU time 18.08 seconds
Started Dec 31 01:15:34 PM PST 23
Finished Dec 31 01:15:53 PM PST 23
Peak memory 200200 kb
Host smart-90d62d67-2d8a-4dd0-ae6d-4223fba2529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802505785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1802505785
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.4037903110
Short name T247
Test name
Test status
Simulation time 53629354353 ps
CPU time 73.3 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:17:01 PM PST 23
Peak memory 200056 kb
Host smart-be6eceec-aebd-4707-92da-0eb58868370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037903110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.4037903110
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1994108825
Short name T696
Test name
Test status
Simulation time 516020281926 ps
CPU time 1815.28 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:43:48 PM PST 23
Peak memory 230084 kb
Host smart-bf9c9510-0f8e-4156-9a79-3ebc82fc7c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994108825 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1994108825
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.284827218
Short name T371
Test name
Test status
Simulation time 360985025739 ps
CPU time 915.51 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:30:14 PM PST 23
Peak memory 231080 kb
Host smart-a6b25961-b153-4c81-9d52-3e14e30f2afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284827218 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.284827218
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.489084959
Short name T407
Test name
Test status
Simulation time 31330460145 ps
CPU time 38.27 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:16:09 PM PST 23
Peak memory 200184 kb
Host smart-42bd2670-72c2-40ca-83ef-46c95167a5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489084959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.489084959
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1758405551
Short name T439
Test name
Test status
Simulation time 17902816057 ps
CPU time 27.95 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 200072 kb
Host smart-c9545570-72f2-4d8c-b633-fe6c5825db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758405551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1758405551
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2630315506
Short name T251
Test name
Test status
Simulation time 55498898270 ps
CPU time 46.77 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 200268 kb
Host smart-f8074809-77f5-412a-90cd-7cf413303bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630315506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2630315506
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.485559394
Short name T284
Test name
Test status
Simulation time 70428690846 ps
CPU time 24.75 seconds
Started Dec 31 01:15:38 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200060 kb
Host smart-33fb323b-353b-44be-a955-d9a4b5b1a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485559394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.485559394
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3854224385
Short name T197
Test name
Test status
Simulation time 38945403288 ps
CPU time 66.91 seconds
Started Dec 31 01:13:32 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 200192 kb
Host smart-64fec5c9-1d21-4c80-b74e-27c9f7d2f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854224385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3854224385
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3033189258
Short name T167
Test name
Test status
Simulation time 42316562184 ps
CPU time 9.89 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:14:35 PM PST 23
Peak memory 200188 kb
Host smart-e6baad24-f32d-4a8a-b0bc-9e93df9185ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033189258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3033189258
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.136141034
Short name T391
Test name
Test status
Simulation time 217896922935 ps
CPU time 231.97 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:18:57 PM PST 23
Peak memory 216996 kb
Host smart-b3857c03-c391-40ff-aed3-8d04168ceaec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136141034 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.136141034
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2864625416
Short name T393
Test name
Test status
Simulation time 135210794931 ps
CPU time 51.81 seconds
Started Dec 31 01:12:57 PM PST 23
Finished Dec 31 01:14:02 PM PST 23
Peak memory 200208 kb
Host smart-8d46df36-0863-4cfb-956c-f679c72deb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864625416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2864625416
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2759535693
Short name T157
Test name
Test status
Simulation time 129828048696 ps
CPU time 80.31 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:16:31 PM PST 23
Peak memory 200228 kb
Host smart-99777cda-f13d-480d-8ec9-f03bd1db0ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759535693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2759535693
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3156956377
Short name T394
Test name
Test status
Simulation time 47805739288 ps
CPU time 22.49 seconds
Started Dec 31 01:13:06 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 198992 kb
Host smart-285b7849-41d5-4307-9041-98b15bb9ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156956377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3156956377
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.776130920
Short name T358
Test name
Test status
Simulation time 67185421053 ps
CPU time 114.43 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:17:22 PM PST 23
Peak memory 200232 kb
Host smart-ea272f66-665d-4a8d-9d81-d60731c5e52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776130920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.776130920
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3990459764
Short name T266
Test name
Test status
Simulation time 151527671298 ps
CPU time 63.24 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:16:14 PM PST 23
Peak memory 199536 kb
Host smart-7c113435-de46-448d-9bd9-397ed6906803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990459764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3990459764
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2726940080
Short name T486
Test name
Test status
Simulation time 28570708497 ps
CPU time 267.21 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:18:02 PM PST 23
Peak memory 213560 kb
Host smart-c68382ef-a399-491d-bd8d-a9a964d7cbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726940080 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2726940080
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4088017660
Short name T413
Test name
Test status
Simulation time 38553807184 ps
CPU time 7.84 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200160 kb
Host smart-cbd7a7e1-cc99-4f48-867f-2b8954c59945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088017660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4088017660
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3373422740
Short name T290
Test name
Test status
Simulation time 204322671441 ps
CPU time 34.35 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:16:02 PM PST 23
Peak memory 200260 kb
Host smart-8cadaaa9-ef19-4bab-9d5d-5ed97147fde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373422740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3373422740
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3319357453
Short name T367
Test name
Test status
Simulation time 145221514193 ps
CPU time 68.35 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:16:38 PM PST 23
Peak memory 200124 kb
Host smart-118704ba-d0a3-40ff-8532-59dc4a9a2460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319357453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3319357453
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3102070830
Short name T238
Test name
Test status
Simulation time 198874997253 ps
CPU time 73.77 seconds
Started Dec 31 01:15:38 PM PST 23
Finished Dec 31 01:16:53 PM PST 23
Peak memory 199884 kb
Host smart-24619a26-2909-4ce4-bce4-19ec8e205fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102070830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3102070830
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.42128723
Short name T210
Test name
Test status
Simulation time 61657405299 ps
CPU time 18.47 seconds
Started Dec 31 01:15:54 PM PST 23
Finished Dec 31 01:16:13 PM PST 23
Peak memory 199700 kb
Host smart-329086df-6c47-48d1-b501-3e1935320728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42128723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.42128723
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.110581446
Short name T223
Test name
Test status
Simulation time 70200734159 ps
CPU time 22.96 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:15:59 PM PST 23
Peak memory 200236 kb
Host smart-fa368967-216f-47fb-90d7-1cb667d5eff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110581446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.110581446
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.24434829
Short name T263
Test name
Test status
Simulation time 72559536433 ps
CPU time 92.49 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:17:09 PM PST 23
Peak memory 200204 kb
Host smart-dadeceb6-5a4e-438a-a9d0-444685127fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24434829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.24434829
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.250799271
Short name T185
Test name
Test status
Simulation time 63466696762 ps
CPU time 33.4 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:23 PM PST 23
Peak memory 200204 kb
Host smart-9adcc102-0103-48f6-a98f-69df796e8fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250799271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.250799271
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.195439554
Short name T190
Test name
Test status
Simulation time 23025415547 ps
CPU time 10.51 seconds
Started Dec 31 01:15:53 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200128 kb
Host smart-63efae79-b0a2-469a-94fd-9a2fc177f8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195439554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.195439554
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.664529065
Short name T179
Test name
Test status
Simulation time 31094251573 ps
CPU time 24.46 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:13 PM PST 23
Peak memory 200200 kb
Host smart-9ec4e3dd-8a5c-4947-8496-3d2744218a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664529065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.664529065
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1343037968
Short name T301
Test name
Test status
Simulation time 251753370987 ps
CPU time 696.37 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:26:42 PM PST 23
Peak memory 225136 kb
Host smart-8da677b1-bc90-43f7-91c6-5aab21b4b603
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343037968 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1343037968
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.1068370419
Short name T134
Test name
Test status
Simulation time 103359752557 ps
CPU time 451.97 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:22:38 PM PST 23
Peak memory 200216 kb
Host smart-58eafb4a-3d76-455f-8ccd-0817dc0f1ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068370419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1068370419
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2752020061
Short name T229
Test name
Test status
Simulation time 133664098279 ps
CPU time 110.56 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:14:22 PM PST 23
Peak memory 200236 kb
Host smart-893e511c-5dfb-46d7-89e2-9e9c45e0421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752020061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2752020061
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.691992231
Short name T307
Test name
Test status
Simulation time 72819948284 ps
CPU time 126.09 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:17:36 PM PST 23
Peak memory 199732 kb
Host smart-e892881e-338e-44f2-99ab-64f804db2809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691992231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.691992231
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1895198239
Short name T144
Test name
Test status
Simulation time 15835967292 ps
CPU time 26.87 seconds
Started Dec 31 01:12:32 PM PST 23
Finished Dec 31 01:13:03 PM PST 23
Peak memory 200244 kb
Host smart-a6715374-47db-4aaf-8542-ae823d4d9c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895198239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1895198239
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1009463691
Short name T417
Test name
Test status
Simulation time 36170694 ps
CPU time 0.52 seconds
Started Dec 31 12:47:00 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 185152 kb
Host smart-8ba46998-9463-4f21-aaa2-155b8cf0a7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009463691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1009463691
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1039547635
Short name T245
Test name
Test status
Simulation time 28734873191 ps
CPU time 25.7 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:12:57 PM PST 23
Peak memory 200184 kb
Host smart-358be793-9fad-4458-bb31-94f64f91cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039547635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1039547635
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3663111296
Short name T281
Test name
Test status
Simulation time 27873831948 ps
CPU time 11.72 seconds
Started Dec 31 01:12:55 PM PST 23
Finished Dec 31 01:13:16 PM PST 23
Peak memory 200296 kb
Host smart-9122a387-4b95-4683-9ef6-c1a4d2529860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663111296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3663111296
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.36822312
Short name T352
Test name
Test status
Simulation time 49108584864 ps
CPU time 74.42 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:16:25 PM PST 23
Peak memory 200056 kb
Host smart-66f09731-375d-4e0a-a704-ca29cb9f44a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36822312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.36822312
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.131498370
Short name T141
Test name
Test status
Simulation time 38006229921 ps
CPU time 27.57 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:15:57 PM PST 23
Peak memory 200204 kb
Host smart-7482bfdc-f046-49e5-9f84-41ab0756f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131498370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.131498370
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.566516841
Short name T218
Test name
Test status
Simulation time 130129263543 ps
CPU time 92.22 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:16:43 PM PST 23
Peak memory 200192 kb
Host smart-5916659b-25e1-4c83-947c-4ab3fa2acf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566516841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.566516841
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1170719651
Short name T328
Test name
Test status
Simulation time 74748354550 ps
CPU time 109.1 seconds
Started Dec 31 01:15:31 PM PST 23
Finished Dec 31 01:17:21 PM PST 23
Peak memory 199452 kb
Host smart-d0e01924-03d9-449c-9743-90222d13c8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170719651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1170719651
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3262490275
Short name T305
Test name
Test status
Simulation time 20105632342 ps
CPU time 35.08 seconds
Started Dec 31 01:13:02 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 199356 kb
Host smart-e76d0b49-6637-49cd-a795-f3aeda84d59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262490275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3262490275
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1458729530
Short name T1215
Test name
Test status
Simulation time 22184669862 ps
CPU time 40.12 seconds
Started Dec 31 01:13:04 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 200148 kb
Host smart-90b8b7e2-9102-4ac5-abbc-fcb45ab19172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458729530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1458729530
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1411601588
Short name T365
Test name
Test status
Simulation time 16347391894 ps
CPU time 27.17 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:15:56 PM PST 23
Peak memory 199824 kb
Host smart-f5ffc2a6-dab3-4da5-8710-2c3dc35f8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411601588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1411601588
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1278968143
Short name T372
Test name
Test status
Simulation time 55491332246 ps
CPU time 104.65 seconds
Started Dec 31 01:15:08 PM PST 23
Finished Dec 31 01:16:57 PM PST 23
Peak memory 200212 kb
Host smart-8fdc4cf7-449d-404d-a5ae-e656bdafc116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278968143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1278968143
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.4119155205
Short name T297
Test name
Test status
Simulation time 22715367228 ps
CPU time 38.36 seconds
Started Dec 31 01:13:04 PM PST 23
Finished Dec 31 01:13:53 PM PST 23
Peak memory 200180 kb
Host smart-57e2c4ac-438c-491c-bd69-d37a32fd28a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119155205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4119155205
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3469817698
Short name T176
Test name
Test status
Simulation time 18139480637 ps
CPU time 14.05 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:15:51 PM PST 23
Peak memory 200148 kb
Host smart-7bd59f3a-a139-4199-a0d9-cbd00c9b5fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469817698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3469817698
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2532543607
Short name T142
Test name
Test status
Simulation time 36660981921 ps
CPU time 56.14 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:16:32 PM PST 23
Peak memory 198912 kb
Host smart-d3e28048-4247-4497-8cb3-713eaf8b2cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532543607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2532543607
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.730718512
Short name T386
Test name
Test status
Simulation time 95425193332 ps
CPU time 168.16 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:18:26 PM PST 23
Peak memory 199096 kb
Host smart-7156a78f-e7f2-4f10-a4d8-3cdae02b0707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730718512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.730718512
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.2579362637
Short name T11
Test name
Test status
Simulation time 545627013474 ps
CPU time 232.84 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:17:28 PM PST 23
Peak memory 200216 kb
Host smart-c9b79e09-805f-45b7-944f-003b08881bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579362637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2579362637
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2524462759
Short name T403
Test name
Test status
Simulation time 315855134525 ps
CPU time 72.16 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:16:49 PM PST 23
Peak memory 199944 kb
Host smart-1238f119-cded-4661-b65d-a8cde0bfc297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524462759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2524462759
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_perf.3326748983
Short name T310
Test name
Test status
Simulation time 11465062420 ps
CPU time 92.48 seconds
Started Dec 31 01:13:16 PM PST 23
Finished Dec 31 01:14:54 PM PST 23
Peak memory 199828 kb
Host smart-80ad520a-51b0-4027-8e6e-25ac8a867f87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326748983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3326748983
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3912610460
Short name T392
Test name
Test status
Simulation time 32022108739 ps
CPU time 52.61 seconds
Started Dec 31 01:15:54 PM PST 23
Finished Dec 31 01:16:48 PM PST 23
Peak memory 200068 kb
Host smart-99c11e85-39b5-49fb-9bda-ddce373d66f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912610460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3912610460
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.478552866
Short name T217
Test name
Test status
Simulation time 96595122661 ps
CPU time 146.17 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:17:54 PM PST 23
Peak memory 199696 kb
Host smart-56a3ee59-6749-4327-9918-16ba0dc7fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478552866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.478552866
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2639629062
Short name T330
Test name
Test status
Simulation time 24556886061 ps
CPU time 37.57 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:16:14 PM PST 23
Peak memory 200144 kb
Host smart-e2f85ab9-0449-418e-a3aa-d85f65efcab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639629062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2639629062
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1066965571
Short name T213
Test name
Test status
Simulation time 50147431318 ps
CPU time 21.71 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200132 kb
Host smart-880a9a24-dde3-4907-a801-3af0625f8d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066965571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1066965571
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1305247328
Short name T155
Test name
Test status
Simulation time 125022046773 ps
CPU time 57.87 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:26 PM PST 23
Peak memory 200132 kb
Host smart-ea744ae3-9b4a-4538-a512-fb4cb1a87ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305247328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1305247328
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.524073345
Short name T402
Test name
Test status
Simulation time 722824822713 ps
CPU time 1735.08 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:42:21 PM PST 23
Peak memory 237804 kb
Host smart-ea03cf7a-a6f8-40c3-bb51-52066edc7c60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524073345 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.524073345
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.434531603
Short name T370
Test name
Test status
Simulation time 21478509086 ps
CPU time 32.94 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:16:24 PM PST 23
Peak memory 200188 kb
Host smart-6162879c-f9cc-462a-8497-c3636d20d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434531603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.434531603
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1384827140
Short name T343
Test name
Test status
Simulation time 64118280981 ps
CPU time 47.1 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:35 PM PST 23
Peak memory 200156 kb
Host smart-088a085a-eb82-40de-9898-62a4db6f1b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384827140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1384827140
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2698087726
Short name T308
Test name
Test status
Simulation time 73254699195 ps
CPU time 85.81 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:15:03 PM PST 23
Peak memory 199108 kb
Host smart-0b5570da-82a5-4637-ae18-3773afce9f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698087726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2698087726
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2727236423
Short name T408
Test name
Test status
Simulation time 75408082664 ps
CPU time 113.43 seconds
Started Dec 31 01:15:43 PM PST 23
Finished Dec 31 01:17:37 PM PST 23
Peak memory 200176 kb
Host smart-2e09e4e6-9eb4-493e-a2d1-0181fc3eb5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727236423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2727236423
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2826500464
Short name T304
Test name
Test status
Simulation time 10921963639 ps
CPU time 19.09 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:08 PM PST 23
Peak memory 199892 kb
Host smart-6cc21b90-353b-44f6-844d-760a41ef8517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826500464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2826500464
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1961081710
Short name T315
Test name
Test status
Simulation time 34802787853 ps
CPU time 38.45 seconds
Started Dec 31 01:15:50 PM PST 23
Finished Dec 31 01:16:30 PM PST 23
Peak memory 200084 kb
Host smart-83544d15-86c8-4a52-abe6-8ceccc1efc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961081710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1961081710
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3888458906
Short name T373
Test name
Test status
Simulation time 15048454391 ps
CPU time 8.33 seconds
Started Dec 31 01:15:52 PM PST 23
Finished Dec 31 01:16:01 PM PST 23
Peak memory 200136 kb
Host smart-28fc56ce-595f-4889-92b5-cabfc7591e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888458906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3888458906
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.129355725
Short name T237
Test name
Test status
Simulation time 214539464163 ps
CPU time 33.37 seconds
Started Dec 31 01:15:50 PM PST 23
Finished Dec 31 01:16:25 PM PST 23
Peak memory 200132 kb
Host smart-9eae692e-a345-4237-af1d-4d42ee7a2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129355725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.129355725
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2044118838
Short name T320
Test name
Test status
Simulation time 90210272127 ps
CPU time 39.23 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:28 PM PST 23
Peak memory 200192 kb
Host smart-1e8ac24e-3ae0-4190-9bf7-d053a3b90349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044118838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2044118838
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1730466390
Short name T382
Test name
Test status
Simulation time 21402473386 ps
CPU time 27.7 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:59 PM PST 23
Peak memory 200120 kb
Host smart-2d316b33-3ad5-46ff-8eb1-12e25d6e272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730466390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1730466390
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.4237298647
Short name T360
Test name
Test status
Simulation time 57527269546 ps
CPU time 322.83 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:17:49 PM PST 23
Peak memory 209028 kb
Host smart-4409e8f8-7da4-4e47-9abb-312bfa8ec457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237298647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.4237298647
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_perf.2547266626
Short name T302
Test name
Test status
Simulation time 14966761723 ps
CPU time 930.63 seconds
Started Dec 31 01:13:40 PM PST 23
Finished Dec 31 01:29:14 PM PST 23
Peak memory 200164 kb
Host smart-8c403cfb-9eed-471c-a10a-43c56a1a8195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547266626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2547266626
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1993846000
Short name T68
Test name
Test status
Simulation time 266576306287 ps
CPU time 602.32 seconds
Started Dec 31 01:13:44 PM PST 23
Finished Dec 31 01:23:48 PM PST 23
Peak memory 225112 kb
Host smart-f00449fd-096f-4d38-92ab-803d9e754680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993846000 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1993846000
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1162564272
Short name T411
Test name
Test status
Simulation time 168781542040 ps
CPU time 113.54 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:16:55 PM PST 23
Peak memory 200116 kb
Host smart-4d16a151-f236-4f49-8da2-e8fe29b3dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162564272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1162564272
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3746128325
Short name T113
Test name
Test status
Simulation time 106047894594 ps
CPU time 42.62 seconds
Started Dec 31 01:14:25 PM PST 23
Finished Dec 31 01:15:09 PM PST 23
Peak memory 200276 kb
Host smart-d81e82b4-5390-4ba8-be5b-7aeae99adee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746128325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3746128325
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1456093396
Short name T409
Test name
Test status
Simulation time 78670885456 ps
CPU time 31.9 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:33 PM PST 23
Peak memory 200208 kb
Host smart-fe2387e0-4ecc-4d95-bfde-06a58b17bc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456093396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1456093396
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2829296797
Short name T116
Test name
Test status
Simulation time 10496251454 ps
CPU time 10.06 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:20 PM PST 23
Peak memory 198864 kb
Host smart-02a8a224-c422-474f-a106-64994f325273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829296797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2829296797
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_stress_all.2196482351
Short name T182
Test name
Test status
Simulation time 161382827638 ps
CPU time 57.75 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:15:40 PM PST 23
Peak memory 200388 kb
Host smart-907cc484-6fae-412c-8594-713a61a72172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196482351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2196482351
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2617777015
Short name T405
Test name
Test status
Simulation time 793866016292 ps
CPU time 430.31 seconds
Started Dec 31 01:15:33 PM PST 23
Finished Dec 31 01:22:44 PM PST 23
Peak memory 216576 kb
Host smart-02888ca9-c96f-44a9-bdde-5067e247be12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617777015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2617777015
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3724932097
Short name T303
Test name
Test status
Simulation time 164916833687 ps
CPU time 221.31 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:18:46 PM PST 23
Peak memory 200152 kb
Host smart-c2197f30-34cd-4706-beda-d81ca9bdd2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724932097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3724932097
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.717564708
Short name T380
Test name
Test status
Simulation time 787353768757 ps
CPU time 603.01 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:25:10 PM PST 23
Peak memory 225100 kb
Host smart-59abae43-67aa-40f4-b6ba-fa081ec9452d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717564708 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.717564708
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1181429983
Short name T375
Test name
Test status
Simulation time 63673035334 ps
CPU time 702.48 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:24:12 PM PST 23
Peak memory 225124 kb
Host smart-a6d7330b-6e94-4824-ac7d-9e493fb85bba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181429983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1181429983
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2965545157
Short name T397
Test name
Test status
Simulation time 89457217142 ps
CPU time 42.68 seconds
Started Dec 31 01:15:32 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 200224 kb
Host smart-8e72686d-4083-4108-b01d-37705497a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965545157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2965545157
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3093334838
Short name T398
Test name
Test status
Simulation time 10124298178 ps
CPU time 15.6 seconds
Started Dec 31 01:15:08 PM PST 23
Finished Dec 31 01:15:27 PM PST 23
Peak memory 198908 kb
Host smart-ff4aa390-d330-418a-a00e-eff72e7ac862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093334838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3093334838
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1281706115
Short name T311
Test name
Test status
Simulation time 26428844083 ps
CPU time 24.22 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:12:58 PM PST 23
Peak memory 200236 kb
Host smart-35c2062f-3891-43af-8eb9-8bc5e57b5fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281706115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1281706115
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.275374719
Short name T341
Test name
Test status
Simulation time 29049420442 ps
CPU time 50.45 seconds
Started Dec 31 01:14:46 PM PST 23
Finished Dec 31 01:15:38 PM PST 23
Peak memory 200196 kb
Host smart-242f1d05-bbc5-415c-ba42-fef43a2f6284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275374719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.275374719
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1721141595
Short name T278
Test name
Test status
Simulation time 48502088397 ps
CPU time 27.24 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 200196 kb
Host smart-e8e186e5-d9d3-49a5-9441-86fab8d01db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721141595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1721141595
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.499105060
Short name T1276
Test name
Test status
Simulation time 114688388 ps
CPU time 0.66 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:40 PM PST 23
Peak memory 195408 kb
Host smart-c0812d34-602e-41a5-a55a-3489af296754
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499105060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.499105060
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1295323844
Short name T79
Test name
Test status
Simulation time 207941395 ps
CPU time 0.59 seconds
Started Dec 31 12:46:52 PM PST 23
Finished Dec 31 12:46:59 PM PST 23
Peak memory 195368 kb
Host smart-5427ea39-69b8-4889-9acd-164d4255294f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295323844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1295323844
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2905910721
Short name T1261
Test name
Test status
Simulation time 42106391 ps
CPU time 1.13 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 200028 kb
Host smart-2a479269-59e6-4896-83d1-a5d0b4f1215a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905910721 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2905910721
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3966689072
Short name T1270
Test name
Test status
Simulation time 11613370 ps
CPU time 0.61 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 195412 kb
Host smart-1fde540a-3fdc-4ba4-a76f-e814aa2be4df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966689072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3966689072
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3030300226
Short name T7
Test name
Test status
Simulation time 119808189 ps
CPU time 0.67 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 195652 kb
Host smart-af6541f5-1e09-4407-b905-629016682bdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030300226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3030300226
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2209648850
Short name T504
Test name
Test status
Simulation time 89396091 ps
CPU time 2.22 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:26 PM PST 23
Peak memory 200008 kb
Host smart-26203a89-c5de-4512-b065-fb2db3acc573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209648850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2209648850
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1326422662
Short name T33
Test name
Test status
Simulation time 98143101 ps
CPU time 1.31 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:46:50 PM PST 23
Peak memory 199272 kb
Host smart-554ec9b1-2f79-4df9-8848-7a0e070f3168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326422662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1326422662
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2993700681
Short name T9
Test name
Test status
Simulation time 57064688 ps
CPU time 0.77 seconds
Started Dec 31 12:47:06 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 196324 kb
Host smart-5a797e4d-c993-4b12-bcdd-f92f2da15081
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993700681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2993700681
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.306849172
Short name T1291
Test name
Test status
Simulation time 3124133203 ps
CPU time 2.47 seconds
Started Dec 31 12:46:23 PM PST 23
Finished Dec 31 12:46:27 PM PST 23
Peak memory 197476 kb
Host smart-e8175772-b389-4658-8ff1-6212f9903c4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306849172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.306849172
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3268275774
Short name T6
Test name
Test status
Simulation time 30164775 ps
CPU time 0.59 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 195456 kb
Host smart-da2b2595-1f8a-4496-a633-4ca3412c6735
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268275774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3268275774
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2138867599
Short name T515
Test name
Test status
Simulation time 17063754 ps
CPU time 0.83 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 199776 kb
Host smart-961bc2cc-ee4b-445b-a28b-ce6b6f1e6c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138867599 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2138867599
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3650068817
Short name T55
Test name
Test status
Simulation time 32407063 ps
CPU time 0.55 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 12:46:26 PM PST 23
Peak memory 195444 kb
Host smart-21940f11-5ebf-4416-83f7-cdcdc7110a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650068817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3650068817
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3524021521
Short name T522
Test name
Test status
Simulation time 61772484 ps
CPU time 0.55 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 12:46:15 PM PST 23
Peak memory 194324 kb
Host smart-42e83065-7fbe-4007-8113-2b6016cd996f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524021521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3524021521
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3954381211
Short name T48
Test name
Test status
Simulation time 43615789 ps
CPU time 0.72 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:31 PM PST 23
Peak memory 196900 kb
Host smart-bb0ea80e-489b-4fb6-ae39-0918c4160dd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954381211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3954381211
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3928655758
Short name T32
Test name
Test status
Simulation time 26506291 ps
CPU time 0.62 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:27 PM PST 23
Peak memory 197572 kb
Host smart-86cf6513-ef79-47b7-8943-f61a71ce9278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928655758 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3928655758
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3348186363
Short name T517
Test name
Test status
Simulation time 173210920 ps
CPU time 0.57 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 195432 kb
Host smart-f2588994-b206-4737-8c0a-d040c2c82fa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348186363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3348186363
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3912391492
Short name T1274
Test name
Test status
Simulation time 11997268 ps
CPU time 0.55 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 194448 kb
Host smart-f5e22e17-a607-40d3-a7a0-f420eca4e473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912391492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3912391492
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2716440135
Short name T1280
Test name
Test status
Simulation time 416049413 ps
CPU time 2.02 seconds
Started Dec 31 12:46:41 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 200056 kb
Host smart-da17bb48-2522-4aed-a40c-0a45ba84b93d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716440135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2716440135
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3158061686
Short name T1289
Test name
Test status
Simulation time 379153532 ps
CPU time 1.3 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 199160 kb
Host smart-08a0a85d-4114-45f0-9f2f-6dc4431e41f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158061686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3158061686
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.787070181
Short name T510
Test name
Test status
Simulation time 93681085 ps
CPU time 1.15 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 200088 kb
Host smart-309f7747-20ac-48d0-b30f-09b100ea8515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787070181 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.787070181
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1209206898
Short name T493
Test name
Test status
Simulation time 25128046 ps
CPU time 0.62 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 195576 kb
Host smart-b1230f1b-810b-4647-adaa-210887fe6432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209206898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1209206898
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1110908481
Short name T1297
Test name
Test status
Simulation time 21565625 ps
CPU time 0.55 seconds
Started Dec 31 12:46:49 PM PST 23
Finished Dec 31 12:46:53 PM PST 23
Peak memory 185112 kb
Host smart-905fb7fd-a0e4-4f3b-8b68-2cb2819e9fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110908481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1110908481
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1072593833
Short name T58
Test name
Test status
Simulation time 72241996 ps
CPU time 0.64 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:25 PM PST 23
Peak memory 195668 kb
Host smart-4d6a6a75-d97e-4c54-94f2-d16418cc9946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072593833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1072593833
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1511089251
Short name T1282
Test name
Test status
Simulation time 54534426 ps
CPU time 1.43 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 200000 kb
Host smart-1dd573eb-4575-4707-b3f1-1bb0df0e00ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511089251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1511089251
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2743992846
Short name T42
Test name
Test status
Simulation time 22322495 ps
CPU time 1.12 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 200044 kb
Host smart-bb0a7886-1c03-44b6-9afe-7f01da11f0f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743992846 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2743992846
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1179229453
Short name T56
Test name
Test status
Simulation time 102655646 ps
CPU time 0.58 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:28 PM PST 23
Peak memory 195432 kb
Host smart-61a89658-8f4a-4890-9fff-3704611bffd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179229453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1179229453
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1064348681
Short name T1256
Test name
Test status
Simulation time 12827881 ps
CPU time 0.55 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 185092 kb
Host smart-c7650f8e-0eb6-4309-ae5d-851e79f09753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064348681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1064348681
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1431118444
Short name T60
Test name
Test status
Simulation time 106023263 ps
CPU time 0.72 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 197156 kb
Host smart-0bb81e0a-cae1-4e13-b4be-9d391126b8d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431118444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1431118444
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2217384763
Short name T43
Test name
Test status
Simulation time 363048054 ps
CPU time 1.84 seconds
Started Dec 31 12:46:54 PM PST 23
Finished Dec 31 12:46:57 PM PST 23
Peak memory 199996 kb
Host smart-770042ad-32f2-41fd-aab5-47412c7a6096
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217384763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2217384763
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3839610780
Short name T39
Test name
Test status
Simulation time 394360349 ps
CPU time 1.25 seconds
Started Dec 31 12:47:05 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 199164 kb
Host smart-818e538f-4380-46c7-88fc-5b0c33c68166
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839610780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3839610780
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2837204498
Short name T35
Test name
Test status
Simulation time 95966729 ps
CPU time 0.62 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 197756 kb
Host smart-c1f94d61-f2f9-4794-8b95-7df2507c713c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837204498 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2837204498
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2922628264
Short name T66
Test name
Test status
Simulation time 116003363 ps
CPU time 0.58 seconds
Started Dec 31 12:46:25 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 195456 kb
Host smart-e19014a3-65d5-47f7-b78f-8b819566e94e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922628264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2922628264
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.4178558185
Short name T513
Test name
Test status
Simulation time 53629610 ps
CPU time 0.55 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:19 PM PST 23
Peak memory 185108 kb
Host smart-c23b4e83-05ce-42da-abdd-8a91fa763926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178558185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4178558185
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.13137514
Short name T1299
Test name
Test status
Simulation time 100061315 ps
CPU time 0.71 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 195740 kb
Host smart-fac4bedc-8bb2-402a-971f-3e8fca0e8d83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_
outstanding.13137514
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1079348599
Short name T54
Test name
Test status
Simulation time 71539902 ps
CPU time 1.86 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 200152 kb
Host smart-b362e719-7ec1-4923-81d2-7187a7b89e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079348599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1079348599
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1631897728
Short name T52
Test name
Test status
Simulation time 38697384 ps
CPU time 0.86 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 198780 kb
Host smart-4fef0b35-f8e3-4e3c-a13b-b2ad0d81b26d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631897728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1631897728
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3539784957
Short name T1268
Test name
Test status
Simulation time 63381574 ps
CPU time 0.63 seconds
Started Dec 31 12:46:55 PM PST 23
Finished Dec 31 12:46:56 PM PST 23
Peak memory 196248 kb
Host smart-5b7f7c98-aa4b-4bee-8d23-cd31932ad1f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539784957 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3539784957
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2638806849
Short name T1271
Test name
Test status
Simulation time 15192900 ps
CPU time 0.55 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 195544 kb
Host smart-1774b7c0-3dd9-4db7-bb3a-2341bea018e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638806849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2638806849
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1211329156
Short name T97
Test name
Test status
Simulation time 22905940 ps
CPU time 0.54 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 185164 kb
Host smart-4c6cebf6-4615-4fdb-8233-316792ab64de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211329156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1211329156
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1823573389
Short name T1248
Test name
Test status
Simulation time 24964972 ps
CPU time 0.6 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:35 PM PST 23
Peak memory 195564 kb
Host smart-218e1407-2442-4902-a21b-3fc07d6ed9bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823573389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1823573389
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.4214647192
Short name T1292
Test name
Test status
Simulation time 269382859 ps
CPU time 1.47 seconds
Started Dec 31 12:46:58 PM PST 23
Finished Dec 31 12:47:01 PM PST 23
Peak memory 200008 kb
Host smart-21344e5a-a507-4876-861f-57b0c0f8df22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214647192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.4214647192
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3349164374
Short name T51
Test name
Test status
Simulation time 226002331 ps
CPU time 0.88 seconds
Started Dec 31 12:46:16 PM PST 23
Finished Dec 31 12:46:18 PM PST 23
Peak memory 198964 kb
Host smart-2ddb1482-5691-4af9-938a-2674e30dcb4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349164374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3349164374
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.789947559
Short name T30
Test name
Test status
Simulation time 78168322 ps
CPU time 1.06 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 200068 kb
Host smart-b78e30a0-dd46-4164-a821-82b29b1ecf7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789947559 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.789947559
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3553184218
Short name T1266
Test name
Test status
Simulation time 15746242 ps
CPU time 0.63 seconds
Started Dec 31 12:46:51 PM PST 23
Finished Dec 31 12:46:53 PM PST 23
Peak memory 195512 kb
Host smart-7dd23310-616c-443e-8630-ae5b7fff20fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553184218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3553184218
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1813961082
Short name T1258
Test name
Test status
Simulation time 52015513 ps
CPU time 0.55 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 194356 kb
Host smart-b4490c5b-d8fa-46d0-bb0a-2ab8b616a3b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813961082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1813961082
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3917787629
Short name T82
Test name
Test status
Simulation time 161027550 ps
CPU time 0.65 seconds
Started Dec 31 12:47:00 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 195792 kb
Host smart-ab36dc53-1528-4955-96cc-80860580cd8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917787629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3917787629
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1046902935
Short name T521
Test name
Test status
Simulation time 105811977 ps
CPU time 1.71 seconds
Started Dec 31 12:46:59 PM PST 23
Finished Dec 31 12:47:03 PM PST 23
Peak memory 200012 kb
Host smart-36b3da6d-24c5-4146-aa49-8d90abdfa4ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046902935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1046902935
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3578169809
Short name T89
Test name
Test status
Simulation time 240304960 ps
CPU time 1.22 seconds
Started Dec 31 12:46:49 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 199216 kb
Host smart-c598847c-844a-4e2b-8e56-29ed83ac2672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578169809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3578169809
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1781675975
Short name T78
Test name
Test status
Simulation time 75200388 ps
CPU time 0.78 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 199708 kb
Host smart-f6d0f2ab-c2fa-4efd-9e56-895e49c11eac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781675975 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1781675975
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3886766105
Short name T1272
Test name
Test status
Simulation time 46688015 ps
CPU time 0.57 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 195432 kb
Host smart-f78059d0-048e-424e-948b-009d1d01dc3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886766105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3886766105
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.663887742
Short name T518
Test name
Test status
Simulation time 51905173 ps
CPU time 0.56 seconds
Started Dec 31 12:46:48 PM PST 23
Finished Dec 31 12:46:50 PM PST 23
Peak memory 185208 kb
Host smart-d7348552-88e4-4218-8a96-bc53c2bf5849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663887742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.663887742
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.674138713
Short name T1247
Test name
Test status
Simulation time 25209285 ps
CPU time 0.65 seconds
Started Dec 31 12:47:00 PM PST 23
Finished Dec 31 12:47:03 PM PST 23
Peak memory 195556 kb
Host smart-9dbae987-b6a8-4c66-9460-a294320578b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674138713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.674138713
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4163066261
Short name T520
Test name
Test status
Simulation time 135668146 ps
CPU time 1.72 seconds
Started Dec 31 12:46:50 PM PST 23
Finished Dec 31 12:46:53 PM PST 23
Peak memory 200012 kb
Host smart-924fa94e-91de-4a82-b17a-72050bc872d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163066261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4163066261
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.226452669
Short name T1257
Test name
Test status
Simulation time 358338450 ps
CPU time 1.26 seconds
Started Dec 31 12:46:49 PM PST 23
Finished Dec 31 12:46:51 PM PST 23
Peak memory 199248 kb
Host smart-12f2fd32-5e54-4885-afa2-9f0ef339a5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226452669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.226452669
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.157051781
Short name T73
Test name
Test status
Simulation time 33697660 ps
CPU time 0.66 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:25 PM PST 23
Peak memory 197900 kb
Host smart-c7ebb980-b10f-4b8e-81f7-1fe2bb584ef1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157051781 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.157051781
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3312374521
Short name T83
Test name
Test status
Simulation time 24094322 ps
CPU time 0.62 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 195544 kb
Host smart-184bf246-8afd-44bf-8345-3cddbea51311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312374521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3312374521
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3337555721
Short name T49
Test name
Test status
Simulation time 39655551 ps
CPU time 0.53 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 185132 kb
Host smart-1f5ebdec-1e92-4df7-b063-6a693d3dd3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337555721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3337555721
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2656278535
Short name T77
Test name
Test status
Simulation time 31062119 ps
CPU time 0.73 seconds
Started Dec 31 12:46:57 PM PST 23
Finished Dec 31 12:46:59 PM PST 23
Peak memory 195952 kb
Host smart-5399f448-5234-4b56-a4a0-f2dcb82a466b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656278535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2656278535
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2426053861
Short name T1264
Test name
Test status
Simulation time 37589506 ps
CPU time 1.83 seconds
Started Dec 31 12:46:49 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 200000 kb
Host smart-630a0d31-cf50-4215-be02-73e47db9d4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426053861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2426053861
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3533709045
Short name T88
Test name
Test status
Simulation time 47830454 ps
CPU time 0.93 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 198668 kb
Host smart-b5508018-09df-4ed8-8715-94695b0c56cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533709045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3533709045
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1072248047
Short name T1273
Test name
Test status
Simulation time 65994296 ps
CPU time 1.02 seconds
Started Dec 31 12:47:04 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 200020 kb
Host smart-bdda9b34-8da6-4c0a-87bf-4fd5b808bcd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072248047 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1072248047
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1996079804
Short name T61
Test name
Test status
Simulation time 14350028 ps
CPU time 0.55 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 195440 kb
Host smart-fb9ae011-dcd9-4de3-b802-0e758b49b0c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996079804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1996079804
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.707630484
Short name T1254
Test name
Test status
Simulation time 50293323 ps
CPU time 0.55 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 185132 kb
Host smart-95d67654-a107-48a5-ba23-3f14c8ecf838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707630484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.707630484
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.845493231
Short name T10
Test name
Test status
Simulation time 21686254 ps
CPU time 0.65 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 194412 kb
Host smart-c0f0137f-4131-404c-8192-6c3e2f60f4c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845493231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.845493231
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.736896003
Short name T416
Test name
Test status
Simulation time 176874189 ps
CPU time 0.92 seconds
Started Dec 31 12:47:03 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 198896 kb
Host smart-9f2e1574-fd6f-4bb4-a2ed-26396b8427a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736896003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.736896003
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1021588450
Short name T1244
Test name
Test status
Simulation time 167328671 ps
CPU time 0.76 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 199676 kb
Host smart-00f7140d-2150-483c-9d03-073b731ba382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021588450 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1021588450
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3118178065
Short name T1250
Test name
Test status
Simulation time 57376166 ps
CPU time 0.59 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 195508 kb
Host smart-ed0ed21f-bfa0-4b4c-be05-417571196873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118178065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3118178065
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.4009878251
Short name T499
Test name
Test status
Simulation time 13125622 ps
CPU time 0.53 seconds
Started Dec 31 12:46:49 PM PST 23
Finished Dec 31 12:46:50 PM PST 23
Peak memory 185148 kb
Host smart-2834e2e4-60ed-4915-a30c-3230fedb476f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009878251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.4009878251
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3584537602
Short name T59
Test name
Test status
Simulation time 16405436 ps
CPU time 0.65 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 196020 kb
Host smart-fd7f9388-b570-4a75-a973-4eaa8481e5f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584537602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3584537602
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3278147059
Short name T519
Test name
Test status
Simulation time 225408313 ps
CPU time 1.97 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 200016 kb
Host smart-dd485bd2-cf98-44fa-99a0-384d5ca75007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278147059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3278147059
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2740599740
Short name T45
Test name
Test status
Simulation time 428600966 ps
CPU time 1.23 seconds
Started Dec 31 12:46:59 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 199272 kb
Host smart-e951218e-f642-4c8c-b160-e0df68ad49d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740599740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2740599740
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3333392526
Short name T72
Test name
Test status
Simulation time 14050637 ps
CPU time 0.64 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:46:16 PM PST 23
Peak memory 194920 kb
Host smart-3c2e5787-ed10-4ce8-8735-278cb8e4c65f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333392526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3333392526
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1330827383
Short name T1263
Test name
Test status
Simulation time 176235466 ps
CPU time 1.47 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 12:46:23 PM PST 23
Peak memory 197724 kb
Host smart-2cd08d40-337f-4f69-ac78-7948277c5f28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330827383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1330827383
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4138869695
Short name T503
Test name
Test status
Simulation time 37856562 ps
CPU time 0.55 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 195376 kb
Host smart-c30fade1-a254-4d74-aa29-677aeb2cff40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138869695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4138869695
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.279534403
Short name T523
Test name
Test status
Simulation time 12478295 ps
CPU time 0.73 seconds
Started Dec 31 12:46:52 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 198080 kb
Host smart-2bb7daa2-2657-47c9-87d9-de539424eeed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279534403 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.279534403
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1558072181
Short name T509
Test name
Test status
Simulation time 13400844 ps
CPU time 0.55 seconds
Started Dec 31 12:47:00 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 195388 kb
Host smart-bd257946-b7c1-4d00-a970-2ce65af1c825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558072181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1558072181
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.19307465
Short name T495
Test name
Test status
Simulation time 78551582 ps
CPU time 0.55 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 12:46:36 PM PST 23
Peak memory 185056 kb
Host smart-0770cc44-6134-4a62-9d5d-0da65e9659f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19307465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.19307465
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1678472174
Short name T74
Test name
Test status
Simulation time 16931153 ps
CPU time 0.68 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 196620 kb
Host smart-37879a1b-8ff8-4071-8900-f3354692da6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678472174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1678472174
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1060078274
Short name T502
Test name
Test status
Simulation time 22994085 ps
CPU time 1.05 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 199860 kb
Host smart-08091f89-7059-467d-bcf4-84336aad14ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060078274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1060078274
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3247053525
Short name T90
Test name
Test status
Simulation time 182813340 ps
CPU time 0.93 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 198760 kb
Host smart-cc3d766f-9532-402e-ba95-077f62505d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247053525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3247053525
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3887290216
Short name T1298
Test name
Test status
Simulation time 28539250 ps
CPU time 0.55 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 185088 kb
Host smart-9600f072-b8c1-4d9b-8cca-9b97b1ffdd57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887290216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3887290216
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1786592993
Short name T1260
Test name
Test status
Simulation time 19066799 ps
CPU time 0.54 seconds
Started Dec 31 12:46:45 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 185092 kb
Host smart-7b3014ad-5c8c-4819-bcb0-8299a4ec6a46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786592993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1786592993
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.50854747
Short name T497
Test name
Test status
Simulation time 14835912 ps
CPU time 0.54 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 185240 kb
Host smart-ccb1d560-70b1-47c6-a82e-b3e0ff169d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50854747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.50854747
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3573999781
Short name T1245
Test name
Test status
Simulation time 49591608 ps
CPU time 0.56 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 194372 kb
Host smart-9d82a39b-45f7-48c4-bd19-ebdc3c0cff8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573999781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3573999781
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3097923584
Short name T1267
Test name
Test status
Simulation time 12660431 ps
CPU time 0.55 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 185096 kb
Host smart-04fd9a9e-62c0-4a39-a210-efe1e78d76cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097923584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3097923584
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.965406705
Short name T96
Test name
Test status
Simulation time 13469541 ps
CPU time 0.56 seconds
Started Dec 31 12:46:48 PM PST 23
Finished Dec 31 12:46:50 PM PST 23
Peak memory 194428 kb
Host smart-67be90a5-4443-41af-bec9-97cc46230247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965406705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.965406705
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3871169311
Short name T3
Test name
Test status
Simulation time 83419146 ps
CPU time 0.55 seconds
Started Dec 31 12:47:02 PM PST 23
Finished Dec 31 12:47:08 PM PST 23
Peak memory 185180 kb
Host smart-42b89fae-b0f0-43d9-b793-5b48a8cef21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871169311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3871169311
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3630096033
Short name T1246
Test name
Test status
Simulation time 45315776 ps
CPU time 0.52 seconds
Started Dec 31 12:46:41 PM PST 23
Finished Dec 31 12:46:44 PM PST 23
Peak memory 185088 kb
Host smart-96af7a3b-020d-49d3-a6ac-ffbd0b910fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630096033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3630096033
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.71939854
Short name T516
Test name
Test status
Simulation time 12636702 ps
CPU time 0.53 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 185192 kb
Host smart-060e2f5b-1e1b-4ad7-9722-8b460663b44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71939854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.71939854
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.570713900
Short name T110
Test name
Test status
Simulation time 23421925 ps
CPU time 0.65 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 195416 kb
Host smart-da6d08b5-f645-48e1-8c9e-5b9282f92c40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570713900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.570713900
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4269447883
Short name T47
Test name
Test status
Simulation time 872417338 ps
CPU time 2.46 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:40 PM PST 23
Peak memory 197620 kb
Host smart-7a9dc767-6ac4-4ec6-bda1-c9343712cf54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269447883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4269447883
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3764537958
Short name T109
Test name
Test status
Simulation time 12460539 ps
CPU time 0.68 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 198092 kb
Host smart-490779c1-9344-42c2-85d7-856a1da4d481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764537958 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3764537958
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.996070506
Short name T69
Test name
Test status
Simulation time 28519510 ps
CPU time 0.59 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:46:18 PM PST 23
Peak memory 195388 kb
Host smart-0ff7a7ed-7d94-45e1-a591-9e3325fbc459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996070506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.996070506
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.784716018
Short name T1278
Test name
Test status
Simulation time 17288684 ps
CPU time 0.56 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 194336 kb
Host smart-d35d20ce-fa8f-4eab-b463-f6bd2a51b971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784716018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.784716018
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2695407289
Short name T8
Test name
Test status
Simulation time 18473716 ps
CPU time 0.72 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 196980 kb
Host smart-00d017bb-f4bd-4db8-ad59-6ac5e419c9e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695407289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2695407289
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1796771567
Short name T46
Test name
Test status
Simulation time 404872594 ps
CPU time 1.6 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 199968 kb
Host smart-783603ca-6d96-4760-ae52-c8e5359866a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796771567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1796771567
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1448845779
Short name T505
Test name
Test status
Simulation time 45036552 ps
CPU time 0.88 seconds
Started Dec 31 12:47:10 PM PST 23
Finished Dec 31 12:47:14 PM PST 23
Peak memory 198720 kb
Host smart-8e1d45de-7f12-44b4-a1f1-24df89270382
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448845779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1448845779
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.590799710
Short name T1265
Test name
Test status
Simulation time 80609178 ps
CPU time 0.55 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 185124 kb
Host smart-1427b7ae-2737-4af4-ab21-dcdc003ce8a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590799710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.590799710
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3977205151
Short name T111
Test name
Test status
Simulation time 16018759 ps
CPU time 0.56 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:46:50 PM PST 23
Peak memory 185128 kb
Host smart-3caf08e2-e7da-4b76-b15b-80b2198d3987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977205151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3977205151
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2766942849
Short name T419
Test name
Test status
Simulation time 33515318 ps
CPU time 0.56 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 194460 kb
Host smart-36d73b6d-bf62-42ec-b490-b92118241017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766942849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2766942849
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2479505315
Short name T1295
Test name
Test status
Simulation time 43495824 ps
CPU time 0.52 seconds
Started Dec 31 12:46:53 PM PST 23
Finished Dec 31 12:46:55 PM PST 23
Peak memory 194408 kb
Host smart-6155ddba-de64-4bdc-9c4e-13f8e6aeb105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479505315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2479505315
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3351996999
Short name T512
Test name
Test status
Simulation time 37490440 ps
CPU time 0.53 seconds
Started Dec 31 12:47:06 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 185144 kb
Host smart-84ea79c6-59df-4600-8e73-0b5c25dfc6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351996999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3351996999
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.817038937
Short name T496
Test name
Test status
Simulation time 42292536 ps
CPU time 0.55 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 185132 kb
Host smart-2f863959-a70a-43e0-8864-d41246f0c91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817038937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.817038937
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.4056965488
Short name T5
Test name
Test status
Simulation time 13561107 ps
CPU time 0.53 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 185184 kb
Host smart-9eaca976-dd71-464e-8948-02d8637c7b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056965488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4056965488
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2534066273
Short name T1277
Test name
Test status
Simulation time 12137747 ps
CPU time 0.56 seconds
Started Dec 31 12:47:12 PM PST 23
Finished Dec 31 12:47:15 PM PST 23
Peak memory 194356 kb
Host smart-78272680-11e9-4dce-8e31-0f64214750be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534066273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2534066273
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2433481655
Short name T418
Test name
Test status
Simulation time 43082723 ps
CPU time 0.56 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 185128 kb
Host smart-8a3a7866-4cfd-4fc8-be43-60d48b4c2048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433481655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2433481655
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1545676480
Short name T1255
Test name
Test status
Simulation time 31061243 ps
CPU time 0.58 seconds
Started Dec 31 12:46:49 PM PST 23
Finished Dec 31 12:46:51 PM PST 23
Peak memory 194440 kb
Host smart-29fe3b7a-43dc-472f-b6a5-bc3112151294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545676480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1545676480
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2776204048
Short name T70
Test name
Test status
Simulation time 27531498 ps
CPU time 0.65 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 12:46:23 PM PST 23
Peak memory 195512 kb
Host smart-bc9caf90-49b4-4f8a-a082-dde7859f79dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776204048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2776204048
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1742344916
Short name T1288
Test name
Test status
Simulation time 110517265 ps
CPU time 1.53 seconds
Started Dec 31 12:46:45 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 198004 kb
Host smart-084d64a0-8245-4926-aa21-c986f49f2a66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742344916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1742344916
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1181500386
Short name T37
Test name
Test status
Simulation time 43411288 ps
CPU time 0.58 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:44 PM PST 23
Peak memory 195440 kb
Host smart-b0a3f70b-2a00-46fe-ab2d-292429f54c56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181500386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1181500386
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3385810319
Short name T1283
Test name
Test status
Simulation time 52297840 ps
CPU time 0.79 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 199864 kb
Host smart-5e011f04-119c-4b64-bcdd-3183204c3a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385810319 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3385810319
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3216875886
Short name T80
Test name
Test status
Simulation time 16729027 ps
CPU time 0.58 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 195548 kb
Host smart-384c9cab-dcbd-4060-82a9-50a386376c9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216875886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3216875886
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3881265520
Short name T420
Test name
Test status
Simulation time 30034415 ps
CPU time 0.55 seconds
Started Dec 31 12:46:45 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 185128 kb
Host smart-89cfe0d9-7bb7-4eb4-8b9d-d6819df5a64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881265520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3881265520
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.501316957
Short name T1243
Test name
Test status
Simulation time 25079519 ps
CPU time 0.74 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 197768 kb
Host smart-998b7335-848d-45fe-8c34-5a0afe346a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501316957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.501316957
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2921195025
Short name T1285
Test name
Test status
Simulation time 69379443 ps
CPU time 1.75 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:46:25 PM PST 23
Peak memory 200028 kb
Host smart-4ef5fc4c-53c3-46fc-af80-01384894b25b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921195025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2921195025
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.11777597
Short name T1251
Test name
Test status
Simulation time 27781660 ps
CPU time 0.59 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 185068 kb
Host smart-f1c78826-1ed3-456b-af66-e0e5bf6b556f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.11777597
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3253088668
Short name T1294
Test name
Test status
Simulation time 48693891 ps
CPU time 0.56 seconds
Started Dec 31 12:46:45 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 185108 kb
Host smart-f69dfdfc-5fad-4c7c-b824-785ce6e9971d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253088668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3253088668
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4191785215
Short name T500
Test name
Test status
Simulation time 15153726 ps
CPU time 0.6 seconds
Started Dec 31 12:47:24 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 194456 kb
Host smart-52f5528c-23e9-46cb-90bc-a00c76c56e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191785215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4191785215
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.53692438
Short name T1253
Test name
Test status
Simulation time 18123247 ps
CPU time 0.54 seconds
Started Dec 31 12:47:07 PM PST 23
Finished Dec 31 12:47:09 PM PST 23
Peak memory 185176 kb
Host smart-f31d0935-0d87-4a37-a47c-d30d74485ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53692438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.53692438
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3780858030
Short name T2
Test name
Test status
Simulation time 15444865 ps
CPU time 0.54 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 185128 kb
Host smart-d21889ad-a62e-463d-9b56-d9bfc74d5f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780858030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3780858030
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1300257850
Short name T524
Test name
Test status
Simulation time 15820758 ps
CPU time 0.54 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 185164 kb
Host smart-6eb8a103-4a24-443e-82e6-0eaeee6e8a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300257850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1300257850
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1419020819
Short name T1286
Test name
Test status
Simulation time 11059620 ps
CPU time 0.57 seconds
Started Dec 31 12:46:56 PM PST 23
Finished Dec 31 12:46:57 PM PST 23
Peak memory 194300 kb
Host smart-852740e5-d239-44e9-b52d-d128a074954a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419020819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1419020819
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2197572018
Short name T1279
Test name
Test status
Simulation time 15248000 ps
CPU time 0.58 seconds
Started Dec 31 12:46:58 PM PST 23
Finished Dec 31 12:46:59 PM PST 23
Peak memory 185116 kb
Host smart-b3fa9d33-6ac9-42e0-9877-ab2ddd4b04fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197572018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2197572018
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1464966927
Short name T492
Test name
Test status
Simulation time 11090724 ps
CPU time 0.6 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 196892 kb
Host smart-a260c422-2053-40e7-aae8-9938c17395fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464966927 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1464966927
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3549132598
Short name T494
Test name
Test status
Simulation time 126391701 ps
CPU time 0.59 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 195412 kb
Host smart-75b22efa-2568-48a4-80af-2b0be1f8ebc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549132598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3549132598
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2251944509
Short name T1275
Test name
Test status
Simulation time 52606722 ps
CPU time 0.56 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 12:46:36 PM PST 23
Peak memory 185180 kb
Host smart-54d57e28-38f5-473b-ad38-b61b79fef919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251944509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2251944509
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2692633070
Short name T1269
Test name
Test status
Simulation time 17829706 ps
CPU time 0.7 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 196860 kb
Host smart-f0cd52c4-0f76-4648-8d30-4f6166fb1272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692633070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2692633070
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.929488249
Short name T1284
Test name
Test status
Simulation time 32336842 ps
CPU time 1.5 seconds
Started Dec 31 12:46:41 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 200024 kb
Host smart-a0ec7dc2-e0ae-43c4-a34b-2c861f1f895b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929488249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.929488249
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.120820653
Short name T53
Test name
Test status
Simulation time 49932491 ps
CPU time 0.92 seconds
Started Dec 31 12:46:14 PM PST 23
Finished Dec 31 12:46:16 PM PST 23
Peak memory 198928 kb
Host smart-d095be3c-66b8-48c6-8dc1-86760113d25e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120820653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.120820653
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1299958101
Short name T1259
Test name
Test status
Simulation time 68613962 ps
CPU time 0.73 seconds
Started Dec 31 12:46:59 PM PST 23
Finished Dec 31 12:47:02 PM PST 23
Peak memory 197920 kb
Host smart-e24905c6-12af-4626-8a6d-116e0737e574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299958101 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1299958101
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2654274130
Short name T508
Test name
Test status
Simulation time 20357768 ps
CPU time 0.57 seconds
Started Dec 31 12:46:51 PM PST 23
Finished Dec 31 12:46:52 PM PST 23
Peak memory 195468 kb
Host smart-e4af59c7-4c86-4a90-b746-b771540902fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654274130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2654274130
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.494725273
Short name T506
Test name
Test status
Simulation time 68301262 ps
CPU time 0.56 seconds
Started Dec 31 12:46:52 PM PST 23
Finished Dec 31 12:46:58 PM PST 23
Peak memory 185068 kb
Host smart-2b1c6d46-4bca-4454-ab2d-cc42e9552985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494725273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.494725273
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1432495809
Short name T507
Test name
Test status
Simulation time 152174972 ps
CPU time 0.71 seconds
Started Dec 31 12:46:52 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 195736 kb
Host smart-996444f5-d6fc-4ece-8611-9c3942a94621
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432495809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1432495809
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2358795162
Short name T75
Test name
Test status
Simulation time 95538836 ps
CPU time 1.1 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 199952 kb
Host smart-27eeab54-5468-4126-9eaa-3aba2ec61f56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358795162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2358795162
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4172504335
Short name T415
Test name
Test status
Simulation time 86161407 ps
CPU time 0.91 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 198884 kb
Host smart-a4dc6c68-3f85-4d38-870d-4454f8dd0abb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172504335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4172504335
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.904283425
Short name T1287
Test name
Test status
Simulation time 13683628 ps
CPU time 0.63 seconds
Started Dec 31 12:46:37 PM PST 23
Finished Dec 31 12:46:40 PM PST 23
Peak memory 196116 kb
Host smart-37d53e74-ee91-4362-878e-2759fd54e00b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904283425 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.904283425
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3075673885
Short name T1262
Test name
Test status
Simulation time 11354848 ps
CPU time 0.56 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 195500 kb
Host smart-4091c306-4263-41d3-b90f-77b011f28d51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075673885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3075673885
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1707333981
Short name T76
Test name
Test status
Simulation time 133152378 ps
CPU time 0.56 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 194292 kb
Host smart-7669944b-0192-405a-8650-4ec07dea13c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707333981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1707333981
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2636573087
Short name T1252
Test name
Test status
Simulation time 21732690 ps
CPU time 0.64 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 194600 kb
Host smart-156e1441-cacb-456d-8fff-0f95da091c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636573087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2636573087
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1807242453
Short name T44
Test name
Test status
Simulation time 265966500 ps
CPU time 2.2 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 200016 kb
Host smart-c47be113-a488-43f7-804d-819cfc0c360d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807242453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1807242453
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2536200120
Short name T511
Test name
Test status
Simulation time 244386167 ps
CPU time 1.32 seconds
Started Dec 31 12:46:46 PM PST 23
Finished Dec 31 12:46:49 PM PST 23
Peak memory 199188 kb
Host smart-2645eb95-9726-49f9-acf1-cd17bbe42545
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536200120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2536200120
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3849313076
Short name T1290
Test name
Test status
Simulation time 15487646 ps
CPU time 0.64 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 197680 kb
Host smart-e83cb141-f45e-4517-8213-b6ba1f0c04ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849313076 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3849313076
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2609420474
Short name T57
Test name
Test status
Simulation time 19975114 ps
CPU time 0.56 seconds
Started Dec 31 12:46:41 PM PST 23
Finished Dec 31 12:46:44 PM PST 23
Peak memory 195468 kb
Host smart-cd73ef1f-39c2-4540-8bf1-a422b2e7a08d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609420474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2609420474
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.932703830
Short name T498
Test name
Test status
Simulation time 12997952 ps
CPU time 0.58 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 194300 kb
Host smart-834657a5-a21d-408e-81c3-c7804519abfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932703830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.932703830
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3692057133
Short name T50
Test name
Test status
Simulation time 100857016 ps
CPU time 0.72 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 197156 kb
Host smart-bfe63309-6604-4b1c-afc1-02ba288f8a11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692057133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3692057133
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.58257516
Short name T1249
Test name
Test status
Simulation time 23768193 ps
CPU time 1.18 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:46:17 PM PST 23
Peak memory 200072 kb
Host smart-6c2b9bea-b877-49f7-9b6a-3fcef02774e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58257516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.58257516
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3231761794
Short name T41
Test name
Test status
Simulation time 147397314 ps
CPU time 1.25 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 199140 kb
Host smart-257f8d86-88bd-4f0b-b508-3ef095ec25e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231761794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3231761794
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2424747595
Short name T108
Test name
Test status
Simulation time 68898776 ps
CPU time 0.68 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 197800 kb
Host smart-6be8e3b4-e351-4385-b4dd-08f0326cfc17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424747595 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2424747595
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2279544497
Short name T71
Test name
Test status
Simulation time 18995282 ps
CPU time 0.57 seconds
Started Dec 31 12:46:32 PM PST 23
Finished Dec 31 12:46:37 PM PST 23
Peak memory 195448 kb
Host smart-4fa70da6-0334-4e3c-82f0-4c5d97e018df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279544497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2279544497
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3321036450
Short name T1293
Test name
Test status
Simulation time 23524316 ps
CPU time 0.58 seconds
Started Dec 31 12:46:52 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 185104 kb
Host smart-a2c1aaec-e803-4eae-ade6-2a097a4aa14a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321036450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3321036450
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1777915079
Short name T1296
Test name
Test status
Simulation time 110519155 ps
CPU time 0.76 seconds
Started Dec 31 12:47:21 PM PST 23
Finished Dec 31 12:47:23 PM PST 23
Peak memory 196928 kb
Host smart-fa016a84-9701-40bf-8c4d-c3eab3569052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777915079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1777915079
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.860632774
Short name T501
Test name
Test status
Simulation time 89692842 ps
CPU time 1.16 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 200040 kb
Host smart-a929124a-dc67-47c2-a04e-f63b2811e822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860632774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.860632774
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.951409994
Short name T414
Test name
Test status
Simulation time 654901796 ps
CPU time 1.51 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 199248 kb
Host smart-b6377450-1928-4430-8d75-e5720e943029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951409994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.951409994
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.975522598
Short name T1139
Test name
Test status
Simulation time 11429691 ps
CPU time 0.55 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:23 PM PST 23
Peak memory 194548 kb
Host smart-ebbc3521-e2fa-42cc-95a9-16ff18ddd72f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975522598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.975522598
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1314769697
Short name T1021
Test name
Test status
Simulation time 87386705482 ps
CPU time 142.7 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:14:40 PM PST 23
Peak memory 200240 kb
Host smart-4033568d-4b25-4285-849a-1c7ed603ee52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314769697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1314769697
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3317344978
Short name T276
Test name
Test status
Simulation time 56736650840 ps
CPU time 22.96 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:47 PM PST 23
Peak memory 198976 kb
Host smart-224684ca-d5ce-41a6-b85b-7a2c9b138faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317344978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3317344978
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.801317375
Short name T1166
Test name
Test status
Simulation time 176563779190 ps
CPU time 167.43 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:15:05 PM PST 23
Peak memory 200180 kb
Host smart-edf6d0a8-262c-49c4-8de0-a17251c76952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801317375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.801317375
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1369828826
Short name T1089
Test name
Test status
Simulation time 39580439272 ps
CPU time 231.27 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 200156 kb
Host smart-e74f4b6c-6f05-4c56-b3c8-f4d151e8423b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369828826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1369828826
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2972234928
Short name T1095
Test name
Test status
Simulation time 4507610764 ps
CPU time 1.81 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 198256 kb
Host smart-f22c2845-9975-4431-9850-8824ff34eaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972234928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2972234928
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.783953751
Short name T867
Test name
Test status
Simulation time 73470695136 ps
CPU time 33.87 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:50 PM PST 23
Peak memory 198240 kb
Host smart-9077b073-8250-44f8-97a8-8ab325c21241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783953751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.783953751
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1516893174
Short name T752
Test name
Test status
Simulation time 7208903078 ps
CPU time 93.05 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 200160 kb
Host smart-c927f4d6-7f74-48ec-8ea7-5c4c2afbfd64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516893174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1516893174
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.170627355
Short name T18
Test name
Test status
Simulation time 2859323264 ps
CPU time 5.51 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 198652 kb
Host smart-03442ee0-ed60-448a-b006-7127de3df73b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170627355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.170627355
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.4037713559
Short name T1097
Test name
Test status
Simulation time 155219242306 ps
CPU time 226.42 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200176 kb
Host smart-a74556a4-c0f0-4ccf-82ce-2a1969497baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037713559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.4037713559
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.100645183
Short name T832
Test name
Test status
Simulation time 1282383713 ps
CPU time 2.54 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:19 PM PST 23
Peak memory 195612 kb
Host smart-ca88a905-6f13-4428-aa2b-493fcf1b6fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100645183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.100645183
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2660082039
Short name T1221
Test name
Test status
Simulation time 452067033 ps
CPU time 2.22 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:29 PM PST 23
Peak memory 199132 kb
Host smart-9a0f5641-b618-48e9-b288-083830c853fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660082039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2660082039
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3326428566
Short name T204
Test name
Test status
Simulation time 102806721850 ps
CPU time 201.35 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:15:49 PM PST 23
Peak memory 216548 kb
Host smart-b7508ea6-2cdf-4348-8927-73945bf0f106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326428566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3326428566
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2743323271
Short name T461
Test name
Test status
Simulation time 148332764500 ps
CPU time 303.53 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:17:29 PM PST 23
Peak memory 216716 kb
Host smart-df71b004-1175-4a00-9216-49826f56ea12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743323271 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2743323271
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1471013031
Short name T778
Test name
Test status
Simulation time 1328387594 ps
CPU time 3.1 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 199432 kb
Host smart-b9701ca8-2bb5-425e-ac8d-dcbc916aded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471013031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1471013031
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1571855652
Short name T1109
Test name
Test status
Simulation time 45493353961 ps
CPU time 73.45 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:13:34 PM PST 23
Peak memory 200192 kb
Host smart-72c01528-b525-44ee-96b4-8e2efb080124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571855652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1571855652
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1808266176
Short name T1087
Test name
Test status
Simulation time 52281280 ps
CPU time 0.54 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 195580 kb
Host smart-f35c94d7-0d6d-4ee9-b4c8-244d763aa3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808266176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1808266176
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3383980153
Short name T23
Test name
Test status
Simulation time 114741881631 ps
CPU time 96.57 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:14:00 PM PST 23
Peak memory 200236 kb
Host smart-5428c029-36e2-4916-834b-1773c5c213a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383980153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3383980153
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_intr.1644083696
Short name T479
Test name
Test status
Simulation time 2183466519471 ps
CPU time 3004.98 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 02:02:32 PM PST 23
Peak memory 200184 kb
Host smart-3997078f-a864-4f95-9671-ccd7d2f33b4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644083696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1644083696
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2105286626
Short name T1032
Test name
Test status
Simulation time 125777065488 ps
CPU time 723.11 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:24:39 PM PST 23
Peak memory 200208 kb
Host smart-f8a44fee-6062-494f-9060-4a5b95011f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105286626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2105286626
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.230749794
Short name T528
Test name
Test status
Simulation time 5529015558 ps
CPU time 5.13 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 200008 kb
Host smart-e84991e0-bee1-4691-b34f-4f8bdf90ef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230749794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.230749794
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1556025195
Short name T720
Test name
Test status
Simulation time 16779851692 ps
CPU time 32.52 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:58 PM PST 23
Peak memory 198520 kb
Host smart-028422c2-6d3d-492a-9dae-47af396eec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556025195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1556025195
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.627578615
Short name T471
Test name
Test status
Simulation time 13908122621 ps
CPU time 195.71 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200168 kb
Host smart-b1220fef-b18e-494d-b5cd-103b04c37349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627578615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.627578615
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1445401232
Short name T1168
Test name
Test status
Simulation time 1606596010 ps
CPU time 1.8 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 198308 kb
Host smart-ee9ba3be-b964-459a-b265-ee06dfa48d37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445401232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1445401232
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4103230246
Short name T252
Test name
Test status
Simulation time 39272593515 ps
CPU time 39.95 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:13:12 PM PST 23
Peak memory 200244 kb
Host smart-88e4dd1a-731a-48e8-9c1e-a341f806476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103230246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4103230246
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.657056557
Short name T1107
Test name
Test status
Simulation time 3820715002 ps
CPU time 3.61 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 195964 kb
Host smart-8d60b46f-8df4-48ea-acae-3b41a11d8ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657056557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.657056557
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3106571505
Short name T98
Test name
Test status
Simulation time 74782287 ps
CPU time 0.84 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 217736 kb
Host smart-d3707e85-20cb-4d95-9f75-0abd612b26ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106571505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3106571505
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.978346657
Short name T918
Test name
Test status
Simulation time 292011103 ps
CPU time 1.43 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 198568 kb
Host smart-4ff0205e-ea7c-483c-b290-ee90a1172690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978346657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.978346657
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3392932986
Short name T314
Test name
Test status
Simulation time 365481487741 ps
CPU time 979.72 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:28:44 PM PST 23
Peak memory 200184 kb
Host smart-a7b152ba-8132-4910-93a7-f92401e20ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392932986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3392932986
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.4276890787
Short name T106
Test name
Test status
Simulation time 329584404351 ps
CPU time 492.92 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:20:37 PM PST 23
Peak memory 216940 kb
Host smart-72f24cbd-10de-47d9-ad9b-409b85c29868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276890787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.4276890787
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2458542377
Short name T1125
Test name
Test status
Simulation time 1924007224 ps
CPU time 2.89 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:32 PM PST 23
Peak memory 198796 kb
Host smart-ff66226f-f2c0-45ab-b848-ae53f9d404d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458542377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2458542377
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.3455380752
Short name T644
Test name
Test status
Simulation time 7066702152 ps
CPU time 3.51 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 197076 kb
Host smart-286bcc6c-920a-46c0-af45-d084fc0ab01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455380752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3455380752
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1063662484
Short name T983
Test name
Test status
Simulation time 19454398 ps
CPU time 0.55 seconds
Started Dec 31 01:12:35 PM PST 23
Finished Dec 31 01:12:38 PM PST 23
Peak memory 195624 kb
Host smart-519493a1-e73e-48bc-8e4d-d00708f5de23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063662484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1063662484
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2808151930
Short name T1208
Test name
Test status
Simulation time 125223736724 ps
CPU time 154.84 seconds
Started Dec 31 01:12:57 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200060 kb
Host smart-24edc8e3-5c73-4fd1-9b7e-4e5371fd5ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808151930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2808151930
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.40431044
Short name T432
Test name
Test status
Simulation time 553424200330 ps
CPU time 962 seconds
Started Dec 31 01:12:33 PM PST 23
Finished Dec 31 01:28:39 PM PST 23
Peak memory 200192 kb
Host smart-4f2a6a0c-34a3-451c-8b20-bbf01c7ba8b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40431044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.40431044
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3321534363
Short name T882
Test name
Test status
Simulation time 93157418408 ps
CPU time 672.59 seconds
Started Dec 31 01:13:00 PM PST 23
Finished Dec 31 01:24:26 PM PST 23
Peak memory 200184 kb
Host smart-9f7356e3-aea4-4455-8205-2c5823c52aac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3321534363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3321534363
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2189302227
Short name T560
Test name
Test status
Simulation time 5104866580 ps
CPU time 10.98 seconds
Started Dec 31 01:13:06 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 199148 kb
Host smart-33a919f2-acc4-45f9-88b1-af405a8e42fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189302227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2189302227
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.483669622
Short name T427
Test name
Test status
Simulation time 75407218940 ps
CPU time 121.5 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:15:12 PM PST 23
Peak memory 199524 kb
Host smart-124fe723-0b49-4b6e-b198-933019390359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483669622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.483669622
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1681692976
Short name T549
Test name
Test status
Simulation time 15221418319 ps
CPU time 849.51 seconds
Started Dec 31 01:12:55 PM PST 23
Finished Dec 31 01:27:15 PM PST 23
Peak memory 200176 kb
Host smart-cf307e05-06e6-42c4-a796-f196b5d29c52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681692976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1681692976
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3891826662
Short name T959
Test name
Test status
Simulation time 2710717821 ps
CPU time 7.75 seconds
Started Dec 31 01:12:45 PM PST 23
Finished Dec 31 01:12:54 PM PST 23
Peak memory 198264 kb
Host smart-7428fb58-f7cc-47b4-a8b7-8f380c7272ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3891826662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3891826662
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2763330944
Short name T848
Test name
Test status
Simulation time 91813703926 ps
CPU time 127.08 seconds
Started Dec 31 01:12:43 PM PST 23
Finished Dec 31 01:14:51 PM PST 23
Peak memory 199720 kb
Host smart-d1592ec9-83f6-43a9-992f-2a551c8e2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763330944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2763330944
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3290274898
Short name T583
Test name
Test status
Simulation time 2722582077 ps
CPU time 4.69 seconds
Started Dec 31 01:12:34 PM PST 23
Finished Dec 31 01:12:42 PM PST 23
Peak memory 195688 kb
Host smart-97614feb-dbd8-404e-b237-ea056dee8bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290274898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3290274898
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2696857369
Short name T1242
Test name
Test status
Simulation time 719889731 ps
CPU time 1.42 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:13:08 PM PST 23
Peak memory 198568 kb
Host smart-ecefb7e5-be64-499c-8ae9-a8515e74ca3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696857369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2696857369
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.756495390
Short name T965
Test name
Test status
Simulation time 484328396917 ps
CPU time 406.08 seconds
Started Dec 31 01:13:00 PM PST 23
Finished Dec 31 01:20:00 PM PST 23
Peak memory 200188 kb
Host smart-65ece115-4e34-4cd2-8ba5-3c3409f45e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756495390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.756495390
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.990924118
Short name T209
Test name
Test status
Simulation time 291116543756 ps
CPU time 1167.85 seconds
Started Dec 31 01:12:55 PM PST 23
Finished Dec 31 01:32:34 PM PST 23
Peak memory 227836 kb
Host smart-4dfd538e-6753-4fb4-935a-a7b8dacb73da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990924118 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.990924118
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.282482351
Short name T1155
Test name
Test status
Simulation time 848203924 ps
CPU time 2.78 seconds
Started Dec 31 01:13:03 PM PST 23
Finished Dec 31 01:13:18 PM PST 23
Peak memory 198268 kb
Host smart-9356e41c-40aa-4cc2-a9c4-d87c163e2a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282482351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.282482351
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1142389946
Short name T191
Test name
Test status
Simulation time 59714312260 ps
CPU time 13.12 seconds
Started Dec 31 01:12:52 PM PST 23
Finished Dec 31 01:13:09 PM PST 23
Peak memory 200160 kb
Host smart-10cd18e1-e476-4291-97be-18ee513900c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142389946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1142389946
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3177880603
Short name T332
Test name
Test status
Simulation time 49613366851 ps
CPU time 79.81 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:16:30 PM PST 23
Peak memory 200320 kb
Host smart-ca1e94b6-d321-4710-82e3-6c3df01bce4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177880603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3177880603
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3389836063
Short name T357
Test name
Test status
Simulation time 82239401436 ps
CPU time 67.41 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:16:14 PM PST 23
Peak memory 200172 kb
Host smart-7cc8b41b-1160-452d-965c-54985d4f37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389836063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3389836063
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2649486633
Short name T201
Test name
Test status
Simulation time 32584538851 ps
CPU time 11.99 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:15:40 PM PST 23
Peak memory 198068 kb
Host smart-8bf5f2d3-df83-44c2-9098-5a13d1c15b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649486633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2649486633
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1294608568
Short name T273
Test name
Test status
Simulation time 38338893310 ps
CPU time 17.23 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:18 PM PST 23
Peak memory 200172 kb
Host smart-1f0c3c68-453d-4cd8-b633-b7ea09bf5972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294608568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1294608568
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3181986164
Short name T255
Test name
Test status
Simulation time 161142077627 ps
CPU time 37.26 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:15:43 PM PST 23
Peak memory 200164 kb
Host smart-341c8309-7024-4f89-930c-889bebf59354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181986164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3181986164
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1866177561
Short name T890
Test name
Test status
Simulation time 18601286326 ps
CPU time 39.19 seconds
Started Dec 31 01:15:07 PM PST 23
Finished Dec 31 01:15:50 PM PST 23
Peak memory 200100 kb
Host smart-990661eb-a4a6-4072-a36f-f570d4f61404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866177561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1866177561
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.974675006
Short name T236
Test name
Test status
Simulation time 14139708695 ps
CPU time 25.47 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 200228 kb
Host smart-16f75d97-6161-4d76-86a1-ed264ac9d5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974675006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.974675006
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.323354649
Short name T690
Test name
Test status
Simulation time 26951254 ps
CPU time 0.59 seconds
Started Dec 31 01:13:05 PM PST 23
Finished Dec 31 01:13:17 PM PST 23
Peak memory 195656 kb
Host smart-8c9880c6-1fe7-4723-b819-b0df5d492a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323354649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.323354649
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3373472737
Short name T661
Test name
Test status
Simulation time 77735434314 ps
CPU time 57.27 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:14:07 PM PST 23
Peak memory 200172 kb
Host smart-129fac7e-5990-42bb-88a4-3bd90b7c2093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373472737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3373472737
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3677858397
Short name T436
Test name
Test status
Simulation time 348038615926 ps
CPU time 553.7 seconds
Started Dec 31 01:12:44 PM PST 23
Finished Dec 31 01:21:59 PM PST 23
Peak memory 200168 kb
Host smart-2b20d372-4285-4f81-ab93-e3ad18392340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677858397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3677858397
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.520625834
Short name T351
Test name
Test status
Simulation time 47939650865 ps
CPU time 73.12 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:14:35 PM PST 23
Peak memory 200212 kb
Host smart-f70b2871-1618-4065-b770-8a9a34925e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520625834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.520625834
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3452952305
Short name T909
Test name
Test status
Simulation time 139497904945 ps
CPU time 25.41 seconds
Started Dec 31 01:13:00 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 198368 kb
Host smart-59912720-3927-4214-b16a-f814ce63801a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452952305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3452952305
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3645238213
Short name T682
Test name
Test status
Simulation time 87158264313 ps
CPU time 342.96 seconds
Started Dec 31 01:13:01 PM PST 23
Finished Dec 31 01:18:55 PM PST 23
Peak memory 200176 kb
Host smart-316985f5-5ba1-4169-b2c7-1c0fc758e741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645238213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3645238213
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1383001559
Short name T535
Test name
Test status
Simulation time 1484188056 ps
CPU time 3.18 seconds
Started Dec 31 01:12:59 PM PST 23
Finished Dec 31 01:13:13 PM PST 23
Peak memory 196904 kb
Host smart-8eea0663-730a-4374-965d-d3919e22bf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383001559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1383001559
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.4243515833
Short name T1130
Test name
Test status
Simulation time 132102699685 ps
CPU time 60.61 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:14:08 PM PST 23
Peak memory 200428 kb
Host smart-ca2d355f-e43c-4a38-bb2e-87339c205712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243515833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.4243515833
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3938961010
Short name T773
Test name
Test status
Simulation time 11257912406 ps
CPU time 548.53 seconds
Started Dec 31 01:13:07 PM PST 23
Finished Dec 31 01:22:28 PM PST 23
Peak memory 200204 kb
Host smart-4df9d5d2-36ef-4384-97b1-2eb3e6203d95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938961010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3938961010
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3758900849
Short name T1193
Test name
Test status
Simulation time 2043856941 ps
CPU time 21.3 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:13:27 PM PST 23
Peak memory 198268 kb
Host smart-98ff9b24-c600-45b6-a824-ba5db17172bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758900849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3758900849
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2085281410
Short name T735
Test name
Test status
Simulation time 41844444064 ps
CPU time 30.2 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:14:06 PM PST 23
Peak memory 195624 kb
Host smart-46e55b2b-5166-4ad0-8b7d-fd5398201757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085281410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2085281410
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2551546024
Short name T1177
Test name
Test status
Simulation time 5756074913 ps
CPU time 10.73 seconds
Started Dec 31 01:13:06 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 199612 kb
Host smart-d3baa63b-7204-43c2-abff-effe6c574308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551546024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2551546024
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.967262000
Short name T1219
Test name
Test status
Simulation time 228903504771 ps
CPU time 1202.8 seconds
Started Dec 31 01:13:05 PM PST 23
Finished Dec 31 01:33:19 PM PST 23
Peak memory 200188 kb
Host smart-376e4602-4207-4f31-bf18-2acc06ee952e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967262000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.967262000
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1148446379
Short name T968
Test name
Test status
Simulation time 38939988998 ps
CPU time 765.57 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:25:52 PM PST 23
Peak memory 216004 kb
Host smart-f452a687-d78b-4869-8cd3-3727bcce53d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148446379 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1148446379
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1752599882
Short name T1150
Test name
Test status
Simulation time 5853403762 ps
CPU time 17.59 seconds
Started Dec 31 01:12:55 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 199616 kb
Host smart-2cab284d-b5e8-4cb8-88ed-47510aae2e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752599882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1752599882
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1000009138
Short name T966
Test name
Test status
Simulation time 57513550136 ps
CPU time 57.38 seconds
Started Dec 31 01:12:46 PM PST 23
Finished Dec 31 01:13:44 PM PST 23
Peak memory 200052 kb
Host smart-8045b4af-a5cc-4514-91cf-4cfaaaf667b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000009138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1000009138
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3135465221
Short name T960
Test name
Test status
Simulation time 156931319340 ps
CPU time 17.74 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:20 PM PST 23
Peak memory 200260 kb
Host smart-145fe218-6685-44da-b9c2-94b0e890c74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135465221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3135465221
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.344903650
Short name T1012
Test name
Test status
Simulation time 37893193254 ps
CPU time 29.77 seconds
Started Dec 31 01:15:34 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200260 kb
Host smart-578efbf6-01e5-49f8-93f3-23eca9f83635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344903650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.344903650
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2504874532
Short name T1036
Test name
Test status
Simulation time 70734816397 ps
CPU time 192.62 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:18:23 PM PST 23
Peak memory 200236 kb
Host smart-1560748b-4e8d-4dca-a69b-72b1273982f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504874532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2504874532
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3288310320
Short name T996
Test name
Test status
Simulation time 159284155571 ps
CPU time 173.72 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:18:05 PM PST 23
Peak memory 200200 kb
Host smart-f072859a-8ef2-4ce7-9473-50792e7e05ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288310320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3288310320
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.467111125
Short name T992
Test name
Test status
Simulation time 157506740377 ps
CPU time 23.23 seconds
Started Dec 31 01:15:34 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200216 kb
Host smart-b4508d76-64eb-4564-8edc-6dbbfc604646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467111125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.467111125
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2908932632
Short name T1038
Test name
Test status
Simulation time 83648301 ps
CPU time 0.54 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 195632 kb
Host smart-6b64d0e1-906b-4962-bc5d-176375e7a0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908932632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2908932632
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3123781218
Short name T1015
Test name
Test status
Simulation time 22497749475 ps
CPU time 36.66 seconds
Started Dec 31 01:12:58 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 200124 kb
Host smart-9cacc07d-b2e2-487d-89b7-e14700e49751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123781218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3123781218
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_intr.3141916230
Short name T664
Test name
Test status
Simulation time 400519811999 ps
CPU time 328.91 seconds
Started Dec 31 01:12:59 PM PST 23
Finished Dec 31 01:18:39 PM PST 23
Peak memory 200188 kb
Host smart-77fa44e4-aebb-4cf1-a93d-ad3327330946
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141916230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3141916230
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1965633826
Short name T1147
Test name
Test status
Simulation time 118086137745 ps
CPU time 296.58 seconds
Started Dec 31 01:13:05 PM PST 23
Finished Dec 31 01:18:12 PM PST 23
Peak memory 200120 kb
Host smart-4a4a5baf-6055-4a11-a559-41c760d19c01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965633826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1965633826
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2942227477
Short name T1018
Test name
Test status
Simulation time 1763913732 ps
CPU time 3.89 seconds
Started Dec 31 01:12:58 PM PST 23
Finished Dec 31 01:13:14 PM PST 23
Peak memory 197008 kb
Host smart-d259e9cf-19c5-479a-811b-d8347e65f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942227477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2942227477
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3491533466
Short name T145
Test name
Test status
Simulation time 53836318840 ps
CPU time 23.51 seconds
Started Dec 31 01:13:03 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 198680 kb
Host smart-24f2a967-989a-4c9a-b09d-d53b14f8390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491533466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3491533466
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3970749623
Short name T621
Test name
Test status
Simulation time 14017465431 ps
CPU time 819.81 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:27:09 PM PST 23
Peak memory 200260 kb
Host smart-1762edaa-36e7-46b7-b078-502d4fd27a7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970749623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3970749623
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3277364885
Short name T618
Test name
Test status
Simulation time 1912693060 ps
CPU time 2.55 seconds
Started Dec 31 01:13:01 PM PST 23
Finished Dec 31 01:13:17 PM PST 23
Peak memory 198212 kb
Host smart-7641964b-7dbe-4f65-b9ed-53f848893b73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277364885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3277364885
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4104263057
Short name T355
Test name
Test status
Simulation time 20418391871 ps
CPU time 17.85 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:13:27 PM PST 23
Peak memory 199160 kb
Host smart-dacac9c0-d9af-466e-be45-d4f0c6ab000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104263057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4104263057
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1138924738
Short name T572
Test name
Test status
Simulation time 1597598196 ps
CPU time 3.08 seconds
Started Dec 31 01:12:56 PM PST 23
Finished Dec 31 01:13:11 PM PST 23
Peak memory 195596 kb
Host smart-90dde5e3-0dff-4a68-b965-a63ad35d587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138924738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1138924738
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2298731336
Short name T760
Test name
Test status
Simulation time 5423099261 ps
CPU time 31.49 seconds
Started Dec 31 01:12:57 PM PST 23
Finished Dec 31 01:13:42 PM PST 23
Peak memory 199036 kb
Host smart-c21f2232-e922-4596-838b-674fe049303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298731336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2298731336
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.4073159635
Short name T819
Test name
Test status
Simulation time 145574550879 ps
CPU time 1025.49 seconds
Started Dec 31 01:13:02 PM PST 23
Finished Dec 31 01:30:20 PM PST 23
Peak memory 208736 kb
Host smart-cb5dee36-2887-4c11-86d1-26dc071a7a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073159635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4073159635
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.500637121
Short name T292
Test name
Test status
Simulation time 738288100932 ps
CPU time 886.97 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:28:23 PM PST 23
Peak memory 225052 kb
Host smart-39fb774a-18bd-4ecc-8f75-6c8f813d6eb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500637121 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.500637121
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3727955327
Short name T1061
Test name
Test status
Simulation time 7435111573 ps
CPU time 13.5 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:45 PM PST 23
Peak memory 199808 kb
Host smart-b908982f-1a99-4186-8c0d-b3db327775f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727955327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3727955327
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2706255928
Short name T742
Test name
Test status
Simulation time 35294226368 ps
CPU time 17.34 seconds
Started Dec 31 01:12:58 PM PST 23
Finished Dec 31 01:13:27 PM PST 23
Peak memory 200204 kb
Host smart-bdfd7e4d-30c3-43fe-a239-955863833baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706255928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2706255928
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3613859368
Short name T647
Test name
Test status
Simulation time 16802377772 ps
CPU time 13.63 seconds
Started Dec 31 01:15:31 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200120 kb
Host smart-133dbd25-9b06-4953-ba5a-1ee3b9920513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613859368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3613859368
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3005402287
Short name T615
Test name
Test status
Simulation time 50910079958 ps
CPU time 73.02 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:16:22 PM PST 23
Peak memory 200136 kb
Host smart-02d6ca55-3856-426f-98cb-91ba174daa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005402287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3005402287
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2967950141
Short name T214
Test name
Test status
Simulation time 147978745624 ps
CPU time 59.47 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:16:10 PM PST 23
Peak memory 200160 kb
Host smart-34957088-4807-48c0-a1dd-a5aeea900be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967950141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2967950141
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2394749248
Short name T766
Test name
Test status
Simulation time 168443677722 ps
CPU time 84.46 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:17:02 PM PST 23
Peak memory 200236 kb
Host smart-5122affd-1b6b-4c2e-aaea-91ce87d166b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394749248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2394749248
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3175767806
Short name T653
Test name
Test status
Simulation time 47954990005 ps
CPU time 33.52 seconds
Started Dec 31 01:15:41 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 199932 kb
Host smart-6eef9442-e6bb-4a1c-a79e-9b11b1d58452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175767806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3175767806
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.908401576
Short name T712
Test name
Test status
Simulation time 270796643435 ps
CPU time 181.92 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:18:40 PM PST 23
Peak memory 199824 kb
Host smart-45a389b8-faae-4118-81bf-bc41676d2ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908401576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.908401576
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1102511842
Short name T354
Test name
Test status
Simulation time 169715922130 ps
CPU time 50.35 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:16:29 PM PST 23
Peak memory 200272 kb
Host smart-a6f88a57-7f71-45a9-becd-c9c06280fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102511842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1102511842
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2605174415
Short name T1211
Test name
Test status
Simulation time 231679647550 ps
CPU time 124.26 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:17:42 PM PST 23
Peak memory 200200 kb
Host smart-4d058ba8-8c1f-4f3c-bcbb-6ac0100a427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605174415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2605174415
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2449573122
Short name T869
Test name
Test status
Simulation time 29032016 ps
CPU time 0.55 seconds
Started Dec 31 01:13:03 PM PST 23
Finished Dec 31 01:13:16 PM PST 23
Peak memory 195620 kb
Host smart-63982f76-1a28-471f-8283-7d5face8074f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449573122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2449573122
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2207417020
Short name T571
Test name
Test status
Simulation time 32485824681 ps
CPU time 44.09 seconds
Started Dec 31 01:12:59 PM PST 23
Finished Dec 31 01:13:54 PM PST 23
Peak memory 198984 kb
Host smart-84972117-4f4f-46d6-a18f-7d28db2f3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207417020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2207417020
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1656849225
Short name T389
Test name
Test status
Simulation time 95928839352 ps
CPU time 38.33 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:14:06 PM PST 23
Peak memory 199564 kb
Host smart-72d3cb82-7f5f-4db9-b4d8-52afaf6e9575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656849225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1656849225
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1009764190
Short name T203
Test name
Test status
Simulation time 87334482607 ps
CPU time 61.65 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:14:25 PM PST 23
Peak memory 200196 kb
Host smart-99aafaca-b6e7-4e04-aab2-4e7fe8e294c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009764190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1009764190
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.240414000
Short name T1149
Test name
Test status
Simulation time 187747662692 ps
CPU time 307.21 seconds
Started Dec 31 01:13:02 PM PST 23
Finished Dec 31 01:18:22 PM PST 23
Peak memory 199628 kb
Host smart-139989dc-9110-4ba1-82ed-e030a0a429e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240414000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.240414000
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1326988874
Short name T736
Test name
Test status
Simulation time 79130797959 ps
CPU time 379.48 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:19:42 PM PST 23
Peak memory 200236 kb
Host smart-d18abfaf-3362-4ed8-8d53-1a6f16d7068b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326988874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1326988874
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2341160314
Short name T526
Test name
Test status
Simulation time 5555859365 ps
CPU time 11.19 seconds
Started Dec 31 01:13:03 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 199396 kb
Host smart-917df552-55cb-4933-ac05-9869ac2eab74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341160314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2341160314
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2571495373
Short name T741
Test name
Test status
Simulation time 152261923529 ps
CPU time 96.89 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:14:59 PM PST 23
Peak memory 200468 kb
Host smart-55ef4e0a-b7f9-4f54-96c7-642aaf46a5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571495373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2571495373
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1662376123
Short name T813
Test name
Test status
Simulation time 5450958959 ps
CPU time 276.24 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:18:00 PM PST 23
Peak memory 200156 kb
Host smart-c8ad63d5-1e3d-45ed-bc09-2aeaf5713427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662376123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1662376123
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3653208702
Short name T821
Test name
Test status
Simulation time 3452828166 ps
CPU time 6.36 seconds
Started Dec 31 01:13:01 PM PST 23
Finished Dec 31 01:13:20 PM PST 23
Peak memory 198432 kb
Host smart-a600eed1-1c3c-4691-af4a-209d97f67fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3653208702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3653208702
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.250329349
Short name T473
Test name
Test status
Simulation time 23441868518 ps
CPU time 10.69 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 195808 kb
Host smart-a058771b-85b6-4df7-b821-f9791be5c3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250329349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.250329349
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1903709701
Short name T1135
Test name
Test status
Simulation time 647256084 ps
CPU time 2.59 seconds
Started Dec 31 01:13:06 PM PST 23
Finished Dec 31 01:13:22 PM PST 23
Peak memory 198668 kb
Host smart-9cd9aa8f-c946-4226-ab16-5c5db949302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903709701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1903709701
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3072575155
Short name T770
Test name
Test status
Simulation time 970704445 ps
CPU time 3.32 seconds
Started Dec 31 01:13:04 PM PST 23
Finished Dec 31 01:13:19 PM PST 23
Peak memory 198676 kb
Host smart-5fe53c61-f4f7-43db-b478-bd1f8bb40d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072575155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3072575155
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2459903115
Short name T794
Test name
Test status
Simulation time 120681485524 ps
CPU time 19.14 seconds
Started Dec 31 01:13:07 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 200216 kb
Host smart-5e6d98be-f1a5-4705-96f9-fb8cc736767f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459903115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2459903115
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3336109080
Short name T1233
Test name
Test status
Simulation time 36387338290 ps
CPU time 38.55 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 199480 kb
Host smart-fab2aa3c-c1bc-4f5f-86be-51d17dbe871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336109080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3336109080
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.764270651
Short name T194
Test name
Test status
Simulation time 37638592374 ps
CPU time 36.78 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200180 kb
Host smart-e5b262fd-c17b-4f72-8453-f808551cfbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764270651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.764270651
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1473203676
Short name T282
Test name
Test status
Simulation time 87569419168 ps
CPU time 129.55 seconds
Started Dec 31 01:15:30 PM PST 23
Finished Dec 31 01:17:41 PM PST 23
Peak memory 200204 kb
Host smart-7fb43edd-02d4-49d9-9a51-cae8c8262334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473203676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1473203676
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.913968669
Short name T164
Test name
Test status
Simulation time 39264007916 ps
CPU time 15.68 seconds
Started Dec 31 01:15:14 PM PST 23
Finished Dec 31 01:15:31 PM PST 23
Peak memory 199924 kb
Host smart-bdc9d39f-a007-48f9-934b-2bbbae50f0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913968669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.913968669
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.608000913
Short name T562
Test name
Test status
Simulation time 20655803584 ps
CPU time 35.94 seconds
Started Dec 31 01:15:08 PM PST 23
Finished Dec 31 01:15:48 PM PST 23
Peak memory 200212 kb
Host smart-9f1bf103-b216-4158-82bd-f6f81cbe1292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608000913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.608000913
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1770344763
Short name T889
Test name
Test status
Simulation time 45950191090 ps
CPU time 38.62 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 199904 kb
Host smart-cc0dad61-d309-4180-a069-5c1ea1765325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770344763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1770344763
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1307566571
Short name T543
Test name
Test status
Simulation time 39775052906 ps
CPU time 16.19 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:15:43 PM PST 23
Peak memory 200008 kb
Host smart-ab995238-869f-4153-bd4f-ca8121ed1d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307566571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1307566571
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.358866827
Short name T912
Test name
Test status
Simulation time 79628029 ps
CPU time 0.56 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:33 PM PST 23
Peak memory 195672 kb
Host smart-84100587-45ba-4472-81c2-6350fd6df492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358866827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.358866827
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.478493721
Short name T115
Test name
Test status
Simulation time 287212363300 ps
CPU time 431.44 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:20:36 PM PST 23
Peak memory 200164 kb
Host smart-f43feb7d-7686-428d-b7ee-4ce0edc36df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478493721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.478493721
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1791724312
Short name T969
Test name
Test status
Simulation time 81377948259 ps
CPU time 150.91 seconds
Started Dec 31 01:13:08 PM PST 23
Finished Dec 31 01:15:51 PM PST 23
Peak memory 200228 kb
Host smart-f83a44a5-18ff-483b-89f8-41b6cd58422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791724312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1791724312
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1113914773
Short name T347
Test name
Test status
Simulation time 25647073229 ps
CPU time 11.26 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:45 PM PST 23
Peak memory 199696 kb
Host smart-d182f2f5-726c-4f3c-91ff-6f8f7cdc22c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113914773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1113914773
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3028293021
Short name T757
Test name
Test status
Simulation time 166508598366 ps
CPU time 256.49 seconds
Started Dec 31 01:12:59 PM PST 23
Finished Dec 31 01:17:27 PM PST 23
Peak memory 200208 kb
Host smart-ec8e4177-1d60-4617-9ae1-a3dd82b46361
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028293021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3028293021
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2879735852
Short name T632
Test name
Test status
Simulation time 107823146455 ps
CPU time 788.58 seconds
Started Dec 31 01:13:01 PM PST 23
Finished Dec 31 01:26:24 PM PST 23
Peak memory 200160 kb
Host smart-f1a8210e-a936-4b02-b83f-c58ff6d47e42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879735852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2879735852
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2760693584
Short name T1206
Test name
Test status
Simulation time 4634464764 ps
CPU time 6.71 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 199072 kb
Host smart-a5bfe8d5-0b62-4264-88d0-d6258bb7cef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760693584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2760693584
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.538979559
Short name T582
Test name
Test status
Simulation time 40208950528 ps
CPU time 80.83 seconds
Started Dec 31 01:13:00 PM PST 23
Finished Dec 31 01:14:31 PM PST 23
Peak memory 198564 kb
Host smart-96a633b5-e05c-42f9-983f-29ffc8bb6c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538979559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.538979559
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1167976775
Short name T672
Test name
Test status
Simulation time 24160899669 ps
CPU time 555.55 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:22:46 PM PST 23
Peak memory 200180 kb
Host smart-07c88517-49f1-4848-9e3c-315b45737d57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167976775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1167976775
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1579258392
Short name T1073
Test name
Test status
Simulation time 1901298252 ps
CPU time 6.41 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:35 PM PST 23
Peak memory 198444 kb
Host smart-da6eca0e-3d8a-4a1f-bf8a-a7222aeaf253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579258392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1579258392
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2079934249
Short name T1079
Test name
Test status
Simulation time 33238164154 ps
CPU time 25.41 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 198304 kb
Host smart-68074e82-d244-4a58-a2e1-eeebaff4ef4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079934249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2079934249
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3268583118
Short name T705
Test name
Test status
Simulation time 44906422475 ps
CPU time 70.62 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:14:38 PM PST 23
Peak memory 195700 kb
Host smart-de33b228-44f8-4ecc-8bcf-bd258454fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268583118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3268583118
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.414578613
Short name T1199
Test name
Test status
Simulation time 670729304 ps
CPU time 3.08 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 198656 kb
Host smart-6c7fe720-f884-4663-ab1e-4a620c75c71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414578613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.414578613
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.737169465
Short name T1065
Test name
Test status
Simulation time 103978590843 ps
CPU time 43.9 seconds
Started Dec 31 01:13:05 PM PST 23
Finished Dec 31 01:14:00 PM PST 23
Peak memory 200156 kb
Host smart-7063cc66-3b68-4127-a27c-dffe9a67d362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737169465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.737169465
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3562953423
Short name T1027
Test name
Test status
Simulation time 73206081399 ps
CPU time 391.68 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:19:55 PM PST 23
Peak memory 216740 kb
Host smart-4830bf04-2079-47dd-9140-fb9b4aa27a14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562953423 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3562953423
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3448186677
Short name T591
Test name
Test status
Simulation time 575377071 ps
CPU time 1.87 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 198364 kb
Host smart-534a95e4-ce37-42d8-b27c-a1951569ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448186677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3448186677
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2101580138
Short name T600
Test name
Test status
Simulation time 83956189004 ps
CPU time 34.43 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:14:00 PM PST 23
Peak memory 200140 kb
Host smart-39d8c0a9-4113-4c8d-a32a-62ef38dd83d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101580138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2101580138
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3213141826
Short name T924
Test name
Test status
Simulation time 22547269340 ps
CPU time 35.24 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:46 PM PST 23
Peak memory 200160 kb
Host smart-2322fe86-6cb6-4b87-ac22-99ebc4732d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213141826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3213141826
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.75066109
Short name T122
Test name
Test status
Simulation time 192617666825 ps
CPU time 162.81 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:18:20 PM PST 23
Peak memory 200208 kb
Host smart-82ef79fd-f16b-4f36-bbc0-9312dda26fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75066109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.75066109
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.524787094
Short name T724
Test name
Test status
Simulation time 84585075297 ps
CPU time 34.22 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:16:10 PM PST 23
Peak memory 200112 kb
Host smart-431637aa-14b8-4ae9-b39c-3afa0b8abf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524787094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.524787094
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3247436256
Short name T744
Test name
Test status
Simulation time 65195334080 ps
CPU time 30.84 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200200 kb
Host smart-acf1be8e-7cc9-4e0d-a435-e7984267436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247436256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3247436256
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3744592705
Short name T1085
Test name
Test status
Simulation time 24683320852 ps
CPU time 35.93 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:16:12 PM PST 23
Peak memory 200028 kb
Host smart-d9164c40-ad17-447b-afc1-aabcdf2c112b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744592705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3744592705
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3067990296
Short name T1035
Test name
Test status
Simulation time 172075067091 ps
CPU time 75.51 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:43 PM PST 23
Peak memory 200176 kb
Host smart-1346ab1c-ec01-4c22-a28e-814f33c1e6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067990296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3067990296
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2390171639
Short name T1232
Test name
Test status
Simulation time 107726360288 ps
CPU time 92.6 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:16:59 PM PST 23
Peak memory 200236 kb
Host smart-6f8e7360-ba69-47a9-b924-8e5832b2cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390171639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2390171639
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2016575895
Short name T447
Test name
Test status
Simulation time 58196396647 ps
CPU time 88.74 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:57 PM PST 23
Peak memory 200132 kb
Host smart-aec7bba6-3132-48b2-8742-64e62bd4837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016575895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2016575895
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1184909729
Short name T136
Test name
Test status
Simulation time 137740188422 ps
CPU time 200.81 seconds
Started Dec 31 01:15:34 PM PST 23
Finished Dec 31 01:18:56 PM PST 23
Peak memory 200232 kb
Host smart-d614242a-4823-457e-9564-a44146a1c2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184909729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1184909729
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.538562585
Short name T1112
Test name
Test status
Simulation time 12189969 ps
CPU time 0.55 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 195588 kb
Host smart-86e156d0-28fe-4f71-803a-a2eb79d0a3ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538562585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.538562585
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1286194121
Short name T187
Test name
Test status
Simulation time 21113943937 ps
CPU time 9.46 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:13:32 PM PST 23
Peak memory 198076 kb
Host smart-fc67d6b1-a9f4-4603-9083-604e4f29aa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286194121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1286194121
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2619013880
Short name T381
Test name
Test status
Simulation time 160284715855 ps
CPU time 71.13 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:14:38 PM PST 23
Peak memory 199308 kb
Host smart-2e441dca-6941-4877-afbe-81d917424d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619013880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2619013880
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.126495298
Short name T976
Test name
Test status
Simulation time 239390685427 ps
CPU time 364.55 seconds
Started Dec 31 01:12:58 PM PST 23
Finished Dec 31 01:19:15 PM PST 23
Peak memory 199396 kb
Host smart-b0b27380-f248-4427-8c59-77322b91ea07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126495298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.126495298
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1969463317
Short name T835
Test name
Test status
Simulation time 132549744946 ps
CPU time 139.07 seconds
Started Dec 31 01:13:04 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 200348 kb
Host smart-f086267b-84d9-49f2-8478-6a9035ff97d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969463317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1969463317
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3517824395
Short name T987
Test name
Test status
Simulation time 191128451526 ps
CPU time 45.72 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:14:08 PM PST 23
Peak memory 208496 kb
Host smart-f87dee8b-7793-4a35-9427-b8ee14930421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517824395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3517824395
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2096122266
Short name T619
Test name
Test status
Simulation time 7418797427 ps
CPU time 88.08 seconds
Started Dec 31 01:13:02 PM PST 23
Finished Dec 31 01:14:42 PM PST 23
Peak memory 200260 kb
Host smart-0074b2ad-72ca-406c-b98f-1d873b53bca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096122266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2096122266
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1655648922
Short name T732
Test name
Test status
Simulation time 2426887682 ps
CPU time 10.3 seconds
Started Dec 31 01:13:02 PM PST 23
Finished Dec 31 01:13:25 PM PST 23
Peak memory 198188 kb
Host smart-e6d9fb3e-0a6a-4467-a1f3-f5eed02f624e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655648922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1655648922
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3911745781
Short name T785
Test name
Test status
Simulation time 27228867548 ps
CPU time 15.7 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 200116 kb
Host smart-0400008e-b306-4ed3-a843-39601e81c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911745781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3911745781
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.196301750
Short name T474
Test name
Test status
Simulation time 1355428971 ps
CPU time 1.01 seconds
Started Dec 31 01:13:00 PM PST 23
Finished Dec 31 01:13:15 PM PST 23
Peak memory 195764 kb
Host smart-008241e3-18ba-4310-9d4e-de1f3a5e937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196301750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.196301750
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.881169994
Short name T776
Test name
Test status
Simulation time 712414299 ps
CPU time 1.55 seconds
Started Dec 31 01:13:04 PM PST 23
Finished Dec 31 01:13:17 PM PST 23
Peak memory 198548 kb
Host smart-dfb302f0-2f78-41cc-8535-fc056f632572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881169994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.881169994
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.789871874
Short name T485
Test name
Test status
Simulation time 51478197346 ps
CPU time 598.82 seconds
Started Dec 31 01:13:02 PM PST 23
Finished Dec 31 01:23:14 PM PST 23
Peak memory 216932 kb
Host smart-1710cb8d-6e56-4c40-86ea-622c05a49c4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789871874 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.789871874
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.927437067
Short name T469
Test name
Test status
Simulation time 1629604227 ps
CPU time 2.89 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 198600 kb
Host smart-46fe124f-ae31-4dd4-b7eb-d1c55436e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927437067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.927437067
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1059397610
Short name T156
Test name
Test status
Simulation time 16057973345 ps
CPU time 5.66 seconds
Started Dec 31 01:13:04 PM PST 23
Finished Dec 31 01:13:21 PM PST 23
Peak memory 200012 kb
Host smart-02c2beaf-b49c-4263-b3db-aac6de2c2d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059397610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1059397610
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2823940242
Short name T952
Test name
Test status
Simulation time 21768703999 ps
CPU time 37.66 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:16:08 PM PST 23
Peak memory 200212 kb
Host smart-75f8f0be-22e7-4c9b-a9ad-0a3195a9af5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823940242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2823940242
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.872158979
Short name T140
Test name
Test status
Simulation time 18336561012 ps
CPU time 9.43 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:15:39 PM PST 23
Peak memory 200148 kb
Host smart-993a3ce8-564e-4e1f-90b3-72d1263dc50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872158979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.872158979
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1856747411
Short name T997
Test name
Test status
Simulation time 179029562238 ps
CPU time 27.31 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200120 kb
Host smart-c913feb6-cf97-43bb-b7d5-0c062c3e081d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856747411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1856747411
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3133981957
Short name T350
Test name
Test status
Simulation time 71726777898 ps
CPU time 10.64 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:15:38 PM PST 23
Peak memory 199844 kb
Host smart-42e8a670-d7ce-4a7b-84f7-84e6eaeb4e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133981957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3133981957
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1661172838
Short name T268
Test name
Test status
Simulation time 16855033986 ps
CPU time 27.31 seconds
Started Dec 31 01:15:32 PM PST 23
Finished Dec 31 01:16:00 PM PST 23
Peak memory 200232 kb
Host smart-b3123114-a978-4bc6-a326-d45f4fd279ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661172838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1661172838
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.967506419
Short name T708
Test name
Test status
Simulation time 227849682110 ps
CPU time 108.71 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:17:17 PM PST 23
Peak memory 200096 kb
Host smart-5e7e4b03-7a76-4585-854b-c276833083d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967506419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.967506419
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.644661939
Short name T15
Test name
Test status
Simulation time 82735819456 ps
CPU time 138.2 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:17:55 PM PST 23
Peak memory 200204 kb
Host smart-abfadc8a-56d8-41b3-b692-395b33e4ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644661939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.644661939
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3210624287
Short name T881
Test name
Test status
Simulation time 22883144664 ps
CPU time 10.93 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 198976 kb
Host smart-a93036a3-f299-4cda-a514-49c1ddfe924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210624287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3210624287
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.634389300
Short name T1138
Test name
Test status
Simulation time 175761041115 ps
CPU time 325.2 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:18:49 PM PST 23
Peak memory 199896 kb
Host smart-a96fb737-27e2-4b95-8d0d-d601ca292b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634389300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.634389300
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.593213315
Short name T1195
Test name
Test status
Simulation time 225008616798 ps
CPU time 123.81 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:15:32 PM PST 23
Peak memory 199708 kb
Host smart-25251fbd-4bb1-44e5-9d88-48a5613dd425
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593213315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.593213315
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1364509290
Short name T657
Test name
Test status
Simulation time 56378938335 ps
CPU time 225.26 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:17:07 PM PST 23
Peak memory 200220 kb
Host smart-c2c3c5b1-baa0-4029-b306-9c262c4d0c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364509290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1364509290
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1758536965
Short name T532
Test name
Test status
Simulation time 2620489182 ps
CPU time 3.43 seconds
Started Dec 31 01:13:05 PM PST 23
Finished Dec 31 01:13:20 PM PST 23
Peak memory 198516 kb
Host smart-3f3c64bc-8a2d-4d03-ac1b-c9ad9a770313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758536965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1758536965
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.690003283
Short name T1202
Test name
Test status
Simulation time 34455172476 ps
CPU time 34.52 seconds
Started Dec 31 01:13:03 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 199460 kb
Host smart-03333492-dd33-44da-85ff-363d9b978857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690003283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.690003283
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.1934144328
Short name T908
Test name
Test status
Simulation time 17507798800 ps
CPU time 990.04 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:29:53 PM PST 23
Peak memory 200192 kb
Host smart-fe4cf6a4-4cc8-4b22-807a-e16c7789cd4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1934144328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1934144328
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3261930155
Short name T359
Test name
Test status
Simulation time 9258458357 ps
CPU time 7.86 seconds
Started Dec 31 01:13:00 PM PST 23
Finished Dec 31 01:13:21 PM PST 23
Peak memory 198336 kb
Host smart-6d7bef27-66bb-4bb7-b324-aaf87639cb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261930155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3261930155
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1224125669
Short name T728
Test name
Test status
Simulation time 3469805920 ps
CPU time 1.99 seconds
Started Dec 31 01:13:01 PM PST 23
Finished Dec 31 01:13:16 PM PST 23
Peak memory 195924 kb
Host smart-d1a63189-ce31-4659-aacc-07bba5bc1210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224125669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1224125669
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2901868002
Short name T442
Test name
Test status
Simulation time 5764844593 ps
CPU time 8.34 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:13:31 PM PST 23
Peak memory 199548 kb
Host smart-a30abb3b-67f1-469a-bc4f-298cda291da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901868002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2901868002
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1383772819
Short name T1186
Test name
Test status
Simulation time 122614716430 ps
CPU time 1052.62 seconds
Started Dec 31 01:13:04 PM PST 23
Finished Dec 31 01:30:48 PM PST 23
Peak memory 231280 kb
Host smart-fac4a039-59e7-43c1-808e-2f7c3bdb8372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383772819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1383772819
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2485287882
Short name T942
Test name
Test status
Simulation time 1728206347 ps
CPU time 1.67 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:27 PM PST 23
Peak memory 198120 kb
Host smart-a0b15c32-dbc5-45c8-b1dc-2082a605620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485287882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2485287882
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.4190358251
Short name T1052
Test name
Test status
Simulation time 40558425781 ps
CPU time 34.04 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:14:03 PM PST 23
Peak memory 200228 kb
Host smart-804bd03c-a83a-4fc3-b881-877cceba6cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190358251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.4190358251
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3345586851
Short name T1001
Test name
Test status
Simulation time 60054134797 ps
CPU time 20.56 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:15:47 PM PST 23
Peak memory 200008 kb
Host smart-27144303-eab4-4920-ad17-019059ba4d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345586851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3345586851
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1312176481
Short name T1137
Test name
Test status
Simulation time 41984248482 ps
CPU time 16.6 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200284 kb
Host smart-fe34b2d9-9069-40fc-9aa3-e08600226546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312176481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1312176481
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1517456277
Short name T102
Test name
Test status
Simulation time 135775989543 ps
CPU time 224.67 seconds
Started Dec 31 01:15:42 PM PST 23
Finished Dec 31 01:19:28 PM PST 23
Peak memory 199680 kb
Host smart-d3852091-dbd9-4d1f-bf0f-29cde7e8e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517456277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1517456277
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1520819290
Short name T1098
Test name
Test status
Simulation time 36792709009 ps
CPU time 60.16 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:46 PM PST 23
Peak memory 200148 kb
Host smart-36447f2d-b8a8-45ef-a729-57434d8bf9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520819290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1520819290
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2345456583
Short name T139
Test name
Test status
Simulation time 8035559445 ps
CPU time 15.37 seconds
Started Dec 31 01:15:53 PM PST 23
Finished Dec 31 01:16:09 PM PST 23
Peak memory 200204 kb
Host smart-3ad88d61-6536-40bd-a1f8-4366cf0adb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345456583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2345456583
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.363913468
Short name T753
Test name
Test status
Simulation time 21208836448 ps
CPU time 37.11 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200080 kb
Host smart-6cf9aefb-775c-4277-a6a5-7ff11911ff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363913468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.363913468
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1202755589
Short name T879
Test name
Test status
Simulation time 35524405 ps
CPU time 0.55 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 195564 kb
Host smart-00bd7847-5b14-4824-a754-3a3f6855b301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202755589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1202755589
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.96180338
Short name T1133
Test name
Test status
Simulation time 51653258838 ps
CPU time 87.71 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:15:02 PM PST 23
Peak memory 200156 kb
Host smart-f8d67401-d2ba-4038-97ea-f5115fb6e6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96180338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.96180338
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.520879154
Short name T285
Test name
Test status
Simulation time 65096829759 ps
CPU time 39.1 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:14:14 PM PST 23
Peak memory 200220 kb
Host smart-45c47289-48de-4546-90b1-6b0b5cb03fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520879154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.520879154
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1543467578
Short name T1030
Test name
Test status
Simulation time 34277741058 ps
CPU time 14.26 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:45 PM PST 23
Peak memory 200224 kb
Host smart-d29c0180-ed93-454b-bdc5-2f89481adc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543467578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1543467578
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.87148402
Short name T559
Test name
Test status
Simulation time 1393148653366 ps
CPU time 2303.16 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:52:01 PM PST 23
Peak memory 198984 kb
Host smart-c02490ab-4fb6-46e6-899a-e2977589eaca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87148402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.87148402
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.101340360
Short name T595
Test name
Test status
Simulation time 157371270595 ps
CPU time 426.95 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:20:40 PM PST 23
Peak memory 200212 kb
Host smart-887cea88-198a-485d-9b89-246ae723baae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=101340360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.101340360
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.64363786
Short name T566
Test name
Test status
Simulation time 3275539901 ps
CPU time 3.72 seconds
Started Dec 31 01:13:16 PM PST 23
Finished Dec 31 01:13:25 PM PST 23
Peak memory 199228 kb
Host smart-a441efbd-b1f5-475b-8efd-219f1dd80296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64363786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.64363786
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3658163292
Short name T974
Test name
Test status
Simulation time 28260515906 ps
CPU time 51 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:14:27 PM PST 23
Peak memory 199372 kb
Host smart-f84ee40d-99e1-42d5-977d-8974f212f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658163292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3658163292
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.845040964
Short name T587
Test name
Test status
Simulation time 1636206671 ps
CPU time 7.68 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:37 PM PST 23
Peak memory 198248 kb
Host smart-e025259c-b92f-4eef-80d0-921139ddf02a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=845040964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.845040964
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2808508978
Short name T196
Test name
Test status
Simulation time 93115550874 ps
CPU time 146.47 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:15:48 PM PST 23
Peak memory 200192 kb
Host smart-9a3e9613-d1ea-4db6-9450-ae435544aef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808508978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2808508978
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4250582625
Short name T986
Test name
Test status
Simulation time 48206862357 ps
CPU time 9.72 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:13:46 PM PST 23
Peak memory 196004 kb
Host smart-202a1b3e-a0b2-4231-a825-fa48bcd88b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250582625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4250582625
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1504691765
Short name T603
Test name
Test status
Simulation time 807830648 ps
CPU time 2.77 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:34 PM PST 23
Peak memory 198992 kb
Host smart-1a672fe9-3de4-4658-96ac-0bacd61014cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504691765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1504691765
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.173657268
Short name T737
Test name
Test status
Simulation time 6948110490 ps
CPU time 25.44 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:48 PM PST 23
Peak memory 199704 kb
Host smart-85bed15e-55b0-4d7d-9d51-fbeec6d84f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173657268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.173657268
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3973823236
Short name T671
Test name
Test status
Simulation time 9389335896 ps
CPU time 14.78 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:48 PM PST 23
Peak memory 197620 kb
Host smart-2b7378f5-f42d-4299-bb23-c3bd0337d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973823236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3973823236
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3475431807
Short name T1046
Test name
Test status
Simulation time 19587115163 ps
CPU time 16.05 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:16:07 PM PST 23
Peak memory 199048 kb
Host smart-ee8954f8-2cff-4aa9-b30b-f44d5993b71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475431807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3475431807
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3473768746
Short name T226
Test name
Test status
Simulation time 58161463869 ps
CPU time 25.35 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200156 kb
Host smart-7a6c53ff-1b40-4797-b0a7-82394a9694b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473768746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3473768746
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1845662093
Short name T1228
Test name
Test status
Simulation time 68764881188 ps
CPU time 67.74 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:16:39 PM PST 23
Peak memory 200236 kb
Host smart-0996dc92-aade-41be-af54-9b0ced196383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845662093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1845662093
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3786310301
Short name T240
Test name
Test status
Simulation time 75966267056 ps
CPU time 63.45 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:50 PM PST 23
Peak memory 200276 kb
Host smart-5f2d94d6-e1ac-4251-b16f-b5f57ab6730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786310301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3786310301
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.658339773
Short name T1093
Test name
Test status
Simulation time 48486690725 ps
CPU time 20.02 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:10 PM PST 23
Peak memory 199704 kb
Host smart-ac58d014-ec0c-456f-9e05-867ac5482289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658339773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.658339773
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3233044680
Short name T834
Test name
Test status
Simulation time 24156945211 ps
CPU time 46.63 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:34 PM PST 23
Peak memory 200272 kb
Host smart-37547540-5967-4dc5-9be1-386a5554bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233044680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3233044680
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.382136965
Short name T177
Test name
Test status
Simulation time 56877935510 ps
CPU time 24.87 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:11 PM PST 23
Peak memory 199968 kb
Host smart-781ea1ce-7551-46e7-96d8-7ada28444310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382136965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.382136965
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.925230769
Short name T886
Test name
Test status
Simulation time 35941284999 ps
CPU time 12.89 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:00 PM PST 23
Peak memory 198632 kb
Host smart-74332135-762e-4a3f-94b1-155c90cb6e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925230769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.925230769
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4003621903
Short name T816
Test name
Test status
Simulation time 23559888690 ps
CPU time 38.9 seconds
Started Dec 31 01:15:51 PM PST 23
Finished Dec 31 01:16:31 PM PST 23
Peak memory 200148 kb
Host smart-f0ad951a-5b52-44c4-a9ec-26675e5b8524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003621903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4003621903
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1571729927
Short name T160
Test name
Test status
Simulation time 41449079102 ps
CPU time 14.75 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 199588 kb
Host smart-20293c12-8361-4d03-8384-6789c68b04ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571729927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1571729927
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3761074371
Short name T679
Test name
Test status
Simulation time 13422879 ps
CPU time 0.56 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:13:22 PM PST 23
Peak memory 195616 kb
Host smart-12082c4c-f169-477e-a315-3a71020bdd0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761074371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3761074371
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.4036824043
Short name T739
Test name
Test status
Simulation time 57301443486 ps
CPU time 6.6 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 199900 kb
Host smart-d685b2a1-325f-4e1f-b19c-ba6e3cb80793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036824043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.4036824043
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2949705343
Short name T1053
Test name
Test status
Simulation time 20845020219 ps
CPU time 16.15 seconds
Started Dec 31 01:13:16 PM PST 23
Finished Dec 31 01:13:37 PM PST 23
Peak memory 199576 kb
Host smart-e79f3534-5482-44b8-97c5-6ee51a6bb378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949705343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2949705343
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1230511456
Short name T188
Test name
Test status
Simulation time 216068802438 ps
CPU time 628.9 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:23:59 PM PST 23
Peak memory 200216 kb
Host smart-2a25c74e-827b-4bf3-8cf0-5edce02ef568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230511456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1230511456
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3774377521
Short name T1075
Test name
Test status
Simulation time 82049442538 ps
CPU time 22.87 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 199916 kb
Host smart-07296ab0-3003-49b0-9a51-4edb09a8a42a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774377521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3774377521
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2950255701
Short name T1003
Test name
Test status
Simulation time 265232985291 ps
CPU time 278.24 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:18:00 PM PST 23
Peak memory 200252 kb
Host smart-146aae95-d624-497c-b34e-1f2996dc682c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950255701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2950255701
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3002524058
Short name T1010
Test name
Test status
Simulation time 1032457354 ps
CPU time 0.89 seconds
Started Dec 31 01:13:15 PM PST 23
Finished Dec 31 01:13:22 PM PST 23
Peak memory 195616 kb
Host smart-e283c2d0-ee65-4dd1-bedf-a94aa4a859f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002524058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3002524058
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1933680158
Short name T1176
Test name
Test status
Simulation time 171944622650 ps
CPU time 113.98 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:15:16 PM PST 23
Peak memory 200464 kb
Host smart-84e70186-c79d-4a2c-83f4-6c865ed52c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933680158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1933680158
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1208213694
Short name T883
Test name
Test status
Simulation time 18646219724 ps
CPU time 934.29 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:29:03 PM PST 23
Peak memory 200212 kb
Host smart-ac8c0719-27cf-45a4-8455-5ca2123c4341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1208213694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1208213694
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3303298839
Short name T1222
Test name
Test status
Simulation time 4687734032 ps
CPU time 46.19 seconds
Started Dec 31 01:13:15 PM PST 23
Finished Dec 31 01:14:07 PM PST 23
Peak memory 198980 kb
Host smart-c08a7a44-b4c8-4088-9989-a892b846073c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3303298839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3303298839
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2807077364
Short name T401
Test name
Test status
Simulation time 26013333162 ps
CPU time 41.04 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:14:03 PM PST 23
Peak memory 200188 kb
Host smart-07421f24-0ba6-44e7-9413-61f0f01cee42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807077364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2807077364
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3744069124
Short name T1214
Test name
Test status
Simulation time 40181862793 ps
CPU time 14.93 seconds
Started Dec 31 01:13:14 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 195668 kb
Host smart-50e60857-1cc4-4bb8-839d-142d8ee0824a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744069124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3744069124
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1599413787
Short name T648
Test name
Test status
Simulation time 663458473 ps
CPU time 1.84 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 199356 kb
Host smart-5375430c-81e4-4b56-b96f-384a6ed2a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599413787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1599413787
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.414769692
Short name T939
Test name
Test status
Simulation time 414081018107 ps
CPU time 1303.39 seconds
Started Dec 31 01:13:16 PM PST 23
Finished Dec 31 01:35:05 PM PST 23
Peak memory 200232 kb
Host smart-732d573b-a4cb-4298-b73e-da3abd3cc726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414769692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.414769692
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.4046138116
Short name T67
Test name
Test status
Simulation time 202724715836 ps
CPU time 1402.31 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:36:48 PM PST 23
Peak memory 226980 kb
Host smart-8c28de97-ab3a-490b-aacb-da8e4c091680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046138116 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.4046138116
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3525562741
Short name T932
Test name
Test status
Simulation time 618755070 ps
CPU time 2.29 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:33 PM PST 23
Peak memory 198696 kb
Host smart-2d3b9da3-6eb8-4dc9-ab00-523d92d5c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525562741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3525562741
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2653090352
Short name T650
Test name
Test status
Simulation time 24189322306 ps
CPU time 38.27 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:14:01 PM PST 23
Peak memory 198760 kb
Host smart-84ca44e4-ca85-476d-9b69-bb2c43357f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653090352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2653090352
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2344154007
Short name T244
Test name
Test status
Simulation time 21395264089 ps
CPU time 34.98 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:25 PM PST 23
Peak memory 200408 kb
Host smart-76837562-337d-412d-a5ec-314ecaf34aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344154007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2344154007
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2477417
Short name T563
Test name
Test status
Simulation time 86491231495 ps
CPU time 142.12 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:18:11 PM PST 23
Peak memory 200124 kb
Host smart-9d175125-6a8e-4c8f-95cc-5aea80f02d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2477417
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2837413376
Short name T1104
Test name
Test status
Simulation time 44031576462 ps
CPU time 69.56 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:57 PM PST 23
Peak memory 200128 kb
Host smart-78040ebd-eec5-4ea0-a212-8c1fb3fc9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837413376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2837413376
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.417913083
Short name T272
Test name
Test status
Simulation time 156125578158 ps
CPU time 18.58 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:15:56 PM PST 23
Peak memory 199444 kb
Host smart-8416c5e9-b38a-420d-9d9c-6da7c3bf7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417913083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.417913083
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1320576950
Short name T129
Test name
Test status
Simulation time 99085242951 ps
CPU time 475.38 seconds
Started Dec 31 01:15:31 PM PST 23
Finished Dec 31 01:23:27 PM PST 23
Peak memory 200236 kb
Host smart-fe2ec070-96c3-41e0-bb38-c4332a09d2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320576950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1320576950
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.4031013341
Short name T138
Test name
Test status
Simulation time 11139581477 ps
CPU time 31.37 seconds
Started Dec 31 01:15:25 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200272 kb
Host smart-faf063bc-6bba-485c-88cb-7e961b8817bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031013341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.4031013341
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2884486336
Short name T239
Test name
Test status
Simulation time 22513685089 ps
CPU time 37.62 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 200192 kb
Host smart-d61324a2-c766-43f3-8d91-1cd22f04f636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884486336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2884486336
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.4228639863
Short name T971
Test name
Test status
Simulation time 12015863 ps
CPU time 0.6 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:33 PM PST 23
Peak memory 195652 kb
Host smart-e12d4c85-30df-4093-8912-ea6b5c463c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228639863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4228639863
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.315217597
Short name T926
Test name
Test status
Simulation time 146388554283 ps
CPU time 124.18 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:15:43 PM PST 23
Peak memory 200216 kb
Host smart-d8923c59-7914-40fe-b742-b8ecf3849f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315217597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.315217597
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2206362988
Short name T270
Test name
Test status
Simulation time 207754055174 ps
CPU time 93.7 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:15:03 PM PST 23
Peak memory 200192 kb
Host smart-3f4bdb51-6517-488c-95c1-0e2e28d7a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206362988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2206362988
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.11595732
Short name T884
Test name
Test status
Simulation time 23340132458 ps
CPU time 36.64 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:59 PM PST 23
Peak memory 200120 kb
Host smart-68469309-9889-4004-bfdd-824d797247c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11595732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.11595732
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.265824823
Short name T541
Test name
Test status
Simulation time 41011436060 ps
CPU time 67.42 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:14:46 PM PST 23
Peak memory 198448 kb
Host smart-f70429f8-d252-45c3-9043-e0ae6c4191ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265824823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.265824823
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.483462138
Short name T769
Test name
Test status
Simulation time 97754613400 ps
CPU time 111.59 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:15:14 PM PST 23
Peak memory 200156 kb
Host smart-06c98a1c-fec5-4a06-8dc1-bc8a0b3dec91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483462138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.483462138
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2877965890
Short name T1158
Test name
Test status
Simulation time 9352687591 ps
CPU time 8.62 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 199672 kb
Host smart-ed175470-8c92-4030-8022-71008cdbc4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877965890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2877965890
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3086331894
Short name T701
Test name
Test status
Simulation time 9483602664 ps
CPU time 10 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 197620 kb
Host smart-41208bed-1ab0-40b4-bd1f-b8c8498e528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086331894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3086331894
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2231224791
Short name T1197
Test name
Test status
Simulation time 16724305550 ps
CPU time 179.4 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:16:32 PM PST 23
Peak memory 200220 kb
Host smart-8c2e6c34-c046-48e8-9f7f-45309c84cfb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2231224791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2231224791
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.4180363226
Short name T490
Test name
Test status
Simulation time 1203556007 ps
CPU time 6.32 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:33 PM PST 23
Peak memory 198316 kb
Host smart-c2fb32f6-656a-4c24-bb03-ba2113bc59b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180363226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4180363226
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2938561892
Short name T937
Test name
Test status
Simulation time 125211743679 ps
CPU time 254.08 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:17:43 PM PST 23
Peak memory 199812 kb
Host smart-3bea5825-ede7-4aea-821a-66be804d1dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938561892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2938561892
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2354532879
Short name T557
Test name
Test status
Simulation time 2878254118 ps
CPU time 5.45 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:31 PM PST 23
Peak memory 195812 kb
Host smart-8f69f19b-c541-431d-a159-f19eabec583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354532879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2354532879
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2610230889
Short name T706
Test name
Test status
Simulation time 1049938831 ps
CPU time 1.3 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 198020 kb
Host smart-1f65bffb-78c8-4d6b-a00f-97e53014ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610230889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2610230889
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.3384803283
Short name T1022
Test name
Test status
Simulation time 137932501503 ps
CPU time 283.2 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:18:17 PM PST 23
Peak memory 216880 kb
Host smart-4966c716-ddf7-4da0-a79f-d99a6a8ebb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384803283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3384803283
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1704155694
Short name T295
Test name
Test status
Simulation time 80971079716 ps
CPU time 717.63 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:25:32 PM PST 23
Peak memory 216920 kb
Host smart-08c88d10-d607-4768-acb6-ff75a836ded9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704155694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1704155694
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.592849939
Short name T722
Test name
Test status
Simulation time 1458747566 ps
CPU time 1.93 seconds
Started Dec 31 01:13:16 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 199168 kb
Host smart-89cdcb32-c96f-4b6f-850c-38ee5f81f4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592849939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.592849939
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3027341092
Short name T665
Test name
Test status
Simulation time 14951201785 ps
CPU time 21.25 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:44 PM PST 23
Peak memory 196708 kb
Host smart-ba537a5c-e60a-445e-a1c6-0f499da9d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027341092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3027341092
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1820890590
Short name T870
Test name
Test status
Simulation time 105516486716 ps
CPU time 156.72 seconds
Started Dec 31 01:15:41 PM PST 23
Finished Dec 31 01:18:19 PM PST 23
Peak memory 199744 kb
Host smart-a5b1f8e1-4193-4e8b-8561-44ffa8bef855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820890590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1820890590
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2826917495
Short name T152
Test name
Test status
Simulation time 72218657654 ps
CPU time 180.04 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:18:39 PM PST 23
Peak memory 200216 kb
Host smart-5b9d1ec2-4731-46ff-a71f-8a62645bd91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826917495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2826917495
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.181720463
Short name T814
Test name
Test status
Simulation time 40586639784 ps
CPU time 17.29 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:15:54 PM PST 23
Peak memory 200216 kb
Host smart-4e4a7eef-92a6-4a0e-874a-3e0df2da8a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181720463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.181720463
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3360247557
Short name T988
Test name
Test status
Simulation time 48833531411 ps
CPU time 21.91 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:15:49 PM PST 23
Peak memory 199796 kb
Host smart-ebc2d0bf-721a-485c-94ea-7f4eb2dc5906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360247557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3360247557
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3569564297
Short name T955
Test name
Test status
Simulation time 31998060486 ps
CPU time 55.82 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:16:32 PM PST 23
Peak memory 200204 kb
Host smart-760b8f4a-9cb5-448d-872b-bbd5210f16aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569564297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3569564297
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1678316408
Short name T552
Test name
Test status
Simulation time 28670724 ps
CPU time 0.58 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 195880 kb
Host smart-0f4cc48b-7fda-4250-8e56-89c99c11d877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678316408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1678316408
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1001565486
Short name T934
Test name
Test status
Simulation time 77857597532 ps
CPU time 95.08 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:13:58 PM PST 23
Peak memory 200148 kb
Host smart-744893d4-dd31-471d-b07e-83424a1e8c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001565486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1001565486
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2068121400
Short name T1238
Test name
Test status
Simulation time 15334463394 ps
CPU time 12.66 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 199364 kb
Host smart-0acee797-d3cf-47c2-b481-d9fd17e37023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068121400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2068121400
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4250582151
Short name T1180
Test name
Test status
Simulation time 23196026307 ps
CPU time 21.27 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:12:43 PM PST 23
Peak memory 199664 kb
Host smart-2679f7a2-4bff-4ee0-ba21-e77ecfdfc886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250582151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4250582151
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.664375376
Short name T531
Test name
Test status
Simulation time 323343581840 ps
CPU time 237.83 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:16:23 PM PST 23
Peak memory 199120 kb
Host smart-b5f9abe4-1413-4db5-95e3-db1df75bf64c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664375376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.664375376
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2128916283
Short name T558
Test name
Test status
Simulation time 65146880106 ps
CPU time 168.47 seconds
Started Dec 31 01:12:16 PM PST 23
Finished Dec 31 01:15:09 PM PST 23
Peak memory 200236 kb
Host smart-aef737da-796c-4a6e-a838-0375bb16a7f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2128916283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2128916283
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.290322428
Short name T542
Test name
Test status
Simulation time 8582911543 ps
CPU time 9.57 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 199868 kb
Host smart-993f5b38-5060-47e7-8353-b8b22f25e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290322428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.290322428
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2615360717
Short name T810
Test name
Test status
Simulation time 70426530096 ps
CPU time 98.69 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:14:00 PM PST 23
Peak memory 199064 kb
Host smart-d9527dd0-298b-44f8-869c-c318985113c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615360717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2615360717
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1416467126
Short name T856
Test name
Test status
Simulation time 21525132724 ps
CPU time 540.46 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:21:27 PM PST 23
Peak memory 200160 kb
Host smart-e4bfeb12-7828-4f5a-adb4-1a697315a605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416467126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1416467126
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2065462968
Short name T817
Test name
Test status
Simulation time 2359928485 ps
CPU time 17.37 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:12:38 PM PST 23
Peak memory 198856 kb
Host smart-e762e465-9042-4529-b4d7-56aaeaa8dd89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065462968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2065462968
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.383591877
Short name T806
Test name
Test status
Simulation time 56008346599 ps
CPU time 50.84 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:13:14 PM PST 23
Peak memory 200196 kb
Host smart-5af8de58-8bda-4618-9f14-128a713d08e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383591877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.383591877
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2248074117
Short name T104
Test name
Test status
Simulation time 6448631995 ps
CPU time 3.01 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 196064 kb
Host smart-6cc25d0a-965c-4f89-afd0-e7ae77b80a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248074117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2248074117
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1059751751
Short name T86
Test name
Test status
Simulation time 35732644 ps
CPU time 0.79 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 217804 kb
Host smart-b1f29fb2-f778-4b05-a3c5-174dd0a94e5b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059751751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1059751751
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2017069310
Short name T833
Test name
Test status
Simulation time 627646475 ps
CPU time 2.86 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 198148 kb
Host smart-f38d91aa-8988-4439-a928-2048bcc38ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017069310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2017069310
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.618502314
Short name T925
Test name
Test status
Simulation time 341721448873 ps
CPU time 754.16 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:25:00 PM PST 23
Peak memory 200004 kb
Host smart-b12abeac-3dd1-4060-839e-4cf332f2a1a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618502314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.618502314
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1574572559
Short name T1136
Test name
Test status
Simulation time 46862827031 ps
CPU time 854.73 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:26:36 PM PST 23
Peak memory 225088 kb
Host smart-f9e94ff0-4acb-4e5b-bf93-15e36b007882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574572559 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1574572559
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.253021979
Short name T1009
Test name
Test status
Simulation time 3511630961 ps
CPU time 1.83 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 199052 kb
Host smart-c8238f52-23e1-4680-95ca-99edd24565e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253021979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.253021979
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2576589683
Short name T200
Test name
Test status
Simulation time 76410915011 ps
CPU time 157.32 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:15:11 PM PST 23
Peak memory 200188 kb
Host smart-ec4c2bea-a904-45a5-a9d1-0f24cb5216d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576589683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2576589683
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.908313912
Short name T596
Test name
Test status
Simulation time 35883743 ps
CPU time 0.63 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 195056 kb
Host smart-92127fc9-16af-4ae5-8940-3f8d2b3ca396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908313912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.908313912
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1435303517
Short name T709
Test name
Test status
Simulation time 158495969848 ps
CPU time 230 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:17:19 PM PST 23
Peak memory 200192 kb
Host smart-956093ee-97dd-45e0-91ba-c9a46118730a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435303517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1435303517
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2770581324
Short name T399
Test name
Test status
Simulation time 101695485572 ps
CPU time 33.69 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:14:09 PM PST 23
Peak memory 200156 kb
Host smart-e74d4bcd-a392-4ee6-96bf-4432ef61f390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770581324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2770581324
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1442390368
Short name T227
Test name
Test status
Simulation time 25770514756 ps
CPU time 23.4 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:13:58 PM PST 23
Peak memory 199664 kb
Host smart-9cea0985-24a7-401a-8e2a-41c386b41c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442390368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1442390368
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2167939189
Short name T1028
Test name
Test status
Simulation time 148011321066 ps
CPU time 289.19 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:18:14 PM PST 23
Peak memory 200208 kb
Host smart-956dbad2-6e2f-4af1-b602-d28fa4fcafd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167939189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2167939189
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.4110706936
Short name T837
Test name
Test status
Simulation time 61909654 ps
CPU time 0.65 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:30 PM PST 23
Peak memory 193652 kb
Host smart-3ff433df-45eb-4e70-99ff-bee6656e9e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110706936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.4110706936
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1165272212
Short name T1059
Test name
Test status
Simulation time 37547571696 ps
CPU time 62.64 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:14:31 PM PST 23
Peak memory 198728 kb
Host smart-bf3c70fb-4379-4131-b573-be2e8c11ae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165272212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1165272212
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.815384222
Short name T567
Test name
Test status
Simulation time 3036186499 ps
CPU time 155.69 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200172 kb
Host smart-0b046cce-b1de-423d-9555-1f003b4137da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815384222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.815384222
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1193062296
Short name T1017
Test name
Test status
Simulation time 2270882753 ps
CPU time 16.4 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:13:53 PM PST 23
Peak memory 198232 kb
Host smart-e04cc1b4-c8e1-4a29-acb9-b317e9c5d184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193062296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1193062296
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3988342834
Short name T990
Test name
Test status
Simulation time 93031803532 ps
CPU time 75.1 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:14:46 PM PST 23
Peak memory 200204 kb
Host smart-bb6bd239-68e3-4105-a684-3630ad7ac4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988342834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3988342834
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3391642854
Short name T1143
Test name
Test status
Simulation time 4737783108 ps
CPU time 2.62 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 195820 kb
Host smart-3c84f8ae-df22-4c53-9ec3-70beb3adf0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391642854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3391642854
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1453198757
Short name T743
Test name
Test status
Simulation time 142264868 ps
CPU time 0.81 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:13:22 PM PST 23
Peak memory 196876 kb
Host smart-83a32449-cb56-42d0-9557-f65283450ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453198757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1453198757
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.107656263
Short name T1153
Test name
Test status
Simulation time 26808347932 ps
CPU time 306.53 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:18:37 PM PST 23
Peak memory 211420 kb
Host smart-3d45a082-93c8-429d-9453-8e158472233b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107656263 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.107656263
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1569995417
Short name T646
Test name
Test status
Simulation time 1171527737 ps
CPU time 2.09 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 198588 kb
Host smart-874a9719-5ff0-4465-ac44-593666e895c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569995417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1569995417
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.223298843
Short name T547
Test name
Test status
Simulation time 35437438558 ps
CPU time 59.56 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:14:21 PM PST 23
Peak memory 200200 kb
Host smart-12102179-1bac-428a-8c3b-5fb6f1a1c43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223298843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.223298843
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1958811230
Short name T907
Test name
Test status
Simulation time 19703850857 ps
CPU time 17.57 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:15:53 PM PST 23
Peak memory 199128 kb
Host smart-9b68cad2-add5-4bce-84e9-442236dff831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958811230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1958811230
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2225787121
Short name T318
Test name
Test status
Simulation time 27081031497 ps
CPU time 22.94 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:15:51 PM PST 23
Peak memory 200340 kb
Host smart-c8c1e643-83c2-44ab-bf4b-f5ad844ecac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225787121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2225787121
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.70092749
Short name T327
Test name
Test status
Simulation time 137123266825 ps
CPU time 240.57 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:19:29 PM PST 23
Peak memory 200180 kb
Host smart-2e10855c-cdcd-420f-9489-c952ea65e847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70092749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.70092749
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.543967987
Short name T1236
Test name
Test status
Simulation time 263741959059 ps
CPU time 354.05 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:21:31 PM PST 23
Peak memory 200200 kb
Host smart-f301e389-74d0-40f1-8e00-e892654a9080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543967987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.543967987
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1794188634
Short name T964
Test name
Test status
Simulation time 16422712720 ps
CPU time 27.98 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200240 kb
Host smart-c97e03b8-d1ff-4903-8f46-b8192d38dd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794188634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1794188634
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1717257181
Short name T325
Test name
Test status
Simulation time 94370547994 ps
CPU time 36.29 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200188 kb
Host smart-b18f085c-2e4b-4a14-94e8-538dc4053300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717257181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1717257181
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4253673529
Short name T1146
Test name
Test status
Simulation time 13775112505 ps
CPU time 23.37 seconds
Started Dec 31 01:15:41 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 199976 kb
Host smart-cb88f3b8-e011-4015-bc12-ab91eb67b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253673529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4253673529
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.545843048
Short name T876
Test name
Test status
Simulation time 23995359 ps
CPU time 0.55 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:32 PM PST 23
Peak memory 195620 kb
Host smart-544634bc-576f-4271-9ce0-549c42b1e2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545843048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.545843048
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.125934698
Short name T1152
Test name
Test status
Simulation time 140955362314 ps
CPU time 115.06 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:15:19 PM PST 23
Peak memory 200172 kb
Host smart-05f24be5-fff5-4757-9fe6-3ef60948b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125934698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.125934698
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4077659390
Short name T745
Test name
Test status
Simulation time 42539665713 ps
CPU time 29.12 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:58 PM PST 23
Peak memory 199196 kb
Host smart-f08dea33-28ed-41f1-889b-8162afc207e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077659390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4077659390
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1984635826
Short name T836
Test name
Test status
Simulation time 145979259538 ps
CPU time 966.48 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:29:41 PM PST 23
Peak memory 200140 kb
Host smart-d6ce56a1-cd02-41cc-9fb9-bc3e6d265cfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984635826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1984635826
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2477933302
Short name T989
Test name
Test status
Simulation time 4468175377 ps
CPU time 8.55 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 198648 kb
Host smart-df8a4113-b123-46ef-b761-67dee8b7cd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477933302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2477933302
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.2592025734
Short name T921
Test name
Test status
Simulation time 97369636403 ps
CPU time 198.71 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:16:41 PM PST 23
Peak memory 200332 kb
Host smart-acefd41c-19af-4331-a2a3-d7f846c5d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592025734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2592025734
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.996895960
Short name T1204
Test name
Test status
Simulation time 16438663075 ps
CPU time 898.5 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:28:23 PM PST 23
Peak memory 200172 kb
Host smart-d2235983-9faf-4cc7-9062-3ce1decd30d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996895960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.996895960
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2464003191
Short name T702
Test name
Test status
Simulation time 2069857029 ps
CPU time 21.04 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 198364 kb
Host smart-a8546411-e56f-4c4e-9906-eac2cd3a7471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464003191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2464003191
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3028290627
Short name T369
Test name
Test status
Simulation time 17405418307 ps
CPU time 14.14 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:46 PM PST 23
Peak memory 199696 kb
Host smart-1426a749-9ab6-44ed-abd5-924fb2b20b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028290627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3028290627
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.617014388
Short name T854
Test name
Test status
Simulation time 4389903962 ps
CPU time 1.29 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 196064 kb
Host smart-61a0d1f1-60b2-4085-b43e-f4afff3418d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617014388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.617014388
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.68959013
Short name T1063
Test name
Test status
Simulation time 6212106474 ps
CPU time 13.74 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:13:51 PM PST 23
Peak memory 199648 kb
Host smart-3d69c6bc-05f4-4f4f-bf72-298c7499a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68959013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.68959013
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.945198543
Short name T1132
Test name
Test status
Simulation time 110866950759 ps
CPU time 512.19 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:22:08 PM PST 23
Peak memory 200216 kb
Host smart-fd659e6d-bece-4feb-b7eb-10151f12570b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945198543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.945198543
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3596147590
Short name T779
Test name
Test status
Simulation time 281089414469 ps
CPU time 1050.99 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:30:59 PM PST 23
Peak memory 216604 kb
Host smart-670ccb06-5b73-42f3-9ffc-b250e4804ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596147590 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3596147590
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1444953977
Short name T871
Test name
Test status
Simulation time 7911455569 ps
CPU time 7.83 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:13:44 PM PST 23
Peak memory 200232 kb
Host smart-ae6d90de-0fea-48c3-a220-6e81e078d341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444953977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1444953977
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3703017548
Short name T715
Test name
Test status
Simulation time 42587028594 ps
CPU time 32.64 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:57 PM PST 23
Peak memory 200240 kb
Host smart-e4572d5e-b6ad-42e0-b889-29df60090fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703017548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3703017548
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1929395400
Short name T761
Test name
Test status
Simulation time 18067844469 ps
CPU time 16.62 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 199856 kb
Host smart-143727d0-34cc-483c-826d-0f3a5d16234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929395400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1929395400
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1698368939
Short name T183
Test name
Test status
Simulation time 3870649303 ps
CPU time 6.9 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:15:54 PM PST 23
Peak memory 199084 kb
Host smart-63453f89-5918-4908-93ed-9cd14781b3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698368939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1698368939
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2861135009
Short name T275
Test name
Test status
Simulation time 65717031853 ps
CPU time 28.51 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 198868 kb
Host smart-a900ed03-12a4-4845-9429-527bea15e5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861135009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2861135009
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2714162863
Short name T146
Test name
Test status
Simulation time 17727085791 ps
CPU time 30.93 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 200008 kb
Host smart-684116b2-ed87-4481-a697-17251bbbfc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714162863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2714162863
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2399830043
Short name T698
Test name
Test status
Simulation time 23760528355 ps
CPU time 38.02 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:24 PM PST 23
Peak memory 200264 kb
Host smart-4b2daa71-dc9a-4c23-bd15-87e76f1f1083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399830043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2399830043
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1260385109
Short name T334
Test name
Test status
Simulation time 122724298695 ps
CPU time 181.65 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:18:40 PM PST 23
Peak memory 200280 kb
Host smart-2dca8c09-56ac-445c-837a-d71e37e09d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260385109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1260385109
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3814648435
Short name T271
Test name
Test status
Simulation time 25991669998 ps
CPU time 50.49 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:16:29 PM PST 23
Peak memory 200232 kb
Host smart-d793056f-01c3-43f1-8f3e-19abb8268146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814648435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3814648435
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4079992103
Short name T335
Test name
Test status
Simulation time 131956790198 ps
CPU time 93.09 seconds
Started Dec 31 01:15:38 PM PST 23
Finished Dec 31 01:17:12 PM PST 23
Peak memory 199708 kb
Host smart-890c49e5-e435-4e02-a8ab-a79d1ba017aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079992103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4079992103
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.969919077
Short name T92
Test name
Test status
Simulation time 13777124 ps
CPU time 0.55 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:31 PM PST 23
Peak memory 195668 kb
Host smart-130dbf32-11a3-4760-aa50-48d3961a8ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969919077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.969919077
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1146449073
Short name T459
Test name
Test status
Simulation time 129620413421 ps
CPU time 96.6 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:15:00 PM PST 23
Peak memory 200120 kb
Host smart-4ea5fef4-e678-439e-af1a-1a5c6832f457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146449073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1146449073
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3541021854
Short name T309
Test name
Test status
Simulation time 19124015118 ps
CPU time 29.91 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:59 PM PST 23
Peak memory 199860 kb
Host smart-7903132d-fc97-46de-bb79-0098e97a2377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541021854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3541021854
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.855244862
Short name T551
Test name
Test status
Simulation time 30932898734 ps
CPU time 14.6 seconds
Started Dec 31 01:13:17 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 200200 kb
Host smart-439c8f1d-8da1-4e54-a1fd-52cf287e841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855244862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.855244862
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.4244217393
Short name T791
Test name
Test status
Simulation time 61657783615 ps
CPU time 23.25 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:59 PM PST 23
Peak memory 200140 kb
Host smart-3d0b8e8a-973d-49d9-8a6f-8cb9f74a1880
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244217393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4244217393
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.736536572
Short name T1148
Test name
Test status
Simulation time 92076874657 ps
CPU time 156.21 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200256 kb
Host smart-c26b8a75-0ae3-4d93-9310-49951c18d25b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=736536572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.736536572
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3281711731
Short name T772
Test name
Test status
Simulation time 3977021039 ps
CPU time 2.81 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:30 PM PST 23
Peak memory 200372 kb
Host smart-d2eee44e-1a05-4a45-86ce-780b947d012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281711731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3281711731
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3196396799
Short name T1159
Test name
Test status
Simulation time 92665317115 ps
CPU time 53.3 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:14:23 PM PST 23
Peak memory 199712 kb
Host smart-01b96d34-c51c-43be-83f2-86ff9a8a65bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196396799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3196396799
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2698979323
Short name T962
Test name
Test status
Simulation time 23555196737 ps
CPU time 96.2 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:15:11 PM PST 23
Peak memory 200216 kb
Host smart-62bcfbd0-d63e-4d44-bea6-3500187bfc97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2698979323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2698979323
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2262826772
Short name T767
Test name
Test status
Simulation time 2722922016 ps
CPU time 26.16 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:58 PM PST 23
Peak memory 198768 kb
Host smart-2b9a34ad-35ee-42ec-8b24-1d5c2f19da10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262826772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2262826772
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.402680875
Short name T931
Test name
Test status
Simulation time 40119061118 ps
CPU time 65.67 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:14:29 PM PST 23
Peak memory 200016 kb
Host smart-bda776f5-af84-41a3-ba8b-9317d55575a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402680875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.402680875
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.633321920
Short name T607
Test name
Test status
Simulation time 4095565344 ps
CPU time 6.6 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:32 PM PST 23
Peak memory 195908 kb
Host smart-a9b07a5a-13dc-4530-b59b-59568d660380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633321920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.633321920
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1775642907
Short name T674
Test name
Test status
Simulation time 6160338093 ps
CPU time 21.23 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:13:44 PM PST 23
Peak memory 199664 kb
Host smart-5109d7db-bec7-4e2b-b542-9f8d47687b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775642907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1775642907
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.4137302382
Short name T617
Test name
Test status
Simulation time 949110221874 ps
CPU time 508.78 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:21:57 PM PST 23
Peak memory 208720 kb
Host smart-370ada6a-15e4-4e78-b7e8-efc2a43f6fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137302382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4137302382
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4183839330
Short name T540
Test name
Test status
Simulation time 1665064389 ps
CPU time 2.99 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:32 PM PST 23
Peak memory 198920 kb
Host smart-5e1d2a85-7264-4ecb-bf8b-9b2de0c8a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183839330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4183839330
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3369305882
Short name T768
Test name
Test status
Simulation time 22903421098 ps
CPU time 13.7 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 198592 kb
Host smart-48ed8220-3be9-4019-83fc-98889c090748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369305882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3369305882
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.69068226
Short name T1040
Test name
Test status
Simulation time 44720674147 ps
CPU time 15.68 seconds
Started Dec 31 01:15:50 PM PST 23
Finished Dec 31 01:16:07 PM PST 23
Peak memory 200120 kb
Host smart-445ddc94-a1be-49a4-b39e-fb0d0e436ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69068226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.69068226
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2615942423
Short name T1041
Test name
Test status
Simulation time 25290992360 ps
CPU time 24.7 seconds
Started Dec 31 01:15:38 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 200024 kb
Host smart-624be6ca-8476-40d2-b5cb-8702180f9ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615942423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2615942423
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1462994384
Short name T207
Test name
Test status
Simulation time 18937314987 ps
CPU time 16.53 seconds
Started Dec 31 01:15:52 PM PST 23
Finished Dec 31 01:16:09 PM PST 23
Peak memory 200004 kb
Host smart-49521081-f047-4fca-a1ab-14754c4e1aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462994384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1462994384
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3105255362
Short name T228
Test name
Test status
Simulation time 168980103230 ps
CPU time 28.87 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 199932 kb
Host smart-c32d0c3e-28b7-42e3-bee4-3ec927f95653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105255362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3105255362
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2157999664
Short name T150
Test name
Test status
Simulation time 129479795320 ps
CPU time 55.65 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:43 PM PST 23
Peak memory 200028 kb
Host smart-07124d11-64b7-48e4-8c7d-22bdbf2480b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157999664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2157999664
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3538270991
Short name T258
Test name
Test status
Simulation time 177653877843 ps
CPU time 50.95 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:41 PM PST 23
Peak memory 200188 kb
Host smart-f84c9f67-82c3-4b61-b381-69bcd2fd8f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538270991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3538270991
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3270944635
Short name T319
Test name
Test status
Simulation time 63765561988 ps
CPU time 27.66 seconds
Started Dec 31 01:15:37 PM PST 23
Finished Dec 31 01:16:06 PM PST 23
Peak memory 200120 kb
Host smart-ba1673a1-7f0c-47eb-8100-7849c7bc13e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270944635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3270944635
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2478622738
Short name T333
Test name
Test status
Simulation time 24836044416 ps
CPU time 45.46 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:35 PM PST 23
Peak memory 200208 kb
Host smart-0ac7533a-12fd-46de-b055-2c19a2df8909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478622738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2478622738
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.718631336
Short name T1203
Test name
Test status
Simulation time 98046261442 ps
CPU time 138.46 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:18:09 PM PST 23
Peak memory 200220 kb
Host smart-0ef5aa13-46cd-4060-8e72-86d18342462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718631336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.718631336
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1995045211
Short name T687
Test name
Test status
Simulation time 12165292 ps
CPU time 0.56 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 195704 kb
Host smart-8b6d4f7c-24fe-441b-8dbb-2f485b8e22df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995045211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1995045211
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2307332751
Short name T267
Test name
Test status
Simulation time 57152836783 ps
CPU time 24.72 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 200216 kb
Host smart-05438209-747b-472a-b80b-ad6b8e23643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307332751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2307332751
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.22866632
Short name T858
Test name
Test status
Simulation time 239036414174 ps
CPU time 341.15 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:19:19 PM PST 23
Peak memory 200136 kb
Host smart-ccf3ed7b-1802-48ac-ad30-18602c64a5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22866632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.22866632
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3334990339
Short name T154
Test name
Test status
Simulation time 43105272774 ps
CPU time 35.84 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:14:14 PM PST 23
Peak memory 199364 kb
Host smart-5aee65fb-5c60-4f67-be81-903f68e2b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334990339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3334990339
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.876737074
Short name T680
Test name
Test status
Simulation time 432387061202 ps
CPU time 550.72 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:22:43 PM PST 23
Peak memory 200244 kb
Host smart-03e7f4cc-6abf-4d9e-b768-b9667dada944
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876737074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.876737074
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3017604492
Short name T317
Test name
Test status
Simulation time 75972164903 ps
CPU time 350.79 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:19:28 PM PST 23
Peak memory 200160 kb
Host smart-589827e4-bc25-4a15-8f69-05dea80ca9d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017604492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3017604492
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3691572168
Short name T895
Test name
Test status
Simulation time 263688948713 ps
CPU time 64.36 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:14:41 PM PST 23
Peak memory 208636 kb
Host smart-4a4e4cf9-5ed7-4b31-b1a3-2927711c2568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691572168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3691572168
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1189508756
Short name T898
Test name
Test status
Simulation time 32571061041 ps
CPU time 268.89 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:18:05 PM PST 23
Peak memory 200228 kb
Host smart-418228c1-5d08-46fd-87d2-33b1fe938510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189508756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1189508756
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3572049290
Short name T656
Test name
Test status
Simulation time 1177816505 ps
CPU time 6.42 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 198240 kb
Host smart-2e1e6d5b-e05e-44ba-9529-57e2e6b43f47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572049290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3572049290
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.143277563
Short name T887
Test name
Test status
Simulation time 23892389875 ps
CPU time 49.96 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:14:25 PM PST 23
Peak memory 200156 kb
Host smart-1841a211-131f-4343-bb62-0fe942e94cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143277563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.143277563
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.759632567
Short name T1237
Test name
Test status
Simulation time 4206893835 ps
CPU time 7.16 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:42 PM PST 23
Peak memory 195924 kb
Host smart-8584b14a-e5b3-4e3b-a71a-bd7985616169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759632567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.759632567
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3641900768
Short name T860
Test name
Test status
Simulation time 118340233 ps
CPU time 0.79 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 196824 kb
Host smart-39514b89-9fd2-4108-ac32-ca4e59e26679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641900768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3641900768
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3356145724
Short name T868
Test name
Test status
Simulation time 60359430937 ps
CPU time 314.24 seconds
Started Dec 31 01:13:18 PM PST 23
Finished Dec 31 01:18:36 PM PST 23
Peak memory 200216 kb
Host smart-92c99264-cb7e-464f-a5b4-3bf2a053c30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356145724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3356145724
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.904676215
Short name T711
Test name
Test status
Simulation time 39302034640 ps
CPU time 108.23 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 215752 kb
Host smart-a1ca8f4f-b3eb-4b0c-9744-bf00cd40d529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904676215 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.904676215
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3419742500
Short name T1210
Test name
Test status
Simulation time 7131078634 ps
CPU time 22.79 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:56 PM PST 23
Peak memory 200120 kb
Host smart-fb80fc82-d516-4e9a-9bce-e8d7ad60d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419742500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3419742500
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1202481304
Short name T859
Test name
Test status
Simulation time 14553472920 ps
CPU time 16.07 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 200080 kb
Host smart-cfe09cfc-7857-4b38-87b3-a7176efc32fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202481304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1202481304
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2071048703
Short name T783
Test name
Test status
Simulation time 49328761181 ps
CPU time 81.97 seconds
Started Dec 31 01:15:53 PM PST 23
Finished Dec 31 01:17:16 PM PST 23
Peak memory 200272 kb
Host smart-2d22f296-6113-4254-83c6-e9cf6eefe49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071048703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2071048703
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2010097448
Short name T716
Test name
Test status
Simulation time 36580428160 ps
CPU time 16.45 seconds
Started Dec 31 01:15:54 PM PST 23
Finished Dec 31 01:16:12 PM PST 23
Peak memory 199632 kb
Host smart-02933b9a-f70d-4e60-8580-e854d1df7867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010097448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2010097448
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3398548214
Short name T192
Test name
Test status
Simulation time 20287253966 ps
CPU time 34.23 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:24 PM PST 23
Peak memory 199868 kb
Host smart-f72d14c5-5ce9-498b-a0c6-6d17e193106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398548214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3398548214
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3496085509
Short name T1163
Test name
Test status
Simulation time 107940040125 ps
CPU time 153.09 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:18:22 PM PST 23
Peak memory 200232 kb
Host smart-42504e53-1a8d-407f-b91d-a47295a3ab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496085509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3496085509
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.461059131
Short name T993
Test name
Test status
Simulation time 75712259864 ps
CPU time 30.36 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 200176 kb
Host smart-61d9dec4-2f40-445b-a7c7-80e09cfe8b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461059131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.461059131
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3041569881
Short name T198
Test name
Test status
Simulation time 22340622453 ps
CPU time 54.5 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:43 PM PST 23
Peak memory 200232 kb
Host smart-5a2ae3b1-40a6-4bde-a64b-c0ae1e369199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041569881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3041569881
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.775503376
Short name T212
Test name
Test status
Simulation time 116409827865 ps
CPU time 174.81 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:18:41 PM PST 23
Peak memory 199836 kb
Host smart-39e24677-fc48-4276-8ec3-8f2aea34904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775503376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.775503376
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3627853184
Short name T286
Test name
Test status
Simulation time 12803393408 ps
CPU time 20.49 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:10 PM PST 23
Peak memory 200112 kb
Host smart-fd93784a-8d4b-4892-b169-8d0aa6761063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627853184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3627853184
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.666197486
Short name T675
Test name
Test status
Simulation time 108768014027 ps
CPU time 38.03 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:28 PM PST 23
Peak memory 199720 kb
Host smart-6ad8183b-e84a-4d20-ab6d-753d712dea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666197486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.666197486
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3748122094
Short name T1174
Test name
Test status
Simulation time 16597802 ps
CPU time 0.55 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 194688 kb
Host smart-0d8f62d9-0bde-41df-8350-955870449f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748122094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3748122094
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.53867521
Short name T243
Test name
Test status
Simulation time 38185091885 ps
CPU time 59.7 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:14:28 PM PST 23
Peak memory 200268 kb
Host smart-ea2d8a76-0846-49b7-b7e6-5c1086845947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53867521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.53867521
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.376072047
Short name T733
Test name
Test status
Simulation time 12799869934 ps
CPU time 59.1 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:14:33 PM PST 23
Peak memory 200208 kb
Host smart-54afe337-1df1-4815-b547-cbbc69738ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376072047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.376072047
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2751675362
Short name T336
Test name
Test status
Simulation time 21956890447 ps
CPU time 16.49 seconds
Started Dec 31 01:13:30 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 199524 kb
Host smart-c0b44298-4da5-4d6c-b7d7-35f446d94a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751675362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2751675362
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1509050353
Short name T686
Test name
Test status
Simulation time 1167185945697 ps
CPU time 542.51 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:22:31 PM PST 23
Peak memory 198876 kb
Host smart-ce0fe77a-b250-49d4-9498-8bc89493083b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509050353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1509050353
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1825574365
Short name T807
Test name
Test status
Simulation time 114429088711 ps
CPU time 380.93 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:19:44 PM PST 23
Peak memory 200224 kb
Host smart-e87fa5df-b60b-41c8-862a-f8ecb8eff212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825574365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1825574365
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2966289626
Short name T948
Test name
Test status
Simulation time 7246275756 ps
CPU time 16.49 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:40 PM PST 23
Peak memory 199276 kb
Host smart-e99d4291-fa1d-4547-9c39-fd6b7cfd04bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966289626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2966289626
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1685653052
Short name T1235
Test name
Test status
Simulation time 114706739527 ps
CPU time 55.95 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:14:22 PM PST 23
Peak memory 200480 kb
Host smart-738e690a-b834-45fd-8230-91891208adec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685653052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1685653052
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1539943484
Short name T692
Test name
Test status
Simulation time 4744640958 ps
CPU time 264.54 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:17:56 PM PST 23
Peak memory 200168 kb
Host smart-7ebfb5b7-d17d-4cac-9f3f-60eb566fa9e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539943484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1539943484
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.4067355096
Short name T376
Test name
Test status
Simulation time 195578677564 ps
CPU time 112.74 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 200216 kb
Host smart-1db6dfcc-bbdc-4f90-913b-a3f1d98fcf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067355096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.4067355096
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1656042313
Short name T449
Test name
Test status
Simulation time 1468763339 ps
CPU time 2.99 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:30 PM PST 23
Peak memory 195648 kb
Host smart-7283eca2-9033-410e-a083-bfc79be89eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656042313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1656042313
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.503999391
Short name T678
Test name
Test status
Simulation time 120987970 ps
CPU time 0.75 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 197000 kb
Host smart-26a31d76-d106-4158-a15e-71650e78ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503999391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.503999391
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3867027257
Short name T28
Test name
Test status
Simulation time 105959371572 ps
CPU time 184.14 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:16:38 PM PST 23
Peak memory 208744 kb
Host smart-85764dd5-35ae-4a45-83a1-ea14ad4ff4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867027257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3867027257
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3227204020
Short name T390
Test name
Test status
Simulation time 112799775859 ps
CPU time 346.93 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:19:14 PM PST 23
Peak memory 216908 kb
Host smart-14a4cb06-eb40-4d3e-84ec-dbaa1a9d769e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227204020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3227204020
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1129452260
Short name T481
Test name
Test status
Simulation time 7166635119 ps
CPU time 23.61 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 200056 kb
Host smart-dd87a488-06d4-461a-bca8-2a4db5353dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129452260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1129452260
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.544826531
Short name T1184
Test name
Test status
Simulation time 15510495611 ps
CPU time 24.5 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:14:01 PM PST 23
Peak memory 200244 kb
Host smart-8880c2db-2b7f-4578-96a7-51c4af1f7be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544826531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.544826531
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2793872706
Short name T262
Test name
Test status
Simulation time 131589640486 ps
CPU time 239.33 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:19:46 PM PST 23
Peak memory 200144 kb
Host smart-2f835414-5ca1-43dd-8f75-dba4f8040451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793872706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2793872706
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1810834348
Short name T205
Test name
Test status
Simulation time 57941544938 ps
CPU time 28.66 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 200084 kb
Host smart-ea0df378-27f7-40e7-b735-a3c918def540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810834348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1810834348
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3697763857
Short name T565
Test name
Test status
Simulation time 33482083003 ps
CPU time 13.4 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:01 PM PST 23
Peak memory 200220 kb
Host smart-80d37f75-2a94-4738-9fd5-5e0e966f0ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697763857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3697763857
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3319675284
Short name T1056
Test name
Test status
Simulation time 145256738798 ps
CPU time 28.11 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 200188 kb
Host smart-4ea77bf3-31d2-4d5b-9c13-f7140bc0dcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319675284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3319675284
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.276226398
Short name T224
Test name
Test status
Simulation time 33940863297 ps
CPU time 30.43 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 199956 kb
Host smart-1b20d5a2-377c-4442-b098-863cd191b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276226398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.276226398
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2191154515
Short name T166
Test name
Test status
Simulation time 19023787709 ps
CPU time 16.52 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 199328 kb
Host smart-59d6a8c1-8c8a-4bdf-9c15-d2dc4c75d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191154515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2191154515
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3674305795
Short name T246
Test name
Test status
Simulation time 73996116783 ps
CPU time 125.57 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:17:52 PM PST 23
Peak memory 199656 kb
Host smart-781cfdfd-5acf-4f9c-a098-99468b04dddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674305795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3674305795
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2797266751
Short name T162
Test name
Test status
Simulation time 65967875759 ps
CPU time 35.14 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:23 PM PST 23
Peak memory 200220 kb
Host smart-fb52c760-89b0-47e8-9111-a93e7c5df98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797266751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2797266751
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3766967190
Short name T248
Test name
Test status
Simulation time 39259012376 ps
CPU time 30.1 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:16 PM PST 23
Peak memory 200236 kb
Host smart-dbe7008c-a54d-4a2f-94e9-fbbd234a2d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766967190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3766967190
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.511505988
Short name T610
Test name
Test status
Simulation time 14394306 ps
CPU time 0.55 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:31 PM PST 23
Peak memory 195608 kb
Host smart-51109e69-cda4-45b1-8974-737224ca6b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511505988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.511505988
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1540773532
Short name T862
Test name
Test status
Simulation time 369756027049 ps
CPU time 44.41 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:14:10 PM PST 23
Peak memory 200248 kb
Host smart-f7e73e9b-1d9d-4698-ac00-eca77f4ce607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540773532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1540773532
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2006870887
Short name T575
Test name
Test status
Simulation time 34711279651 ps
CPU time 74.9 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 200216 kb
Host smart-9b629c28-9e8c-439c-9f96-3c0fbf3cb6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006870887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2006870887
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.131788830
Short name T294
Test name
Test status
Simulation time 25172215991 ps
CPU time 40.85 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:14:17 PM PST 23
Peak memory 200172 kb
Host smart-c8e56dab-ea1f-4f69-84eb-18a3fdda5b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131788830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.131788830
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.837036649
Short name T554
Test name
Test status
Simulation time 1512752274 ps
CPU time 1.28 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:32 PM PST 23
Peak memory 195656 kb
Host smart-b0bf99b7-eda2-42a3-b17d-12806a00c1c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837036649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.837036649
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.561507457
Short name T601
Test name
Test status
Simulation time 167763708617 ps
CPU time 1568.27 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:39:46 PM PST 23
Peak memory 200116 kb
Host smart-e83f6fbd-2031-4192-aadf-67b6a07beac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561507457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.561507457
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2498605821
Short name T902
Test name
Test status
Simulation time 7803576411 ps
CPU time 13.04 seconds
Started Dec 31 01:13:30 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 199968 kb
Host smart-adbb54dc-55e5-46d6-8f01-1bb3f8dbdec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498605821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2498605821
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1489868936
Short name T1105
Test name
Test status
Simulation time 61079461829 ps
CPU time 56.59 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:14:28 PM PST 23
Peak memory 200588 kb
Host smart-459c7629-4705-41dd-a6d2-b9dd81a221d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489868936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1489868936
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3044250155
Short name T313
Test name
Test status
Simulation time 37987135514 ps
CPU time 100.35 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:15:11 PM PST 23
Peak memory 200188 kb
Host smart-d525ee9e-a132-473d-bd40-37bce087bbbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044250155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3044250155
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.636618332
Short name T589
Test name
Test status
Simulation time 2455045495 ps
CPU time 9.82 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 196864 kb
Host smart-01496d29-43cb-4b81-8544-3024abbef73b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636618332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.636618332
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2908143507
Short name T366
Test name
Test status
Simulation time 35830723932 ps
CPU time 34.67 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:14:06 PM PST 23
Peak memory 200052 kb
Host smart-334dc04c-9ec4-440a-9a12-7963015e5c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908143507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2908143507
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1481495194
Short name T797
Test name
Test status
Simulation time 1392441897 ps
CPU time 1.65 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:35 PM PST 23
Peak memory 195504 kb
Host smart-d98bca88-a85c-40c9-b397-27d136155298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481495194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1481495194
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1679653188
Short name T444
Test name
Test status
Simulation time 5357438099 ps
CPU time 11.74 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 200216 kb
Host smart-d970de77-3a11-4217-95dd-49e8a38f7738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679653188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1679653188
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2050465760
Short name T556
Test name
Test status
Simulation time 292404882329 ps
CPU time 862.34 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:27:59 PM PST 23
Peak memory 200156 kb
Host smart-c1dc5b3a-84d2-4e96-8fe2-6ccdcd1415b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050465760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2050465760
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1645828571
Short name T792
Test name
Test status
Simulation time 1000452476385 ps
CPU time 618.59 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:23:56 PM PST 23
Peak memory 216628 kb
Host smart-98325522-c577-4805-9e75-7c5dc823d117
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645828571 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1645828571
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3377598214
Short name T533
Test name
Test status
Simulation time 843657591 ps
CPU time 2.4 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 198548 kb
Host smart-26c1695d-d515-4783-a2e2-7d6ac252bbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377598214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3377598214
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.809187795
Short name T1185
Test name
Test status
Simulation time 42942929157 ps
CPU time 68.9 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:14:42 PM PST 23
Peak memory 200272 kb
Host smart-455cd427-9274-4a6b-a53a-0fe27f44a0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809187795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.809187795
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.911477599
Short name T873
Test name
Test status
Simulation time 11857447418 ps
CPU time 19.66 seconds
Started Dec 31 01:15:54 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 198364 kb
Host smart-c2027d05-4c52-4549-b9fd-a6b81c043a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911477599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.911477599
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1114276865
Short name T235
Test name
Test status
Simulation time 12710318918 ps
CPU time 22.97 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:13 PM PST 23
Peak memory 199456 kb
Host smart-2f81ba7d-dc69-41cd-82c2-b2fcacf48fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114276865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1114276865
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3740683598
Short name T16
Test name
Test status
Simulation time 25365618724 ps
CPU time 40.12 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:27 PM PST 23
Peak memory 199732 kb
Host smart-a0e5894e-1788-43d2-a5c9-2d3a7e5ce4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740683598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3740683598
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1199274908
Short name T553
Test name
Test status
Simulation time 61845448665 ps
CPU time 27.99 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 197372 kb
Host smart-a497b8bb-2ebd-4dfc-adb7-426c49d90f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199274908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1199274908
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1648626656
Short name T323
Test name
Test status
Simulation time 75316128567 ps
CPU time 108.25 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:17:36 PM PST 23
Peak memory 200256 kb
Host smart-9ab9047d-796b-460e-9523-abcc8fbb4d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648626656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1648626656
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2987206220
Short name T127
Test name
Test status
Simulation time 21761366099 ps
CPU time 34.96 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:23 PM PST 23
Peak memory 200244 kb
Host smart-0a390082-589d-48f5-820c-04e2a4927326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987206220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2987206220
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2777063506
Short name T830
Test name
Test status
Simulation time 30369755431 ps
CPU time 25.7 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 200212 kb
Host smart-98c11a42-61d0-47f2-bd6b-1754010639ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777063506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2777063506
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4175804054
Short name T564
Test name
Test status
Simulation time 12912715 ps
CPU time 0.56 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 195632 kb
Host smart-102d03e7-1020-4163-9e8b-b66a6aca0e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175804054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4175804054
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.346447740
Short name T1096
Test name
Test status
Simulation time 91116682371 ps
CPU time 30.21 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:14:10 PM PST 23
Peak memory 200024 kb
Host smart-b8a2e09b-c8ee-4835-9b47-4fa48512ab91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346447740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.346447740
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.535120041
Short name T423
Test name
Test status
Simulation time 124367868538 ps
CPU time 53.99 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:14:31 PM PST 23
Peak memory 199876 kb
Host smart-a3a81114-6b10-4fd5-9861-e20c74567fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535120041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.535120041
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.4149702462
Short name T1047
Test name
Test status
Simulation time 437342079725 ps
CPU time 871.45 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:28:08 PM PST 23
Peak memory 200048 kb
Host smart-eb83bf1a-1fbb-4dad-9eed-cfac05b82bec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149702462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.4149702462
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2323785151
Short name T1167
Test name
Test status
Simulation time 215390335752 ps
CPU time 144.04 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:15:59 PM PST 23
Peak memory 200216 kb
Host smart-57116b49-dad1-4ff7-a57b-3147f0b1293b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323785151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2323785151
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.299130574
Short name T685
Test name
Test status
Simulation time 822310144 ps
CPU time 1.91 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:33 PM PST 23
Peak memory 195908 kb
Host smart-6b7fb910-7b11-4348-854a-30e7734937cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299130574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.299130574
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3567962229
Short name T1031
Test name
Test status
Simulation time 115540563476 ps
CPU time 60.73 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:14:36 PM PST 23
Peak memory 200120 kb
Host smart-70038e45-15cc-4e8e-a02d-934aa3517fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567962229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3567962229
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3807519794
Short name T1188
Test name
Test status
Simulation time 24169282622 ps
CPU time 1259.75 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:34:27 PM PST 23
Peak memory 200444 kb
Host smart-2122e005-6874-4edd-b981-6092d78c1189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807519794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3807519794
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.128814110
Short name T588
Test name
Test status
Simulation time 4596574629 ps
CPU time 10.09 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:44 PM PST 23
Peak memory 199012 kb
Host smart-37db5acc-8b09-4df4-8bc4-d0ae538b8bcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128814110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.128814110
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2181056299
Short name T24
Test name
Test status
Simulation time 262152697995 ps
CPU time 547.76 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:22:42 PM PST 23
Peak memory 200256 kb
Host smart-7bcaf25b-cacb-432f-a7d0-3312708ad07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181056299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2181056299
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3978398393
Short name T441
Test name
Test status
Simulation time 45108990887 ps
CPU time 20.17 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:51 PM PST 23
Peak memory 195680 kb
Host smart-2a71c534-2db9-4def-b957-c6a295418876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978398393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3978398393
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2464512267
Short name T1169
Test name
Test status
Simulation time 5381135172 ps
CPU time 19.1 seconds
Started Dec 31 01:13:25 PM PST 23
Finished Dec 31 01:13:54 PM PST 23
Peak memory 199560 kb
Host smart-0c3de674-feca-45d8-ab34-5440ffc2b3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464512267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2464512267
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1479975913
Short name T125
Test name
Test status
Simulation time 1538591595346 ps
CPU time 2588.45 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:56:41 PM PST 23
Peak memory 200216 kb
Host smart-7a6309e6-5e4f-4eae-bf21-f1e88b4575b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479975913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1479975913
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.967920431
Short name T472
Test name
Test status
Simulation time 41992194849 ps
CPU time 355.64 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:19:31 PM PST 23
Peak memory 216904 kb
Host smart-2a5043be-4f93-4ac7-b9bd-b5406269cf96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967920431 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.967920431
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1678083329
Short name T755
Test name
Test status
Simulation time 834908191 ps
CPU time 1.9 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:34 PM PST 23
Peak memory 198236 kb
Host smart-d69e8649-9c5d-4eef-bb92-082dd0fe00a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678083329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1678083329
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2855299824
Short name T1054
Test name
Test status
Simulation time 16900709348 ps
CPU time 13.87 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 198288 kb
Host smart-47cd1bf4-434b-439e-812c-a69869a372df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855299824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2855299824
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3649455131
Short name T1026
Test name
Test status
Simulation time 165066019604 ps
CPU time 60.87 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:47 PM PST 23
Peak memory 199792 kb
Host smart-15a9a6ac-c9c5-47ca-92ce-2193dfc3c1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649455131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3649455131
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.4273931080
Short name T1123
Test name
Test status
Simulation time 55649215580 ps
CPU time 43.35 seconds
Started Dec 31 01:15:51 PM PST 23
Finished Dec 31 01:16:35 PM PST 23
Peak memory 200148 kb
Host smart-a98057e0-490d-4829-9b5a-a52107a92c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273931080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.4273931080
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3073535501
Short name T878
Test name
Test status
Simulation time 54259348808 ps
CPU time 24.32 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:11 PM PST 23
Peak memory 200156 kb
Host smart-a670e7b5-45a3-4d2e-8310-206a10e9839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073535501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3073535501
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2575249999
Short name T1092
Test name
Test status
Simulation time 38190128007 ps
CPU time 65.63 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:53 PM PST 23
Peak memory 200012 kb
Host smart-6a3e9cdb-07d7-4527-b8df-3572e899e834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575249999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2575249999
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4110299112
Short name T1066
Test name
Test status
Simulation time 32487693382 ps
CPU time 41.83 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:31 PM PST 23
Peak memory 200224 kb
Host smart-003be067-797f-4449-85fc-4df4fb1e628d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110299112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4110299112
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.4181809201
Short name T838
Test name
Test status
Simulation time 34096168976 ps
CPU time 29.13 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:18 PM PST 23
Peak memory 200124 kb
Host smart-2787c3cf-ed91-4634-b356-8db9433f1905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181809201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4181809201
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2941664228
Short name T353
Test name
Test status
Simulation time 180353106566 ps
CPU time 154.85 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:18:21 PM PST 23
Peak memory 200204 kb
Host smart-fd37de96-ec3e-40af-a792-3f2092c5fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941664228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2941664228
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.258951171
Short name T94
Test name
Test status
Simulation time 35748093 ps
CPU time 0.58 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 195660 kb
Host smart-ac8db5ec-f6e4-4d6b-9263-7cebd625667e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258951171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.258951171
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.861862868
Short name T400
Test name
Test status
Simulation time 51795427205 ps
CPU time 20.9 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:56 PM PST 23
Peak memory 200084 kb
Host smart-a1222003-271c-4de4-affe-20e848fae99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861862868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.861862868
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.698895633
Short name T658
Test name
Test status
Simulation time 282512206931 ps
CPU time 141.5 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200284 kb
Host smart-d9250eb1-562c-4e60-bfcb-a0dc1a78d00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698895633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.698895633
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1040803046
Short name T727
Test name
Test status
Simulation time 22405309268 ps
CPU time 11.83 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 199960 kb
Host smart-3de54b89-7419-45aa-a533-844ddf6bc9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040803046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1040803046
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.4243699711
Short name T751
Test name
Test status
Simulation time 953422574271 ps
CPU time 312.93 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:18:40 PM PST 23
Peak memory 199664 kb
Host smart-5277dfb5-7043-4f65-a13f-ae43ff1ed055
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243699711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4243699711
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.38830065
Short name T573
Test name
Test status
Simulation time 100559730703 ps
CPU time 438.74 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:20:47 PM PST 23
Peak memory 200208 kb
Host smart-5fb1a3e9-ff27-4c44-a496-72bcc367e4ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38830065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.38830065
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3334959502
Short name T645
Test name
Test status
Simulation time 6883850574 ps
CPU time 11.2 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:42 PM PST 23
Peak memory 198368 kb
Host smart-f19b8718-4dd0-403d-9193-750c5e5f2715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334959502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3334959502
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.996373130
Short name T731
Test name
Test status
Simulation time 80699687240 ps
CPU time 44.46 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:14:21 PM PST 23
Peak memory 208484 kb
Host smart-a310aacf-4e49-4a6c-b1ae-7910d28c6e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996373130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.996373130
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1959482082
Short name T1094
Test name
Test status
Simulation time 24329813877 ps
CPU time 323.83 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:18:53 PM PST 23
Peak memory 200208 kb
Host smart-ade167e2-9acf-4454-9f4d-869801b5867c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959482082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1959482082
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.478769618
Short name T602
Test name
Test status
Simulation time 2037002297 ps
CPU time 5.27 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 198392 kb
Host smart-0693bbd3-9e29-4fa2-bf66-d13092efc5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478769618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.478769618
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1664615009
Short name T241
Test name
Test status
Simulation time 35829120544 ps
CPU time 60.37 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:14:38 PM PST 23
Peak memory 199556 kb
Host smart-1db77abb-3f46-497b-9908-14d1b01476ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664615009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1664615009
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1674357567
Short name T1121
Test name
Test status
Simulation time 2287917897 ps
CPU time 4 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:29 PM PST 23
Peak memory 195800 kb
Host smart-349b0a99-d964-450a-bf80-7d71aac1299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674357567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1674357567
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3353362544
Short name T1049
Test name
Test status
Simulation time 517705537 ps
CPU time 2.17 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:37 PM PST 23
Peak memory 198128 kb
Host smart-26e8fa66-fa8f-4890-ba17-416275396a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353362544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3353362544
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.714175849
Short name T850
Test name
Test status
Simulation time 69543225057 ps
CPU time 59.17 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:14:32 PM PST 23
Peak memory 200228 kb
Host smart-17441244-5d3b-44b7-9fda-49651084f043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714175849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.714175849
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3169018985
Short name T649
Test name
Test status
Simulation time 7055771960 ps
CPU time 15.36 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 199656 kb
Host smart-9539cdb8-0a59-450f-990d-543e487cb62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169018985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3169018985
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2974362948
Short name T914
Test name
Test status
Simulation time 59184254772 ps
CPU time 81.97 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:14:53 PM PST 23
Peak memory 200248 kb
Host smart-089fb130-6c5e-4e7f-af83-93e3fdab10e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974362948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2974362948
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2763048497
Short name T169
Test name
Test status
Simulation time 157440927642 ps
CPU time 65.15 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:54 PM PST 23
Peak memory 200392 kb
Host smart-b4e87965-06b4-43df-affa-117882a754ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763048497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2763048497
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3572421576
Short name T1119
Test name
Test status
Simulation time 35127778752 ps
CPU time 27.22 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 200172 kb
Host smart-49244aff-c13c-4d91-b4f9-66d24364ba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572421576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3572421576
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2942429447
Short name T994
Test name
Test status
Simulation time 48455018769 ps
CPU time 21.87 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:08 PM PST 23
Peak memory 200252 kb
Host smart-b8563a4c-0eac-4d96-939a-2f11d6eb83e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942429447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2942429447
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1185955956
Short name T604
Test name
Test status
Simulation time 156159793957 ps
CPU time 55.93 seconds
Started Dec 31 01:15:44 PM PST 23
Finished Dec 31 01:16:41 PM PST 23
Peak memory 200216 kb
Host smart-53455198-1436-47f3-894d-4f8a29d7d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185955956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1185955956
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.189674723
Short name T1013
Test name
Test status
Simulation time 10166921072 ps
CPU time 15.06 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200180 kb
Host smart-adfc47e1-b204-484a-9ecf-3d855d102e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189674723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.189674723
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2689296479
Short name T337
Test name
Test status
Simulation time 35759319381 ps
CPU time 14.26 seconds
Started Dec 31 01:15:44 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200132 kb
Host smart-5a77dbea-9845-4352-9bdb-eb170faeaa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689296479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2689296479
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.244434932
Short name T718
Test name
Test status
Simulation time 93522196296 ps
CPU time 79.03 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:17:09 PM PST 23
Peak memory 200188 kb
Host smart-9ec2a71a-132b-4d7c-b492-bc3f13ea8764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244434932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.244434932
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2900027336
Short name T406
Test name
Test status
Simulation time 44156452658 ps
CPU time 19.37 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:16:10 PM PST 23
Peak memory 200220 kb
Host smart-d03debd7-2c3a-4cc1-aee1-17e207c7fbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900027336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2900027336
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3048070627
Short name T95
Test name
Test status
Simulation time 34527897 ps
CPU time 0.52 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:34 PM PST 23
Peak memory 194636 kb
Host smart-50fbc1d4-2842-43ee-9ef2-5df23f6440dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048070627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3048070627
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3948718976
Short name T1216
Test name
Test status
Simulation time 40028581532 ps
CPU time 13.49 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:13:44 PM PST 23
Peak memory 200188 kb
Host smart-b8df3a08-c20b-4147-95a2-6f109e537047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948718976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3948718976
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2968295815
Short name T866
Test name
Test status
Simulation time 7109775718 ps
CPU time 6.55 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:13:45 PM PST 23
Peak memory 198680 kb
Host smart-c3d53307-ea4b-45f1-99ad-73a5bf300972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968295815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2968295815
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1822397993
Short name T279
Test name
Test status
Simulation time 35703398050 ps
CPU time 30.07 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:14:04 PM PST 23
Peak memory 200356 kb
Host smart-0fe5876a-fcab-4a08-a6ce-ebc48a6c6031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822397993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1822397993
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3375624356
Short name T555
Test name
Test status
Simulation time 80924889027 ps
CPU time 38.26 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:14:14 PM PST 23
Peak memory 199392 kb
Host smart-f47a5c46-8d80-4aef-b105-3d44bcb42849
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375624356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3375624356
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1809684010
Short name T681
Test name
Test status
Simulation time 152970123814 ps
CPU time 545.09 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:22:39 PM PST 23
Peak memory 200192 kb
Host smart-a9e9ac78-8946-476f-a624-6b2edbf144b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809684010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1809684010
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.4125207081
Short name T584
Test name
Test status
Simulation time 7352410352 ps
CPU time 5.37 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:13:45 PM PST 23
Peak memory 198788 kb
Host smart-bd79a231-b283-4ae2-bc83-dd86f39915e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125207081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4125207081
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.3265298420
Short name T1200
Test name
Test status
Simulation time 171964428034 ps
CPU time 210.32 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:17:02 PM PST 23
Peak memory 200368 kb
Host smart-9c79f5e2-03f1-4b27-abc3-df0cc1e34235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265298420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3265298420
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1791984788
Short name T1024
Test name
Test status
Simulation time 5937415685 ps
CPU time 171.53 seconds
Started Dec 31 01:13:30 PM PST 23
Finished Dec 31 01:16:31 PM PST 23
Peak memory 200240 kb
Host smart-b673e5b6-9d5e-4ca8-bdb0-91cb0240a357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791984788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1791984788
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2438662697
Short name T800
Test name
Test status
Simulation time 3250315145 ps
CPU time 23.64 seconds
Started Dec 31 01:13:20 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 198172 kb
Host smart-983da84c-ff41-4b6f-9f6e-8556c5b0ca1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438662697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2438662697
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1687026124
Short name T684
Test name
Test status
Simulation time 231529973516 ps
CPU time 96.6 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:15:13 PM PST 23
Peak memory 200016 kb
Host smart-62026617-c950-4b76-839e-61d26d71ce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687026124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1687026124
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3826540922
Short name T677
Test name
Test status
Simulation time 3399420643 ps
CPU time 5.83 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 195944 kb
Host smart-360336e2-e597-477b-8378-00945611bef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826540922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3826540922
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2987881950
Short name T613
Test name
Test status
Simulation time 558289078 ps
CPU time 2.76 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 198672 kb
Host smart-81a8eb20-20fe-4cfb-9aa3-ae3b2b48283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987881950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2987881950
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1595896754
Short name T1156
Test name
Test status
Simulation time 225704317152 ps
CPU time 338.64 seconds
Started Dec 31 01:13:21 PM PST 23
Finished Dec 31 01:19:06 PM PST 23
Peak memory 200256 kb
Host smart-986c92ee-6248-44c6-95f1-543fadf95862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595896754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1595896754
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2803951069
Short name T928
Test name
Test status
Simulation time 72951845545 ps
CPU time 1249.18 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:34:22 PM PST 23
Peak memory 225368 kb
Host smart-02650ee6-ab4f-4b59-b17a-f545bc0154ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803951069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2803951069
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4268470627
Short name T460
Test name
Test status
Simulation time 6921258249 ps
CPU time 16.4 seconds
Started Dec 31 01:13:24 PM PST 23
Finished Dec 31 01:13:50 PM PST 23
Peak memory 199876 kb
Host smart-87507d72-82c8-4791-9dd3-24a850a49b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268470627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4268470627
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.974063602
Short name T839
Test name
Test status
Simulation time 37711011152 ps
CPU time 31.18 seconds
Started Dec 31 01:13:19 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 200092 kb
Host smart-71712364-34bd-42c9-86fe-df4cf049d534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974063602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.974063602
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.333626681
Short name T329
Test name
Test status
Simulation time 38655905770 ps
CPU time 19.74 seconds
Started Dec 31 01:15:51 PM PST 23
Finished Dec 31 01:16:12 PM PST 23
Peak memory 200144 kb
Host smart-3a9baabc-9a14-454a-8df2-234536bacbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333626681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.333626681
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3247732351
Short name T211
Test name
Test status
Simulation time 14768273751 ps
CPU time 34.59 seconds
Started Dec 31 01:15:44 PM PST 23
Finished Dec 31 01:16:19 PM PST 23
Peak memory 200132 kb
Host smart-632c92a1-1bb2-439a-9ae7-48652035b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247732351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3247732351
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1653580098
Short name T978
Test name
Test status
Simulation time 36333078990 ps
CPU time 16.38 seconds
Started Dec 31 01:15:45 PM PST 23
Finished Dec 31 01:16:02 PM PST 23
Peak memory 200028 kb
Host smart-664b797e-123a-4ac5-a053-048d9500b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653580098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1653580098
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1867606329
Short name T280
Test name
Test status
Simulation time 95826104724 ps
CPU time 52.68 seconds
Started Dec 31 01:15:46 PM PST 23
Finished Dec 31 01:16:40 PM PST 23
Peak memory 200036 kb
Host smart-100d3e64-f317-4971-86b9-f0549950d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867606329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1867606329
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.4021851952
Short name T299
Test name
Test status
Simulation time 28218128114 ps
CPU time 12.3 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:01 PM PST 23
Peak memory 199348 kb
Host smart-f265f9f5-f8e7-4418-9ecc-b733ae1d84dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021851952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.4021851952
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1164564286
Short name T121
Test name
Test status
Simulation time 41357872629 ps
CPU time 16.04 seconds
Started Dec 31 01:15:55 PM PST 23
Finished Dec 31 01:16:12 PM PST 23
Peak memory 200016 kb
Host smart-83350ad7-dce9-423a-8c79-da83811fdd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164564286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1164564286
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2167659873
Short name T897
Test name
Test status
Simulation time 11881678 ps
CPU time 0.55 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 195580 kb
Host smart-19c39f8e-74ef-478f-8369-f3245c990b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167659873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2167659873
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.188651655
Short name T673
Test name
Test status
Simulation time 36740363293 ps
CPU time 15.31 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 199820 kb
Host smart-92fd00c4-ed69-42e5-a45e-b054bee736bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188651655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.188651655
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3738212032
Short name T1173
Test name
Test status
Simulation time 83913397206 ps
CPU time 65.96 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:14:45 PM PST 23
Peak memory 200252 kb
Host smart-85165200-d92e-4f11-af0f-c5b2ba0bf5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738212032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3738212032
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.469590930
Short name T1080
Test name
Test status
Simulation time 99570900279 ps
CPU time 38.37 seconds
Started Dec 31 01:13:23 PM PST 23
Finished Dec 31 01:14:11 PM PST 23
Peak memory 200232 kb
Host smart-adca64c7-436a-480c-b417-8fbebf06b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469590930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.469590930
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1441741722
Short name T1074
Test name
Test status
Simulation time 2143896544498 ps
CPU time 1645.41 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:41:03 PM PST 23
Peak memory 200132 kb
Host smart-6bb28a7a-c6e7-477c-a3cd-d801e9ee82a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441741722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1441741722
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2507275004
Short name T597
Test name
Test status
Simulation time 188377945467 ps
CPU time 1325.84 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:35:43 PM PST 23
Peak memory 200180 kb
Host smart-fcae2d79-f839-45fa-8eac-7e4326115d1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507275004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2507275004
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2478130872
Short name T631
Test name
Test status
Simulation time 2877250777 ps
CPU time 2.14 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 198976 kb
Host smart-a6587880-3146-4275-9334-6cdd9f83c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478130872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2478130872
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1137272259
Short name T451
Test name
Test status
Simulation time 244924679591 ps
CPU time 247.17 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:17:47 PM PST 23
Peak memory 208684 kb
Host smart-7d7d174e-002e-4b08-9db2-af95cc0b5a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137272259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1137272259
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2747409178
Short name T1115
Test name
Test status
Simulation time 21676228526 ps
CPU time 536.31 seconds
Started Dec 31 01:13:22 PM PST 23
Finished Dec 31 01:22:26 PM PST 23
Peak memory 200216 kb
Host smart-a36e9112-1284-454a-beaf-0ac2ce4fe6b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747409178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2747409178
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3266693621
Short name T1048
Test name
Test status
Simulation time 3298577532 ps
CPU time 23.71 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:14:00 PM PST 23
Peak memory 198672 kb
Host smart-90448db7-426a-4078-bb7c-2d52e794fbdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266693621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3266693621
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1246565684
Short name T230
Test name
Test status
Simulation time 119262984325 ps
CPU time 46.58 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:14:24 PM PST 23
Peak memory 199892 kb
Host smart-a74957c1-d96b-4342-abfd-ebd2fbbcc954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246565684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1246565684
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3582159460
Short name T793
Test name
Test status
Simulation time 605125817 ps
CPU time 1.68 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 195564 kb
Host smart-459ef311-e819-437d-bf51-6c952e1705ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582159460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3582159460
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3401391076
Short name T431
Test name
Test status
Simulation time 5905725106 ps
CPU time 17.59 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:53 PM PST 23
Peak memory 200156 kb
Host smart-95b2563f-609d-40c2-99a7-ac6d33284625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401391076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3401391076
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.742766959
Short name T1175
Test name
Test status
Simulation time 1492849252618 ps
CPU time 1022.7 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:30:39 PM PST 23
Peak memory 200204 kb
Host smart-dd5ea442-0b1b-4779-bd76-1b2c6d903ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742766959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.742766959
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2596758217
Short name T101
Test name
Test status
Simulation time 93521068597 ps
CPU time 756.86 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:26:14 PM PST 23
Peak memory 216860 kb
Host smart-e08db8f8-444b-48d5-aff1-49399fc7ed5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596758217 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2596758217
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2484609038
Short name T1037
Test name
Test status
Simulation time 1067108396 ps
CPU time 3.78 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:13:43 PM PST 23
Peak memory 200100 kb
Host smart-3e740a2c-a53e-407b-9a0e-32af7748eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484609038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2484609038
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.307858593
Short name T944
Test name
Test status
Simulation time 23849871034 ps
CPU time 13.58 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:51 PM PST 23
Peak memory 200176 kb
Host smart-43aa39b2-5b6b-4633-a958-f12de758d682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307858593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.307858593
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.4022533961
Short name T378
Test name
Test status
Simulation time 92133418406 ps
CPU time 133.96 seconds
Started Dec 31 01:15:50 PM PST 23
Finished Dec 31 01:18:06 PM PST 23
Peak memory 200164 kb
Host smart-ded47e2e-340c-4f83-96d5-1f48baabc98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022533961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.4022533961
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.277850627
Short name T180
Test name
Test status
Simulation time 35593230697 ps
CPU time 16.05 seconds
Started Dec 31 01:15:55 PM PST 23
Finished Dec 31 01:16:12 PM PST 23
Peak memory 199896 kb
Host smart-e0a2e030-5e4f-49ef-978d-710f64895c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277850627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.277850627
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3396205604
Short name T693
Test name
Test status
Simulation time 204558664537 ps
CPU time 51.82 seconds
Started Dec 31 01:15:50 PM PST 23
Finished Dec 31 01:16:44 PM PST 23
Peak memory 200124 kb
Host smart-08fa7bf2-3cd0-4f2f-8901-ea769d8af51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396205604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3396205604
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1540392681
Short name T216
Test name
Test status
Simulation time 147730278639 ps
CPU time 62.37 seconds
Started Dec 31 01:15:55 PM PST 23
Finished Dec 31 01:16:58 PM PST 23
Peak memory 199808 kb
Host smart-4e7063b0-c5e3-40c3-a149-d4ae4c08e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540392681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1540392681
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2567546025
Short name T919
Test name
Test status
Simulation time 65562024294 ps
CPU time 94.37 seconds
Started Dec 31 01:15:49 PM PST 23
Finished Dec 31 01:17:25 PM PST 23
Peak memory 200196 kb
Host smart-f9cbb6d6-b1ff-46a9-b171-4100f4ddf4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567546025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2567546025
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1917659815
Short name T660
Test name
Test status
Simulation time 157069097917 ps
CPU time 30.02 seconds
Started Dec 31 01:15:47 PM PST 23
Finished Dec 31 01:16:19 PM PST 23
Peak memory 200200 kb
Host smart-b40e935a-5af9-4154-963f-1e57fcbd9983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917659815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1917659815
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1540083316
Short name T446
Test name
Test status
Simulation time 45515354831 ps
CPU time 75.88 seconds
Started Dec 31 01:15:50 PM PST 23
Finished Dec 31 01:17:07 PM PST 23
Peak memory 200200 kb
Host smart-9792a591-197b-4651-b108-353f360242db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540083316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1540083316
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1112571957
Short name T1050
Test name
Test status
Simulation time 133158604752 ps
CPU time 240.86 seconds
Started Dec 31 01:15:50 PM PST 23
Finished Dec 31 01:19:52 PM PST 23
Peak memory 200284 kb
Host smart-6e14eae4-32d8-421f-b9a9-76b29b746a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112571957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1112571957
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2559292591
Short name T338
Test name
Test status
Simulation time 75142816809 ps
CPU time 32.15 seconds
Started Dec 31 01:15:48 PM PST 23
Finished Dec 31 01:16:22 PM PST 23
Peak memory 200160 kb
Host smart-2d102ddb-ad61-4e0f-b9f7-d05260f46f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559292591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2559292591
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3332134381
Short name T826
Test name
Test status
Simulation time 93328160 ps
CPU time 0.55 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:28 PM PST 23
Peak memory 195796 kb
Host smart-a76b37a5-afe5-46c2-9253-13c37026ace3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332134381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3332134381
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2957522421
Short name T1019
Test name
Test status
Simulation time 73718157131 ps
CPU time 124.62 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:14:26 PM PST 23
Peak memory 200172 kb
Host smart-f13d292c-e570-40fe-a235-a35a20988e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957522421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2957522421
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1172161195
Short name T599
Test name
Test status
Simulation time 155157744087 ps
CPU time 24.15 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:12:47 PM PST 23
Peak memory 199884 kb
Host smart-2deb2555-cabf-4573-a49f-4064942af5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172161195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1172161195
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.3724798778
Short name T1224
Test name
Test status
Simulation time 164160743012 ps
CPU time 66.6 seconds
Started Dec 31 01:12:15 PM PST 23
Finished Dec 31 01:13:25 PM PST 23
Peak memory 199352 kb
Host smart-60705d10-559c-42d7-a188-734bbc8b266f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724798778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3724798778
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2702724652
Short name T941
Test name
Test status
Simulation time 105868496683 ps
CPU time 216.91 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200200 kb
Host smart-03347bb7-3d12-4058-9031-65d19c4d0268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702724652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2702724652
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3176990404
Short name T1183
Test name
Test status
Simulation time 4571474894 ps
CPU time 8.39 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 196572 kb
Host smart-7f662125-ee6e-438b-acc0-a815a8af7632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176990404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3176990404
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2559264903
Short name T746
Test name
Test status
Simulation time 102499101458 ps
CPU time 84.81 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 208888 kb
Host smart-8f42bfbd-9149-4a08-a120-e8300e7805d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559264903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2559264903
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3383053191
Short name T1198
Test name
Test status
Simulation time 5583237790 ps
CPU time 51.88 seconds
Started Dec 31 01:12:18 PM PST 23
Finished Dec 31 01:13:14 PM PST 23
Peak memory 200152 kb
Host smart-8c1d6b8a-6ad4-466b-94a3-c32276597e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383053191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3383053191
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1756757374
Short name T590
Test name
Test status
Simulation time 1866385333 ps
CPU time 17.5 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:42 PM PST 23
Peak memory 198228 kb
Host smart-31c4f410-8fda-4a0c-8523-a03841c233eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756757374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1756757374
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4251628497
Short name T805
Test name
Test status
Simulation time 175967195323 ps
CPU time 239.29 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:16:26 PM PST 23
Peak memory 200056 kb
Host smart-bf2e98b5-b711-4eab-9355-75f8ce562660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251628497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4251628497
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.4004099922
Short name T747
Test name
Test status
Simulation time 28495256488 ps
CPU time 20.68 seconds
Started Dec 31 01:12:14 PM PST 23
Finished Dec 31 01:12:38 PM PST 23
Peak memory 195588 kb
Host smart-f34c9cce-e9ff-4987-9503-c619af17e5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004099922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4004099922
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2681513825
Short name T85
Test name
Test status
Simulation time 279855974 ps
CPU time 0.79 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:31 PM PST 23
Peak memory 217732 kb
Host smart-a52104fb-8118-4031-adad-e23b30c6240a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681513825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2681513825
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1196793763
Short name T612
Test name
Test status
Simulation time 341258881 ps
CPU time 1.21 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 198536 kb
Host smart-6ba6d705-e4ca-4dd9-b951-45b3fcd66174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196793763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1196793763
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.251717053
Short name T825
Test name
Test status
Simulation time 408750979 ps
CPU time 1.42 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 197976 kb
Host smart-a0a72fe8-5d7b-45a3-8e98-aba48356521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251717053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.251717053
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.244052648
Short name T1082
Test name
Test status
Simulation time 11992044778 ps
CPU time 9.78 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 200184 kb
Host smart-a2c8cc9f-4e00-45d5-b21d-18434a9981d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244052648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.244052648
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1995737151
Short name T579
Test name
Test status
Simulation time 40163753 ps
CPU time 0.55 seconds
Started Dec 31 01:13:35 PM PST 23
Finished Dec 31 01:13:42 PM PST 23
Peak memory 195588 kb
Host smart-fa037194-1da8-405e-948a-3f4574674751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995737151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1995737151
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1328911084
Short name T849
Test name
Test status
Simulation time 269779065349 ps
CPU time 299.38 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:18:38 PM PST 23
Peak memory 200172 kb
Host smart-d2158bfc-fc56-492c-b3cd-3f08712517a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328911084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1328911084
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2269520503
Short name T578
Test name
Test status
Simulation time 84833791502 ps
CPU time 75.09 seconds
Started Dec 31 01:13:27 PM PST 23
Finished Dec 31 01:14:52 PM PST 23
Peak memory 200168 kb
Host smart-cf6f88bd-2d4a-46a2-a292-94e7ff9c8faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269520503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2269520503
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3938771688
Short name T283
Test name
Test status
Simulation time 49838837916 ps
CPU time 18.91 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:13:57 PM PST 23
Peak memory 200148 kb
Host smart-6fd8e1c9-764c-4576-b84d-176b3def86d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938771688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3938771688
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2897585106
Short name T1070
Test name
Test status
Simulation time 149006925505 ps
CPU time 63.25 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:14:41 PM PST 23
Peak memory 195876 kb
Host smart-c40a3d95-3484-4487-b889-d55dcf8e7540
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897585106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2897585106
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2793263196
Short name T1111
Test name
Test status
Simulation time 214948033992 ps
CPU time 271.26 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:18:09 PM PST 23
Peak memory 200104 kb
Host smart-72c6e2d0-7b28-44b5-9375-e3c81e440c82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793263196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2793263196
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1805760103
Short name T689
Test name
Test status
Simulation time 6326541933 ps
CPU time 3.95 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 198976 kb
Host smart-a2bbb8a7-b8f3-4c05-ba53-25bed14b8342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805760103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1805760103
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3579143173
Short name T775
Test name
Test status
Simulation time 326918725497 ps
CPU time 168.64 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:16:28 PM PST 23
Peak memory 208772 kb
Host smart-60d683e3-4c3f-4d75-844f-5185aaea0234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579143173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3579143173
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1818802297
Short name T1196
Test name
Test status
Simulation time 11785354158 ps
CPU time 146.55 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200240 kb
Host smart-2233ca25-7661-4331-9d79-f311188dfb07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818802297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1818802297
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3581594730
Short name T922
Test name
Test status
Simulation time 1378947589 ps
CPU time 4.72 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:13:43 PM PST 23
Peak memory 198216 kb
Host smart-0f065174-19a6-4bc7-89d7-c802da06f5ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581594730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3581594730
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.374871288
Short name T691
Test name
Test status
Simulation time 193668084718 ps
CPU time 183.99 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:16:41 PM PST 23
Peak memory 200224 kb
Host smart-2eb5a07a-94db-460f-b277-9a7bcf48a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374871288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.374871288
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2333312100
Short name T864
Test name
Test status
Simulation time 2020979026 ps
CPU time 0.96 seconds
Started Dec 31 01:13:28 PM PST 23
Finished Dec 31 01:13:38 PM PST 23
Peak memory 195764 kb
Host smart-b434ab95-fefb-470e-a97b-190d77a65f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333312100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2333312100
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2682742321
Short name T569
Test name
Test status
Simulation time 5564645441 ps
CPU time 9.56 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:13:46 PM PST 23
Peak memory 199048 kb
Host smart-bda8bea0-54dc-4e69-83d6-d0dbe9dbf7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682742321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2682742321
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.2529278059
Short name T676
Test name
Test status
Simulation time 96882443674 ps
CPU time 495.1 seconds
Started Dec 31 01:13:33 PM PST 23
Finished Dec 31 01:21:55 PM PST 23
Peak memory 216628 kb
Host smart-08e9a545-cfac-4df8-9402-8e1823403ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529278059 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2529278059
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3708919052
Short name T857
Test name
Test status
Simulation time 2250427127 ps
CPU time 2.64 seconds
Started Dec 31 01:13:29 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 198768 kb
Host smart-18c2e674-4a79-4551-8eb1-77846dee860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708919052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3708919052
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.78395865
Short name T1227
Test name
Test status
Simulation time 39880172056 ps
CPU time 73.67 seconds
Started Dec 31 01:13:26 PM PST 23
Finished Dec 31 01:14:49 PM PST 23
Peak memory 200284 kb
Host smart-403b1ba0-aa10-4d37-a387-78f16a0f5241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78395865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.78395865
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.343554830
Short name T694
Test name
Test status
Simulation time 28955493 ps
CPU time 0.58 seconds
Started Dec 31 01:13:30 PM PST 23
Finished Dec 31 01:13:40 PM PST 23
Peak memory 194660 kb
Host smart-2179be1f-0461-427e-836a-956ae6cf6e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343554830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.343554830
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2921129054
Short name T100
Test name
Test status
Simulation time 122739040054 ps
CPU time 260.63 seconds
Started Dec 31 01:13:33 PM PST 23
Finished Dec 31 01:18:01 PM PST 23
Peak memory 200252 kb
Host smart-9dd2c68f-65d6-458c-89df-e3c8a75b45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921129054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2921129054
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2771955952
Short name T1191
Test name
Test status
Simulation time 59530543234 ps
CPU time 76.21 seconds
Started Dec 31 01:13:34 PM PST 23
Finished Dec 31 01:14:58 PM PST 23
Peak memory 200180 kb
Host smart-abc8242e-83d0-47eb-89b1-c504ff7aa3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771955952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2771955952
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.2024867496
Short name T548
Test name
Test status
Simulation time 101127312887 ps
CPU time 47.94 seconds
Started Dec 31 01:13:34 PM PST 23
Finished Dec 31 01:14:29 PM PST 23
Peak memory 200200 kb
Host smart-aab73ae7-2634-4379-af25-97c734187161
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024867496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2024867496
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1051081992
Short name T1045
Test name
Test status
Simulation time 108928144453 ps
CPU time 702.65 seconds
Started Dec 31 01:13:33 PM PST 23
Finished Dec 31 01:25:23 PM PST 23
Peak memory 200188 kb
Host smart-dff64888-bcf4-4646-8090-a3e7462da985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051081992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1051081992
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1416971442
Short name T598
Test name
Test status
Simulation time 8026701303 ps
CPU time 3.88 seconds
Started Dec 31 01:13:37 PM PST 23
Finished Dec 31 01:13:46 PM PST 23
Peak memory 198392 kb
Host smart-e4b182fa-6f3f-4a2d-a358-d1c99dbdfff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416971442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1416971442
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.905018363
Short name T973
Test name
Test status
Simulation time 103532841596 ps
CPU time 224.89 seconds
Started Dec 31 01:13:33 PM PST 23
Finished Dec 31 01:17:26 PM PST 23
Peak memory 199816 kb
Host smart-c2b25d11-8b15-4488-9a9b-caf0c8f0d8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905018363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.905018363
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1311251629
Short name T938
Test name
Test status
Simulation time 13439623916 ps
CPU time 393.51 seconds
Started Dec 31 01:13:34 PM PST 23
Finished Dec 31 01:20:15 PM PST 23
Peak memory 200284 kb
Host smart-6eb2cadd-6ae7-4307-a26e-c2b7689d8e2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1311251629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1311251629
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3681687391
Short name T529
Test name
Test status
Simulation time 4949539371 ps
CPU time 31.57 seconds
Started Dec 31 01:13:32 PM PST 23
Finished Dec 31 01:14:11 PM PST 23
Peak memory 198480 kb
Host smart-5f61d708-1e13-4862-9521-1b92c97b3faf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681687391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3681687391
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1714407311
Short name T385
Test name
Test status
Simulation time 237522172020 ps
CPU time 113 seconds
Started Dec 31 01:13:37 PM PST 23
Finished Dec 31 01:15:36 PM PST 23
Peak memory 200200 kb
Host smart-9da1c14d-0d2f-45df-a038-76ab4d9a508c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714407311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1714407311
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1655521018
Short name T771
Test name
Test status
Simulation time 1769961622 ps
CPU time 1.37 seconds
Started Dec 31 01:13:32 PM PST 23
Finished Dec 31 01:13:41 PM PST 23
Peak memory 195572 kb
Host smart-8a649b9e-f33e-4c2b-a3fc-b66b8868a337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655521018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1655521018
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3242265628
Short name T452
Test name
Test status
Simulation time 515327976 ps
CPU time 2.06 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:13:42 PM PST 23
Peak memory 198612 kb
Host smart-15570892-5041-40b1-9b27-52adcaad1be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242265628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3242265628
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3520918467
Short name T874
Test name
Test status
Simulation time 69796864919 ps
CPU time 419.3 seconds
Started Dec 31 01:13:32 PM PST 23
Finished Dec 31 01:20:39 PM PST 23
Peak memory 216972 kb
Host smart-12ff1aa4-434b-49a9-bd2e-3c43f62d45d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520918467 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3520918467
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3970171226
Short name T454
Test name
Test status
Simulation time 669112578 ps
CPU time 2.52 seconds
Started Dec 31 01:13:31 PM PST 23
Finished Dec 31 01:13:42 PM PST 23
Peak memory 198328 kb
Host smart-9d81ee92-9fb1-4c9a-b6b9-28c206e6623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970171226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3970171226
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1769247364
Short name T609
Test name
Test status
Simulation time 76662957950 ps
CPU time 24.98 seconds
Started Dec 31 01:13:37 PM PST 23
Finished Dec 31 01:14:07 PM PST 23
Peak memory 200284 kb
Host smart-b22ddfac-ef52-4885-9a02-ab74cda0944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769247364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1769247364
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2185843425
Short name T1004
Test name
Test status
Simulation time 31987868 ps
CPU time 0.56 seconds
Started Dec 31 01:13:37 PM PST 23
Finished Dec 31 01:13:43 PM PST 23
Peak memory 195628 kb
Host smart-c3e24190-2295-414f-94e6-6105e4570bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185843425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2185843425
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2279379573
Short name T877
Test name
Test status
Simulation time 142746010440 ps
CPU time 214.11 seconds
Started Dec 31 01:13:39 PM PST 23
Finished Dec 31 01:17:17 PM PST 23
Peak memory 200224 kb
Host smart-63883f8c-5cc8-4302-a42e-019495a070d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279379573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2279379573
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3171097891
Short name T730
Test name
Test status
Simulation time 30932419492 ps
CPU time 49.34 seconds
Started Dec 31 01:13:39 PM PST 23
Finished Dec 31 01:14:32 PM PST 23
Peak memory 200164 kb
Host smart-4d02a4a3-ce7f-4316-abb4-82dc7e5104ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171097891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3171097891
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3523155365
Short name T296
Test name
Test status
Simulation time 12613580421 ps
CPU time 6.36 seconds
Started Dec 31 01:13:36 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 200240 kb
Host smart-0704b667-1868-440b-bcd8-6479800d1023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523155365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3523155365
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2254560000
Short name T620
Test name
Test status
Simulation time 577389239842 ps
CPU time 936.97 seconds
Started Dec 31 01:13:41 PM PST 23
Finished Dec 31 01:29:21 PM PST 23
Peak memory 198484 kb
Host smart-2f4f4913-3d4c-4be9-9717-53c6356c9be9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254560000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2254560000
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2804075823
Short name T801
Test name
Test status
Simulation time 88947849071 ps
CPU time 172.81 seconds
Started Dec 31 01:13:37 PM PST 23
Finished Dec 31 01:16:36 PM PST 23
Peak memory 200164 kb
Host smart-4a3647c2-53ec-4f54-a525-bc8e8ced7327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2804075823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2804075823
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2417931436
Short name T1064
Test name
Test status
Simulation time 7410327825 ps
CPU time 5.33 seconds
Started Dec 31 01:13:35 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 198928 kb
Host smart-238612f6-0a20-404a-803f-1bc922ec0fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417931436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2417931436
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2569895921
Short name T1091
Test name
Test status
Simulation time 7484065674 ps
CPU time 11.99 seconds
Started Dec 31 01:13:37 PM PST 23
Finished Dec 31 01:13:55 PM PST 23
Peak memory 195768 kb
Host smart-d1db37dd-ab65-46c7-abb9-aecb4a071310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569895921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2569895921
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.951495784
Short name T1078
Test name
Test status
Simulation time 2434577129 ps
CPU time 5.92 seconds
Started Dec 31 01:13:39 PM PST 23
Finished Dec 31 01:13:49 PM PST 23
Peak memory 198544 kb
Host smart-6108db75-dba6-44a7-8254-359994780106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951495784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.951495784
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2817835177
Short name T249
Test name
Test status
Simulation time 147460702969 ps
CPU time 66.53 seconds
Started Dec 31 01:13:38 PM PST 23
Finished Dec 31 01:14:49 PM PST 23
Peak memory 199336 kb
Host smart-3d367b6f-79ca-4278-8172-b582c73cb2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817835177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2817835177
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1636316303
Short name T422
Test name
Test status
Simulation time 6310138792 ps
CPU time 3.27 seconds
Started Dec 31 01:13:38 PM PST 23
Finished Dec 31 01:13:46 PM PST 23
Peak memory 196036 kb
Host smart-cc7a54e4-b268-47ef-ba8d-14915f323a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636316303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1636316303
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1499004470
Short name T1058
Test name
Test status
Simulation time 886295702 ps
CPU time 4.38 seconds
Started Dec 31 01:13:42 PM PST 23
Finished Dec 31 01:13:48 PM PST 23
Peak memory 198084 kb
Host smart-f937de53-48b9-4801-b4cc-fc0fa9ee497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499004470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1499004470
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3186845747
Short name T395
Test name
Test status
Simulation time 21842061936 ps
CPU time 253.66 seconds
Started Dec 31 01:13:41 PM PST 23
Finished Dec 31 01:17:57 PM PST 23
Peak memory 211300 kb
Host smart-44213f0c-c71e-49a8-ba07-63526ba8877f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186845747 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3186845747
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3950083667
Short name T1062
Test name
Test status
Simulation time 6410103415 ps
CPU time 22.33 seconds
Started Dec 31 01:13:42 PM PST 23
Finished Dec 31 01:14:06 PM PST 23
Peak memory 199768 kb
Host smart-c7b761ef-4b11-4de6-a0e8-cf374dd7efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950083667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3950083667
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.203266213
Short name T669
Test name
Test status
Simulation time 7306185299 ps
CPU time 11.13 seconds
Started Dec 31 01:13:38 PM PST 23
Finished Dec 31 01:13:54 PM PST 23
Peak memory 197596 kb
Host smart-f233b5d3-1a83-4b4f-b0ce-7d0bbb29a78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203266213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.203266213
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.529901265
Short name T1071
Test name
Test status
Simulation time 67272022 ps
CPU time 0.56 seconds
Started Dec 31 01:13:46 PM PST 23
Finished Dec 31 01:13:48 PM PST 23
Peak memory 195544 kb
Host smart-392991e4-855b-4b8f-9747-1e6326283f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529901265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.529901265
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1766843865
Short name T339
Test name
Test status
Simulation time 114729562184 ps
CPU time 59.93 seconds
Started Dec 31 01:13:44 PM PST 23
Finished Dec 31 01:14:45 PM PST 23
Peak memory 200200 kb
Host smart-c3aca5d5-7ffc-47be-95cd-ff6d6feb5711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766843865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1766843865
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2953159386
Short name T118
Test name
Test status
Simulation time 106838769398 ps
CPU time 42.65 seconds
Started Dec 31 01:13:46 PM PST 23
Finished Dec 31 01:14:30 PM PST 23
Peak memory 199732 kb
Host smart-0850cdd3-7c2f-4abd-b524-40af42d54a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953159386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2953159386
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2004204443
Short name T790
Test name
Test status
Simulation time 149601123554 ps
CPU time 158.19 seconds
Started Dec 31 01:13:43 PM PST 23
Finished Dec 31 01:16:23 PM PST 23
Peak memory 200156 kb
Host smart-e0378304-cfb1-488e-a541-a6026188fa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004204443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2004204443
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.62092543
Short name T1179
Test name
Test status
Simulation time 43484650345 ps
CPU time 67.86 seconds
Started Dec 31 01:13:42 PM PST 23
Finished Dec 31 01:14:52 PM PST 23
Peak memory 199440 kb
Host smart-4522d0fa-d442-4160-a753-243855c514cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62092543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.62092543
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3443922623
Short name T117
Test name
Test status
Simulation time 155468666769 ps
CPU time 435.58 seconds
Started Dec 31 01:13:41 PM PST 23
Finished Dec 31 01:20:59 PM PST 23
Peak memory 200248 kb
Host smart-a69518f5-e63f-4756-ab54-966573fd35aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443922623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3443922623
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3382945590
Short name T636
Test name
Test status
Simulation time 7476536953 ps
CPU time 7.64 seconds
Started Dec 31 01:13:44 PM PST 23
Finished Dec 31 01:13:53 PM PST 23
Peak memory 198012 kb
Host smart-ab7e4d03-3904-4328-813c-58868858003c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382945590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3382945590
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1847289028
Short name T135
Test name
Test status
Simulation time 193612263727 ps
CPU time 77.07 seconds
Started Dec 31 01:13:40 PM PST 23
Finished Dec 31 01:15:00 PM PST 23
Peak memory 199508 kb
Host smart-29c176f7-c6bb-465e-9b77-7cceb2c9c851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847289028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1847289028
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3108683984
Short name T654
Test name
Test status
Simulation time 23856072907 ps
CPU time 209.93 seconds
Started Dec 31 01:13:41 PM PST 23
Finished Dec 31 01:17:14 PM PST 23
Peak memory 200176 kb
Host smart-ca33d645-6185-458d-8370-06c73b525c5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108683984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3108683984
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.246165171
Short name T1072
Test name
Test status
Simulation time 1769014700 ps
CPU time 6.21 seconds
Started Dec 31 01:13:43 PM PST 23
Finished Dec 31 01:13:51 PM PST 23
Peak memory 198228 kb
Host smart-be015e63-9eed-4bf8-9d53-857bc1ecf4e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246165171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.246165171
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1144284825
Short name T977
Test name
Test status
Simulation time 266676407838 ps
CPU time 205.05 seconds
Started Dec 31 01:13:41 PM PST 23
Finished Dec 31 01:17:09 PM PST 23
Peak memory 200160 kb
Host smart-eb8908cb-9d9e-45b3-917d-94852862a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144284825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1144284825
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1895566507
Short name T781
Test name
Test status
Simulation time 448386047 ps
CPU time 1.32 seconds
Started Dec 31 01:13:43 PM PST 23
Finished Dec 31 01:13:46 PM PST 23
Peak memory 195784 kb
Host smart-196364dd-f4c4-4c3e-b902-c9cd02b6d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895566507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1895566507
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1406846374
Short name T822
Test name
Test status
Simulation time 429094770 ps
CPU time 1.95 seconds
Started Dec 31 01:13:44 PM PST 23
Finished Dec 31 01:13:47 PM PST 23
Peak memory 200048 kb
Host smart-3178d14c-ff32-4aa8-a860-a6843713be69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406846374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1406846374
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3985688815
Short name T762
Test name
Test status
Simulation time 7426508429 ps
CPU time 6.92 seconds
Started Dec 31 01:13:43 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 199628 kb
Host smart-aca31980-ae44-4216-b974-7958e5374219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985688815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3985688815
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1135139785
Short name T633
Test name
Test status
Simulation time 58992003221 ps
CPU time 104.77 seconds
Started Dec 31 01:13:41 PM PST 23
Finished Dec 31 01:15:28 PM PST 23
Peak memory 200124 kb
Host smart-21efb8ba-7dba-42c7-8056-32c902985a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135139785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1135139785
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3394996738
Short name T831
Test name
Test status
Simulation time 15282652 ps
CPU time 0.56 seconds
Started Dec 31 01:14:08 PM PST 23
Finished Dec 31 01:14:12 PM PST 23
Peak memory 195648 kb
Host smart-730d50aa-2350-42cc-a384-523c8ca5d8b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394996738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3394996738
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1910716273
Short name T784
Test name
Test status
Simulation time 134485883560 ps
CPU time 57.08 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:15:09 PM PST 23
Peak memory 200184 kb
Host smart-ebe7d8eb-d7d2-4be9-a153-ab19af6136b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910716273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1910716273
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3467070054
Short name T782
Test name
Test status
Simulation time 36612904954 ps
CPU time 66.69 seconds
Started Dec 31 01:14:02 PM PST 23
Finished Dec 31 01:15:14 PM PST 23
Peak memory 200236 kb
Host smart-265b57be-1893-4ab7-b58f-7eac2f71c18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467070054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3467070054
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2256311278
Short name T1239
Test name
Test status
Simulation time 48609867511 ps
CPU time 20.32 seconds
Started Dec 31 01:13:50 PM PST 23
Finished Dec 31 01:14:11 PM PST 23
Peak memory 200144 kb
Host smart-ef0c1927-7172-4101-8d6d-477d689a5066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256311278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2256311278
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.612847479
Short name T234
Test name
Test status
Simulation time 1100540950541 ps
CPU time 1997.61 seconds
Started Dec 31 01:14:10 PM PST 23
Finished Dec 31 01:47:30 PM PST 23
Peak memory 199960 kb
Host smart-06adfcca-3643-445e-8fe0-3db56291d4f4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612847479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.612847479
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1503547109
Short name T1118
Test name
Test status
Simulation time 186387021481 ps
CPU time 704.88 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:25:57 PM PST 23
Peak memory 200144 kb
Host smart-e13b7e61-f28b-409f-80f5-ad173ad36e7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503547109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1503547109
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3901482921
Short name T581
Test name
Test status
Simulation time 8947739910 ps
CPU time 17.25 seconds
Started Dec 31 01:14:03 PM PST 23
Finished Dec 31 01:14:24 PM PST 23
Peak memory 200144 kb
Host smart-d097f250-574d-40bd-b3f3-aeb06750f19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901482921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3901482921
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3118676955
Short name T434
Test name
Test status
Simulation time 141058913726 ps
CPU time 52.7 seconds
Started Dec 31 01:14:03 PM PST 23
Finished Dec 31 01:15:00 PM PST 23
Peak memory 208400 kb
Host smart-dc63dd69-cb09-4bef-bb6b-054d701c3946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118676955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3118676955
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3135819803
Short name T424
Test name
Test status
Simulation time 3377351754 ps
CPU time 167.85 seconds
Started Dec 31 01:13:51 PM PST 23
Finished Dec 31 01:16:40 PM PST 23
Peak memory 200220 kb
Host smart-28e411c3-cff1-423f-945d-e78cc50cae6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135819803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3135819803
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.664543423
Short name T764
Test name
Test status
Simulation time 3465258189 ps
CPU time 19.34 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:14:43 PM PST 23
Peak memory 198964 kb
Host smart-7a96ce01-777b-4709-aa7b-545d91a1a499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664543423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.664543423
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.673491288
Short name T1051
Test name
Test status
Simulation time 26105280048 ps
CPU time 39.31 seconds
Started Dec 31 01:14:25 PM PST 23
Finished Dec 31 01:15:06 PM PST 23
Peak memory 200204 kb
Host smart-8e59e102-a2df-46b5-b958-85aeee2479a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673491288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.673491288
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1337875495
Short name T1000
Test name
Test status
Simulation time 6988723003 ps
CPU time 3.28 seconds
Started Dec 31 01:14:03 PM PST 23
Finished Dec 31 01:14:10 PM PST 23
Peak memory 195904 kb
Host smart-090a259c-e525-4f7b-ae98-0dee74b74549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337875495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1337875495
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1072245914
Short name T1005
Test name
Test status
Simulation time 729059939 ps
CPU time 1.45 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:14:25 PM PST 23
Peak memory 198544 kb
Host smart-bf744dd4-7ae5-48af-a26e-55ad98a0035b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072245914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1072245914
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1132538170
Short name T861
Test name
Test status
Simulation time 260498338405 ps
CPU time 117.49 seconds
Started Dec 31 01:14:02 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200236 kb
Host smart-ec7fc444-f136-4b3a-94de-a47501dd974e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132538170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1132538170
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2649228880
Short name T1034
Test name
Test status
Simulation time 60948823171 ps
CPU time 530.9 seconds
Started Dec 31 01:14:21 PM PST 23
Finished Dec 31 01:23:13 PM PST 23
Peak memory 216572 kb
Host smart-105cb207-e2c2-4e02-8d61-27ada4f904c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649228880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2649228880
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1900007031
Short name T851
Test name
Test status
Simulation time 1088601586 ps
CPU time 5.42 seconds
Started Dec 31 01:13:46 PM PST 23
Finished Dec 31 01:13:53 PM PST 23
Peak memory 198156 kb
Host smart-959600e4-6adc-40d6-8d91-17d5c8367ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900007031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1900007031
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3774223537
Short name T433
Test name
Test status
Simulation time 29779187525 ps
CPU time 48.4 seconds
Started Dec 31 01:14:04 PM PST 23
Finished Dec 31 01:14:56 PM PST 23
Peak memory 200168 kb
Host smart-0e2c836e-7037-4ef9-9a7d-c2368e5c9e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774223537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3774223537
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2045813648
Short name T1100
Test name
Test status
Simulation time 18176288 ps
CPU time 0.56 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:14:24 PM PST 23
Peak memory 195676 kb
Host smart-cf5c90d4-3bfe-4a57-b70a-a0f31f03fe36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045813648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2045813648
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.281427051
Short name T195
Test name
Test status
Simulation time 17863867988 ps
CPU time 31.96 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:15:10 PM PST 23
Peak memory 200144 kb
Host smart-bbf57ed3-ceb8-4531-b502-2d3b5730619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281427051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.281427051
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2597947752
Short name T1117
Test name
Test status
Simulation time 2578217909284 ps
CPU time 1032.61 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:31:39 PM PST 23
Peak memory 200036 kb
Host smart-58bae4bb-e44a-4d23-b3e1-986371e5d04d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597947752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2597947752
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2907411871
Short name T855
Test name
Test status
Simulation time 101709274749 ps
CPU time 415.34 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:21:07 PM PST 23
Peak memory 200148 kb
Host smart-5acdd76f-a54d-4b7c-a7a0-9fbdb480b806
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907411871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2907411871
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.548705906
Short name T1122
Test name
Test status
Simulation time 4267886533 ps
CPU time 8.08 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:14:33 PM PST 23
Peak memory 198452 kb
Host smart-2354200e-8799-41ff-b6ba-959a5af70875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548705906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.548705906
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.764682581
Short name T885
Test name
Test status
Simulation time 85445650301 ps
CPU time 196.03 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:17:39 PM PST 23
Peak memory 200288 kb
Host smart-faaa34b1-27c0-4f53-94b0-6592b0d2f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764682581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.764682581
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3169602852
Short name T1212
Test name
Test status
Simulation time 12959996473 ps
CPU time 727.7 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:26:33 PM PST 23
Peak memory 200204 kb
Host smart-7f8ae40a-3ef1-44d8-929f-89808f005100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169602852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3169602852
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1100926909
Short name T488
Test name
Test status
Simulation time 1072081296 ps
CPU time 12.49 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:14:51 PM PST 23
Peak memory 198428 kb
Host smart-2b3d2bdc-ce1d-4e0a-b03b-e1fc1a999bdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100926909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1100926909
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.756207446
Short name T1226
Test name
Test status
Simulation time 106703463258 ps
CPU time 40.2 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:15:03 PM PST 23
Peak memory 198852 kb
Host smart-758a8acb-d8fe-4975-aa01-cd73f97cff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756207446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.756207446
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1532844889
Short name T445
Test name
Test status
Simulation time 46786119008 ps
CPU time 4.73 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:15:03 PM PST 23
Peak memory 195824 kb
Host smart-f6b038d5-7a1f-445a-afae-8fa0eed87e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532844889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1532844889
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2571316405
Short name T827
Test name
Test status
Simulation time 6070032378 ps
CPU time 5.52 seconds
Started Dec 31 01:14:02 PM PST 23
Finished Dec 31 01:14:12 PM PST 23
Peak memory 199728 kb
Host smart-582aa1bd-68f8-4f61-813e-00ed409496ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571316405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2571316405
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.112466552
Short name T1126
Test name
Test status
Simulation time 51423846515 ps
CPU time 87.73 seconds
Started Dec 31 01:14:57 PM PST 23
Finished Dec 31 01:16:26 PM PST 23
Peak memory 200472 kb
Host smart-a0427cf7-5eda-4205-a702-b098bf8801f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112466552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.112466552
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2848987436
Short name T448
Test name
Test status
Simulation time 100403642330 ps
CPU time 176.32 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:17:19 PM PST 23
Peak memory 216576 kb
Host smart-2e692632-9983-4a1f-abb5-28233b26ceee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848987436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2848987436
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.521227750
Short name T1006
Test name
Test status
Simulation time 12633886104 ps
CPU time 20.93 seconds
Started Dec 31 01:14:08 PM PST 23
Finished Dec 31 01:14:33 PM PST 23
Peak memory 199980 kb
Host smart-22e9677e-07bf-448e-9622-992116c96d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521227750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.521227750
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3581055952
Short name T917
Test name
Test status
Simulation time 59705971030 ps
CPU time 34.49 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:14:46 PM PST 23
Peak memory 200240 kb
Host smart-d4689d37-ef0c-45d4-8f01-dd26a2ae68af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581055952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3581055952
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2933517995
Short name T923
Test name
Test status
Simulation time 11491444 ps
CPU time 0.56 seconds
Started Dec 31 01:14:36 PM PST 23
Finished Dec 31 01:14:37 PM PST 23
Peak memory 194588 kb
Host smart-238b8a6b-5d4e-443e-b697-011b4a15ebce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933517995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2933517995
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1872662032
Short name T1084
Test name
Test status
Simulation time 82751639529 ps
CPU time 30.69 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:14:42 PM PST 23
Peak memory 200196 kb
Host smart-741cb30f-3dd3-4f37-92c8-b3f3d23d0c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872662032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1872662032
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3425619146
Short name T820
Test name
Test status
Simulation time 129513822709 ps
CPU time 27.81 seconds
Started Dec 31 01:14:25 PM PST 23
Finished Dec 31 01:14:54 PM PST 23
Peak memory 199436 kb
Host smart-ee4e15c7-7b45-47ac-98eb-9a3c84b24cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425619146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3425619146
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3073692543
Short name T1114
Test name
Test status
Simulation time 238907738656 ps
CPU time 25.2 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 200036 kb
Host smart-e1f01af8-b507-4f07-82ae-8b5dd21c7846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073692543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3073692543
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1493173704
Short name T606
Test name
Test status
Simulation time 21955187800 ps
CPU time 35.69 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 197032 kb
Host smart-1cd7e0a8-7a83-4545-a58f-d13aa2bf452a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493173704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1493173704
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.16967726
Short name T1178
Test name
Test status
Simulation time 84495474709 ps
CPU time 399.57 seconds
Started Dec 31 01:14:11 PM PST 23
Finished Dec 31 01:20:52 PM PST 23
Peak memory 200220 kb
Host smart-75190ccd-1238-4d8c-b39f-898a965a8c69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16967726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.16967726
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3389041148
Short name T842
Test name
Test status
Simulation time 5834221707 ps
CPU time 4.42 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:14:30 PM PST 23
Peak memory 198588 kb
Host smart-4623ca7a-f9d0-4fe9-a96b-3f5bac3fd85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389041148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3389041148
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1497490398
Short name T22
Test name
Test status
Simulation time 111449510588 ps
CPU time 42.21 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:15:08 PM PST 23
Peak memory 208480 kb
Host smart-831c1f5d-548d-4fc2-b625-5c687ed754df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497490398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1497490398
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1779327016
Short name T786
Test name
Test status
Simulation time 20769490927 ps
CPU time 917.71 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:30:18 PM PST 23
Peak memory 200220 kb
Host smart-97a79f79-0ddf-4fd3-8060-d34ee38ea1cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779327016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1779327016
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3174941334
Short name T999
Test name
Test status
Simulation time 51532343109 ps
CPU time 43.57 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:15:08 PM PST 23
Peak memory 200052 kb
Host smart-88edd070-0741-4bfa-a9c8-8bd6d7ff3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174941334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3174941334
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.760296920
Short name T462
Test name
Test status
Simulation time 3174365716 ps
CPU time 1.9 seconds
Started Dec 31 01:14:56 PM PST 23
Finished Dec 31 01:14:59 PM PST 23
Peak memory 195880 kb
Host smart-7aa9b85b-abe6-4e19-8367-8feecf5f56d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760296920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.760296920
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3295230977
Short name T1067
Test name
Test status
Simulation time 674282439 ps
CPU time 2.86 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:14:29 PM PST 23
Peak memory 198104 kb
Host smart-04871777-1860-4d9f-ac9c-d77e03c9193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295230977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3295230977
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4087695015
Short name T324
Test name
Test status
Simulation time 320148140014 ps
CPU time 543.71 seconds
Started Dec 31 01:14:28 PM PST 23
Finished Dec 31 01:23:32 PM PST 23
Peak memory 200156 kb
Host smart-e37fdaee-1cfe-4265-8e60-e56cde0000f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087695015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4087695015
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3947462471
Short name T824
Test name
Test status
Simulation time 36688532553 ps
CPU time 783.75 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:28:14 PM PST 23
Peak memory 215480 kb
Host smart-974d96bc-89a7-451c-b512-3691e653997b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947462471 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3947462471
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2308378881
Short name T616
Test name
Test status
Simulation time 1006747649 ps
CPU time 3.82 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:15:05 PM PST 23
Peak memory 198468 kb
Host smart-d9c7766c-c405-46a5-b3c2-868b19d4efd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308378881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2308378881
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4278847884
Short name T1165
Test name
Test status
Simulation time 99049309050 ps
CPU time 169.7 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:17:55 PM PST 23
Peak memory 200220 kb
Host smart-cbccf7a2-040f-461f-9fae-a668f8a978d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278847884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4278847884
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1036955246
Short name T954
Test name
Test status
Simulation time 13435512 ps
CPU time 0.55 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:14:39 PM PST 23
Peak memory 195632 kb
Host smart-3a1e97f9-a51a-4adb-93e3-e4680e023b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036955246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1036955246
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3558377147
Short name T719
Test name
Test status
Simulation time 148191824472 ps
CPU time 125.49 seconds
Started Dec 31 01:14:21 PM PST 23
Finished Dec 31 01:16:28 PM PST 23
Peak memory 199912 kb
Host smart-80e95a7f-7425-417a-922a-aaca3f513ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558377147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3558377147
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.3386002224
Short name T626
Test name
Test status
Simulation time 84782183906 ps
CPU time 33.38 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:14:57 PM PST 23
Peak memory 198804 kb
Host smart-b5451de7-ae6f-4643-a97e-5a9c1ffa75ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386002224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3386002224
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3352743422
Short name T546
Test name
Test status
Simulation time 161082167270 ps
CPU time 846.48 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:28:29 PM PST 23
Peak memory 200284 kb
Host smart-adb8d8f8-8cb6-43d6-ab60-639f7168c5d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352743422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3352743422
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2097317207
Short name T1164
Test name
Test status
Simulation time 6038671564 ps
CPU time 12.34 seconds
Started Dec 31 01:14:56 PM PST 23
Finished Dec 31 01:15:10 PM PST 23
Peak memory 198720 kb
Host smart-01d670b5-3c2f-41a1-b4de-7d69c8c59310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097317207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2097317207
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1828936705
Short name T967
Test name
Test status
Simulation time 256074865903 ps
CPU time 86.16 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:15:50 PM PST 23
Peak memory 208496 kb
Host smart-911aeda0-b879-4a5a-9048-ad7b525a71b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828936705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1828936705
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1537996022
Short name T958
Test name
Test status
Simulation time 18037524362 ps
CPU time 287.87 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:19:12 PM PST 23
Peak memory 200160 kb
Host smart-9c2b7901-03cd-454d-b85b-4f84da3b42b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1537996022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1537996022
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3246880220
Short name T852
Test name
Test status
Simulation time 134478912963 ps
CPU time 48.3 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:15:00 PM PST 23
Peak memory 200156 kb
Host smart-77715676-efda-4096-8a86-4fcef0d63d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246880220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3246880220
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3562062807
Short name T995
Test name
Test status
Simulation time 4227467034 ps
CPU time 2.52 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:14:26 PM PST 23
Peak memory 196172 kb
Host smart-d86e8a63-2fb5-4e89-8eb2-2eb423026a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562062807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3562062807
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1640083095
Short name T21
Test name
Test status
Simulation time 555839739 ps
CPU time 1.78 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:14:25 PM PST 23
Peak memory 198644 kb
Host smart-b9744781-e073-41cb-8f20-4dd55d20c7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640083095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1640083095
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.504741915
Short name T260
Test name
Test status
Simulation time 558048830035 ps
CPU time 223.4 seconds
Started Dec 31 01:14:12 PM PST 23
Finished Dec 31 01:17:56 PM PST 23
Peak memory 216796 kb
Host smart-5bbbe8f9-d78e-4021-9389-af60f293b570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504741915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.504741915
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3164670392
Short name T63
Test name
Test status
Simulation time 56568467668 ps
CPU time 847.02 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:28:19 PM PST 23
Peak memory 216912 kb
Host smart-4cca8646-b000-47d9-ac95-744059157985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164670392 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3164670392
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1194650536
Short name T580
Test name
Test status
Simulation time 566893240 ps
CPU time 1.24 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:15:01 PM PST 23
Peak memory 197776 kb
Host smart-18e28e1b-0446-4cd9-9a8f-79d5ff9f6322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194650536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1194650536
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1553739752
Short name T440
Test name
Test status
Simulation time 43117036599 ps
CPU time 89.87 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:15:53 PM PST 23
Peak memory 200196 kb
Host smart-7b122117-f3b1-46c8-a5d5-9e3a81b65a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553739752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1553739752
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.413858385
Short name T1207
Test name
Test status
Simulation time 14582609 ps
CPU time 0.58 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:14:38 PM PST 23
Peak memory 195544 kb
Host smart-05fdd55f-a61d-4c0e-bfc2-6f3d5d9aa0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413858385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.413858385
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1594928676
Short name T536
Test name
Test status
Simulation time 37576957125 ps
CPU time 58.3 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:15:57 PM PST 23
Peak memory 199908 kb
Host smart-76110977-4181-4799-a030-6f5907e2cdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594928676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1594928676
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2332738675
Short name T316
Test name
Test status
Simulation time 149212538104 ps
CPU time 252.01 seconds
Started Dec 31 01:14:25 PM PST 23
Finished Dec 31 01:18:39 PM PST 23
Peak memory 200184 kb
Host smart-dac96ab6-8b7a-4ec8-84f0-5d8c57765699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332738675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2332738675
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.563164266
Short name T1039
Test name
Test status
Simulation time 850881741852 ps
CPU time 774.23 seconds
Started Dec 31 01:14:25 PM PST 23
Finished Dec 31 01:27:21 PM PST 23
Peak memory 200204 kb
Host smart-e116f807-c2af-4909-a927-d9621962a538
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563164266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.563164266
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.4115986343
Short name T756
Test name
Test status
Simulation time 47040525819 ps
CPU time 300.82 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:19:24 PM PST 23
Peak memory 200228 kb
Host smart-f8066f8d-ec89-4b41-9175-34410dee1802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115986343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4115986343
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1353370106
Short name T530
Test name
Test status
Simulation time 5887725423 ps
CPU time 8.66 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:14:52 PM PST 23
Peak memory 199400 kb
Host smart-c39853a8-b14c-4cdc-b6ed-8ad847dee43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353370106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1353370106
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1178027532
Short name T1220
Test name
Test status
Simulation time 74906135751 ps
CPU time 80.61 seconds
Started Dec 31 01:14:21 PM PST 23
Finished Dec 31 01:15:43 PM PST 23
Peak memory 200256 kb
Host smart-b5b7c092-abb7-448c-a749-f8a329cca4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178027532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1178027532
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2932445237
Short name T634
Test name
Test status
Simulation time 4573862574 ps
CPU time 229.37 seconds
Started Dec 31 01:14:21 PM PST 23
Finished Dec 31 01:18:11 PM PST 23
Peak memory 200040 kb
Host smart-8ad373c0-18d0-414a-a24f-e07977c6282d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2932445237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2932445237
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2712379267
Short name T527
Test name
Test status
Simulation time 1935606388 ps
CPU time 15.74 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:14:39 PM PST 23
Peak memory 198940 kb
Host smart-a352ca14-b348-404e-9809-be14ba3b19a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712379267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2712379267
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4101559905
Short name T872
Test name
Test status
Simulation time 51927311776 ps
CPU time 44.96 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:14:57 PM PST 23
Peak memory 200248 kb
Host smart-3cc9ad49-b11d-491b-aecf-95f98ff75410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101559905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4101559905
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2667490445
Short name T443
Test name
Test status
Simulation time 3786848994 ps
CPU time 3.66 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:14:29 PM PST 23
Peak memory 196124 kb
Host smart-ff71fb54-2c6e-4614-927c-abc2999d9118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667490445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2667490445
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1177294983
Short name T713
Test name
Test status
Simulation time 6014484506 ps
CPU time 25.99 seconds
Started Dec 31 01:14:56 PM PST 23
Finished Dec 31 01:15:23 PM PST 23
Peak memory 199648 kb
Host smart-94d3ebe3-66d8-4382-913f-eda3b392ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177294983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1177294983
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.4241034658
Short name T1230
Test name
Test status
Simulation time 296512774350 ps
CPU time 126.13 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:16:30 PM PST 23
Peak memory 200264 kb
Host smart-38c7b9e3-209e-4026-80f0-a8df64a22074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241034658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4241034658
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4166707742
Short name T844
Test name
Test status
Simulation time 55747662847 ps
CPU time 896.25 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:29:21 PM PST 23
Peak memory 216724 kb
Host smart-93c29ddf-a0b2-4cc8-bf22-ab17c464c188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166707742 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4166707742
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1748987847
Short name T1042
Test name
Test status
Simulation time 7264468229 ps
CPU time 11.62 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:14:55 PM PST 23
Peak memory 199656 kb
Host smart-08f23816-0c0a-416c-b722-0c44be682bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748987847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1748987847
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1113196514
Short name T475
Test name
Test status
Simulation time 18786471441 ps
CPU time 28 seconds
Started Dec 31 01:14:23 PM PST 23
Finished Dec 31 01:14:52 PM PST 23
Peak memory 200132 kb
Host smart-772bee69-6b55-41d5-b0eb-b65ca0706b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113196514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1113196514
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.715621609
Short name T624
Test name
Test status
Simulation time 50789254 ps
CPU time 0.53 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:15:30 PM PST 23
Peak memory 194648 kb
Host smart-d5e8e34c-df43-4bc7-839f-b74bbdfc37e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715621609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.715621609
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.15917685
Short name T537
Test name
Test status
Simulation time 10371747696 ps
CPU time 16.5 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:14:39 PM PST 23
Peak memory 200368 kb
Host smart-c6b3e1f6-eaa5-47fc-93a5-2e9d3eb02763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15917685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.15917685
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.329202946
Short name T605
Test name
Test status
Simulation time 20119951020 ps
CPU time 32.09 seconds
Started Dec 31 01:14:09 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 200236 kb
Host smart-d0d80c26-cbcf-40f7-b353-cb7df70baa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329202946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.329202946
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2381908284
Short name T159
Test name
Test status
Simulation time 12757795488 ps
CPU time 19.77 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:15:20 PM PST 23
Peak memory 200164 kb
Host smart-eb533bcf-877d-4863-8a57-975ef655c5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381908284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2381908284
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2220119640
Short name T788
Test name
Test status
Simulation time 1576801428434 ps
CPU time 1034.72 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:31:53 PM PST 23
Peak memory 198744 kb
Host smart-d2b77a5b-33a0-4857-9278-01d3d6b7fa28
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220119640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2220119640
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1633691706
Short name T936
Test name
Test status
Simulation time 105031055960 ps
CPU time 998.96 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:31:46 PM PST 23
Peak memory 200156 kb
Host smart-b8e7ab14-0ed0-42f7-bbf6-7de6414075d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1633691706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1633691706
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1765923434
Short name T26
Test name
Test status
Simulation time 5827105608 ps
CPU time 9.31 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:18 PM PST 23
Peak memory 199436 kb
Host smart-de552a93-37a0-48ac-b25a-da675c86ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765923434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1765923434
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2150485190
Short name T913
Test name
Test status
Simulation time 56500059028 ps
CPU time 107.46 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:16:51 PM PST 23
Peak memory 199888 kb
Host smart-9a9af19f-0651-4122-8fee-3f0743b76cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150485190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2150485190
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3754075654
Short name T1083
Test name
Test status
Simulation time 46619116637 ps
CPU time 223.32 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:18:50 PM PST 23
Peak memory 200216 kb
Host smart-3c019f20-ea8a-4504-9128-2a99a3037fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754075654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3754075654
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2499726787
Short name T623
Test name
Test status
Simulation time 4482922308 ps
CPU time 36.2 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:04 PM PST 23
Peak memory 198472 kb
Host smart-87f0bfd2-ed16-4622-98f8-0246b8399d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2499726787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2499726787
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1453775062
Short name T853
Test name
Test status
Simulation time 29993774224 ps
CPU time 51.53 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:16:00 PM PST 23
Peak memory 200152 kb
Host smart-1b216732-1b40-4160-bac1-b49cef74169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453775062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1453775062
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.449561398
Short name T1090
Test name
Test status
Simulation time 48113454597 ps
CPU time 9.64 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:14:54 PM PST 23
Peak memory 196124 kb
Host smart-2835a45b-e569-4a36-8337-1da466e1633f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449561398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.449561398
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2865981466
Short name T477
Test name
Test status
Simulation time 5773532675 ps
CPU time 5.95 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 199620 kb
Host smart-c429db23-a07d-4da6-803f-6ac5d0f2d646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865981466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2865981466
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1236962284
Short name T1124
Test name
Test status
Simulation time 451284986642 ps
CPU time 854.68 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:29:21 PM PST 23
Peak memory 200788 kb
Host smart-69285b46-ac01-41a4-8437-5866f9f4c522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236962284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1236962284
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3414734916
Short name T463
Test name
Test status
Simulation time 1017970095 ps
CPU time 5.38 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:14:51 PM PST 23
Peak memory 198700 kb
Host smart-5b138087-fa73-4cd7-b2f5-807814a12ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414734916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3414734916
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2620865674
Short name T1043
Test name
Test status
Simulation time 166619892630 ps
CPU time 30.25 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:15:37 PM PST 23
Peak memory 197964 kb
Host smart-f4da7531-8727-42c0-885e-0c9551e9773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620865674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2620865674
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3988736027
Short name T643
Test name
Test status
Simulation time 16393039 ps
CPU time 0.52 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 194568 kb
Host smart-b1077dc6-4cef-4aed-b8ea-baa47bea5d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988736027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3988736027
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.528263579
Short name T539
Test name
Test status
Simulation time 98532730185 ps
CPU time 170.71 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:15:17 PM PST 23
Peak memory 200260 kb
Host smart-68b35931-7216-47cd-8f0c-a0f5ee6fa0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528263579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.528263579
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4230179224
Short name T1154
Test name
Test status
Simulation time 42723970156 ps
CPU time 33.1 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:58 PM PST 23
Peak memory 199512 kb
Host smart-aea09ffa-724c-4923-b776-4c2573ba4be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230179224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4230179224
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1706926178
Short name T950
Test name
Test status
Simulation time 126563388770 ps
CPU time 38.6 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:13:04 PM PST 23
Peak memory 200236 kb
Host smart-b6b39697-b220-4edd-b166-ef2c006767a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706926178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1706926178
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.774094196
Short name T808
Test name
Test status
Simulation time 58679656893 ps
CPU time 26.28 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:12:56 PM PST 23
Peak memory 199124 kb
Host smart-30c9ca31-b901-4003-a9d3-23fa96785792
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774094196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.774094196
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.586136
Short name T1189
Test name
Test status
Simulation time 163287240337 ps
CPU time 84.03 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:13:52 PM PST 23
Peak memory 200248 kb
Host smart-0c6b739e-7789-40ad-9fb0-c9af8a6cb128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.586136
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1456637786
Short name T748
Test name
Test status
Simulation time 1821324641 ps
CPU time 1.42 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:12:30 PM PST 23
Peak memory 195620 kb
Host smart-d2474ca0-f0b9-4866-9e9f-91bd3869d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456637786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1456637786
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3701751288
Short name T916
Test name
Test status
Simulation time 76029550401 ps
CPU time 37.81 seconds
Started Dec 31 01:12:22 PM PST 23
Finished Dec 31 01:13:06 PM PST 23
Peak memory 198972 kb
Host smart-93af21f7-7d82-44f5-b1ae-5de2fc7301fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701751288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3701751288
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1751630119
Short name T298
Test name
Test status
Simulation time 16212630220 ps
CPU time 474.47 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:20:31 PM PST 23
Peak memory 200228 kb
Host smart-af9e9a0e-f648-4e0f-ab73-ca2db8a4fea7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1751630119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1751630119
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.727693034
Short name T594
Test name
Test status
Simulation time 122239207693 ps
CPU time 46.53 seconds
Started Dec 31 01:12:17 PM PST 23
Finished Dec 31 01:13:08 PM PST 23
Peak memory 199940 kb
Host smart-feada7c9-7687-406a-81aa-0a30e005aa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727693034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.727693034
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2164919230
Short name T639
Test name
Test status
Simulation time 5455044080 ps
CPU time 2.97 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:27 PM PST 23
Peak memory 195888 kb
Host smart-2099a40b-7d2e-441e-9406-9e962893cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164919230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2164919230
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.36659205
Short name T99
Test name
Test status
Simulation time 133167612 ps
CPU time 0.75 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 217708 kb
Host smart-71eb6128-6f16-4ff4-986e-c90d7c7682ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36659205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.36659205
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2315272430
Short name T550
Test name
Test status
Simulation time 726657160 ps
CPU time 1.58 seconds
Started Dec 31 01:12:19 PM PST 23
Finished Dec 31 01:12:25 PM PST 23
Peak memory 198044 kb
Host smart-f7b45502-904b-48da-ae08-5ebd1c3f4a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315272430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2315272430
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3031181490
Short name T1241
Test name
Test status
Simulation time 426356965352 ps
CPU time 800.87 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:25:51 PM PST 23
Peak memory 200264 kb
Host smart-6f5d3a68-9f8d-470c-a89b-c3d313887b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031181490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3031181490
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1666313841
Short name T1008
Test name
Test status
Simulation time 50552271401 ps
CPU time 554.69 seconds
Started Dec 31 01:12:32 PM PST 23
Finished Dec 31 01:21:51 PM PST 23
Peak memory 216964 kb
Host smart-cf69f288-c9af-48bf-9e13-d4f491648cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666313841 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1666313841
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2983588446
Short name T910
Test name
Test status
Simulation time 261610494 ps
CPU time 1.2 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:12:37 PM PST 23
Peak memory 198120 kb
Host smart-97d9f3fe-513b-425e-a6d8-799211dbf0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983588446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2983588446
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3143898529
Short name T651
Test name
Test status
Simulation time 30829854403 ps
CPU time 35.16 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:13:02 PM PST 23
Peak memory 200368 kb
Host smart-c063e9b2-111d-421a-bac9-1034f2337e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143898529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3143898529
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2219805955
Short name T568
Test name
Test status
Simulation time 11087692 ps
CPU time 0.55 seconds
Started Dec 31 01:14:36 PM PST 23
Finished Dec 31 01:14:38 PM PST 23
Peak memory 194588 kb
Host smart-ee6f997a-179e-42d8-b34c-abec11293577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219805955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2219805955
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3870826853
Short name T953
Test name
Test status
Simulation time 99521311219 ps
CPU time 154.38 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:17:42 PM PST 23
Peak memory 200256 kb
Host smart-9942845d-31c8-458f-87b3-70438d16a8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870826853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3870826853
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1979316042
Short name T667
Test name
Test status
Simulation time 83491394866 ps
CPU time 102.92 seconds
Started Dec 31 01:14:22 PM PST 23
Finished Dec 31 01:16:06 PM PST 23
Peak memory 200144 kb
Host smart-e28a2d05-f4ba-4de8-9d0f-c442d151dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979316042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1979316042
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1812811853
Short name T153
Test name
Test status
Simulation time 18903478575 ps
CPU time 18.49 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:15:23 PM PST 23
Peak memory 200276 kb
Host smart-f05bb797-28a9-46d2-b0e2-a08c4610aa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812811853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1812811853
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.873675585
Short name T1110
Test name
Test status
Simulation time 19697598374 ps
CPU time 14.21 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:14:40 PM PST 23
Peak memory 197836 kb
Host smart-10f8db45-56e9-4996-850f-7129dd81fb4e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873675585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.873675585
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2779565824
Short name T622
Test name
Test status
Simulation time 94720730761 ps
CPU time 691.11 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:26:36 PM PST 23
Peak memory 200252 kb
Host smart-c3403fb8-bc02-44ec-a4af-dc265866c4e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779565824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2779565824
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2708882509
Short name T758
Test name
Test status
Simulation time 497745079 ps
CPU time 1.17 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 196800 kb
Host smart-71013b69-b2c9-4fc8-be00-23f8aa521f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708882509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2708882509
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1052768888
Short name T489
Test name
Test status
Simulation time 124985707741 ps
CPU time 104.01 seconds
Started Dec 31 01:14:40 PM PST 23
Finished Dec 31 01:16:26 PM PST 23
Peak memory 199936 kb
Host smart-ac881198-9f5b-4a17-aee9-1263b154b0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052768888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1052768888
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1758574370
Short name T683
Test name
Test status
Simulation time 16372497808 ps
CPU time 478.53 seconds
Started Dec 31 01:14:45 PM PST 23
Finished Dec 31 01:22:45 PM PST 23
Peak memory 200144 kb
Host smart-4e888b16-489b-4478-be72-f0480f7dc51a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758574370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1758574370
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2429429027
Short name T345
Test name
Test status
Simulation time 75251430978 ps
CPU time 108.13 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:16:49 PM PST 23
Peak memory 200208 kb
Host smart-d6ae39ea-f4fa-48da-a47c-1c507dbbebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429429027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2429429027
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1778465482
Short name T905
Test name
Test status
Simulation time 5295992973 ps
CPU time 9.74 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:14:49 PM PST 23
Peak memory 195948 kb
Host smart-bcc9bdb5-dffe-410b-9417-09bd70e03c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778465482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1778465482
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3632493074
Short name T929
Test name
Test status
Simulation time 5389087221 ps
CPU time 26.46 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:15:54 PM PST 23
Peak memory 199684 kb
Host smart-b4d48741-1677-4b0e-a922-e66f82a3046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632493074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3632493074
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3131799529
Short name T841
Test name
Test status
Simulation time 104206550865 ps
CPU time 899.23 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:29:59 PM PST 23
Peak memory 200556 kb
Host smart-0433dd29-27f6-465c-a82d-d0d915ae6d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131799529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3131799529
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1923525549
Short name T666
Test name
Test status
Simulation time 1308742469 ps
CPU time 2.54 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:15:02 PM PST 23
Peak memory 198520 kb
Host smart-6e8cda83-9440-4d8c-a623-0581e02733cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923525549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1923525549
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2392498795
Short name T133
Test name
Test status
Simulation time 205213209997 ps
CPU time 33.12 seconds
Started Dec 31 01:14:36 PM PST 23
Finished Dec 31 01:15:09 PM PST 23
Peak memory 200212 kb
Host smart-000bf390-0412-41ab-ab8e-d8544f3f909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392498795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2392498795
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2413366789
Short name T985
Test name
Test status
Simulation time 103487681 ps
CPU time 0.59 seconds
Started Dec 31 01:14:39 PM PST 23
Finished Dec 31 01:14:40 PM PST 23
Peak memory 195628 kb
Host smart-23b10a9f-fd97-4864-a06a-7b1dc6f49ca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413366789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2413366789
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3284422234
Short name T980
Test name
Test status
Simulation time 59952949874 ps
CPU time 28.33 seconds
Started Dec 31 01:14:25 PM PST 23
Finished Dec 31 01:14:55 PM PST 23
Peak memory 200168 kb
Host smart-2cf7b52f-b04b-4f33-8606-22d52042ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284422234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3284422234
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2519742777
Short name T1016
Test name
Test status
Simulation time 177701823414 ps
CPU time 290.72 seconds
Started Dec 31 01:14:37 PM PST 23
Finished Dec 31 01:19:29 PM PST 23
Peak memory 200060 kb
Host smart-740c546d-30a4-45d7-af5f-e9f31482c3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519742777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2519742777
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1285972162
Short name T1229
Test name
Test status
Simulation time 17765906406 ps
CPU time 38.32 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:15:22 PM PST 23
Peak memory 199664 kb
Host smart-b873eced-5dab-4b9b-8628-3339c6ee563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285972162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1285972162
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.212790759
Short name T699
Test name
Test status
Simulation time 317508448458 ps
CPU time 229.92 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:18:57 PM PST 23
Peak memory 200188 kb
Host smart-454bff75-6765-474f-91a2-da80e810d1ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212790759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.212790759
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1638010358
Short name T438
Test name
Test status
Simulation time 52789360434 ps
CPU time 420.36 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:22:00 PM PST 23
Peak memory 200144 kb
Host smart-88af1c70-2bf0-44f1-b838-8b33f38f824c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638010358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1638010358
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2452532782
Short name T1194
Test name
Test status
Simulation time 5450087003 ps
CPU time 3.29 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:05 PM PST 23
Peak memory 195976 kb
Host smart-014f3ca0-c956-4c78-b98d-173f8f27ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452532782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2452532782
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.485910026
Short name T982
Test name
Test status
Simulation time 91448355596 ps
CPU time 57.16 seconds
Started Dec 31 01:14:36 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 198796 kb
Host smart-47f52d72-f272-470b-9506-4197499cc370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485910026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.485910026
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.733099452
Short name T608
Test name
Test status
Simulation time 18835245006 ps
CPU time 256.82 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:18:59 PM PST 23
Peak memory 200152 kb
Host smart-8058c72e-351d-4eaf-9d34-cc2a19c4b5f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733099452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.733099452
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4241763559
Short name T765
Test name
Test status
Simulation time 97628034588 ps
CPU time 38.74 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200232 kb
Host smart-b237eba6-96c9-498c-afe4-34b830abea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241763559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4241763559
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1769318291
Short name T450
Test name
Test status
Simulation time 2648349618 ps
CPU time 1.26 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 195732 kb
Host smart-d713dca1-b6a0-480b-aa2b-799e8e3787c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769318291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1769318291
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.4055397863
Short name T476
Test name
Test status
Simulation time 284974598 ps
CPU time 1.44 seconds
Started Dec 31 01:14:24 PM PST 23
Finished Dec 31 01:14:27 PM PST 23
Peak memory 198028 kb
Host smart-e4b0be67-7405-48c9-afb9-f30961930b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055397863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4055397863
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1276048950
Short name T379
Test name
Test status
Simulation time 148007241886 ps
CPU time 245.36 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:18:49 PM PST 23
Peak memory 200212 kb
Host smart-8f5c5025-bbf0-4995-af9d-a186a5413019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276048950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1276048950
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2225872929
Short name T466
Test name
Test status
Simulation time 1342222620 ps
CPU time 1.95 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 197972 kb
Host smart-7ddb4602-9efa-47c9-9f56-34152da6274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225872929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2225872929
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.4000448809
Short name T1190
Test name
Test status
Simulation time 20991087544 ps
CPU time 41.85 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:15:24 PM PST 23
Peak memory 200216 kb
Host smart-8f90fb4c-cfbe-4773-a3b0-c88fa8058b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000448809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.4000448809
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.281539234
Short name T1157
Test name
Test status
Simulation time 20135953 ps
CPU time 0.54 seconds
Started Dec 31 01:15:33 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 194660 kb
Host smart-a3148491-8d1c-46d7-9115-ce51b922d012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281539234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.281539234
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.918282935
Short name T293
Test name
Test status
Simulation time 40861534656 ps
CPU time 10.3 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:15:15 PM PST 23
Peak memory 200164 kb
Host smart-42389290-cb35-4e39-b74e-89fba940a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918282935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.918282935
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3587609089
Short name T780
Test name
Test status
Simulation time 30080915408 ps
CPU time 85.92 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:16:55 PM PST 23
Peak memory 200140 kb
Host smart-af43569e-7e4f-46d2-bf01-ed48f794532c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587609089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3587609089
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3698863870
Short name T364
Test name
Test status
Simulation time 142979731298 ps
CPU time 106.16 seconds
Started Dec 31 01:14:57 PM PST 23
Finished Dec 31 01:16:44 PM PST 23
Peak memory 200208 kb
Host smart-ae07b6a3-10c5-497f-ad5f-a21a847387d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698863870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3698863870
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1066902653
Short name T614
Test name
Test status
Simulation time 1135440771989 ps
CPU time 1868.73 seconds
Started Dec 31 01:14:44 PM PST 23
Finished Dec 31 01:45:55 PM PST 23
Peak memory 198072 kb
Host smart-d348828d-51e7-444d-9de0-5dc9ceaaadd3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066902653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1066902653
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1509731750
Short name T1113
Test name
Test status
Simulation time 175653778635 ps
CPU time 286.09 seconds
Started Dec 31 01:14:40 PM PST 23
Finished Dec 31 01:19:28 PM PST 23
Peak memory 200176 kb
Host smart-9069d9c3-3e5a-4f8a-9ef6-414c6daab56c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509731750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1509731750
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3318294441
Short name T846
Test name
Test status
Simulation time 5775593187 ps
CPU time 10.51 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:19 PM PST 23
Peak memory 199404 kb
Host smart-89d6aeac-7124-4931-9a46-2703832d33ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318294441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3318294441
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2393292841
Short name T896
Test name
Test status
Simulation time 127259934896 ps
CPU time 47.73 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:15:31 PM PST 23
Peak memory 199640 kb
Host smart-805ff6a8-5eca-41a3-932d-dfd2a32ec357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393292841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2393292841
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.796529222
Short name T430
Test name
Test status
Simulation time 27108225346 ps
CPU time 104.9 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:16:45 PM PST 23
Peak memory 200176 kb
Host smart-8ce16f67-7411-4300-8c4e-8d3000c8d811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796529222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.796529222
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3654973764
Short name T534
Test name
Test status
Simulation time 4446788229 ps
CPU time 13.77 seconds
Started Dec 31 01:14:36 PM PST 23
Finished Dec 31 01:14:51 PM PST 23
Peak memory 198884 kb
Host smart-eabd7938-32ef-451b-8334-fde4d526dcb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3654973764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3654973764
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1544847563
Short name T774
Test name
Test status
Simulation time 5851302737 ps
CPU time 2.4 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:14:48 PM PST 23
Peak memory 196052 kb
Host smart-41110f88-22f3-4668-bff8-53e080033b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544847563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1544847563
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4104212268
Short name T803
Test name
Test status
Simulation time 6175470053 ps
CPU time 32.62 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:15:31 PM PST 23
Peak memory 199536 kb
Host smart-bc83d90e-cc6c-4b52-8a2d-b08384502af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104212268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4104212268
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2413910399
Short name T387
Test name
Test status
Simulation time 155895568887 ps
CPU time 539.68 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:24:04 PM PST 23
Peak memory 213836 kb
Host smart-3476dc34-312c-468e-97ea-aec283b9cc08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413910399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2413910399
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2903564033
Short name T470
Test name
Test status
Simulation time 9918560313 ps
CPU time 5.53 seconds
Started Dec 31 01:15:33 PM PST 23
Finished Dec 31 01:15:39 PM PST 23
Peak memory 199088 kb
Host smart-4b27adc4-ee37-4e6a-a0a4-587f2bd49c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903564033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2903564033
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2722874530
Short name T1225
Test name
Test status
Simulation time 16883073276 ps
CPU time 24.57 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:15:10 PM PST 23
Peak memory 200240 kb
Host smart-e3aa525e-67e0-499d-8aaf-9eab531b6bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722874530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2722874530
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1379271602
Short name T935
Test name
Test status
Simulation time 40744878 ps
CPU time 0.55 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:15:05 PM PST 23
Peak memory 195672 kb
Host smart-e7a5a937-0882-4e40-946c-081a46ec4e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379271602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1379271602
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1307452799
Short name T1086
Test name
Test status
Simulation time 168778714776 ps
CPU time 85.61 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:16:36 PM PST 23
Peak memory 200132 kb
Host smart-3882e13a-3897-46e2-865c-c3775c5cd046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307452799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1307452799
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.550215507
Short name T1129
Test name
Test status
Simulation time 56911957738 ps
CPU time 22.84 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:32 PM PST 23
Peak memory 199964 kb
Host smart-5869c077-69cd-4294-9816-b91ddc882cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550215507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.550215507
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.622483663
Short name T585
Test name
Test status
Simulation time 37448463561 ps
CPU time 18.6 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:29 PM PST 23
Peak memory 199752 kb
Host smart-b1dc0402-81bd-479b-9325-bd6ea99dd58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622483663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.622483663
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3140840644
Short name T629
Test name
Test status
Simulation time 139704765898 ps
CPU time 243.88 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:19:13 PM PST 23
Peak memory 200184 kb
Host smart-b9769559-3e1d-4629-8172-6ed32c8411e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140840644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3140840644
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3373776491
Short name T1099
Test name
Test status
Simulation time 77353114828 ps
CPU time 264.41 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:19:29 PM PST 23
Peak memory 200288 kb
Host smart-79fc8c3d-19b7-4f03-95f4-92688fb90bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373776491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3373776491
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1309197657
Short name T888
Test name
Test status
Simulation time 8042535737 ps
CPU time 22.1 seconds
Started Dec 31 01:15:08 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 200032 kb
Host smart-44080690-96e1-4549-9e54-6b65e93db10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309197657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1309197657
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2943189456
Short name T1033
Test name
Test status
Simulation time 40115862930 ps
CPU time 76.55 seconds
Started Dec 31 01:15:14 PM PST 23
Finished Dec 31 01:16:31 PM PST 23
Peak memory 199736 kb
Host smart-7d05435f-ac73-4c0f-a1cb-116d897d2cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943189456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2943189456
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.141402605
Short name T704
Test name
Test status
Simulation time 34045456179 ps
CPU time 167.41 seconds
Started Dec 31 01:15:31 PM PST 23
Finished Dec 31 01:18:19 PM PST 23
Peak memory 200124 kb
Host smart-9b81f096-5994-4ae9-885c-653c6b9979bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141402605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.141402605
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1650383636
Short name T812
Test name
Test status
Simulation time 1076596814 ps
CPU time 6.41 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:17 PM PST 23
Peak memory 197888 kb
Host smart-343184b7-d933-46c8-886e-b35aaf20cc91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650383636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1650383636
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.394426580
Short name T544
Test name
Test status
Simulation time 15029131206 ps
CPU time 17.79 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:15:29 PM PST 23
Peak memory 200232 kb
Host smart-bd5c9944-2d44-4b73-9763-68f60ab5ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394426580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.394426580
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2801099196
Short name T796
Test name
Test status
Simulation time 2976066789 ps
CPU time 1.7 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:12 PM PST 23
Peak memory 195604 kb
Host smart-207b2081-d0a5-4311-8711-f7a62f4e1d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801099196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2801099196
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2824557281
Short name T1141
Test name
Test status
Simulation time 6283432679 ps
CPU time 9.98 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:15:21 PM PST 23
Peak memory 199584 kb
Host smart-a3278ad5-ff84-4ac8-9d8d-b7db5905601c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824557281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2824557281
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2955254249
Short name T468
Test name
Test status
Simulation time 976915800034 ps
CPU time 2233.49 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:51:58 PM PST 23
Peak memory 208684 kb
Host smart-e6df75ad-d250-4413-b3d3-4d6d28b1fba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955254249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2955254249
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2111175993
Short name T81
Test name
Test status
Simulation time 16228298334 ps
CPU time 188.83 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:18:16 PM PST 23
Peak memory 216652 kb
Host smart-3ffdcc8a-d663-4e91-bc93-c420512e27e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111175993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2111175993
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.944872391
Short name T453
Test name
Test status
Simulation time 4893909875 ps
CPU time 2.06 seconds
Started Dec 31 01:15:07 PM PST 23
Finished Dec 31 01:15:14 PM PST 23
Peak memory 198248 kb
Host smart-d8df6641-b0f7-40e2-bde4-9c7acfe91737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944872391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.944872391
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2396704224
Short name T151
Test name
Test status
Simulation time 5759089799 ps
CPU time 5.23 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:15 PM PST 23
Peak memory 198560 kb
Host smart-b507155f-9aac-4afb-a386-9f32dcb432f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396704224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2396704224
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1133594319
Short name T906
Test name
Test status
Simulation time 16698393 ps
CPU time 0.55 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:14:59 PM PST 23
Peak memory 195620 kb
Host smart-a65c451b-5011-46de-9864-526b83c9fab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133594319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1133594319
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1354184041
Short name T1205
Test name
Test status
Simulation time 218413285955 ps
CPU time 15.93 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:15:00 PM PST 23
Peak memory 200204 kb
Host smart-4bee40ad-da6a-406f-9bb5-46b0d32b696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354184041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1354184041
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.758896539
Short name T789
Test name
Test status
Simulation time 158358333448 ps
CPU time 139.99 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:17:05 PM PST 23
Peak memory 200196 kb
Host smart-fb6b0dd9-d67f-41a6-97c8-7eb0f1855908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758896539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.758896539
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3210703675
Short name T254
Test name
Test status
Simulation time 56361687441 ps
CPU time 90.87 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:16:37 PM PST 23
Peak memory 200132 kb
Host smart-d51c2d57-bb65-427e-b27a-5c745ecfa54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210703675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3210703675
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1806176337
Short name T491
Test name
Test status
Simulation time 1185206640551 ps
CPU time 2016.6 seconds
Started Dec 31 01:14:46 PM PST 23
Finished Dec 31 01:48:24 PM PST 23
Peak memory 199876 kb
Host smart-534b46cd-4c83-4ffd-983a-b8c817c18054
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806176337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1806176337
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1962633122
Short name T456
Test name
Test status
Simulation time 112288319463 ps
CPU time 314.65 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:20:22 PM PST 23
Peak memory 200148 kb
Host smart-e66df66e-72bc-478b-83a9-3a03a8e0d5ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1962633122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1962633122
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3714296272
Short name T525
Test name
Test status
Simulation time 1405513879 ps
CPU time 2.55 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:06 PM PST 23
Peak memory 195588 kb
Host smart-cb39c5ba-ba26-4246-80e2-57392dde3983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714296272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3714296272
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.827676156
Short name T1134
Test name
Test status
Simulation time 114306743762 ps
CPU time 253.95 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:19:16 PM PST 23
Peak memory 208584 kb
Host smart-73699b3a-9bf0-4948-bd62-961682801e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827676156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.827676156
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.357264367
Short name T105
Test name
Test status
Simulation time 18014118599 ps
CPU time 255.18 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:19:23 PM PST 23
Peak memory 200264 kb
Host smart-c432c737-845c-4fec-b5a0-951079a1f616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357264367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.357264367
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1538705649
Short name T726
Test name
Test status
Simulation time 2050733951 ps
CPU time 4.32 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:14:49 PM PST 23
Peak memory 198240 kb
Host smart-64368ecc-ab1f-4770-8aff-a8590d5f075e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538705649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1538705649
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3824315136
Short name T361
Test name
Test status
Simulation time 104606116162 ps
CPU time 198 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:18:18 PM PST 23
Peak memory 200208 kb
Host smart-ed950967-1575-439a-a57c-d3f20c396a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824315136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3824315136
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.111563901
Short name T659
Test name
Test status
Simulation time 2175017684 ps
CPU time 1.27 seconds
Started Dec 31 01:14:40 PM PST 23
Finished Dec 31 01:14:43 PM PST 23
Peak memory 195716 kb
Host smart-aac7e6fe-55df-4c91-b31b-6770b39363a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111563901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.111563901
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3945557104
Short name T1172
Test name
Test status
Simulation time 266442485 ps
CPU time 1.22 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:15:05 PM PST 23
Peak memory 198568 kb
Host smart-60b88bec-3a74-4dcd-a93c-c710ce55cd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945557104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3945557104
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2614213508
Short name T1011
Test name
Test status
Simulation time 23987185811 ps
CPU time 727.45 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:27:14 PM PST 23
Peak memory 216588 kb
Host smart-89e4015a-fbc5-437a-8ccd-c799b576df9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614213508 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2614213508
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2646281500
Short name T611
Test name
Test status
Simulation time 828560459 ps
CPU time 1.18 seconds
Started Dec 31 01:14:40 PM PST 23
Finished Dec 31 01:14:43 PM PST 23
Peak memory 198272 kb
Host smart-7c3c0d2f-bf79-471d-9f40-86d0e2d7258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646281500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2646281500
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3981156386
Short name T799
Test name
Test status
Simulation time 18745900634 ps
CPU time 16.68 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:15:01 PM PST 23
Peak memory 200152 kb
Host smart-4a4ac3b5-0f83-466e-bf5b-a9e59889c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981156386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3981156386
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.4211848293
Short name T586
Test name
Test status
Simulation time 10503243 ps
CPU time 0.53 seconds
Started Dec 31 01:15:09 PM PST 23
Finished Dec 31 01:15:12 PM PST 23
Peak memory 194568 kb
Host smart-364757ba-6f69-4dcd-b3fb-c354efa1f22d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211848293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4211848293
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1138609849
Short name T625
Test name
Test status
Simulation time 42817742436 ps
CPU time 79.68 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:16:27 PM PST 23
Peak memory 200152 kb
Host smart-5509c172-f017-4e3f-8c16-3749bae2b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138609849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1138609849
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2863849388
Short name T1076
Test name
Test status
Simulation time 23608167573 ps
CPU time 37.78 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:47 PM PST 23
Peak memory 200136 kb
Host smart-af61fba0-13bd-448c-82f0-acc9adb4bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863849388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2863849388
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.628163291
Short name T40
Test name
Test status
Simulation time 131701439350 ps
CPU time 113.78 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:17:05 PM PST 23
Peak memory 200216 kb
Host smart-19debc26-a1cd-44d5-bed4-1486894d6934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628163291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.628163291
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3492785610
Short name T435
Test name
Test status
Simulation time 2971443249549 ps
CPU time 565.71 seconds
Started Dec 31 01:15:31 PM PST 23
Finished Dec 31 01:24:58 PM PST 23
Peak memory 199892 kb
Host smart-2b116280-53d4-4a3d-896e-1c665e18e7af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492785610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3492785610
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3084528404
Short name T738
Test name
Test status
Simulation time 39238746758 ps
CPU time 172.92 seconds
Started Dec 31 01:15:14 PM PST 23
Finished Dec 31 01:18:08 PM PST 23
Peak memory 200216 kb
Host smart-6aea072b-951b-4fa7-8c51-9aca167f5e62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084528404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3084528404
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.982085960
Short name T940
Test name
Test status
Simulation time 10774406739 ps
CPU time 9.23 seconds
Started Dec 31 01:15:14 PM PST 23
Finished Dec 31 01:15:24 PM PST 23
Peak memory 199100 kb
Host smart-041521d6-e1db-486a-b497-d9027b5845da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982085960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.982085960
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3694417285
Short name T437
Test name
Test status
Simulation time 127219003115 ps
CPU time 57.4 seconds
Started Dec 31 01:15:31 PM PST 23
Finished Dec 31 01:16:30 PM PST 23
Peak memory 200496 kb
Host smart-94a17fd1-9390-4c9c-9e1f-51fd165e1ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694417285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3694417285
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1938973871
Short name T265
Test name
Test status
Simulation time 16554166963 ps
CPU time 194.62 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:18:52 PM PST 23
Peak memory 200228 kb
Host smart-2822044d-8e33-46bc-bfb9-f2dce64df69e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938973871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1938973871
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3492591016
Short name T1171
Test name
Test status
Simulation time 4454230404 ps
CPU time 42.5 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:53 PM PST 23
Peak memory 198892 kb
Host smart-dcf624b3-95b6-492c-bae2-f9173b02645d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492591016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3492591016
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3900549252
Short name T828
Test name
Test status
Simulation time 26081249923 ps
CPU time 12.73 seconds
Started Dec 31 01:15:34 PM PST 23
Finished Dec 31 01:15:48 PM PST 23
Peak memory 199096 kb
Host smart-d15eb911-7dde-405d-8db4-dc001e4e4162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900549252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3900549252
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2297740011
Short name T467
Test name
Test status
Simulation time 5369399662 ps
CPU time 2.66 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:15:14 PM PST 23
Peak memory 195944 kb
Host smart-04dd8a4e-adae-48d0-9eba-9a2f097adf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297740011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2297740011
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1047162787
Short name T734
Test name
Test status
Simulation time 6200982201 ps
CPU time 8.67 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:15:14 PM PST 23
Peak memory 199584 kb
Host smart-145f0fa9-24f2-406b-b584-67d4a02e8ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047162787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1047162787
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1147129527
Short name T1218
Test name
Test status
Simulation time 66689903665 ps
CPU time 109.72 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:17:00 PM PST 23
Peak memory 200176 kb
Host smart-a708d572-4a61-4312-9aac-16dc79875038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147129527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1147129527
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1555489912
Short name T721
Test name
Test status
Simulation time 1776429627 ps
CPU time 3.29 seconds
Started Dec 31 01:15:14 PM PST 23
Finished Dec 31 01:15:18 PM PST 23
Peak memory 198636 kb
Host smart-f1764980-b8dc-4955-9f07-ae502e9eba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555489912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1555489912
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2045972522
Short name T915
Test name
Test status
Simulation time 25820341160 ps
CPU time 45.55 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:15:53 PM PST 23
Peak memory 199456 kb
Host smart-94a9c089-2995-4a6f-8367-e30518718bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045972522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2045972522
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3158653459
Short name T1182
Test name
Test status
Simulation time 14715706 ps
CPU time 0.55 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:02 PM PST 23
Peak memory 195660 kb
Host smart-e3b62eb4-0f94-45fc-9371-bc44096c36da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158653459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3158653459
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2768934169
Short name T714
Test name
Test status
Simulation time 53265317817 ps
CPU time 38.42 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 200156 kb
Host smart-4bdb3a35-b58b-48d6-a1a1-5509ea32f498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768934169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2768934169
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.854231337
Short name T1160
Test name
Test status
Simulation time 60495563593 ps
CPU time 24.08 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:27 PM PST 23
Peak memory 200280 kb
Host smart-ff25260f-896f-4561-8ae1-b22fb0fd61d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854231337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.854231337
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.4070904016
Short name T232
Test name
Test status
Simulation time 118081631827 ps
CPU time 179.1 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:17:42 PM PST 23
Peak memory 200172 kb
Host smart-3e5c5152-965e-4431-8460-8986045bdb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070904016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4070904016
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.4277179498
Short name T637
Test name
Test status
Simulation time 68439638470 ps
CPU time 431.72 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:22:16 PM PST 23
Peak memory 200176 kb
Host smart-98342010-4edb-41d8-9c2d-b6a0f77dfad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277179498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4277179498
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.903012970
Short name T972
Test name
Test status
Simulation time 2907588286 ps
CPU time 3.43 seconds
Started Dec 31 01:14:40 PM PST 23
Finished Dec 31 01:14:45 PM PST 23
Peak memory 197472 kb
Host smart-b7068097-10d9-4285-8f5a-58487ab89426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903012970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.903012970
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4145531053
Short name T1007
Test name
Test status
Simulation time 35405134669 ps
CPU time 42 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:43 PM PST 23
Peak memory 199668 kb
Host smart-75512bbe-eed6-4eeb-8d3c-c63d4c5142d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145531053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4145531053
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2677464552
Short name T943
Test name
Test status
Simulation time 24286141808 ps
CPU time 687.53 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:26:37 PM PST 23
Peak memory 200180 kb
Host smart-46abb48d-5417-4abf-a352-ed92346b7882
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677464552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2677464552
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3546146253
Short name T17
Test name
Test status
Simulation time 1340947513 ps
CPU time 3.87 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 198504 kb
Host smart-c2b245d0-1df1-4fdf-9ab2-a1449ff322e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546146253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3546146253
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2206612806
Short name T412
Test name
Test status
Simulation time 97187563835 ps
CPU time 79.85 seconds
Started Dec 31 01:14:40 PM PST 23
Finished Dec 31 01:16:02 PM PST 23
Peak memory 199660 kb
Host smart-33106692-99eb-4233-b455-4ac47dc74dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206612806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2206612806
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1947163454
Short name T1144
Test name
Test status
Simulation time 595265708 ps
CPU time 1.49 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 195620 kb
Host smart-2e5adf43-958c-4a01-91d6-f3ec3d62efb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947163454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1947163454
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.67977506
Short name T700
Test name
Test status
Simulation time 514180864 ps
CPU time 1.76 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:15:13 PM PST 23
Peak memory 198080 kb
Host smart-43a71b80-9cb6-4f68-b1d4-d3e845f5a90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67977506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.67977506
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1052927820
Short name T148
Test name
Test status
Simulation time 158231298066 ps
CPU time 664.04 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:25:48 PM PST 23
Peak memory 200216 kb
Host smart-3c2d1055-f1ee-4749-a997-b930c9523b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052927820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1052927820
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3980330345
Short name T904
Test name
Test status
Simulation time 43681592789 ps
CPU time 93.54 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:16:18 PM PST 23
Peak memory 215772 kb
Host smart-6e60b002-dcb7-4ebf-93c0-b8f72ec507ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980330345 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3980330345
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2263750802
Short name T847
Test name
Test status
Simulation time 6738256249 ps
CPU time 16.16 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 199196 kb
Host smart-fda227a8-3114-4885-baf9-ee3eb94af31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263750802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2263750802
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1902079288
Short name T1069
Test name
Test status
Simulation time 28207673786 ps
CPU time 41.93 seconds
Started Dec 31 01:15:08 PM PST 23
Finished Dec 31 01:15:54 PM PST 23
Peak memory 200100 kb
Host smart-5ec4b1a5-3184-4f14-b408-b4a7f5551af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902079288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1902079288
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.32204392
Short name T570
Test name
Test status
Simulation time 15189230 ps
CPU time 0.55 seconds
Started Dec 31 01:15:33 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 195628 kb
Host smart-67ab8e42-94f4-45c0-80b5-09ecab49725e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32204392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.32204392
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.52375913
Short name T222
Test name
Test status
Simulation time 232860458859 ps
CPU time 288.55 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:19:33 PM PST 23
Peak memory 200200 kb
Host smart-9864d646-2dbf-493e-9d8f-0e1d4858787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52375913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.52375913
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1317530700
Short name T253
Test name
Test status
Simulation time 92512328316 ps
CPU time 144.82 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:17:30 PM PST 23
Peak memory 200284 kb
Host smart-33070f51-fce0-43ec-98f0-1aa765405935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317530700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1317530700
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1222899778
Short name T220
Test name
Test status
Simulation time 321355884889 ps
CPU time 38.64 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:15:22 PM PST 23
Peak memory 200132 kb
Host smart-9a69ff94-624b-4ff6-8cc8-990c85377f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222899778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1222899778
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3619847895
Short name T1209
Test name
Test status
Simulation time 672314294193 ps
CPU time 284.77 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:20:14 PM PST 23
Peak memory 200204 kb
Host smart-5adcbc1a-1b0f-45c8-880b-27f7692ff331
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619847895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3619847895
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_loopback.2295127149
Short name T903
Test name
Test status
Simulation time 11143685820 ps
CPU time 6.6 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:15:35 PM PST 23
Peak memory 199628 kb
Host smart-c80b2125-60aa-4850-9090-a7e58741bbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295127149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2295127149
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1401361552
Short name T259
Test name
Test status
Simulation time 42651510049 ps
CPU time 67.91 seconds
Started Dec 31 01:14:46 PM PST 23
Finished Dec 31 01:15:55 PM PST 23
Peak memory 198996 kb
Host smart-128cc1b7-1594-4b77-bfb5-bf3a89af4337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401361552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1401361552
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2982923204
Short name T725
Test name
Test status
Simulation time 5110277686 ps
CPU time 300.42 seconds
Started Dec 31 01:15:31 PM PST 23
Finished Dec 31 01:20:32 PM PST 23
Peak memory 200196 kb
Host smart-85ca076c-cde1-4f6d-829e-b0ccde070365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982923204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2982923204
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2963469275
Short name T1213
Test name
Test status
Simulation time 55019682333 ps
CPU time 74.68 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:16:21 PM PST 23
Peak memory 200232 kb
Host smart-413dbdd4-7e9b-4d91-9ada-ad84a3658d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963469275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2963469275
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1571530232
Short name T1145
Test name
Test status
Simulation time 1839207084 ps
CPU time 3.53 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:06 PM PST 23
Peak memory 195604 kb
Host smart-f386ac64-debf-4767-89ec-23a411706bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571530232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1571530232
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3304690348
Short name T1151
Test name
Test status
Simulation time 499995143 ps
CPU time 2.67 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:11 PM PST 23
Peak memory 198516 kb
Host smart-59af0b4a-eb4f-4c3d-ad3d-ec4c2982d7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304690348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3304690348
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1267138921
Short name T428
Test name
Test status
Simulation time 27814134404 ps
CPU time 107.32 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:16:58 PM PST 23
Peak memory 215880 kb
Host smart-869261ea-369d-401d-8a26-c0f8780638c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267138921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1267138921
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3372931943
Short name T638
Test name
Test status
Simulation time 7717747276 ps
CPU time 9.63 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:20 PM PST 23
Peak memory 199564 kb
Host smart-91278e21-bfc5-49b0-9736-1451849bcb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372931943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3372931943
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1836319097
Short name T458
Test name
Test status
Simulation time 51817911050 ps
CPU time 43.4 seconds
Started Dec 31 01:14:45 PM PST 23
Finished Dec 31 01:15:30 PM PST 23
Peak memory 199772 kb
Host smart-79175abf-b7ef-4288-8ba3-3fe5b15332ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836319097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1836319097
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3562185805
Short name T1057
Test name
Test status
Simulation time 14817050 ps
CPU time 0.57 seconds
Started Dec 31 01:14:44 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 195672 kb
Host smart-6aff0d3c-80e2-4f04-9b94-5c6333a5a85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562185805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3562185805
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3873064648
Short name T697
Test name
Test status
Simulation time 175186022424 ps
CPU time 74.27 seconds
Started Dec 31 01:14:47 PM PST 23
Finished Dec 31 01:16:02 PM PST 23
Peak memory 200164 kb
Host smart-31959a89-239f-4808-b5e2-f9441740d5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873064648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3873064648
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.4004833099
Short name T956
Test name
Test status
Simulation time 156824185362 ps
CPU time 235.85 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:19:01 PM PST 23
Peak memory 200224 kb
Host smart-53ac62f9-aeff-4602-8632-2d56187cacf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004833099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.4004833099
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3688350525
Short name T754
Test name
Test status
Simulation time 92786626231 ps
CPU time 35.5 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:15:19 PM PST 23
Peak memory 200452 kb
Host smart-f32ecf19-ecef-4eeb-820a-0373e97cfb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688350525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3688350525
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1512908472
Short name T930
Test name
Test status
Simulation time 63898793665 ps
CPU time 91.12 seconds
Started Dec 31 01:14:44 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 198972 kb
Host smart-519419fd-0c7e-4914-856b-df81792af311
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512908472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1512908472
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2438895007
Short name T759
Test name
Test status
Simulation time 49564600709 ps
CPU time 211.34 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:18:37 PM PST 23
Peak memory 200184 kb
Host smart-7d2036ae-e9fd-475b-bd31-035fb7937cec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438895007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2438895007
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1597615476
Short name T1201
Test name
Test status
Simulation time 4613503794 ps
CPU time 5.07 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:16 PM PST 23
Peak memory 197620 kb
Host smart-1cf63124-1546-45dd-b57e-a555cdd7b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597615476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1597615476
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3353735050
Short name T1029
Test name
Test status
Simulation time 46465378406 ps
CPU time 46.35 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 199992 kb
Host smart-94bd2b43-6bdb-41ae-984c-bb374a8b8188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353735050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3353735050
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.153623050
Short name T740
Test name
Test status
Simulation time 13372153080 ps
CPU time 730.6 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:27:11 PM PST 23
Peak memory 200204 kb
Host smart-9dadf0ef-66f3-4f86-b0cc-aa16fa947d58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153623050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.153623050
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2017727639
Short name T642
Test name
Test status
Simulation time 1595882705 ps
CPU time 5.85 seconds
Started Dec 31 01:15:07 PM PST 23
Finished Dec 31 01:15:17 PM PST 23
Peak memory 197912 kb
Host smart-d7684f17-2640-4461-a3ed-6717dfd6f350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017727639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2017727639
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1297836146
Short name T1223
Test name
Test status
Simulation time 173018605072 ps
CPU time 235.94 seconds
Started Dec 31 01:14:45 PM PST 23
Finished Dec 31 01:18:42 PM PST 23
Peak memory 200244 kb
Host smart-bae67e2f-5a5c-43f9-ad34-7213ac47fee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297836146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1297836146
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.839472604
Short name T538
Test name
Test status
Simulation time 36640056620 ps
CPU time 14.85 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:15:13 PM PST 23
Peak memory 196040 kb
Host smart-560571c3-869e-4a55-94c8-8b2dfb580bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839472604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.839472604
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3562478864
Short name T640
Test name
Test status
Simulation time 472177721 ps
CPU time 1.55 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:15:37 PM PST 23
Peak memory 198192 kb
Host smart-0d7de72c-ae17-46ff-9a26-629bd5fb0e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562478864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3562478864
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1111069143
Short name T880
Test name
Test status
Simulation time 625506537 ps
CPU time 1.83 seconds
Started Dec 31 01:14:40 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 198512 kb
Host smart-e19b8906-2dd6-4254-9da3-31eac0926a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111069143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1111069143
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1383346428
Short name T979
Test name
Test status
Simulation time 94564771669 ps
CPU time 192.42 seconds
Started Dec 31 01:15:06 PM PST 23
Finished Dec 31 01:18:23 PM PST 23
Peak memory 200176 kb
Host smart-b0e5fe84-d8f4-466d-982a-7d6b5eecf40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383346428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1383346428
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2733784891
Short name T1068
Test name
Test status
Simulation time 31459137 ps
CPU time 0.56 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:15:05 PM PST 23
Peak memory 194672 kb
Host smart-c7a60d48-e050-417b-8b9d-69e359cc22c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733784891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2733784891
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1921222367
Short name T981
Test name
Test status
Simulation time 29038354770 ps
CPU time 11.74 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:15:18 PM PST 23
Peak memory 200240 kb
Host smart-6bad82c2-f811-4395-8a9d-2ef05ef1f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921222367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1921222367
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.81946337
Short name T1128
Test name
Test status
Simulation time 147684896702 ps
CPU time 109.25 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:16:58 PM PST 23
Peak memory 200168 kb
Host smart-51a579f7-106d-4ee2-95f1-df376843bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81946337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.81946337
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1116393108
Short name T269
Test name
Test status
Simulation time 216503636507 ps
CPU time 19.07 seconds
Started Dec 31 01:15:25 PM PST 23
Finished Dec 31 01:15:45 PM PST 23
Peak memory 200116 kb
Host smart-0c83a804-3903-4d40-a6c9-4486e6f5f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116393108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1116393108
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.291306592
Short name T1240
Test name
Test status
Simulation time 1673116773764 ps
CPU time 2813.24 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 02:01:58 PM PST 23
Peak memory 200152 kb
Host smart-b1de151e-9d15-41b5-b56d-46f91f9d2d14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291306592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.291306592
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.119949226
Short name T1192
Test name
Test status
Simulation time 99696420986 ps
CPU time 689.64 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:26:13 PM PST 23
Peak memory 200196 kb
Host smart-253342a3-4a40-4e02-9be4-47b5efd7cd50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119949226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.119949226
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3702814107
Short name T1231
Test name
Test status
Simulation time 3936282317 ps
CPU time 2.87 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:15:30 PM PST 23
Peak memory 198280 kb
Host smart-25f19887-2c70-42cd-a817-fbc867fbc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702814107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3702814107
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2253416979
Short name T158
Test name
Test status
Simulation time 140693152903 ps
CPU time 159.77 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:17:46 PM PST 23
Peak memory 199460 kb
Host smart-f0fc2171-7105-4037-b13c-6eeaeab844be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253416979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2253416979
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.4191895006
Short name T264
Test name
Test status
Simulation time 17892349899 ps
CPU time 824.24 seconds
Started Dec 31 01:14:36 PM PST 23
Finished Dec 31 01:28:21 PM PST 23
Peak memory 200264 kb
Host smart-ea571a2e-32fa-4eaa-a74c-1b61ba42fd52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191895006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4191895006
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3840590551
Short name T1131
Test name
Test status
Simulation time 2599968555 ps
CPU time 1.87 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:12 PM PST 23
Peak memory 198644 kb
Host smart-7e9f8fe9-2ef1-4566-8a33-5ff6e1acea77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840590551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3840590551
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3381103651
Short name T695
Test name
Test status
Simulation time 724038007 ps
CPU time 1.86 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:14:46 PM PST 23
Peak memory 195772 kb
Host smart-d9a12fd4-6953-4745-b34e-a8916c46376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381103651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3381103651
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2234490599
Short name T457
Test name
Test status
Simulation time 534877462 ps
CPU time 2.16 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:14:44 PM PST 23
Peak memory 199952 kb
Host smart-42a87b1c-bc30-4f3f-9833-4aee187d93aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234490599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2234490599
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2010786005
Short name T464
Test name
Test status
Simulation time 38159933265 ps
CPU time 430.09 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:21:55 PM PST 23
Peak memory 216964 kb
Host smart-ae144430-3893-44c7-a52c-77f1a04df7fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010786005 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2010786005
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2600478204
Short name T1023
Test name
Test status
Simulation time 1847171481 ps
CPU time 1.63 seconds
Started Dec 31 01:14:44 PM PST 23
Finished Dec 31 01:14:47 PM PST 23
Peak memory 198568 kb
Host smart-6d7efdfb-2d4b-428d-bb7b-1aad80505472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600478204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2600478204
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2689367846
Short name T321
Test name
Test status
Simulation time 10154623944 ps
CPU time 5.14 seconds
Started Dec 31 01:14:46 PM PST 23
Finished Dec 31 01:14:53 PM PST 23
Peak memory 200136 kb
Host smart-5e24aa10-c23c-4f2e-ada0-29df5b55fabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689367846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2689367846
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1308057353
Short name T947
Test name
Test status
Simulation time 65383820 ps
CPU time 0.54 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:12:34 PM PST 23
Peak memory 195612 kb
Host smart-8c13eae6-10b7-4584-b077-d9779d7fe572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308057353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1308057353
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2111945760
Short name T710
Test name
Test status
Simulation time 18482481666 ps
CPU time 32.61 seconds
Started Dec 31 01:12:21 PM PST 23
Finished Dec 31 01:12:59 PM PST 23
Peak memory 200104 kb
Host smart-b0705b43-8bd2-42d2-8c52-314f22f45b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111945760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2111945760
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.832779912
Short name T920
Test name
Test status
Simulation time 31636171239 ps
CPU time 24.56 seconds
Started Dec 31 01:12:20 PM PST 23
Finished Dec 31 01:12:50 PM PST 23
Peak memory 199384 kb
Host smart-a281c13b-5308-40ec-9ea8-8c767ef9b029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832779912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.832779912
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.3398546724
Short name T482
Test name
Test status
Simulation time 8358960747 ps
CPU time 7.31 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:41 PM PST 23
Peak memory 194704 kb
Host smart-d05ca397-c3d4-40d4-a13c-581a91c18e51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398546724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3398546724
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1529743800
Short name T576
Test name
Test status
Simulation time 93358134273 ps
CPU time 135.44 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:14:52 PM PST 23
Peak memory 200136 kb
Host smart-6b691140-1b9e-4ad6-abea-3cb77cb157c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1529743800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1529743800
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3008283831
Short name T957
Test name
Test status
Simulation time 12365162303 ps
CPU time 4.91 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 197828 kb
Host smart-076700c4-3eb7-4f7a-a568-cb36c676feb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008283831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3008283831
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.176841219
Short name T1014
Test name
Test status
Simulation time 73367611905 ps
CPU time 30.68 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:13:04 PM PST 23
Peak memory 198684 kb
Host smart-2f7bc8c2-1a95-440f-84a2-f81923e19763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176841219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.176841219
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3546041880
Short name T963
Test name
Test status
Simulation time 19748663195 ps
CPU time 158.05 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:15:08 PM PST 23
Peak memory 200232 kb
Host smart-9f436f51-cf0e-4e8a-a880-3ad29fb31f13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546041880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3546041880
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1820367694
Short name T1106
Test name
Test status
Simulation time 2495480397 ps
CPU time 22.2 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:12:54 PM PST 23
Peak memory 198340 kb
Host smart-75000e68-ec45-4f49-94a9-d701be8084c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820367694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1820367694
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2708424965
Short name T172
Test name
Test status
Simulation time 33606641886 ps
CPU time 54.55 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:13:26 PM PST 23
Peak memory 198644 kb
Host smart-16209b0e-bb4d-4019-b0ac-268b79b94f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708424965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2708424965
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2789559818
Short name T1088
Test name
Test status
Simulation time 33216103306 ps
CPU time 47.08 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:13:21 PM PST 23
Peak memory 195784 kb
Host smart-56629cfe-8e7e-45b8-b6f6-fbae478e2ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789559818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2789559818
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1526968052
Short name T12
Test name
Test status
Simulation time 11616274830 ps
CPU time 39.49 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:13:11 PM PST 23
Peak memory 200208 kb
Host smart-b4683d1d-458e-4e3b-86db-323fbb469077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526968052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1526968052
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.4152031132
Short name T384
Test name
Test status
Simulation time 360529996017 ps
CPU time 222.8 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:16:14 PM PST 23
Peak memory 208684 kb
Host smart-b09c0978-1181-47aa-9941-d57956b9a26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152031132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4152031132
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3682875961
Short name T404
Test name
Test status
Simulation time 86152337210 ps
CPU time 277.44 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:17:11 PM PST 23
Peak memory 216808 kb
Host smart-75562d48-61a9-4bcc-8bb9-78d4c605935c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682875961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3682875961
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3656271432
Short name T478
Test name
Test status
Simulation time 1518818107 ps
CPU time 1.8 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:12:31 PM PST 23
Peak memory 198216 kb
Host smart-00a86783-bf95-4fc8-88d2-34587bd8f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656271432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3656271432
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2439371574
Short name T170
Test name
Test status
Simulation time 149661671297 ps
CPU time 62.28 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:13:35 PM PST 23
Peak memory 200120 kb
Host smart-a04589b7-93e1-40b5-87b1-535f8e8e7691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439371574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2439371574
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3776149656
Short name T184
Test name
Test status
Simulation time 205388007345 ps
CPU time 69.46 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:16:14 PM PST 23
Peak memory 200356 kb
Host smart-05b481ca-6148-4d30-9c22-4f4d540fc06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776149656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3776149656
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4089486955
Short name T64
Test name
Test status
Simulation time 43015305377 ps
CPU time 304.89 seconds
Started Dec 31 01:15:32 PM PST 23
Finished Dec 31 01:20:37 PM PST 23
Peak memory 216668 kb
Host smart-7f3f33a7-c77d-45d7-9054-3758bd132330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089486955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4089486955
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3585807794
Short name T331
Test name
Test status
Simulation time 16271584410 ps
CPU time 14.18 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:15:44 PM PST 23
Peak memory 200192 kb
Host smart-95dac28d-6bbd-49df-ae9f-86eb832d8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585807794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3585807794
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.4080036545
Short name T723
Test name
Test status
Simulation time 19186764169 ps
CPU time 312.87 seconds
Started Dec 31 01:15:30 PM PST 23
Finished Dec 31 01:20:44 PM PST 23
Peak memory 216884 kb
Host smart-88ace486-c366-4a81-bb40-9f8a1ba850b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080036545 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4080036545
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3961119957
Short name T322
Test name
Test status
Simulation time 58151031056 ps
CPU time 32.38 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:43 PM PST 23
Peak memory 200096 kb
Host smart-994bea1d-db49-430e-ae4b-0fa0fdcadbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961119957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3961119957
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.975907540
Short name T1181
Test name
Test status
Simulation time 63432492409 ps
CPU time 433.47 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:22:22 PM PST 23
Peak memory 210416 kb
Host smart-89be8e6f-6f38-48d6-b595-a04844b43ba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975907540 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.975907540
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1354612390
Short name T181
Test name
Test status
Simulation time 99345174458 ps
CPU time 165.18 seconds
Started Dec 31 01:14:45 PM PST 23
Finished Dec 31 01:17:32 PM PST 23
Peak memory 199872 kb
Host smart-8b5d9819-9036-434e-b668-d7d61302c122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354612390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1354612390
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1762473086
Short name T627
Test name
Test status
Simulation time 9444531719 ps
CPU time 19.07 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:15:19 PM PST 23
Peak memory 200144 kb
Host smart-499ad783-44e6-4944-b6ef-50097cd97bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762473086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1762473086
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3936800462
Short name T894
Test name
Test status
Simulation time 88845003360 ps
CPU time 144.31 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:17:27 PM PST 23
Peak memory 208412 kb
Host smart-6e98be34-9404-452e-ae6d-40ba6354e843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936800462 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3936800462
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.847891278
Short name T1108
Test name
Test status
Simulation time 140606781497 ps
CPU time 33.85 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:36 PM PST 23
Peak memory 200048 kb
Host smart-5f35225a-d99a-443d-8a9a-b9c4651d5209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847891278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.847891278
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3545275615
Short name T561
Test name
Test status
Simulation time 14386228944 ps
CPU time 128.86 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:17:17 PM PST 23
Peak memory 208600 kb
Host smart-c493c166-65e0-47ae-8326-bb9f559c7f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545275615 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3545275615
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.997341047
Short name T107
Test name
Test status
Simulation time 94578568109 ps
CPU time 135.56 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:17:19 PM PST 23
Peak memory 200248 kb
Host smart-6a77ad20-fe23-478b-9e59-b7f0d98a6379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997341047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.997341047
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3614541914
Short name T927
Test name
Test status
Simulation time 63953236119 ps
CPU time 716.9 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:27:06 PM PST 23
Peak memory 208528 kb
Host smart-e54cbb3c-3ed7-4057-848f-ee7e4a3d3925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614541914 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3614541914
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1883462210
Short name T225
Test name
Test status
Simulation time 25292143115 ps
CPU time 25.71 seconds
Started Dec 31 01:15:32 PM PST 23
Finished Dec 31 01:15:58 PM PST 23
Peak memory 200020 kb
Host smart-bb169fb0-3f90-4d48-971d-040b85abad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883462210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1883462210
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.484018408
Short name T65
Test name
Test status
Simulation time 272828085997 ps
CPU time 1510.84 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:39:53 PM PST 23
Peak memory 229972 kb
Host smart-cf12257d-cdfd-4830-a79e-1b2e771c5cc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484018408 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.484018408
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1744917941
Short name T306
Test name
Test status
Simulation time 335202698550 ps
CPU time 65.2 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:15:49 PM PST 23
Peak memory 200132 kb
Host smart-44a549c3-bd46-4c78-84fb-5b61f83540f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744917941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1744917941
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.4087499760
Short name T178
Test name
Test status
Simulation time 95643943604 ps
CPU time 47.47 seconds
Started Dec 31 01:14:58 PM PST 23
Finished Dec 31 01:15:47 PM PST 23
Peak memory 200100 kb
Host smart-483784c5-b925-4ee0-a6ba-391be1533990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087499760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4087499760
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3574527268
Short name T984
Test name
Test status
Simulation time 38559938 ps
CPU time 0.53 seconds
Started Dec 31 01:12:27 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 195596 kb
Host smart-0be17075-6cd9-40ed-a40f-70688dc414a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574527268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3574527268
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.882946402
Short name T1060
Test name
Test status
Simulation time 183573201541 ps
CPU time 88.35 seconds
Started Dec 31 01:12:27 PM PST 23
Finished Dec 31 01:14:01 PM PST 23
Peak memory 200124 kb
Host smart-fa6851cb-043a-4350-ad8b-bccba03b3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882946402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.882946402
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3020264380
Short name T933
Test name
Test status
Simulation time 58878391350 ps
CPU time 95.85 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:14:06 PM PST 23
Peak memory 199432 kb
Host smart-2f88e846-175d-48d3-9fed-943b176853fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020264380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3020264380
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2263408361
Short name T388
Test name
Test status
Simulation time 187250091240 ps
CPU time 157.87 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:15:14 PM PST 23
Peak memory 200104 kb
Host smart-ca517e92-dae1-4d91-9df8-625c3041783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263408361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2263408361
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1014552567
Short name T1102
Test name
Test status
Simulation time 27794048750 ps
CPU time 11.75 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:42 PM PST 23
Peak memory 198704 kb
Host smart-206111c9-9cdb-425c-b260-bf24af9dc62e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014552567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1014552567
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3640219639
Short name T893
Test name
Test status
Simulation time 115588472978 ps
CPU time 193.69 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:15:49 PM PST 23
Peak memory 200116 kb
Host smart-a111666d-3d9a-4745-8d79-47002317f784
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640219639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3640219639
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2573988478
Short name T892
Test name
Test status
Simulation time 8212857121 ps
CPU time 2.9 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 199048 kb
Host smart-569351f7-2e6f-46dc-9d85-8cc264e27c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573988478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2573988478
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.638402031
Short name T787
Test name
Test status
Simulation time 81307805643 ps
CPU time 43.27 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:13:13 PM PST 23
Peak memory 199716 kb
Host smart-72f667c4-6aa1-41eb-9b23-5dffcc65bbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638402031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.638402031
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2226153131
Short name T1170
Test name
Test status
Simulation time 22869358704 ps
CPU time 1127.44 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:31:23 PM PST 23
Peak memory 200140 kb
Host smart-aa603468-d5ea-4eda-af27-8a2a19bda09f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226153131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2226153131
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3720520553
Short name T845
Test name
Test status
Simulation time 2800909135 ps
CPU time 21.11 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:54 PM PST 23
Peak memory 197960 kb
Host smart-71c3ec00-ffb3-4e77-b5c6-2533f3bbb056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720520553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3720520553
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.4065529254
Short name T221
Test name
Test status
Simulation time 30004080676 ps
CPU time 41.16 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:13:12 PM PST 23
Peak memory 199392 kb
Host smart-0a7aa3f1-9f68-4202-b39b-a85aa8665b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065529254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4065529254
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3378633949
Short name T729
Test name
Test status
Simulation time 38051319933 ps
CPU time 56.5 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:13:32 PM PST 23
Peak memory 196048 kb
Host smart-94f47af9-2b7c-4294-ae86-14305b308fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378633949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3378633949
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3805273765
Short name T763
Test name
Test status
Simulation time 5573022358 ps
CPU time 6.7 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:37 PM PST 23
Peak memory 198884 kb
Host smart-e0dd85da-0c54-48d9-982f-38969b5940e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805273765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3805273765
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2935539455
Short name T945
Test name
Test status
Simulation time 118864336912 ps
CPU time 104.59 seconds
Started Dec 31 01:12:26 PM PST 23
Finished Dec 31 01:14:16 PM PST 23
Peak memory 200188 kb
Host smart-0f870471-b93e-4cb2-be68-3a372be2ec6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935539455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2935539455
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1642717602
Short name T1002
Test name
Test status
Simulation time 989904722 ps
CPU time 3.08 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 200100 kb
Host smart-de3e7420-189b-4974-919e-eb5d5014eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642717602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1642717602
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2794537005
Short name T480
Test name
Test status
Simulation time 77254328131 ps
CPU time 36.26 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:13:10 PM PST 23
Peak memory 199044 kb
Host smart-003c7aed-d858-479e-8169-011de9408b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794537005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2794537005
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1095803577
Short name T206
Test name
Test status
Simulation time 280382660948 ps
CPU time 98.37 seconds
Started Dec 31 01:14:43 PM PST 23
Finished Dec 31 01:16:23 PM PST 23
Peak memory 200356 kb
Host smart-7f27f1b1-3da3-45d4-8961-31e03e944584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095803577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1095803577
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.68616134
Short name T189
Test name
Test status
Simulation time 546752210773 ps
CPU time 486.92 seconds
Started Dec 31 01:15:33 PM PST 23
Finished Dec 31 01:23:41 PM PST 23
Peak memory 214060 kb
Host smart-e96fa66b-e765-48d5-91d1-9a9882904555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68616134 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.68616134
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.952469033
Short name T465
Test name
Test status
Simulation time 96310382610 ps
CPU time 522.49 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:23:43 PM PST 23
Peak memory 225064 kb
Host smart-82b0fe9d-d4ba-42e4-9a4e-26f88388a542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952469033 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.952469033
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3585266611
Short name T455
Test name
Test status
Simulation time 232012084190 ps
CPU time 1760.29 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:44:31 PM PST 23
Peak memory 217408 kb
Host smart-f9498029-0262-45c7-98d5-907c1603effa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585266611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3585266611
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3342856282
Short name T670
Test name
Test status
Simulation time 32709007309 ps
CPU time 26.92 seconds
Started Dec 31 01:14:41 PM PST 23
Finished Dec 31 01:15:09 PM PST 23
Peak memory 200252 kb
Host smart-cd0fb081-730d-4ad6-86fc-41eb7ed21e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342856282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3342856282
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.402617305
Short name T1161
Test name
Test status
Simulation time 409604642357 ps
CPU time 1278.64 seconds
Started Dec 31 01:14:42 PM PST 23
Finished Dec 31 01:36:03 PM PST 23
Peak memory 227168 kb
Host smart-c8f89364-9b9d-4edb-9100-d53529aac86f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402617305 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.402617305
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3174722514
Short name T348
Test name
Test status
Simulation time 100416346249 ps
CPU time 71.69 seconds
Started Dec 31 01:15:01 PM PST 23
Finished Dec 31 01:16:15 PM PST 23
Peak memory 200144 kb
Host smart-1c5170e7-926c-4c51-9aaa-4c50dc636a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174722514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3174722514
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3940211137
Short name T426
Test name
Test status
Simulation time 57461362636 ps
CPU time 642.89 seconds
Started Dec 31 01:15:08 PM PST 23
Finished Dec 31 01:25:55 PM PST 23
Peak memory 217404 kb
Host smart-258c883f-f5ec-4d92-b134-fda061d7b533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940211137 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3940211137
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.786379406
Short name T349
Test name
Test status
Simulation time 16968511619 ps
CPU time 13.97 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:15:20 PM PST 23
Peak memory 200228 kb
Host smart-8b91e8b2-5e1b-47c2-a5be-61121350eab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786379406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.786379406
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.804730913
Short name T165
Test name
Test status
Simulation time 320786757165 ps
CPU time 971.28 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:31:14 PM PST 23
Peak memory 224960 kb
Host smart-a9e646ae-f4d6-48b6-860a-07143b059e1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804730913 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.804730913
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3970213977
Short name T326
Test name
Test status
Simulation time 9644602950 ps
CPU time 17.25 seconds
Started Dec 31 01:14:45 PM PST 23
Finished Dec 31 01:15:04 PM PST 23
Peak memory 200192 kb
Host smart-ff9ed21c-24b6-4411-ad3a-b0218dfed619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970213977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3970213977
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3145073918
Short name T219
Test name
Test status
Simulation time 105749295398 ps
CPU time 1639.65 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:42:27 PM PST 23
Peak memory 225184 kb
Host smart-5e260d31-93af-45c4-99da-bf48fce10642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145073918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3145073918
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1680811523
Short name T655
Test name
Test status
Simulation time 225091887676 ps
CPU time 359.7 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:21:09 PM PST 23
Peak memory 200244 kb
Host smart-3c7f6de9-9130-43dc-9389-7a7d279e39ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680811523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1680811523
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3268137669
Short name T277
Test name
Test status
Simulation time 7691692250 ps
CPU time 13.61 seconds
Started Dec 31 01:14:44 PM PST 23
Finished Dec 31 01:15:00 PM PST 23
Peak memory 200128 kb
Host smart-b943e926-c944-4975-98ac-65811a35d00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268137669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3268137669
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.201697649
Short name T1077
Test name
Test status
Simulation time 11271994057 ps
CPU time 114.95 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:17:02 PM PST 23
Peak memory 208736 kb
Host smart-35eec900-1ed5-46f7-ad21-904bcd13145d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201697649 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.201697649
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.4124224277
Short name T1234
Test name
Test status
Simulation time 114233683778 ps
CPU time 218.61 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:18:46 PM PST 23
Peak memory 200240 kb
Host smart-59f18602-7eee-42a8-ba7d-94b88a2eb43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124224277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.4124224277
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2360671219
Short name T811
Test name
Test status
Simulation time 364463475904 ps
CPU time 645.36 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:25:46 PM PST 23
Peak memory 216716 kb
Host smart-e8720596-ddd5-439c-afd8-c4d9ec08232b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360671219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2360671219
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1571289775
Short name T1120
Test name
Test status
Simulation time 36490637 ps
CPU time 0.53 seconds
Started Dec 31 01:12:27 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 194572 kb
Host smart-3aa1050e-fb2a-4aaf-8c97-90dacc96dcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571289775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1571289775
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2354453724
Short name T703
Test name
Test status
Simulation time 41381296983 ps
CPU time 66.17 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 200224 kb
Host smart-76242aa4-3f43-4943-adbd-eeb1f9d5070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354453724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2354453724
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.4035616967
Short name T362
Test name
Test status
Simulation time 84580511144 ps
CPU time 43.16 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:13:13 PM PST 23
Peak memory 199624 kb
Host smart-6ad0eabf-d30c-4b9d-b8cf-1b73808ca974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035616967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.4035616967
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2555899770
Short name T970
Test name
Test status
Simulation time 114226477919 ps
CPU time 190 seconds
Started Dec 31 01:12:26 PM PST 23
Finished Dec 31 01:15:42 PM PST 23
Peak memory 200188 kb
Host smart-f54cbea0-ba53-4201-9d64-ad9685c3391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555899770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2555899770
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3005164751
Short name T19
Test name
Test status
Simulation time 1257465361397 ps
CPU time 635.67 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:23:06 PM PST 23
Peak memory 199948 kb
Host smart-4104ff00-4b96-47c1-bb9c-951d40d00d26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005164751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3005164751
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.929665176
Short name T750
Test name
Test status
Simulation time 187026808651 ps
CPU time 173.42 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 200196 kb
Host smart-532ae351-797c-4279-97f2-a4266b1eed8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929665176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.929665176
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3333413246
Short name T1101
Test name
Test status
Simulation time 3834448015 ps
CPU time 5.79 seconds
Started Dec 31 01:12:25 PM PST 23
Finished Dec 31 01:12:37 PM PST 23
Peak memory 199292 kb
Host smart-995427b0-79b8-488b-aea5-da061ebc73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333413246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3333413246
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2363673457
Short name T147
Test name
Test status
Simulation time 43336681842 ps
CPU time 15.9 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:49 PM PST 23
Peak memory 208484 kb
Host smart-f9a47540-c981-4c3e-89a3-cb2e6dac5b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363673457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2363673457
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1520478753
Short name T1025
Test name
Test status
Simulation time 14093982101 ps
CPU time 710.32 seconds
Started Dec 31 01:12:23 PM PST 23
Finished Dec 31 01:24:20 PM PST 23
Peak memory 200196 kb
Host smart-f86f65cd-724e-4424-b5f3-cda897dbf418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520478753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1520478753
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2873016702
Short name T20
Test name
Test status
Simulation time 1131212184 ps
CPU time 2.71 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:36 PM PST 23
Peak memory 198436 kb
Host smart-5124813f-84ee-44dc-94a3-2d967d1093a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873016702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2873016702
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3021892505
Short name T688
Test name
Test status
Simulation time 2756073430 ps
CPU time 5.27 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:38 PM PST 23
Peak memory 195768 kb
Host smart-8296c1c7-f764-469f-8d82-135082e90fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021892505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3021892505
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3000916232
Short name T1127
Test name
Test status
Simulation time 515370449 ps
CPU time 1.59 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:32 PM PST 23
Peak memory 200052 kb
Host smart-7c871e20-cc12-4d4c-93a6-c212d614715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000916232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3000916232
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1997664315
Short name T289
Test name
Test status
Simulation time 198752793547 ps
CPU time 672.73 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:23:48 PM PST 23
Peak memory 216928 kb
Host smart-9865b5b4-2eba-4ff9-a9d0-1c39c9f52d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997664315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1997664315
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1885183249
Short name T961
Test name
Test status
Simulation time 665504090 ps
CPU time 2.1 seconds
Started Dec 31 01:12:24 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 198364 kb
Host smart-2ce45df2-fa60-4f26-8bb5-48994686e805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885183249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1885183249
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2121633079
Short name T795
Test name
Test status
Simulation time 85083096551 ps
CPU time 166.29 seconds
Started Dec 31 01:12:26 PM PST 23
Finished Dec 31 01:15:19 PM PST 23
Peak memory 200152 kb
Host smart-15de1979-a8c9-4ce0-a013-c5b755c66427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121633079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2121633079
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.705480045
Short name T1140
Test name
Test status
Simulation time 31582720475 ps
CPU time 48.34 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:16:19 PM PST 23
Peak memory 200236 kb
Host smart-e0d524be-1bf3-4278-bc41-e839258a3248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705480045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.705480045
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2671653634
Short name T635
Test name
Test status
Simulation time 187889970510 ps
CPU time 1265.34 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:36:35 PM PST 23
Peak memory 228804 kb
Host smart-b8270d72-d3b2-4672-aa82-c92cc462a540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671653634 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2671653634
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2163861756
Short name T798
Test name
Test status
Simulation time 84265589051 ps
CPU time 188.89 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:18:15 PM PST 23
Peak memory 200192 kb
Host smart-ce146b42-380d-4064-bd65-1e762bb7c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163861756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2163861756
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3222667773
Short name T374
Test name
Test status
Simulation time 106659607800 ps
CPU time 1222.39 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:35:29 PM PST 23
Peak memory 228816 kb
Host smart-dbeb7046-3f02-4baf-be65-67f8692ec114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222667773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3222667773
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.811115889
Short name T161
Test name
Test status
Simulation time 48999897982 ps
CPU time 77.67 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:16:46 PM PST 23
Peak memory 200132 kb
Host smart-9dcf66f0-cb47-4827-a9bf-d61e9db14389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811115889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.811115889
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3812532150
Short name T483
Test name
Test status
Simulation time 10977704103 ps
CPU time 138.84 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:17:47 PM PST 23
Peak memory 200248 kb
Host smart-6ac4c4e5-f727-4e2d-8752-6a131f7efd37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812532150 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3812532150
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3918274547
Short name T865
Test name
Test status
Simulation time 30579365661 ps
CPU time 51.24 seconds
Started Dec 31 01:15:25 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 200064 kb
Host smart-8db90324-2103-4027-ba20-52d05383c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918274547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3918274547
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.234824870
Short name T749
Test name
Test status
Simulation time 66850849664 ps
CPU time 974.1 seconds
Started Dec 31 01:15:07 PM PST 23
Finished Dec 31 01:31:25 PM PST 23
Peak memory 225036 kb
Host smart-1b0f19c1-cae9-4bd7-b57f-71c4796fc0fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234824870 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.234824870
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1629325543
Short name T628
Test name
Test status
Simulation time 59254834482 ps
CPU time 698.89 seconds
Started Dec 31 01:15:33 PM PST 23
Finished Dec 31 01:27:13 PM PST 23
Peak memory 227892 kb
Host smart-e2965448-e6de-42b4-999f-d5d65e5ca458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629325543 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1629325543
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.183146351
Short name T193
Test name
Test status
Simulation time 91584215426 ps
CPU time 91.08 seconds
Started Dec 31 01:15:36 PM PST 23
Finished Dec 31 01:17:09 PM PST 23
Peak memory 200200 kb
Host smart-025e0c64-9e1b-4c2c-afcf-60a1df3ed649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183146351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.183146351
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3252541702
Short name T274
Test name
Test status
Simulation time 120799405286 ps
CPU time 362.61 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:21:12 PM PST 23
Peak memory 216608 kb
Host smart-b4960f54-4f70-4a6d-a10b-23b7d81cbe06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252541702 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3252541702
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3647911119
Short name T911
Test name
Test status
Simulation time 46483213743 ps
CPU time 23.33 seconds
Started Dec 31 01:15:30 PM PST 23
Finished Dec 31 01:15:54 PM PST 23
Peak memory 200240 kb
Host smart-eeeac5ee-6fc1-48fa-9718-3e8818e4b50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647911119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3647911119
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3416017171
Short name T356
Test name
Test status
Simulation time 52231511481 ps
CPU time 43.8 seconds
Started Dec 31 01:15:33 PM PST 23
Finished Dec 31 01:16:17 PM PST 23
Peak memory 200220 kb
Host smart-b242c773-2659-4646-9bb4-0b1981ecfbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416017171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3416017171
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1049649621
Short name T173
Test name
Test status
Simulation time 75812906480 ps
CPU time 852.16 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:29:48 PM PST 23
Peak memory 225168 kb
Host smart-2f6af0f5-80d0-4eb0-a690-3e37a31609ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049649621 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1049649621
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2261394454
Short name T288
Test name
Test status
Simulation time 92821661606 ps
CPU time 195.56 seconds
Started Dec 31 01:15:08 PM PST 23
Finished Dec 31 01:18:27 PM PST 23
Peak memory 200116 kb
Host smart-4e0dbc98-608c-44cb-bb76-eada3b23fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261394454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2261394454
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2627450058
Short name T1142
Test name
Test status
Simulation time 53577976919 ps
CPU time 905.58 seconds
Started Dec 31 01:15:35 PM PST 23
Finished Dec 31 01:30:42 PM PST 23
Peak memory 225140 kb
Host smart-b32c74ee-759a-4d5e-ab4e-7c2e72db6097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627450058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2627450058
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.800068005
Short name T171
Test name
Test status
Simulation time 121700078424 ps
CPU time 132.87 seconds
Started Dec 31 01:15:27 PM PST 23
Finished Dec 31 01:17:41 PM PST 23
Peak memory 200064 kb
Host smart-bd814950-93a4-4dad-a9e3-893707ab5641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800068005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.800068005
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3523814641
Short name T815
Test name
Test status
Simulation time 115522413636 ps
CPU time 181.87 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:18:11 PM PST 23
Peak memory 213556 kb
Host smart-8185bd02-2795-4e36-a617-d92c3e4b1db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523814641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3523814641
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2835919068
Short name T975
Test name
Test status
Simulation time 18013411 ps
CPU time 0.55 seconds
Started Dec 31 01:12:27 PM PST 23
Finished Dec 31 01:12:33 PM PST 23
Peak memory 195668 kb
Host smart-89c2f98b-d49c-45bb-9e87-fe7691ebe19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835919068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2835919068
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3749461348
Short name T900
Test name
Test status
Simulation time 44652732958 ps
CPU time 39.43 seconds
Started Dec 31 01:12:26 PM PST 23
Finished Dec 31 01:13:11 PM PST 23
Peak memory 200156 kb
Host smart-d3815b3b-9a03-40b9-be92-b8597224c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749461348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3749461348
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1274386339
Short name T717
Test name
Test status
Simulation time 128479123040 ps
CPU time 199.26 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:15:56 PM PST 23
Peak memory 200212 kb
Host smart-68c958af-4535-4175-8aae-ad63860ca9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274386339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1274386339
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.81014289
Short name T126
Test name
Test status
Simulation time 57399328051 ps
CPU time 9.41 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:12:43 PM PST 23
Peak memory 199548 kb
Host smart-b36754ea-6885-4af1-89de-ec97a023dc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81014289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.81014289
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.688528727
Short name T891
Test name
Test status
Simulation time 469216250938 ps
CPU time 60.45 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:13:36 PM PST 23
Peak memory 199416 kb
Host smart-f144120a-ab6f-49af-a30d-f83795ee7488
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688528727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.688528727
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3816930717
Short name T1044
Test name
Test status
Simulation time 93444882999 ps
CPU time 124.03 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:14:39 PM PST 23
Peak memory 200192 kb
Host smart-e0d3adb1-f568-46d7-a843-e8aa4862bcd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816930717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3816930717
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1066459306
Short name T663
Test name
Test status
Simulation time 8334982549 ps
CPU time 16.09 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:12:52 PM PST 23
Peak memory 198176 kb
Host smart-1067b9fb-43f7-4929-bc31-3356f1cf3eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066459306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1066459306
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1805331667
Short name T809
Test name
Test status
Simulation time 352084631704 ps
CPU time 32.1 seconds
Started Dec 31 01:12:49 PM PST 23
Finished Dec 31 01:13:24 PM PST 23
Peak memory 197464 kb
Host smart-6c1cbccd-959d-4773-a0ab-32dac97767db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805331667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1805331667
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2355933628
Short name T577
Test name
Test status
Simulation time 25564156622 ps
CPU time 89.25 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:14:05 PM PST 23
Peak memory 200180 kb
Host smart-f6e6921a-25d0-47bd-9186-6dd7c1988293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355933628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2355933628
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.111663640
Short name T901
Test name
Test status
Simulation time 3892757745 ps
CPU time 12.3 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:12:48 PM PST 23
Peak memory 198172 kb
Host smart-110fa323-26d0-45ba-b812-480cc892414f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111663640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.111663640
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.541622902
Short name T168
Test name
Test status
Simulation time 152310325239 ps
CPU time 64.51 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:13:39 PM PST 23
Peak memory 199872 kb
Host smart-43d120a9-503d-468c-ba7b-584b48dadca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541622902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.541622902
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3125791232
Short name T1217
Test name
Test status
Simulation time 1975526872 ps
CPU time 3.29 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:12:38 PM PST 23
Peak memory 195592 kb
Host smart-42154b53-2fd6-40f8-97cd-3b6a7c282514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125791232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3125791232
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1738518086
Short name T802
Test name
Test status
Simulation time 247481114 ps
CPU time 1.45 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 198660 kb
Host smart-2c125cdf-c87c-4dbe-af37-719a69c2a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738518086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1738518086
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4241144936
Short name T103
Test name
Test status
Simulation time 160624372814 ps
CPU time 205.63 seconds
Started Dec 31 01:12:34 PM PST 23
Finished Dec 31 01:16:03 PM PST 23
Peak memory 208640 kb
Host smart-8dbad6af-a638-41c8-8142-aaa262b2a69b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241144936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4241144936
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1437831311
Short name T630
Test name
Test status
Simulation time 412684341 ps
CPU time 2.38 seconds
Started Dec 31 01:12:50 PM PST 23
Finished Dec 31 01:12:55 PM PST 23
Peak memory 198400 kb
Host smart-e3bc10da-4479-400d-ab2c-16c6cb559682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437831311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1437831311
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1958505021
Short name T592
Test name
Test status
Simulation time 61279872124 ps
CPU time 34.57 seconds
Started Dec 31 01:12:27 PM PST 23
Finished Dec 31 01:13:07 PM PST 23
Peak memory 200228 kb
Host smart-3b400d86-8ad2-4e67-b4ca-13f1475a18a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958505021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1958505021
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1671771315
Short name T137
Test name
Test status
Simulation time 8960328171 ps
CPU time 16.76 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:15:24 PM PST 23
Peak memory 198696 kb
Host smart-7113089f-7abc-4730-a59e-be820380ae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671771315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1671771315
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3777530567
Short name T829
Test name
Test status
Simulation time 25553355870 ps
CPU time 159 seconds
Started Dec 31 01:15:07 PM PST 23
Finished Dec 31 01:17:50 PM PST 23
Peak memory 211588 kb
Host smart-68a2530d-9083-4865-87dd-e9698e584d34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777530567 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3777530567
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3098295288
Short name T233
Test name
Test status
Simulation time 68559099279 ps
CPU time 23.32 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:34 PM PST 23
Peak memory 200208 kb
Host smart-20987af7-3934-497b-9def-2e8d8c444345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098295288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3098295288
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1386051848
Short name T377
Test name
Test status
Simulation time 105261482194 ps
CPU time 1015.03 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:32:04 PM PST 23
Peak memory 215388 kb
Host smart-5e60207a-92e7-4e1f-93eb-eccc43cf5f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386051848 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1386051848
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.333262132
Short name T132
Test name
Test status
Simulation time 112929152853 ps
CPU time 291.85 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:20:02 PM PST 23
Peak memory 200212 kb
Host smart-67202855-1b75-42a0-a3b2-e4b22085f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333262132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.333262132
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3813270911
Short name T363
Test name
Test status
Simulation time 54964768778 ps
CPU time 333.65 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:20:42 PM PST 23
Peak memory 216124 kb
Host smart-fbaa72a3-abfa-440e-820e-bd2668b1d5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813270911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3813270911
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.85904248
Short name T208
Test name
Test status
Simulation time 18131923398 ps
CPU time 28.07 seconds
Started Dec 31 01:15:00 PM PST 23
Finished Dec 31 01:15:31 PM PST 23
Peak memory 199096 kb
Host smart-f0183c9a-7883-46e6-a94a-f2667fb8ea78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85904248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.85904248
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1495005561
Short name T593
Test name
Test status
Simulation time 71018612328 ps
CPU time 196.81 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:18:25 PM PST 23
Peak memory 216860 kb
Host smart-881eed45-2c61-4f22-a151-98a2de35af33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495005561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1495005561
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.859122258
Short name T1055
Test name
Test status
Simulation time 152061357270 ps
CPU time 402.72 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:21:52 PM PST 23
Peak memory 216952 kb
Host smart-3d1fb4c5-08dd-4cab-8e91-07a408ad34a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859122258 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.859122258
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3663487774
Short name T346
Test name
Test status
Simulation time 73084078431 ps
CPU time 34.38 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:16:05 PM PST 23
Peak memory 200224 kb
Host smart-c334451b-affd-4fff-bac5-2ef7a6135942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663487774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3663487774
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3269482886
Short name T840
Test name
Test status
Simulation time 189352394643 ps
CPU time 309.32 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:20:09 PM PST 23
Peak memory 200220 kb
Host smart-7210f3ab-7ae4-4323-a5e6-296f9b61ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269482886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3269482886
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3792823600
Short name T25
Test name
Test status
Simulation time 26843478883 ps
CPU time 261.98 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:19:30 PM PST 23
Peak memory 212676 kb
Host smart-d53bb157-372a-47ec-8969-5838086cd7c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792823600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3792823600
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.950969723
Short name T998
Test name
Test status
Simulation time 33000390827 ps
CPU time 27.67 seconds
Started Dec 31 01:15:30 PM PST 23
Finished Dec 31 01:15:59 PM PST 23
Peak memory 200212 kb
Host smart-63ad29bb-087a-44df-b80f-e45c9acf7a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950969723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.950969723
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3638825888
Short name T1103
Test name
Test status
Simulation time 30911384 ps
CPU time 0.53 seconds
Started Dec 31 01:12:48 PM PST 23
Finished Dec 31 01:12:50 PM PST 23
Peak memory 194680 kb
Host smart-29e614de-0b07-433c-bb8e-880c9fe9cae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638825888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3638825888
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1554563718
Short name T777
Test name
Test status
Simulation time 25188742315 ps
CPU time 42.7 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:13:17 PM PST 23
Peak memory 199972 kb
Host smart-65a7dc95-a64c-469e-8b14-a2946b77f1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554563718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1554563718
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3520826213
Short name T951
Test name
Test status
Simulation time 243751825091 ps
CPU time 652.4 seconds
Started Dec 31 01:12:29 PM PST 23
Finished Dec 31 01:23:27 PM PST 23
Peak memory 200284 kb
Host smart-023b591a-93d0-431c-95dc-5950f801e797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520826213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3520826213
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.760187923
Short name T949
Test name
Test status
Simulation time 15977489763 ps
CPU time 8.5 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:42 PM PST 23
Peak memory 199272 kb
Host smart-c9a2ccd7-f1ea-476c-a19c-7f2a7c2aa73f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760187923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.760187923
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3859099618
Short name T652
Test name
Test status
Simulation time 102340785287 ps
CPU time 447.89 seconds
Started Dec 31 01:12:27 PM PST 23
Finished Dec 31 01:20:00 PM PST 23
Peak memory 200192 kb
Host smart-b0b18ee1-7d35-4c63-85d5-e225d22d24cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859099618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3859099618
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.49634762
Short name T875
Test name
Test status
Simulation time 6308686460 ps
CPU time 4.89 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:12:41 PM PST 23
Peak memory 199580 kb
Host smart-0378162a-1f2e-4c01-bdb4-da320c54ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49634762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.49634762
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2885403061
Short name T668
Test name
Test status
Simulation time 135440394744 ps
CPU time 282.63 seconds
Started Dec 31 01:12:36 PM PST 23
Finished Dec 31 01:17:20 PM PST 23
Peak memory 199900 kb
Host smart-140a1e36-2371-4cf0-995f-cc5e6ed1bf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885403061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2885403061
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1410365277
Short name T641
Test name
Test status
Simulation time 4530798105 ps
CPU time 58.1 seconds
Started Dec 31 01:12:31 PM PST 23
Finished Dec 31 01:13:34 PM PST 23
Peak memory 200176 kb
Host smart-3f41e149-6822-4e66-9458-1addc8ca75e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410365277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1410365277
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.261399109
Short name T843
Test name
Test status
Simulation time 707443522 ps
CPU time 2.43 seconds
Started Dec 31 01:12:32 PM PST 23
Finished Dec 31 01:12:39 PM PST 23
Peak memory 198248 kb
Host smart-3cebadf3-0675-4faf-808e-52653217f947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261399109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.261399109
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.780959004
Short name T946
Test name
Test status
Simulation time 244694226652 ps
CPU time 36.21 seconds
Started Dec 31 01:12:36 PM PST 23
Finished Dec 31 01:13:14 PM PST 23
Peak memory 200148 kb
Host smart-e5ff9c46-608e-4af6-91b7-62b90a49956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780959004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.780959004
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2618762221
Short name T804
Test name
Test status
Simulation time 3178748735 ps
CPU time 1.84 seconds
Started Dec 31 01:12:37 PM PST 23
Finished Dec 31 01:12:40 PM PST 23
Peak memory 195804 kb
Host smart-32bd87f3-419f-437b-ad07-2c09b51cdd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618762221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2618762221
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.904101972
Short name T574
Test name
Test status
Simulation time 5911527532 ps
CPU time 21.27 seconds
Started Dec 31 01:12:32 PM PST 23
Finished Dec 31 01:12:58 PM PST 23
Peak memory 199736 kb
Host smart-40fcb3af-0f74-44a9-a92f-a4c401189bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904101972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.904101972
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3048499628
Short name T707
Test name
Test status
Simulation time 174959594950 ps
CPU time 1745.68 seconds
Started Dec 31 01:12:30 PM PST 23
Finished Dec 31 01:41:41 PM PST 23
Peak memory 200468 kb
Host smart-649a7542-c24c-4536-886c-0f6ae5550073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048499628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3048499628
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2339918385
Short name T545
Test name
Test status
Simulation time 303282900 ps
CPU time 1.32 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:12:35 PM PST 23
Peak memory 196996 kb
Host smart-8c768689-5731-4744-a38c-9e0f42fa42a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339918385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2339918385
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3269918686
Short name T863
Test name
Test status
Simulation time 131956273488 ps
CPU time 360.19 seconds
Started Dec 31 01:12:28 PM PST 23
Finished Dec 31 01:18:34 PM PST 23
Peak memory 200208 kb
Host smart-f6219622-fc11-4526-a45f-156661d1df1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269918686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3269918686
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3600557272
Short name T1187
Test name
Test status
Simulation time 699689879173 ps
CPU time 456.57 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:22:43 PM PST 23
Peak memory 225044 kb
Host smart-5d24361f-95ea-4ff1-9883-cd0d09f84337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600557272 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3600557272
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3286945578
Short name T300
Test name
Test status
Simulation time 86013513539 ps
CPU time 59.36 seconds
Started Dec 31 01:15:02 PM PST 23
Finished Dec 31 01:16:06 PM PST 23
Peak memory 200032 kb
Host smart-00ab6730-79a9-4181-b92a-1afaf03e9ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286945578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3286945578
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3572757238
Short name T899
Test name
Test status
Simulation time 62308369054 ps
CPU time 419.28 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:22:06 PM PST 23
Peak memory 216948 kb
Host smart-5e4dda0f-adfa-4791-b920-d39fb3674c69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572757238 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3572757238
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3712195200
Short name T1020
Test name
Test status
Simulation time 49128497367 ps
CPU time 21.3 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:31 PM PST 23
Peak memory 200216 kb
Host smart-afad98f0-7737-4d77-80c6-705525dd6057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712195200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3712195200
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2340300363
Short name T1081
Test name
Test status
Simulation time 41377811837 ps
CPU time 438.87 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:22:28 PM PST 23
Peak memory 216692 kb
Host smart-a71e58aa-ca78-4a5b-bb42-15e06180079f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340300363 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2340300363
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1675525078
Short name T823
Test name
Test status
Simulation time 22376174648 ps
CPU time 9.36 seconds
Started Dec 31 01:15:03 PM PST 23
Finished Dec 31 01:15:17 PM PST 23
Peak memory 200020 kb
Host smart-3657637d-7241-4e63-9f30-d9576ff6cb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675525078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1675525078
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.984310921
Short name T487
Test name
Test status
Simulation time 124315169829 ps
CPU time 1616.38 seconds
Started Dec 31 01:15:25 PM PST 23
Finished Dec 31 01:42:23 PM PST 23
Peak memory 216640 kb
Host smart-5d41340b-738b-4eb2-802d-6d12c931822e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984310921 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.984310921
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3617309497
Short name T1116
Test name
Test status
Simulation time 64369702543 ps
CPU time 62 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:16:12 PM PST 23
Peak memory 200168 kb
Host smart-45e4cf2f-ccd2-4c80-a8e1-e1ab069531a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617309497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3617309497
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1622036917
Short name T410
Test name
Test status
Simulation time 98376622612 ps
CPU time 279.35 seconds
Started Dec 31 01:15:26 PM PST 23
Finished Dec 31 01:20:06 PM PST 23
Peak memory 209436 kb
Host smart-9902a974-a912-4f2d-9cfd-c834e43979ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622036917 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1622036917
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3123317815
Short name T818
Test name
Test status
Simulation time 77240070167 ps
CPU time 69.33 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:16:20 PM PST 23
Peak memory 200176 kb
Host smart-d6bae4f2-8148-479d-9d4d-95958c97aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123317815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3123317815
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1343831656
Short name T991
Test name
Test status
Simulation time 84738283230 ps
CPU time 1051.88 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:33:03 PM PST 23
Peak memory 216868 kb
Host smart-ae37d63e-5336-4e3f-8903-fc6e27e743d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343831656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1343831656
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.523517936
Short name T662
Test name
Test status
Simulation time 30313231802 ps
CPU time 14.47 seconds
Started Dec 31 01:15:05 PM PST 23
Finished Dec 31 01:15:25 PM PST 23
Peak memory 200224 kb
Host smart-f127f78a-2d0c-4a9d-a298-ffb1a2f8aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523517936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.523517936
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1613638788
Short name T1162
Test name
Test status
Simulation time 521798184017 ps
CPU time 1231.86 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:35:40 PM PST 23
Peak memory 233304 kb
Host smart-32fe09fd-295c-470d-81bb-ff7e7d59bf5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613638788 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1613638788
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2443249013
Short name T215
Test name
Test status
Simulation time 146851316784 ps
CPU time 24.72 seconds
Started Dec 31 01:15:29 PM PST 23
Finished Dec 31 01:15:55 PM PST 23
Peak memory 200216 kb
Host smart-84f66337-90b4-4cbb-899b-65835fb304d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443249013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2443249013
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3434703428
Short name T186
Test name
Test status
Simulation time 37952954071 ps
CPU time 14.25 seconds
Started Dec 31 01:15:04 PM PST 23
Finished Dec 31 01:15:23 PM PST 23
Peak memory 200112 kb
Host smart-4a071540-086c-4a82-ad3e-5d54a407c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434703428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3434703428
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3551177830
Short name T484
Test name
Test status
Simulation time 84899554226 ps
CPU time 155.88 seconds
Started Dec 31 01:14:59 PM PST 23
Finished Dec 31 01:17:36 PM PST 23
Peak memory 216844 kb
Host smart-cbcf5e1e-39cf-4e21-b299-365b9a6eb059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551177830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3551177830
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1164849518
Short name T291
Test name
Test status
Simulation time 195425701167 ps
CPU time 21.81 seconds
Started Dec 31 01:15:28 PM PST 23
Finished Dec 31 01:15:51 PM PST 23
Peak memory 200256 kb
Host smart-80dada0a-78b5-4c20-ae1c-e0d401a1489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164849518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1164849518
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1710120525
Short name T62
Test name
Test status
Simulation time 69600638012 ps
CPU time 178.28 seconds
Started Dec 31 01:15:07 PM PST 23
Finished Dec 31 01:18:09 PM PST 23
Peak memory 208456 kb
Host smart-e63876a3-efd2-412d-b33e-d855f7f5568d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710120525 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1710120525
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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