Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	127682	1			T1	5		T2	8		T3	8
all_values[1]	127682	1			T1	5		T2	8		T3	8
all_values[2]	127682	1			T1	5		T2	8		T3	8
all_values[3]	127682	1			T1	5		T2	8		T3	8
all_values[4]	127682	1			T1	5		T2	8		T3	8
all_values[5]	127682	1			T1	5		T2	8		T3	8
all_values[6]	127682	1			T1	5		T2	8		T3	8
all_values[7]	127682	1			T1	5		T2	8		T3	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

517385

1

T1

23

T2

37

T3

26

auto[1]

504071

1

T1

17

T2

27

T3

38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003663

1

T1

21

T2

36

T3

37

auto[1]

17793

1

T1

19

T2

28

T3

27

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	64118	1			T2	2		T3	3		T4	1
all_values[0]	auto[0]	auto[1]	2646	1			T1	2		T2	4		T3	1
all_values[0]	auto[1]	auto[0]	58622	1			T1	1		T3	3		T4	2
all_values[0]	auto[1]	auto[1]	2296	1			T1	2		T2	2		T3	1
all_values[1]	auto[0]	auto[0]	60341	1			T1	1		T2	4		T3	2
all_values[1]	auto[0]	auto[1]	2603	1			T1	3		T3	1		T4	4
all_values[1]	auto[1]	auto[0]	62413	1			T2	2		T3	1		T4	1
all_values[1]	auto[1]	auto[1]	2325	1			T1	1		T2	2		T3	4
all_values[2]	auto[0]	auto[0]	68641	1			T1	3		T2	4		T3	2
all_values[2]	auto[0]	auto[1]	2671	1			T1	2		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	54119	1			T3	2		T4	6		T47	1
all_values[2]	auto[1]	auto[1]	2251	1			T2	1		T3	3		T4	1
all_values[3]	auto[0]	auto[0]	59617	1			T1	3		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	208	1			T1	2		T2	2		T3	1
all_values[3]	auto[1]	auto[0]	67627	1			T2	1		T3	1		T4	4
all_values[3]	auto[1]	auto[1]	230	1			T2	2		T3	3		T4	2
all_values[4]	auto[0]	auto[0]	63300	1			T2	1		T3	1		T4	3
all_values[4]	auto[0]	auto[1]	526	1			T2	1		T3	1		T48	3
all_values[4]	auto[1]	auto[0]	63325	1			T1	4		T2	4		T3	3
all_values[4]	auto[1]	auto[1]	531	1			T1	1		T2	2		T3	3
all_values[5]	auto[0]	auto[0]	65418	1			T1	1		T2	5		T3	3
all_values[5]	auto[0]	auto[1]	176	1			T1	1		T2	1		T47	1
all_values[5]	auto[1]	auto[0]	61910	1			T1	3		T2	2		T3	4
all_values[5]	auto[1]	auto[1]	178	1			T3	1		T4	4		T47	2
all_values[6]	auto[0]	auto[0]	63986	1			T1	4		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	199	1			T2	2		T3	2		T4	2
all_values[6]	auto[1]	auto[0]	63311	1			T2	1		T3	2		T4	2
all_values[6]	auto[1]	auto[1]	186	1			T1	1		T2	3		T3	1
all_values[7]	auto[0]	auto[0]	62537	1			T2	1		T4	3		T10	1
all_values[7]	auto[0]	auto[1]	398	1			T1	1		T2	2		T3	2
all_values[7]	auto[1]	auto[0]	64378	1			T1	1		T2	4		T3	4
all_values[7]	auto[1]	auto[1]	369	1			T1	3		T2	1		T3	2