Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2497

1

T1

1

T2

1

T3

1

auto[UartRx]

2497

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4401	1			T1	2		T2	2		T3	2
values[1]	55	1			T86	2		T70	2		T71	1
values[2]	48	1			T81	1		T85	2		T262	1
values[3]	46	1			T81	4		T85	2		T87	1
values[4]	57	1			T420	1		T85	1		T339	1
values[5]	66	1			T81	1		T85	1		T70	1
values[6]	48	1			T85	1		T86	1		T416	1
values[7]	59	1			T81	1		T339	1		T87	1
values[8]	48	1			T81	1		T69	1		T87	1
values[9]	56	1			T339	1		T416	1		T71	1
values[10]	73	1			T85	1		T339	1		T86	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2287	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	16	1			T86	1		T70	1		T155	1
auto[UartTx]	values[2]	19	1			T85	1		T262	1		T447	1
auto[UartTx]	values[3]	15	1			T81	1		T140	1		T455	1
auto[UartTx]	values[4]	15	1			T416	1		T441	1		T456	1
auto[UartTx]	values[5]	26	1			T81	1		T85	1		T456	1
auto[UartTx]	values[6]	16	1			T85	1		T71	2		T441	1
auto[UartTx]	values[7]	25	1			T70	1		T416	1		T262	1
auto[UartTx]	values[8]	15	1			T81	1		T69	1		T70	1
auto[UartTx]	values[9]	23	1			T71	1		T72	1		T262	1
auto[UartTx]	values[10]	26	1			T85	1		T416	1		T435	1
auto[UartRx]	values[0]	2114	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	39	1			T86	1		T70	1		T71	1
auto[UartRx]	values[2]	29	1			T81	1		T85	1		T140	1
auto[UartRx]	values[3]	31	1			T81	3		T85	2		T87	1
auto[UartRx]	values[4]	42	1			T420	1		T85	1		T339	1
auto[UartRx]	values[5]	40	1			T70	1		T71	2		T441	1
auto[UartRx]	values[6]	32	1			T86	1		T416	1		T72	1
auto[UartRx]	values[7]	34	1			T81	1		T339	1		T87	1
auto[UartRx]	values[8]	33	1			T87	1		T71	2		T72	1
auto[UartRx]	values[9]	33	1			T339	1		T416	1		T262	1
auto[UartRx]	values[10]	47	1			T339	1		T86	1		T70	1