Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1943	1			T12	2		T16	3		T15	1
auto[BaudRate115200]	2068	1			T11	2		T14	1		T15	2
auto[BaudRate230400]	1912	1			T11	1		T12	1		T13	2
auto[BaudRate128Kbps]	1872	1			T12	1		T13	3		T14	3
auto[BaudRate256Kbps]	2102	1			T11	2		T12	1		T13	1
auto[BaudRate1Mbps]	1807	1			T11	2		T13	1		T18	1
auto[BaudRate1p5Mbps]	1336	1			T12	2		T16	2		T19	9

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	949	1			T29	2		T24	10		T126	6
freqs[25]	1355	1			T16	10		T15	5		T108	6
freqs[48]	480	1			T11	7		T153	10		T413	9
freqs[50]	658	1			T308	8		T430	2		T438	2
freqs[100]	1130	1			T19	36		T21	60		T434	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	160	1			T29	1		T126	2		T421	1
auto[BaudRate9600]	freqs[25]	214	1			T16	3		T15	1		T305	2
auto[BaudRate9600]	freqs[48]	60	1			T154	1		T457	7		T158	3
auto[BaudRate9600]	freqs[50]	100	1			T308	1		T430	1		T438	1
auto[BaudRate9600]	freqs[100]	155	1			T19	3		T21	3		T26	1
auto[BaudRate115200]	freqs[24]	149	1			T310	1		T201	4		T69	7
auto[BaudRate115200]	freqs[25]	183	1			T15	2		T108	2		T305	4
auto[BaudRate115200]	freqs[48]	84	1			T11	2		T153	2		T154	1
auto[BaudRate115200]	freqs[50]	80	1			T308	1		T136	1		T70	2
auto[BaudRate115200]	freqs[100]	167	1			T19	3		T21	18		T26	2
auto[BaudRate230400]	freqs[24]	148	1			T126	1		T69	7		T458	2
auto[BaudRate230400]	freqs[25]	212	1			T16	2		T15	2		T108	1
auto[BaudRate230400]	freqs[48]	63	1			T11	1		T153	2		T457	16
auto[BaudRate230400]	freqs[50]	84	1			T308	3		T136	1		T70	7
auto[BaudRate230400]	freqs[100]	130	1			T19	6		T21	3		T410	1
auto[BaudRate128Kbps]	freqs[24]	139	1			T126	2		T310	1		T201	1
auto[BaudRate128Kbps]	freqs[25]	204	1			T16	3		T108	1		T305	4
auto[BaudRate128Kbps]	freqs[48]	51	1			T457	21		T158	1		T311	1
auto[BaudRate128Kbps]	freqs[50]	92	1			T308	1		T438	1		T136	2
auto[BaudRate128Kbps]	freqs[100]	149	1			T21	9		T426	1		T407	1
auto[BaudRate256Kbps]	freqs[24]	122	1			T24	4		T310	3		T421	1
auto[BaudRate256Kbps]	freqs[25]	228	1			T108	1		T305	1		T125	1
auto[BaudRate256Kbps]	freqs[48]	64	1			T11	2		T153	1		T413	2
auto[BaudRate256Kbps]	freqs[50]	108	1			T430	1		T136	2		T459	1
auto[BaudRate256Kbps]	freqs[100]	161	1			T19	3		T21	3		T405	2
auto[BaudRate1Mbps]	freqs[24]	146	1			T24	2		T126	1		T310	1
auto[BaudRate1Mbps]	freqs[25]	200	1			T108	1		T125	2		T339	3
auto[BaudRate1Mbps]	freqs[48]	81	1			T11	2		T153	2		T413	5
auto[BaudRate1Mbps]	freqs[50]	103	1			T308	1		T459	1		T70	5
auto[BaudRate1Mbps]	freqs[100]	203	1			T19	12		T21	15		T434	2
auto[BaudRate1p5Mbps]	freqs[25]	114	1			T16	2		T305	1		T339	4
auto[BaudRate1p5Mbps]	freqs[48]	77	1			T153	3		T413	2		T457	16
auto[BaudRate1p5Mbps]	freqs[50]	91	1			T308	1		T136	1		T70	4
auto[BaudRate1p5Mbps]	freqs[100]	165	1			T19	9		T21	9		T405	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded