Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2374 1 T1 4 T2 2 T3 5
all_levels[1] 515 1 T11 1 T14 7 T19 1
all_levels[2] 518 1 T26 8 T129 1 T152 2
all_levels[3] 401 1 T12 1 T13 2 T14 2
all_levels[4] 449 1 T12 1 T17 1 T109 1
all_levels[5] 269 1 T16 4 T15 1 T418 2
all_levels[6] 174 1 T13 1 T14 3 T116 1
all_levels[7] 221 1 T308 1 T27 2 T309 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%