Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	127682	1			T1	5		T2	8		T3	8
all_pins[1]	127682	1			T1	5		T2	8		T3	8
all_pins[2]	127682	1			T1	5		T2	8		T3	8
all_pins[3]	127682	1			T1	5		T2	8		T3	8
all_pins[4]	127682	1			T1	5		T2	8		T3	8
all_pins[5]	127682	1			T1	5		T2	8		T3	8
all_pins[6]	127682	1			T1	5		T2	8		T3	8
all_pins[7]	127682	1			T1	5		T2	8		T3	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1012337	1			T1	32		T2	51		T3	46
values[0x1]	9119	1			T1	8		T2	13		T3	18
transitions[0x0=>0x1]	8212	1			T1	6		T2	8		T3	10
transitions[0x1=>0x0]	8231	1			T1	6		T2	8		T3	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	125319	1			T1	3		T2	6		T3	7
all_pins[0]	values[0x1]	2363	1			T1	2		T2	2		T3	1
all_pins[0]	transitions[0x0=>0x1]	2077	1			T1	2		T3	1		T4	2
all_pins[0]	transitions[0x1=>0x0]	2035	1			T1	1		T3	4		T47	2
all_pins[1]	values[0x0]	125361	1			T1	4		T2	6		T3	4
all_pins[1]	values[0x1]	2321	1			T1	1		T2	2		T3	4
all_pins[1]	transitions[0x0=>0x1]	2036	1			T1	1		T2	1		T3	2
all_pins[1]	transitions[0x1=>0x0]	2027	1			T3	1		T47	3		T51	3
all_pins[2]	values[0x0]	125370	1			T1	5		T2	7		T3	5
all_pins[2]	values[0x1]	2312	1			T2	1		T3	3		T4	1
all_pins[2]	transitions[0x0=>0x1]	2279	1			T2	1		T3	2		T4	1
all_pins[2]	transitions[0x1=>0x0]	197	1			T2	2		T3	2		T4	2
all_pins[3]	values[0x0]	127452	1			T1	5		T2	6		T3	5
all_pins[3]	values[0x1]	230	1			T2	2		T3	3		T4	2
all_pins[3]	transitions[0x0=>0x1]	191	1			T2	2		T3	2		T4	2
all_pins[3]	transitions[0x1=>0x0]	492	1			T1	1		T2	2		T3	2
all_pins[4]	values[0x0]	127151	1			T1	4		T2	6		T3	5
all_pins[4]	values[0x1]	531	1			T1	1		T2	2		T3	3
all_pins[4]	transitions[0x0=>0x1]	451	1			T1	1		T2	2		T3	2
all_pins[4]	transitions[0x1=>0x0]	174	1			T4	4		T47	1		T51	3
all_pins[5]	values[0x0]	127428	1			T1	5		T2	8		T3	7
all_pins[5]	values[0x1]	254	1			T3	1		T4	4		T47	2
all_pins[5]	transitions[0x0=>0x1]	199	1			T4	3		T47	2		T51	3
all_pins[5]	transitions[0x1=>0x0]	684	1			T1	1		T2	3		T4	1
all_pins[6]	values[0x0]	126943	1			T1	4		T2	5		T3	7
all_pins[6]	values[0x1]	739	1			T1	1		T2	3		T3	1
all_pins[6]	transitions[0x0=>0x1]	680	1			T2	2		T3	1		T4	2
all_pins[6]	transitions[0x1=>0x0]	310	1			T1	2		T3	2		T4	1
all_pins[7]	values[0x0]	127313	1			T1	2		T2	7		T3	6
all_pins[7]	values[0x1]	369	1			T1	3		T2	1		T3	2
all_pins[7]	transitions[0x0=>0x1]	299	1			T1	2		T47	2		T64	1
all_pins[7]	transitions[0x1=>0x0]	2312	1			T1	1		T2	1		T4	2