Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	771	1			T1	4		T2	7		T3	7
all_values[1]	771	1			T1	4		T2	7		T3	7
all_values[2]	771	1			T1	4		T2	7		T3	7
all_values[3]	771	1			T1	4		T2	7		T3	7
all_values[4]	771	1			T1	4		T2	7		T3	7
all_values[5]	771	1			T1	4		T2	7		T3	7
all_values[6]	771	1			T1	4		T2	7		T3	7
all_values[7]	771	1			T1	4		T2	7		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3255

1

T1

20

T2

31

T3

21

auto[1]

2913

1

T1

12

T2

25

T3

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2448

1

T1

12

T2

21

T3

17

auto[1]

3720

1

T1

20

T2

35

T3

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3615

1

T1

18

T2

31

T3

27

auto[1]

2553

1

T1

14

T2

25

T3

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	173	1			T3	1		T47	2		T48	1
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	auto[0]	153	1			T3	2		T4	1		T47	2
all_values[0]	auto[0]	auto[1]	auto[1]	65	1			T1	1		T3	1		T4	2
all_values[0]	auto[1]	auto[0]	auto[1]	177	1			T1	1		T2	3		T3	1
all_values[0]	auto[1]	auto[1]	auto[1]	131	1			T1	1		T2	3		T3	1
all_values[1]	auto[0]	auto[0]	auto[0]	147	1			T2	1		T47	2		T48	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	auto[0]	143	1			T2	2		T48	3		T63	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1			T3	1		T47	1		T64	1
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T1	2		T2	2		T3	3
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T1	1		T2	1		T47	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T2	1		T3	1		T4	3
all_values[2]	auto[0]	auto[1]	auto[1]	82	1			T3	1		T47	2		T51	1
all_values[2]	auto[1]	auto[0]	auto[1]	182	1			T1	1		T2	3		T3	1
all_values[2]	auto[1]	auto[1]	auto[1]	127	1			T2	1		T3	3		T4	2
all_values[3]	auto[0]	auto[0]	auto[0]	171	1			T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T1	1		T2	1		T47	1
all_values[3]	auto[0]	auto[1]	auto[0]	159	1			T4	2		T47	1		T51	1
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T2	1		T3	2		T4	1
all_values[3]	auto[1]	auto[0]	auto[1]	157	1			T1	1		T2	2		T3	2
all_values[3]	auto[1]	auto[1]	auto[1]	147	1			T2	1		T3	2		T4	2
all_values[4]	auto[0]	auto[0]	auto[0]	175	1			T1	1		T2	1		T4	2
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T2	1		T48	2		T51	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T1	2		T2	2		T3	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T2	1		T3	1		T63	1
all_values[4]	auto[1]	auto[0]	auto[1]	169	1			T2	1		T4	1		T48	1
all_values[4]	auto[1]	auto[1]	auto[1]	132	1			T1	1		T2	1		T3	5
all_values[5]	auto[0]	auto[0]	auto[0]	150	1			T2	3		T3	4		T4	1
all_values[5]	auto[0]	auto[0]	auto[1]	73	1			T2	1		T48	1		T51	1
all_values[5]	auto[0]	auto[1]	auto[0]	148	1			T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	auto[1]	69	1			T4	1		T51	1		T404	1
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T1	2		T4	2		T47	2
all_values[5]	auto[1]	auto[1]	auto[1]	157	1			T2	1		T3	2		T4	2
all_values[6]	auto[0]	auto[0]	auto[0]	142	1			T1	3		T2	2		T3	2
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T3	1		T4	2		T48	1
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T3	1		T4	1		T47	2
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T2	2		T3	1		T48	1
all_values[6]	auto[1]	auto[0]	auto[1]	191	1			T2	2		T47	2		T51	3
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T1	1		T2	1		T3	2
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T2	1		T4	1		T47	2
all_values[7]	auto[0]	auto[0]	auto[1]	58	1			T2	1		T4	1		T47	1
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T2	3		T3	2		T4	2
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T1	1		T47	2		T63	1
all_values[7]	auto[1]	auto[0]	auto[1]	168	1			T1	1		T2	1		T3	2
all_values[7]	auto[1]	auto[1]	auto[1]	155	1			T1	2		T2	1		T3	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal