Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.79 98.45 100.00 99.76 100.00 97.54


Total test records in report: 1291
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T1252 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1083271104 Jan 03 12:27:16 PM PST 24 Jan 03 12:27:19 PM PST 24 16360151 ps
T1253 /workspace/coverage/cover_reg_top/33.uart_intr_test.3087301691 Jan 03 12:29:21 PM PST 24 Jan 03 12:29:53 PM PST 24 21951741 ps
T1254 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1405889948 Jan 03 12:29:11 PM PST 24 Jan 03 12:29:40 PM PST 24 104450563 ps
T1255 /workspace/coverage/cover_reg_top/14.uart_csr_rw.4287725410 Jan 03 12:23:46 PM PST 24 Jan 03 12:23:48 PM PST 24 34666577 ps
T1256 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2750959254 Jan 03 12:42:35 PM PST 24 Jan 03 12:44:05 PM PST 24 88622440 ps
T1257 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3585097365 Jan 03 12:29:12 PM PST 24 Jan 03 12:29:40 PM PST 24 122354514 ps
T1258 /workspace/coverage/cover_reg_top/40.uart_intr_test.294252226 Jan 03 12:30:05 PM PST 24 Jan 03 12:30:51 PM PST 24 13082434 ps
T1259 /workspace/coverage/cover_reg_top/25.uart_intr_test.1044920009 Jan 03 12:30:34 PM PST 24 Jan 03 12:31:35 PM PST 24 23276266 ps
T1260 /workspace/coverage/cover_reg_top/12.uart_intr_test.2830914158 Jan 03 12:24:29 PM PST 24 Jan 03 12:24:36 PM PST 24 37328236 ps
T1261 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2728496680 Jan 03 12:23:42 PM PST 24 Jan 03 12:23:44 PM PST 24 22165044 ps
T1262 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.98647244 Jan 03 12:25:08 PM PST 24 Jan 03 12:25:11 PM PST 24 47779061 ps
T1263 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.64070481 Jan 03 12:27:16 PM PST 24 Jan 03 12:27:20 PM PST 24 31128309 ps
T1264 /workspace/coverage/cover_reg_top/30.uart_intr_test.3035738199 Jan 03 12:28:14 PM PST 24 Jan 03 12:28:21 PM PST 24 52462245 ps
T1265 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1531034367 Jan 03 12:30:56 PM PST 24 Jan 03 12:32:02 PM PST 24 129427960 ps
T403 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1276577447 Jan 03 12:28:27 PM PST 24 Jan 03 12:28:40 PM PST 24 171827318 ps
T1266 /workspace/coverage/cover_reg_top/8.uart_intr_test.3149985623 Jan 03 12:27:35 PM PST 24 Jan 03 12:27:39 PM PST 24 49846719 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.275067979 Jan 03 12:30:21 PM PST 24 Jan 03 12:31:16 PM PST 24 16368549 ps
T1268 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.680865325 Jan 03 12:30:50 PM PST 24 Jan 03 12:31:57 PM PST 24 63768151 ps
T1269 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2596447506 Jan 03 12:22:31 PM PST 24 Jan 03 12:22:33 PM PST 24 44389600 ps
T1270 /workspace/coverage/cover_reg_top/35.uart_intr_test.751508505 Jan 03 12:29:20 PM PST 24 Jan 03 12:29:50 PM PST 24 15672622 ps
T1271 /workspace/coverage/cover_reg_top/22.uart_intr_test.2366804330 Jan 03 12:28:42 PM PST 24 Jan 03 12:29:05 PM PST 24 247688055 ps
T1272 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3678279601 Jan 03 12:28:25 PM PST 24 Jan 03 12:28:33 PM PST 24 304930614 ps
T1273 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2858819753 Jan 03 12:28:24 PM PST 24 Jan 03 12:28:32 PM PST 24 16373225 ps
T1274 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2092072597 Jan 03 12:25:22 PM PST 24 Jan 03 12:25:26 PM PST 24 74195083 ps
T1275 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3306890150 Jan 03 12:30:49 PM PST 24 Jan 03 12:31:55 PM PST 24 122457890 ps
T1276 /workspace/coverage/cover_reg_top/18.uart_intr_test.1477229239 Jan 03 12:29:54 PM PST 24 Jan 03 12:30:36 PM PST 24 31828388 ps
T1277 /workspace/coverage/cover_reg_top/42.uart_intr_test.1568029553 Jan 03 12:28:53 PM PST 24 Jan 03 12:29:22 PM PST 24 29680906 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3948578163 Jan 03 12:28:42 PM PST 24 Jan 03 12:29:11 PM PST 24 533180341 ps
T1279 /workspace/coverage/cover_reg_top/11.uart_intr_test.866479638 Jan 03 12:28:22 PM PST 24 Jan 03 12:28:31 PM PST 24 62296919 ps
T1280 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1194522423 Jan 03 12:27:58 PM PST 24 Jan 03 12:28:09 PM PST 24 35052513 ps
T1281 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3895737775 Jan 03 12:29:38 PM PST 24 Jan 03 12:30:17 PM PST 24 211485387 ps
T1282 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1306373668 Jan 03 12:28:49 PM PST 24 Jan 03 12:29:19 PM PST 24 57365898 ps
T1283 /workspace/coverage/cover_reg_top/6.uart_intr_test.3651697205 Jan 03 12:31:02 PM PST 24 Jan 03 12:32:10 PM PST 24 40219671 ps
T1284 /workspace/coverage/cover_reg_top/14.uart_intr_test.2629373833 Jan 03 12:30:07 PM PST 24 Jan 03 12:30:55 PM PST 24 14920125 ps
T1285 /workspace/coverage/cover_reg_top/31.uart_intr_test.433058837 Jan 03 12:28:42 PM PST 24 Jan 03 12:29:03 PM PST 24 21381613 ps
T1286 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.609481642 Jan 03 12:25:31 PM PST 24 Jan 03 12:25:33 PM PST 24 14129164 ps
T1287 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2360770734 Jan 03 12:28:29 PM PST 24 Jan 03 12:28:44 PM PST 24 207400959 ps
T1288 /workspace/coverage/cover_reg_top/8.uart_csr_rw.174126870 Jan 03 12:27:16 PM PST 24 Jan 03 12:27:20 PM PST 24 54765320 ps
T1289 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2389012431 Jan 03 12:29:35 PM PST 24 Jan 03 12:30:15 PM PST 24 405277079 ps
T1290 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.478999339 Jan 03 12:27:38 PM PST 24 Jan 03 12:27:44 PM PST 24 13063027 ps
T1291 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.178278770 Jan 03 12:27:16 PM PST 24 Jan 03 12:27:20 PM PST 24 12196454 ps

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1040158848
Short name T6
Test name
Test status
Simulation time 34132302 ps
CPU time 0.6 seconds
Started Jan 03 12:23:46 PM PST 24
Finished Jan 03 12:23:48 PM PST 24
Peak memory 195396 kb
Host smart-5e9c5d9f-07f6-479d-9d5b-f80c3058df27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040158848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1040158848
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1062381085
Short name T16
Test name
Test status
Simulation time 219252724593 ps
CPU time 103.42 seconds
Started Jan 03 12:50:03 PM PST 24
Finished Jan 03 12:52:11 PM PST 24
Peak memory 199956 kb
Host smart-de661f3a-7e70-4721-8c69-0ebcfec3ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062381085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1062381085
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3463026853
Short name T81
Test name
Test status
Simulation time 734330425364 ps
CPU time 1152.16 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 01:09:05 PM PST 24
Peak memory 216932 kb
Host smart-42483758-259e-45ca-bf27-a847a76d2c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463026853 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3463026853
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3614425704
Short name T2
Test name
Test status
Simulation time 42347400 ps
CPU time 0.57 seconds
Started Jan 03 12:25:14 PM PST 24
Finished Jan 03 12:25:16 PM PST 24
Peak memory 194316 kb
Host smart-33b719fa-d90c-41cc-9c62-0d0ed0cd0d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614425704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3614425704
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2035181875
Short name T71
Test name
Test status
Simulation time 525103147433 ps
CPU time 1028.36 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 01:07:11 PM PST 24
Peak memory 216848 kb
Host smart-9ab503cc-bbcc-48b0-a450-650c1c9adae3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035181875 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2035181875
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1712341568
Short name T34
Test name
Test status
Simulation time 95754341 ps
CPU time 1.35 seconds
Started Jan 03 12:25:40 PM PST 24
Finished Jan 03 12:25:42 PM PST 24
Peak memory 199268 kb
Host smart-37b489a7-d35d-46cd-9006-f1ac75f6f475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712341568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1712341568
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3682334413
Short name T24
Test name
Test status
Simulation time 134752095646 ps
CPU time 291.84 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:53:50 PM PST 24
Peak memory 200208 kb
Host smart-78b63a71-570b-44b0-a826-5154c8455771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682334413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3682334413
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_stress_all.2703441528
Short name T132
Test name
Test status
Simulation time 177880480257 ps
CPU time 989.86 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 01:05:42 PM PST 24
Peak memory 200132 kb
Host smart-6dfacbe4-edcc-4e6e-9838-706d0b8c19af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703441528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2703441528
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.6885162
Short name T69
Test name
Test status
Simulation time 319360013353 ps
CPU time 1003.99 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 01:05:56 PM PST 24
Peak memory 225188 kb
Host smart-b139f112-85ec-4afd-a5ac-8eca49a393e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6885162 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.6885162
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_intr.152344855
Short name T15
Test name
Test status
Simulation time 442216378769 ps
CPU time 239.14 seconds
Started Jan 03 12:48:02 PM PST 24
Finished Jan 03 12:52:33 PM PST 24
Peak memory 200076 kb
Host smart-1fe35989-6727-441c-95fd-d8d4092d573b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152344855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.152344855
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2304832347
Short name T10
Test name
Test status
Simulation time 1181627840 ps
CPU time 2.37 seconds
Started Jan 03 12:27:51 PM PST 24
Finished Jan 03 12:27:57 PM PST 24
Peak memory 199804 kb
Host smart-d48a3c77-8df1-4088-a59d-1cbe6fc7c2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304832347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2304832347
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/default/28.uart_stress_all.138983544
Short name T80
Test name
Test status
Simulation time 907049983623 ps
CPU time 170.36 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 12:52:13 PM PST 24
Peak memory 200624 kb
Host smart-d885f145-2f23-4b1b-8624-7293a995b9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138983544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.138983544
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.767758483
Short name T23
Test name
Test status
Simulation time 140310211918 ps
CPU time 255.21 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:53:11 PM PST 24
Peak memory 200268 kb
Host smart-70ca6ce1-7c4a-4fd0-93ae-6d71975c49e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767758483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.767758483
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2558629350
Short name T70
Test name
Test status
Simulation time 123796131728 ps
CPU time 1313.62 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 01:10:52 PM PST 24
Peak memory 216728 kb
Host smart-7904d181-ca6d-424a-a985-d752a7297e56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558629350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2558629350
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.710082241
Short name T174
Test name
Test status
Simulation time 326638372054 ps
CPU time 575.22 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:59:51 PM PST 24
Peak memory 200200 kb
Host smart-d4f5915a-f22f-44f7-bdf8-a439189fe8d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710082241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.710082241
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1735001286
Short name T82
Test name
Test status
Simulation time 495492359 ps
CPU time 0.87 seconds
Started Jan 03 12:47:58 PM PST 24
Finished Jan 03 12:48:36 PM PST 24
Peak memory 218732 kb
Host smart-3b7691ae-31bd-4db0-be64-5a5cb4dd3e40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735001286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1735001286
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3638261959
Short name T12
Test name
Test status
Simulation time 32104735363 ps
CPU time 48.96 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 199392 kb
Host smart-3b9caaef-c9cd-4397-81e4-9e9ce9275b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638261959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3638261959
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2100541346
Short name T443
Test name
Test status
Simulation time 257957852653 ps
CPU time 223.08 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:52:30 PM PST 24
Peak memory 200080 kb
Host smart-a47f1fcc-4fab-409d-bd88-454fef0150b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100541346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2100541346
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_stress_all.1770500030
Short name T258
Test name
Test status
Simulation time 175061191117 ps
CPU time 253.17 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:53:12 PM PST 24
Peak memory 200252 kb
Host smart-722e814e-8258-4c9d-8ed4-1a42ddefe35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770500030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1770500030
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all.1189890945
Short name T25
Test name
Test status
Simulation time 2011869846119 ps
CPU time 3337.51 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 01:44:34 PM PST 24
Peak memory 200208 kb
Host smart-b0d84c5a-3c12-41c5-9f3d-e647174f2c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189890945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1189890945
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_intr.3486382211
Short name T431
Test name
Test status
Simulation time 1354055640545 ps
CPU time 2390.89 seconds
Started Jan 03 12:47:57 PM PST 24
Finished Jan 03 01:28:23 PM PST 24
Peak memory 200260 kb
Host smart-331434b1-bf15-4e8b-b087-ab83336e6ad0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486382211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3486382211
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2358488280
Short name T447
Test name
Test status
Simulation time 95173038344 ps
CPU time 527.28 seconds
Started Jan 03 12:49:08 PM PST 24
Finished Jan 03 12:58:13 PM PST 24
Peak memory 215536 kb
Host smart-e008cb87-1772-4fa2-bcf6-989f882257d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358488280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2358488280
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.943088864
Short name T47
Test name
Test status
Simulation time 57473870 ps
CPU time 0.54 seconds
Started Jan 03 12:30:22 PM PST 24
Finished Jan 03 12:31:17 PM PST 24
Peak memory 193996 kb
Host smart-66021053-0853-4f94-9726-574e3137c0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943088864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.943088864
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1332393785
Short name T187
Test name
Test status
Simulation time 129330202408 ps
CPU time 253.71 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 200100 kb
Host smart-c5f76fda-24a8-414a-8970-8dacccd277dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332393785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1332393785
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.4016552321
Short name T74
Test name
Test status
Simulation time 37776032 ps
CPU time 0.66 seconds
Started Jan 03 12:29:06 PM PST 24
Finished Jan 03 12:29:34 PM PST 24
Peak memory 194772 kb
Host smart-6bde19c0-3ef6-434e-ac92-ee10fefe7e10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016552321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.4016552321
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3171342064
Short name T296
Test name
Test status
Simulation time 359575305312 ps
CPU time 607.23 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 12:59:22 PM PST 24
Peak memory 216612 kb
Host smart-bb309958-04ee-4b75-95cd-6ed3a4cb9c7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171342064 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3171342064
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1588230338
Short name T89
Test name
Test status
Simulation time 54065470 ps
CPU time 0.95 seconds
Started Jan 03 12:25:29 PM PST 24
Finished Jan 03 12:25:31 PM PST 24
Peak memory 198860 kb
Host smart-94e4b189-e94a-4b85-9120-266a1ad3e1b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588230338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1588230338
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1420507481
Short name T92
Test name
Test status
Simulation time 35330911 ps
CPU time 0.56 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:48:59 PM PST 24
Peak memory 195552 kb
Host smart-4e700c84-6b5a-49d0-9370-9f2328320005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420507481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1420507481
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2804710120
Short name T131
Test name
Test status
Simulation time 38408321810 ps
CPU time 74.02 seconds
Started Jan 03 12:50:03 PM PST 24
Finished Jan 03 12:51:41 PM PST 24
Peak memory 200180 kb
Host smart-f5bcfca6-8767-44a9-854a-71a0caeac9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804710120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2804710120
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3223107241
Short name T153
Test name
Test status
Simulation time 12010322266 ps
CPU time 11.88 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:05 PM PST 24
Peak memory 199948 kb
Host smart-6975d37b-84fa-44d1-a0be-9bca44546237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223107241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3223107241
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3617995857
Short name T135
Test name
Test status
Simulation time 179702816710 ps
CPU time 57.38 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 200112 kb
Host smart-0c6848e9-b923-4aca-9de9-9ea6cc351d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617995857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3617995857
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3241592015
Short name T72
Test name
Test status
Simulation time 91100021464 ps
CPU time 872.17 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 01:03:16 PM PST 24
Peak memory 216996 kb
Host smart-313d2806-649d-4a66-bdc3-ecc0294a00c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241592015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3241592015
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.154746428
Short name T386
Test name
Test status
Simulation time 77053208876 ps
CPU time 115.66 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:51:51 PM PST 24
Peak memory 200160 kb
Host smart-8895dbb7-0618-4bab-8ee7-44620df47a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154746428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.154746428
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.84067167
Short name T231
Test name
Test status
Simulation time 207691266417 ps
CPU time 101.53 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:51:46 PM PST 24
Peak memory 200088 kb
Host smart-8d467d53-8c5d-475f-b0b0-ce9d64ed5ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84067167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.84067167
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1468643139
Short name T181
Test name
Test status
Simulation time 56984201414 ps
CPU time 24.35 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:49:06 PM PST 24
Peak memory 200196 kb
Host smart-5b351693-66ea-4937-bb01-768ec66a5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468643139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1468643139
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.1727539341
Short name T268
Test name
Test status
Simulation time 81533697088 ps
CPU time 150.05 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 12:51:42 PM PST 24
Peak memory 200180 kb
Host smart-a3719049-38cc-4715-8fa5-2c75c000c542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727539341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1727539341
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1032276273
Short name T152
Test name
Test status
Simulation time 82076049417 ps
CPU time 20.25 seconds
Started Jan 03 12:50:05 PM PST 24
Finished Jan 03 12:50:49 PM PST 24
Peak memory 200204 kb
Host smart-36088ec2-83f0-4ccf-b464-99db22e994a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032276273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1032276273
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3510910221
Short name T13
Test name
Test status
Simulation time 20837806923 ps
CPU time 73.66 seconds
Started Jan 03 12:49:48 PM PST 24
Finished Jan 03 12:51:14 PM PST 24
Peak memory 200068 kb
Host smart-9d0afc0c-14be-4e3e-aa09-a1d974807d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510910221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3510910221
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.756799156
Short name T369
Test name
Test status
Simulation time 30764796941 ps
CPU time 27.47 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 200116 kb
Host smart-49fac25f-8b9a-41c2-8635-b3c7a429c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756799156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.756799156
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2051598872
Short name T171
Test name
Test status
Simulation time 99481542467 ps
CPU time 145.74 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:52:30 PM PST 24
Peak memory 200140 kb
Host smart-8a84fd97-c587-48fd-81ff-077997c66071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051598872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2051598872
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1700798257
Short name T208
Test name
Test status
Simulation time 110743293799 ps
CPU time 1129.68 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 01:08:08 PM PST 24
Peak memory 225060 kb
Host smart-49e2da72-1513-4bc5-869d-09afbe7f872d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700798257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1700798257
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2354985498
Short name T4
Test name
Test status
Simulation time 46303254 ps
CPU time 0.57 seconds
Started Jan 03 12:23:56 PM PST 24
Finished Jan 03 12:23:58 PM PST 24
Peak memory 185048 kb
Host smart-0bc79ecd-0759-4135-b7a4-d29bed570fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354985498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2354985498
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3248187205
Short name T186
Test name
Test status
Simulation time 311418485885 ps
CPU time 142.75 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:52:17 PM PST 24
Peak memory 199760 kb
Host smart-6b303749-078a-4789-85f6-a91c0bce4b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248187205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3248187205
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3857325508
Short name T216
Test name
Test status
Simulation time 48549341050 ps
CPU time 75.69 seconds
Started Jan 03 12:49:24 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 200144 kb
Host smart-ccca9756-0ce5-4585-8a86-cfcb0c309a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857325508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3857325508
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3253307335
Short name T274
Test name
Test status
Simulation time 87166740739 ps
CPU time 32.77 seconds
Started Jan 03 12:49:31 PM PST 24
Finished Jan 03 12:50:19 PM PST 24
Peak memory 200172 kb
Host smart-ccfb94e5-b52e-471a-94ec-aaa9c1faccdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253307335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3253307335
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4134055524
Short name T237
Test name
Test status
Simulation time 100179223288 ps
CPU time 157.5 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:53:01 PM PST 24
Peak memory 199420 kb
Host smart-2dbea575-6097-4278-b541-b0e5d388dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134055524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4134055524
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1672550437
Short name T389
Test name
Test status
Simulation time 987801716327 ps
CPU time 738.95 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 01:02:03 PM PST 24
Peak memory 216636 kb
Host smart-e6efda9f-8143-49c9-be42-d949164fd0d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672550437 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1672550437
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1920455965
Short name T139
Test name
Test status
Simulation time 12418643638 ps
CPU time 17.77 seconds
Started Jan 03 12:50:05 PM PST 24
Finished Jan 03 12:50:47 PM PST 24
Peak memory 199900 kb
Host smart-899470ff-656b-491b-86fd-4c0ee12ff65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920455965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1920455965
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3251213315
Short name T360
Test name
Test status
Simulation time 172003336433 ps
CPU time 25.64 seconds
Started Jan 03 12:49:25 PM PST 24
Finished Jan 03 12:50:08 PM PST 24
Peak memory 199912 kb
Host smart-88146ac3-5ebf-4edb-9af8-16a9dd629464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251213315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3251213315
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.834017939
Short name T341
Test name
Test status
Simulation time 131923301972 ps
CPU time 210.41 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:53:29 PM PST 24
Peak memory 200200 kb
Host smart-9230a9db-f090-480e-b99e-b34f36b88810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834017939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.834017939
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1962441964
Short name T366
Test name
Test status
Simulation time 120300100754 ps
CPU time 39.25 seconds
Started Jan 03 12:50:08 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 200168 kb
Host smart-f02fefd7-7ed9-482c-a0f8-78e6ecd21866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962441964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1962441964
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.4211141842
Short name T253
Test name
Test status
Simulation time 18799284314 ps
CPU time 27.85 seconds
Started Jan 03 12:50:01 PM PST 24
Finished Jan 03 12:50:53 PM PST 24
Peak memory 200232 kb
Host smart-7f198d18-0b5d-41fb-8b16-45424039bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211141842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.4211141842
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3945050775
Short name T134
Test name
Test status
Simulation time 229277285000 ps
CPU time 31.35 seconds
Started Jan 03 12:48:42 PM PST 24
Finished Jan 03 12:49:39 PM PST 24
Peak memory 200200 kb
Host smart-0935a12a-47d2-42ed-9b24-35b915f717cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945050775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3945050775
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.347421090
Short name T263
Test name
Test status
Simulation time 74105470670 ps
CPU time 139.27 seconds
Started Jan 03 12:51:19 PM PST 24
Finished Jan 03 12:53:54 PM PST 24
Peak memory 199716 kb
Host smart-73bd42da-04b9-4926-ad49-95f39de2c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347421090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.347421090
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3376978943
Short name T217
Test name
Test status
Simulation time 186765677059 ps
CPU time 62.62 seconds
Started Jan 03 12:50:08 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 200120 kb
Host smart-ebf8dddf-2645-41a8-a564-f153df4a46b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376978943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3376978943
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1168133250
Short name T166
Test name
Test status
Simulation time 96881198148 ps
CPU time 80.24 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:50:47 PM PST 24
Peak memory 200072 kb
Host smart-201a2323-eedf-4b85-b5f5-d4d210344709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168133250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1168133250
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_noise_filter.28283253
Short name T158
Test name
Test status
Simulation time 85478694578 ps
CPU time 84.24 seconds
Started Jan 03 12:49:07 PM PST 24
Finished Jan 03 12:50:49 PM PST 24
Peak memory 200324 kb
Host smart-87961916-96aa-4092-94d8-f47df0f7afa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28283253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.28283253
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3284389244
Short name T370
Test name
Test status
Simulation time 224402266264 ps
CPU time 91.07 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 200084 kb
Host smart-db0c57ab-6a5b-4ba8-be8f-bd9744b1c9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284389244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3284389244
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3664850385
Short name T420
Test name
Test status
Simulation time 256780482160 ps
CPU time 279.1 seconds
Started Jan 03 12:48:04 PM PST 24
Finished Jan 03 12:53:14 PM PST 24
Peak memory 216920 kb
Host smart-e9b0ab16-98f2-4938-b618-eb35bb22a4f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664850385 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3664850385
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1117203208
Short name T301
Test name
Test status
Simulation time 70277918756 ps
CPU time 24.39 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:50:24 PM PST 24
Peak memory 200124 kb
Host smart-ea1856d1-f40e-4329-a57b-b5561ab80079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117203208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1117203208
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2797444900
Short name T41
Test name
Test status
Simulation time 125262554 ps
CPU time 1.33 seconds
Started Jan 03 12:23:57 PM PST 24
Finished Jan 03 12:24:00 PM PST 24
Peak memory 199212 kb
Host smart-a676d88a-0174-4824-aefb-edb100f3c122
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797444900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2797444900
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2907600534
Short name T284
Test name
Test status
Simulation time 44885305630 ps
CPU time 23.74 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 200192 kb
Host smart-b8ce1e03-d5e3-40ca-8819-48d2a8cbb74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907600534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2907600534
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.141788546
Short name T326
Test name
Test status
Simulation time 52179229063 ps
CPU time 22.41 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 200120 kb
Host smart-88e29b0a-e5d0-43d2-92c0-3f0acc029f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141788546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.141788546
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3212041652
Short name T391
Test name
Test status
Simulation time 264288986642 ps
CPU time 139.6 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 200064 kb
Host smart-7e603733-5716-4c5e-9ddb-f274ec539edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212041652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3212041652
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3391965469
Short name T249
Test name
Test status
Simulation time 43702569058 ps
CPU time 14.28 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:12 PM PST 24
Peak memory 199684 kb
Host smart-938f6b5f-9511-44f4-b5c5-143e5e311aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391965469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3391965469
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1282033944
Short name T1038
Test name
Test status
Simulation time 18895400969 ps
CPU time 28.42 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 200072 kb
Host smart-c79b152e-2ebc-4a5b-8d18-c309c65f9128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282033944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1282033944
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2641943958
Short name T299
Test name
Test status
Simulation time 39323001568 ps
CPU time 63.26 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:50:26 PM PST 24
Peak memory 200192 kb
Host smart-c8083f26-e785-42ba-89fa-a23c44087477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641943958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2641943958
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1873204555
Short name T192
Test name
Test status
Simulation time 147107666074 ps
CPU time 219.51 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:53:32 PM PST 24
Peak memory 200120 kb
Host smart-f31782fd-8eda-439f-a7e0-c06259e0dc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873204555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1873204555
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.952569497
Short name T261
Test name
Test status
Simulation time 478596344288 ps
CPU time 1237.79 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 01:09:24 PM PST 24
Peak memory 200172 kb
Host smart-4af65f98-b89f-41c1-9dcf-042f4547ace3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952569497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.952569497
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1250795554
Short name T143
Test name
Test status
Simulation time 21748253251 ps
CPU time 37.31 seconds
Started Jan 03 12:50:04 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 200220 kb
Host smart-9384a218-edd6-42a0-a046-eb0d8977870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250795554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1250795554
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.354164509
Short name T161
Test name
Test status
Simulation time 4765980724 ps
CPU time 7.01 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 12:51:44 PM PST 24
Peak memory 199652 kb
Host smart-75ee5c04-55ca-4b01-b6c6-013fb42e6820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354164509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.354164509
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.3920656109
Short name T281
Test name
Test status
Simulation time 1059707880077 ps
CPU time 472.41 seconds
Started Jan 03 12:48:52 PM PST 24
Finished Jan 03 12:57:07 PM PST 24
Peak memory 200208 kb
Host smart-18e1dd70-7bfe-4ba0-a625-ac98f0e2bff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920656109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3920656109
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.495559729
Short name T374
Test name
Test status
Simulation time 112792344243 ps
CPU time 16.69 seconds
Started Jan 03 12:49:16 PM PST 24
Finished Jan 03 12:49:51 PM PST 24
Peak memory 199396 kb
Host smart-bb565ad3-cfb3-40ce-b0d1-10c7f4600b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495559729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.495559729
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3863263786
Short name T308
Test name
Test status
Simulation time 73069532145 ps
CPU time 59 seconds
Started Jan 03 12:49:08 PM PST 24
Finished Jan 03 12:50:24 PM PST 24
Peak memory 199088 kb
Host smart-9f92d78f-2608-44d4-b8ec-0c3e4c93a526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863263786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3863263786
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.160766331
Short name T350
Test name
Test status
Simulation time 67282954704 ps
CPU time 197.95 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:53:13 PM PST 24
Peak memory 200264 kb
Host smart-59135fc1-7eac-4e3e-9a22-2a934d8213f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160766331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.160766331
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2228625271
Short name T150
Test name
Test status
Simulation time 141572298107 ps
CPU time 54.03 seconds
Started Jan 03 12:49:32 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 200216 kb
Host smart-45fceb06-33eb-4d84-a4b2-6b48f52a7329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228625271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2228625271
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2316612493
Short name T338
Test name
Test status
Simulation time 67762901521 ps
CPU time 650.03 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 01:01:30 PM PST 24
Peak memory 211800 kb
Host smart-12cb0464-4501-443a-9b18-8b00c981634f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316612493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2316612493
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2205793979
Short name T278
Test name
Test status
Simulation time 110162098370 ps
CPU time 44.76 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 200076 kb
Host smart-479c6a94-6588-48ab-bf7c-d045846e9bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205793979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2205793979
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3474969231
Short name T395
Test name
Test status
Simulation time 229839268086 ps
CPU time 153.65 seconds
Started Jan 03 12:47:56 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 199420 kb
Host smart-6066b191-5364-42d0-8dab-7d7865199457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474969231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3474969231
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_stress_all.1692910783
Short name T340
Test name
Test status
Simulation time 356036334003 ps
CPU time 641.41 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:59:28 PM PST 24
Peak memory 208620 kb
Host smart-11b759e0-f3aa-4bea-92e0-108637248e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692910783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1692910783
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1303881402
Short name T218
Test name
Test status
Simulation time 88573721951 ps
CPU time 15.96 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 199964 kb
Host smart-44c03b2d-557f-4e5f-a788-286754cf5136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303881402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1303881402
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.892853543
Short name T200
Test name
Test status
Simulation time 131740660414 ps
CPU time 213.48 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 12:52:49 PM PST 24
Peak memory 199180 kb
Host smart-2a75bc06-77f8-4565-98ae-10600549e49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892853543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.892853543
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4105514508
Short name T251
Test name
Test status
Simulation time 107074019481 ps
CPU time 145.63 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:52:20 PM PST 24
Peak memory 200136 kb
Host smart-2c0d74c5-5d11-4738-987f-bcc69907e661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105514508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4105514508
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.501641874
Short name T145
Test name
Test status
Simulation time 102284243867 ps
CPU time 58.41 seconds
Started Jan 03 12:49:32 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 200172 kb
Host smart-f96148aa-49da-4b93-9075-2a127603029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501641874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.501641874
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2572868864
Short name T222
Test name
Test status
Simulation time 48930338687 ps
CPU time 65.67 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 199772 kb
Host smart-c6e49384-feb8-4a83-afb7-b93328cd338d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572868864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2572868864
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2127024999
Short name T1135
Test name
Test status
Simulation time 70658361326 ps
CPU time 98.91 seconds
Started Jan 03 12:48:34 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 200088 kb
Host smart-2705aaea-6300-4c13-8e4b-b813b1953b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127024999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2127024999
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2320515853
Short name T247
Test name
Test status
Simulation time 122220584889 ps
CPU time 91.52 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:50:13 PM PST 24
Peak memory 200292 kb
Host smart-f5867ca6-4ae6-44ab-8a22-35d1d7123329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320515853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2320515853
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4242213879
Short name T373
Test name
Test status
Simulation time 5820165513 ps
CPU time 7.03 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:50:00 PM PST 24
Peak memory 199552 kb
Host smart-71091892-7e8d-4c83-b341-ab47c0863f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242213879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4242213879
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.234247012
Short name T307
Test name
Test status
Simulation time 69803236751 ps
CPU time 37.48 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:51:28 PM PST 24
Peak memory 200216 kb
Host smart-6e09c621-2748-462a-9c7c-87a9e53ac442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234247012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.234247012
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2386061731
Short name T672
Test name
Test status
Simulation time 7089498221 ps
CPU time 11.09 seconds
Started Jan 03 12:49:29 PM PST 24
Finished Jan 03 12:49:57 PM PST 24
Peak memory 199244 kb
Host smart-8fbdb304-c739-4c3e-9f8a-f295e4b7d8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386061731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2386061731
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1001150223
Short name T303
Test name
Test status
Simulation time 18638887231 ps
CPU time 31.67 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:50:27 PM PST 24
Peak memory 200200 kb
Host smart-b375ab56-58e4-4cae-ae6a-b65348cd467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001150223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1001150223
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4086339740
Short name T17
Test name
Test status
Simulation time 114834390820 ps
CPU time 16.66 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:13 PM PST 24
Peak memory 199920 kb
Host smart-55df1945-dc61-4bd5-89b2-543090b9195f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086339740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4086339740
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.4193247840
Short name T382
Test name
Test status
Simulation time 14689019395 ps
CPU time 23.21 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:26 PM PST 24
Peak memory 199992 kb
Host smart-1c39ff32-6de7-45bd-9512-fa486f664816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193247840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.4193247840
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.960987722
Short name T344
Test name
Test status
Simulation time 17723728618 ps
CPU time 29.1 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 200168 kb
Host smart-37f2f8cb-af3e-4a3b-8072-435aaecb5a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960987722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.960987722
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1529374500
Short name T319
Test name
Test status
Simulation time 22865403860 ps
CPU time 32.62 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 199780 kb
Host smart-fd2160b7-f354-4750-9164-ea688e80bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529374500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1529374500
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1827556905
Short name T234
Test name
Test status
Simulation time 46350093498 ps
CPU time 7.11 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 199832 kb
Host smart-47460904-814f-489b-a0f7-56a6a287f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827556905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1827556905
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2794152012
Short name T335
Test name
Test status
Simulation time 57512066681 ps
CPU time 32.98 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 200144 kb
Host smart-4be9e21a-023f-4eb0-866a-ecb9cbfdab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794152012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2794152012
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3643241031
Short name T405
Test name
Test status
Simulation time 108395539360 ps
CPU time 722.9 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 01:00:59 PM PST 24
Peak memory 200212 kb
Host smart-77253aab-0cb4-4bc4-93a1-635028333e85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643241031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3643241031
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.336224379
Short name T390
Test name
Test status
Simulation time 15045337305 ps
CPU time 9.92 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:49:06 PM PST 24
Peak memory 199676 kb
Host smart-2f548e71-db60-46b0-acfd-ec01a4b87914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336224379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.336224379
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3051693056
Short name T228
Test name
Test status
Simulation time 114482959715 ps
CPU time 133.77 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:52:32 PM PST 24
Peak memory 200116 kb
Host smart-1dea5a2d-4f59-428c-ab51-81e2a3947db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051693056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3051693056
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2896278370
Short name T394
Test name
Test status
Simulation time 105181410156 ps
CPU time 174.32 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:53:12 PM PST 24
Peak memory 200128 kb
Host smart-f5bcf71a-a894-4bed-b839-b7ed3bfc9296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896278370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2896278370
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.754135277
Short name T315
Test name
Test status
Simulation time 41077356346 ps
CPU time 15.6 seconds
Started Jan 03 12:48:35 PM PST 24
Finished Jan 03 12:49:16 PM PST 24
Peak memory 198924 kb
Host smart-2cce950d-37b0-4f5b-810f-9fa235bc694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754135277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.754135277
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2811128669
Short name T294
Test name
Test status
Simulation time 25410997143 ps
CPU time 22.09 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 200192 kb
Host smart-d1cb2e0b-e9f7-4078-8d59-9c99ffa02a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811128669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2811128669
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.636866926
Short name T398
Test name
Test status
Simulation time 6842504895 ps
CPU time 12.47 seconds
Started Jan 03 12:49:06 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 200064 kb
Host smart-9af1fc76-6d24-4957-9d32-8fabcb93a0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636866926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.636866926
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.881954006
Short name T375
Test name
Test status
Simulation time 38266225455 ps
CPU time 64.23 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:51:01 PM PST 24
Peak memory 200080 kb
Host smart-c958ea8e-025d-476d-a5d3-f5d0adf156a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881954006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.881954006
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1493091802
Short name T205
Test name
Test status
Simulation time 140453330064 ps
CPU time 55.06 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 199792 kb
Host smart-99ae3f66-6f43-439f-8387-ec32e26bcb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493091802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1493091802
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1917410103
Short name T276
Test name
Test status
Simulation time 25839303224 ps
CPU time 39.72 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:51:44 PM PST 24
Peak memory 197516 kb
Host smart-80008b86-fbc9-412b-92be-c6da1d2a0a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917410103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1917410103
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.551996134
Short name T379
Test name
Test status
Simulation time 106280674603 ps
CPU time 78.02 seconds
Started Jan 03 12:49:01 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 200260 kb
Host smart-794c44e3-2a05-4e92-8c2a-2ca05e93e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551996134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.551996134
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.4227555901
Short name T297
Test name
Test status
Simulation time 83501024162 ps
CPU time 141.37 seconds
Started Jan 03 12:51:26 PM PST 24
Finished Jan 03 12:54:01 PM PST 24
Peak memory 199840 kb
Host smart-8ab0e913-3359-4f0e-9c0f-3050382f24ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227555901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4227555901
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1842437411
Short name T115
Test name
Test status
Simulation time 156967631137 ps
CPU time 115.33 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 199568 kb
Host smart-79e1b343-16a8-476a-936f-d4d1137cb2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842437411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1842437411
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2343112117
Short name T364
Test name
Test status
Simulation time 17638329143 ps
CPU time 25.93 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 200228 kb
Host smart-bd434406-dc4a-48b8-8d1f-27107ba83dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343112117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2343112117
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.727592861
Short name T361
Test name
Test status
Simulation time 159131640033 ps
CPU time 17.93 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 199912 kb
Host smart-3661773f-2ea0-4ef6-9ab2-a87dabee9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727592861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.727592861
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.3320544949
Short name T215
Test name
Test status
Simulation time 516688400848 ps
CPU time 607.01 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:59:42 PM PST 24
Peak memory 200144 kb
Host smart-ae9bb71c-87f3-4540-891e-66af267aed81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320544949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3320544949
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_rx.916426800
Short name T1058
Test name
Test status
Simulation time 112868999876 ps
CPU time 478.64 seconds
Started Jan 03 12:49:00 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 200108 kb
Host smart-e2318673-d617-4640-9b19-71c5edb15713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916426800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.916426800
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_stress_all.3226142904
Short name T337
Test name
Test status
Simulation time 162196983801 ps
CPU time 2732.37 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 01:34:51 PM PST 24
Peak memory 200096 kb
Host smart-3aa4cd2b-3df6-4e7d-9eed-07f61a3a1439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226142904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3226142904
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all.910110810
Short name T298
Test name
Test status
Simulation time 1368942475949 ps
CPU time 2675.13 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 01:35:25 PM PST 24
Peak memory 200240 kb
Host smart-4d735457-6dc1-4cc4-be5f-fbf9c5153ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910110810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.910110810
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.628454067
Short name T356
Test name
Test status
Simulation time 18454337434 ps
CPU time 16.88 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 12:49:40 PM PST 24
Peak memory 197764 kb
Host smart-de160744-9e35-40a4-b8e2-8a293fbf2cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628454067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.628454067
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_perf.2624556049
Short name T292
Test name
Test status
Simulation time 8614727749 ps
CPU time 110.14 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:52:28 PM PST 24
Peak memory 200116 kb
Host smart-8918ceb5-cbde-424b-9238-df3103b847fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624556049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2624556049
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1673303500
Short name T384
Test name
Test status
Simulation time 219421051372 ps
CPU time 94.19 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:52:12 PM PST 24
Peak memory 200120 kb
Host smart-4a7cb7bf-ed97-45da-a982-c0f010ddeec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673303500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1673303500
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3771679358
Short name T188
Test name
Test status
Simulation time 13210439517 ps
CPU time 11.8 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 199848 kb
Host smart-a81967d2-3b44-4daf-86ba-59d331aef1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771679358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3771679358
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3970982084
Short name T223
Test name
Test status
Simulation time 165259091492 ps
CPU time 64.38 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 200268 kb
Host smart-359dd4f5-440f-4424-9203-ef645263b3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970982084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3970982084
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1467401658
Short name T387
Test name
Test status
Simulation time 40455133409 ps
CPU time 16.07 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:15 PM PST 24
Peak memory 200000 kb
Host smart-7e659a5a-2dd7-4ff4-8b2c-a05550596d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467401658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1467401658
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2283222405
Short name T475
Test name
Test status
Simulation time 29362544 ps
CPU time 0.82 seconds
Started Jan 03 12:28:02 PM PST 24
Finished Jan 03 12:28:10 PM PST 24
Peak memory 195132 kb
Host smart-53dc11ed-51ce-4802-aeec-d020c3b32906
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283222405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2283222405
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.455934024
Short name T1247
Test name
Test status
Simulation time 1007716979 ps
CPU time 2.39 seconds
Started Jan 03 12:27:59 PM PST 24
Finished Jan 03 12:28:11 PM PST 24
Peak memory 197044 kb
Host smart-38f1be50-cc5c-466a-aa00-a156ff316702
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455934024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.455934024
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4145987234
Short name T37
Test name
Test status
Simulation time 41946444 ps
CPU time 0.58 seconds
Started Jan 03 12:24:57 PM PST 24
Finished Jan 03 12:24:58 PM PST 24
Peak memory 195528 kb
Host smart-c3aefad6-c528-4a29-9f7e-e315d8212786
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145987234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4145987234
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2596447506
Short name T1269
Test name
Test status
Simulation time 44389600 ps
CPU time 0.83 seconds
Started Jan 03 12:22:31 PM PST 24
Finished Jan 03 12:22:33 PM PST 24
Peak memory 199884 kb
Host smart-71c05c68-5e8d-404e-881c-3d8089069599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596447506 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2596447506
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.677471564
Short name T480
Test name
Test status
Simulation time 16048767 ps
CPU time 0.59 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:27:43 PM PST 24
Peak memory 195204 kb
Host smart-0ba0ce77-1298-4011-879b-c447c35e12c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677471564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.677471564
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3324428511
Short name T63
Test name
Test status
Simulation time 76068132 ps
CPU time 0.55 seconds
Started Jan 03 12:28:48 PM PST 24
Finished Jan 03 12:29:18 PM PST 24
Peak memory 185032 kb
Host smart-1f7bed2a-b059-4bc5-8005-bf876190b780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324428511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3324428511
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.478999339
Short name T1290
Test name
Test status
Simulation time 13063027 ps
CPU time 0.62 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:27:44 PM PST 24
Peak memory 194320 kb
Host smart-22dba058-368f-49df-81d8-18261971c861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478999339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.478999339
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4032984879
Short name T1226
Test name
Test status
Simulation time 343895614 ps
CPU time 1.62 seconds
Started Jan 03 12:30:24 PM PST 24
Finished Jan 03 12:31:21 PM PST 24
Peak memory 199708 kb
Host smart-7bcb7327-2116-47c6-9d34-fbbb3009ee6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032984879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4032984879
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1306373668
Short name T1282
Test name
Test status
Simulation time 57365898 ps
CPU time 0.9 seconds
Started Jan 03 12:28:49 PM PST 24
Finished Jan 03 12:29:19 PM PST 24
Peak memory 198672 kb
Host smart-446c5cc4-a9c8-4c8b-80ab-30caecb94875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306373668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1306373668
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2517476055
Short name T67
Test name
Test status
Simulation time 59235230 ps
CPU time 0.71 seconds
Started Jan 03 12:29:37 PM PST 24
Finished Jan 03 12:30:13 PM PST 24
Peak memory 196064 kb
Host smart-1043ccee-1c8b-4c4c-852b-63503d1014e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517476055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2517476055
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.591076263
Short name T469
Test name
Test status
Simulation time 56636232 ps
CPU time 2.19 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:29:48 PM PST 24
Peak memory 197532 kb
Host smart-9c3ecab5-c670-47a2-a2a9-dbcefef34c0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591076263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.591076263
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2547533632
Short name T36
Test name
Test status
Simulation time 84294386 ps
CPU time 0.55 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:30:42 PM PST 24
Peak memory 195112 kb
Host smart-de55e1fa-d0ca-41d9-bedf-11075f8f3aaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547533632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2547533632
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3435640545
Short name T5
Test name
Test status
Simulation time 28715110 ps
CPU time 0.58 seconds
Started Jan 03 12:28:38 PM PST 24
Finished Jan 03 12:28:55 PM PST 24
Peak memory 196000 kb
Host smart-9191d76b-c71d-4855-9e81-ad4ce0d711c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435640545 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3435640545
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2362043746
Short name T468
Test name
Test status
Simulation time 19033477 ps
CPU time 0.54 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:44 PM PST 24
Peak memory 195180 kb
Host smart-4a013ba3-b323-4838-b76e-58d0ec755c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362043746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2362043746
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3914546215
Short name T477
Test name
Test status
Simulation time 25520372 ps
CPU time 0.54 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:43 PM PST 24
Peak memory 184812 kb
Host smart-0273f540-2950-4661-8f04-c373cfadcefe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914546215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3914546215
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.497824557
Short name T461
Test name
Test status
Simulation time 164097585 ps
CPU time 0.64 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:36 PM PST 24
Peak memory 194860 kb
Host smart-b941e7b0-80cb-47db-bfff-fa4cd4b23bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497824557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.497824557
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2371496580
Short name T493
Test name
Test status
Simulation time 71503976 ps
CPU time 0.92 seconds
Started Jan 03 12:28:00 PM PST 24
Finished Jan 03 12:28:10 PM PST 24
Peak memory 199260 kb
Host smart-35a9f7f1-6b20-4a9b-871b-c2aaf3e14d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371496580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2371496580
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3921712059
Short name T1250
Test name
Test status
Simulation time 70806354 ps
CPU time 0.81 seconds
Started Jan 03 12:22:45 PM PST 24
Finished Jan 03 12:22:47 PM PST 24
Peak memory 199784 kb
Host smart-faecde01-e617-4e79-bab9-63d0fbb54cc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921712059 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3921712059
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1833978576
Short name T59
Test name
Test status
Simulation time 17752949 ps
CPU time 0.59 seconds
Started Jan 03 12:28:21 PM PST 24
Finished Jan 03 12:28:30 PM PST 24
Peak memory 195452 kb
Host smart-f4cb7086-2134-4430-90fd-aa03013f3fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833978576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1833978576
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3326874266
Short name T486
Test name
Test status
Simulation time 10558444 ps
CPU time 0.53 seconds
Started Jan 03 12:31:04 PM PST 24
Finished Jan 03 12:32:12 PM PST 24
Peak memory 184844 kb
Host smart-3a6aa3bb-19cd-41c4-80cb-172f911e7f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326874266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3326874266
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.609481642
Short name T1286
Test name
Test status
Simulation time 14129164 ps
CPU time 0.75 seconds
Started Jan 03 12:25:31 PM PST 24
Finished Jan 03 12:25:33 PM PST 24
Peak memory 196924 kb
Host smart-bf7556aa-7ad1-41f9-a0e6-600917417628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609481642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.609481642
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1405889948
Short name T1254
Test name
Test status
Simulation time 104450563 ps
CPU time 2.16 seconds
Started Jan 03 12:29:11 PM PST 24
Finished Jan 03 12:29:40 PM PST 24
Peak memory 198748 kb
Host smart-cb69cf32-e0be-4e66-93cf-19771361c217
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405889948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1405889948
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4120818364
Short name T1230
Test name
Test status
Simulation time 113062187 ps
CPU time 1.24 seconds
Started Jan 03 12:30:56 PM PST 24
Finished Jan 03 12:32:03 PM PST 24
Peak memory 198880 kb
Host smart-49e3cceb-08a8-4a23-8a29-998f6b25bb8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120818364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4120818364
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1694160853
Short name T1224
Test name
Test status
Simulation time 117106668 ps
CPU time 1.36 seconds
Started Jan 03 12:36:59 PM PST 24
Finished Jan 03 12:38:09 PM PST 24
Peak memory 198712 kb
Host smart-161316b2-b079-4e89-8df2-5457c08cc44a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694160853 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1694160853
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.866479638
Short name T1279
Test name
Test status
Simulation time 62296919 ps
CPU time 0.52 seconds
Started Jan 03 12:28:22 PM PST 24
Finished Jan 03 12:28:31 PM PST 24
Peak memory 194236 kb
Host smart-ea1a0d96-e969-42de-9310-cc1087eee3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866479638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.866479638
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.46883979
Short name T9
Test name
Test status
Simulation time 30362567 ps
CPU time 0.66 seconds
Started Jan 03 12:28:22 PM PST 24
Finished Jan 03 12:28:31 PM PST 24
Peak memory 196616 kb
Host smart-4317ee09-ee6b-454a-8ccf-c4aefd4d21b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46883979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_
outstanding.46883979
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3224974063
Short name T45
Test name
Test status
Simulation time 110610096 ps
CPU time 1.64 seconds
Started Jan 03 12:31:03 PM PST 24
Finished Jan 03 12:32:11 PM PST 24
Peak memory 199748 kb
Host smart-30686416-905f-44f9-bd29-97475d96bd85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224974063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3224974063
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1276577447
Short name T403
Test name
Test status
Simulation time 171827318 ps
CPU time 0.93 seconds
Started Jan 03 12:28:27 PM PST 24
Finished Jan 03 12:28:40 PM PST 24
Peak memory 198416 kb
Host smart-3226c9bc-154f-415b-8b56-3a4f9d3c5835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276577447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1276577447
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4280528089
Short name T1238
Test name
Test status
Simulation time 36486403 ps
CPU time 0.73 seconds
Started Jan 03 12:30:08 PM PST 24
Finished Jan 03 12:30:55 PM PST 24
Peak memory 197748 kb
Host smart-d2f6953c-5de1-4857-aeaa-f553f550018e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280528089 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.4280528089
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2905003694
Short name T1234
Test name
Test status
Simulation time 43674592 ps
CPU time 0.59 seconds
Started Jan 03 12:25:22 PM PST 24
Finished Jan 03 12:25:25 PM PST 24
Peak memory 195392 kb
Host smart-55463ef3-c61b-4231-92f9-1840ac807746
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905003694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2905003694
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2830914158
Short name T1260
Test name
Test status
Simulation time 37328236 ps
CPU time 0.57 seconds
Started Jan 03 12:24:29 PM PST 24
Finished Jan 03 12:24:36 PM PST 24
Peak memory 194276 kb
Host smart-5870f749-172a-401d-99cd-46f8135a4488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830914158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2830914158
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1196071746
Short name T79
Test name
Test status
Simulation time 34466292 ps
CPU time 0.72 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:19 PM PST 24
Peak memory 196216 kb
Host smart-d7a1e3a2-9530-4640-a55c-e5e1e2f609ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196071746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1196071746
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1531034367
Short name T1265
Test name
Test status
Simulation time 129427960 ps
CPU time 1.55 seconds
Started Jan 03 12:30:56 PM PST 24
Finished Jan 03 12:32:02 PM PST 24
Peak memory 199728 kb
Host smart-f98d63cb-1f09-433a-8e52-cedb19df44da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531034367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1531034367
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3678279601
Short name T1272
Test name
Test status
Simulation time 304930614 ps
CPU time 1.16 seconds
Started Jan 03 12:28:25 PM PST 24
Finished Jan 03 12:28:33 PM PST 24
Peak memory 198896 kb
Host smart-76e08f02-6c81-4bdf-ac9a-f4430598793e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678279601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3678279601
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1287062883
Short name T105
Test name
Test status
Simulation time 77178673 ps
CPU time 0.7 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 197064 kb
Host smart-67186de0-863e-4fbd-89f5-3e21a64c48c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287062883 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1287062883
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2368761739
Short name T1228
Test name
Test status
Simulation time 23988894 ps
CPU time 0.55 seconds
Started Jan 03 12:29:48 PM PST 24
Finished Jan 03 12:30:30 PM PST 24
Peak memory 195208 kb
Host smart-69ed899d-06e4-40ad-a02e-e7149af8d733
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368761739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2368761739
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.518743108
Short name T48
Test name
Test status
Simulation time 18861505 ps
CPU time 0.66 seconds
Started Jan 03 12:27:21 PM PST 24
Finished Jan 03 12:27:25 PM PST 24
Peak memory 184168 kb
Host smart-6d8c99c1-b155-4513-b462-a2dd0a66c4eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518743108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.518743108
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.519954623
Short name T7
Test name
Test status
Simulation time 34862786 ps
CPU time 0.73 seconds
Started Jan 03 12:27:11 PM PST 24
Finished Jan 03 12:27:14 PM PST 24
Peak memory 194868 kb
Host smart-61598e4a-2f82-4099-8fc7-eaa0aa2367f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519954623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.519954623
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3895737775
Short name T1281
Test name
Test status
Simulation time 211485387 ps
CPU time 1.27 seconds
Started Jan 03 12:29:38 PM PST 24
Finished Jan 03 12:30:17 PM PST 24
Peak memory 199800 kb
Host smart-89edbabf-7f67-46fe-8d1b-de18f12ac8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895737775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3895737775
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.847870594
Short name T43
Test name
Test status
Simulation time 153762154 ps
CPU time 0.88 seconds
Started Jan 03 12:22:56 PM PST 24
Finished Jan 03 12:22:58 PM PST 24
Peak memory 198556 kb
Host smart-a12d613c-d861-46c3-ab1f-21e89b42bf47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847870594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.847870594
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1309759547
Short name T42
Test name
Test status
Simulation time 16774792 ps
CPU time 0.72 seconds
Started Jan 03 12:24:14 PM PST 24
Finished Jan 03 12:24:17 PM PST 24
Peak memory 197944 kb
Host smart-c01175f9-c247-45be-8d56-113bef9eec1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309759547 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1309759547
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4287725410
Short name T1255
Test name
Test status
Simulation time 34666577 ps
CPU time 0.62 seconds
Started Jan 03 12:23:46 PM PST 24
Finished Jan 03 12:23:48 PM PST 24
Peak memory 195396 kb
Host smart-68ee00dc-c038-4969-95bb-b49f1903ac57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287725410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4287725410
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2629373833
Short name T1284
Test name
Test status
Simulation time 14920125 ps
CPU time 0.63 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:30:55 PM PST 24
Peak memory 184088 kb
Host smart-b4a52cba-f459-4316-a548-e690ecc02633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629373833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2629373833
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1084551558
Short name T55
Test name
Test status
Simulation time 89215466 ps
CPU time 0.66 seconds
Started Jan 03 12:24:57 PM PST 24
Finished Jan 03 12:24:59 PM PST 24
Peak memory 196740 kb
Host smart-414616f5-991c-434b-86bb-e999ed4be9d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084551558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1084551558
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2092072597
Short name T1274
Test name
Test status
Simulation time 74195083 ps
CPU time 1.56 seconds
Started Jan 03 12:25:22 PM PST 24
Finished Jan 03 12:25:26 PM PST 24
Peak memory 200024 kb
Host smart-b461d207-e2ba-4263-b3db-a4cc0238a660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092072597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2092072597
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3308202917
Short name T32
Test name
Test status
Simulation time 259259109 ps
CPU time 0.87 seconds
Started Jan 03 12:27:51 PM PST 24
Finished Jan 03 12:27:56 PM PST 24
Peak memory 198720 kb
Host smart-9e759eb1-9d31-41f3-86fc-e1609c6546c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308202917 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3308202917
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1017679303
Short name T62
Test name
Test status
Simulation time 25173716 ps
CPU time 0.61 seconds
Started Jan 03 12:28:00 PM PST 24
Finished Jan 03 12:28:09 PM PST 24
Peak memory 195092 kb
Host smart-ff5f12eb-ca60-457f-bc59-047f2457de84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017679303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1017679303
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.651507137
Short name T3
Test name
Test status
Simulation time 35383787 ps
CPU time 0.55 seconds
Started Jan 03 12:30:54 PM PST 24
Finished Jan 03 12:31:59 PM PST 24
Peak memory 193992 kb
Host smart-c02685be-22b6-4505-a0b1-683a6e680190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651507137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.651507137
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3514834813
Short name T495
Test name
Test status
Simulation time 68305409 ps
CPU time 0.59 seconds
Started Jan 03 12:30:37 PM PST 24
Finished Jan 03 12:31:39 PM PST 24
Peak memory 195184 kb
Host smart-1b7b2ef8-abac-4c30-ad07-2238b361a663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514834813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3514834813
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.860812782
Short name T1235
Test name
Test status
Simulation time 102689083 ps
CPU time 2.11 seconds
Started Jan 03 12:27:37 PM PST 24
Finished Jan 03 12:27:43 PM PST 24
Peak memory 199952 kb
Host smart-e249dc75-0ced-468a-98ca-9789210dadea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860812782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.860812782
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3895023652
Short name T1232
Test name
Test status
Simulation time 241069450 ps
CPU time 1.02 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:27:43 PM PST 24
Peak memory 197652 kb
Host smart-7fb406cf-7214-4e2f-a26f-1ceaf1d6bb0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895023652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3895023652
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3303542155
Short name T46
Test name
Test status
Simulation time 77617180 ps
CPU time 1.06 seconds
Started Jan 03 12:38:51 PM PST 24
Finished Jan 03 12:40:11 PM PST 24
Peak memory 200152 kb
Host smart-ac024bc4-f5fe-4a99-a501-6d17ce51e6c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303542155 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3303542155
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1373787466
Short name T77
Test name
Test status
Simulation time 15854777 ps
CPU time 0.59 seconds
Started Jan 03 12:39:13 PM PST 24
Finished Jan 03 12:40:53 PM PST 24
Peak memory 195568 kb
Host smart-605bc73f-73a6-4e1c-9680-3947e2e6986c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373787466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1373787466
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.275067979
Short name T1267
Test name
Test status
Simulation time 16368549 ps
CPU time 0.7 seconds
Started Jan 03 12:30:21 PM PST 24
Finished Jan 03 12:31:16 PM PST 24
Peak memory 196512 kb
Host smart-ff52e5a6-7bd0-45d3-b113-3747d4e41fb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275067979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.275067979
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1360786036
Short name T1251
Test name
Test status
Simulation time 70947835 ps
CPU time 1.31 seconds
Started Jan 03 12:37:09 PM PST 24
Finished Jan 03 12:38:20 PM PST 24
Peak memory 199796 kb
Host smart-9713bde1-309d-47a4-a775-aa2c17788537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360786036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1360786036
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3975247214
Short name T53
Test name
Test status
Simulation time 617849161 ps
CPU time 1.37 seconds
Started Jan 03 12:22:42 PM PST 24
Finished Jan 03 12:22:45 PM PST 24
Peak memory 199408 kb
Host smart-fd9e0e1b-4274-421a-baf2-15c3f64dc4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975247214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3975247214
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.294499620
Short name T487
Test name
Test status
Simulation time 43228897 ps
CPU time 1.06 seconds
Started Jan 03 12:27:48 PM PST 24
Finished Jan 03 12:27:51 PM PST 24
Peak memory 199760 kb
Host smart-17da4885-1a98-44ce-b53f-a476dc688e72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294499620 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.294499620
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2047815335
Short name T490
Test name
Test status
Simulation time 14411462 ps
CPU time 0.52 seconds
Started Jan 03 12:29:48 PM PST 24
Finished Jan 03 12:30:29 PM PST 24
Peak memory 194060 kb
Host smart-d30fc37c-40be-42e6-997e-6f98a31d9181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047815335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2047815335
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2563642655
Short name T1229
Test name
Test status
Simulation time 12438581 ps
CPU time 0.62 seconds
Started Jan 03 12:29:35 PM PST 24
Finished Jan 03 12:30:10 PM PST 24
Peak memory 196164 kb
Host smart-51ace287-4a30-4485-b781-e0e1832ec9bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563642655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2563642655
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.969106679
Short name T39
Test name
Test status
Simulation time 120759871 ps
CPU time 1.75 seconds
Started Jan 03 12:25:17 PM PST 24
Finished Jan 03 12:25:20 PM PST 24
Peak memory 200096 kb
Host smart-a0c2827a-61dc-4c39-9a64-0c22ce2f6140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969106679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.969106679
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2389012431
Short name T1289
Test name
Test status
Simulation time 405277079 ps
CPU time 1.23 seconds
Started Jan 03 12:29:35 PM PST 24
Finished Jan 03 12:30:15 PM PST 24
Peak memory 198860 kb
Host smart-58a8b2b7-9f6b-44d0-be87-8fee47a0b378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389012431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2389012431
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.616860287
Short name T1246
Test name
Test status
Simulation time 290660817 ps
CPU time 0.72 seconds
Started Jan 03 12:29:38 PM PST 24
Finished Jan 03 12:30:16 PM PST 24
Peak memory 198344 kb
Host smart-139f5781-bda4-4f36-b90a-355378db1118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616860287 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.616860287
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2246092022
Short name T58
Test name
Test status
Simulation time 17682924 ps
CPU time 0.6 seconds
Started Jan 03 12:29:34 PM PST 24
Finished Jan 03 12:30:10 PM PST 24
Peak memory 195208 kb
Host smart-bc04904a-2802-4df6-8ee2-8fc1f8c50453
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246092022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2246092022
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1477229239
Short name T1276
Test name
Test status
Simulation time 31828388 ps
CPU time 0.55 seconds
Started Jan 03 12:29:54 PM PST 24
Finished Jan 03 12:30:36 PM PST 24
Peak memory 194300 kb
Host smart-c2914ee2-5a92-4d6b-9a00-0d3edb0f5d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477229239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1477229239
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2728496680
Short name T1261
Test name
Test status
Simulation time 22165044 ps
CPU time 0.64 seconds
Started Jan 03 12:23:42 PM PST 24
Finished Jan 03 12:23:44 PM PST 24
Peak memory 195208 kb
Host smart-1b2f58ab-7896-4619-b35e-38a7d5b097e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728496680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2728496680
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1414946411
Short name T33
Test name
Test status
Simulation time 166096666 ps
CPU time 2.1 seconds
Started Jan 03 12:23:55 PM PST 24
Finished Jan 03 12:23:58 PM PST 24
Peak memory 199696 kb
Host smart-18b2d223-c73e-4882-80b4-e7079473729b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414946411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1414946411
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2977268260
Short name T471
Test name
Test status
Simulation time 812584257 ps
CPU time 0.88 seconds
Started Jan 03 12:27:49 PM PST 24
Finished Jan 03 12:27:53 PM PST 24
Peak memory 198768 kb
Host smart-b324a5b2-cca8-4d0c-9d51-f863228d2733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977268260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2977268260
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.77707469
Short name T494
Test name
Test status
Simulation time 56327034 ps
CPU time 0.64 seconds
Started Jan 03 12:24:45 PM PST 24
Finished Jan 03 12:24:48 PM PST 24
Peak memory 196556 kb
Host smart-5464905f-4e42-4841-9175-80ed5edea0ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77707469 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.77707469
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3799137330
Short name T78
Test name
Test status
Simulation time 29728528 ps
CPU time 0.53 seconds
Started Jan 03 12:30:38 PM PST 24
Finished Jan 03 12:31:40 PM PST 24
Peak memory 195160 kb
Host smart-58028dbe-a20f-4cee-b875-6abd8b93b3a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799137330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3799137330
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2821552161
Short name T49
Test name
Test status
Simulation time 23016136 ps
CPU time 0.73 seconds
Started Jan 03 12:29:28 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 197252 kb
Host smart-f52e8c42-49c6-4057-9f7f-eab0b94901c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821552161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2821552161
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3666912337
Short name T1248
Test name
Test status
Simulation time 349731670 ps
CPU time 2 seconds
Started Jan 03 12:26:14 PM PST 24
Finished Jan 03 12:26:16 PM PST 24
Peak memory 200012 kb
Host smart-98a3cb30-e28a-4f34-8dc2-ed9c7e7e5823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666912337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3666912337
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2750959254
Short name T1256
Test name
Test status
Simulation time 88622440 ps
CPU time 1.31 seconds
Started Jan 03 12:42:35 PM PST 24
Finished Jan 03 12:44:05 PM PST 24
Peak memory 199456 kb
Host smart-d59a5c38-cc18-456a-b7a9-9687937f422f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750959254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2750959254
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.662131880
Short name T52
Test name
Test status
Simulation time 72565159 ps
CPU time 0.63 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:07 PM PST 24
Peak memory 195064 kb
Host smart-7ff8dea8-b518-49ff-a7a1-97bb64688b03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662131880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.662131880
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1398129456
Short name T57
Test name
Test status
Simulation time 131975064 ps
CPU time 1.5 seconds
Started Jan 03 12:28:37 PM PST 24
Finished Jan 03 12:28:53 PM PST 24
Peak memory 197700 kb
Host smart-bcd09c73-5440-4990-859b-0dbb91d031ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398129456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1398129456
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3977371222
Short name T483
Test name
Test status
Simulation time 50304060 ps
CPU time 0.78 seconds
Started Jan 03 12:24:38 PM PST 24
Finished Jan 03 12:24:40 PM PST 24
Peak memory 199596 kb
Host smart-d08ad060-99f7-45bf-a9e5-72877af7fb7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977371222 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3977371222
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4101734972
Short name T68
Test name
Test status
Simulation time 20017425 ps
CPU time 0.58 seconds
Started Jan 03 12:28:45 PM PST 24
Finished Jan 03 12:29:15 PM PST 24
Peak memory 195396 kb
Host smart-23eaf025-2bdf-44a5-9894-fda8fe8ae7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101734972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4101734972
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3617876974
Short name T485
Test name
Test status
Simulation time 34056547 ps
CPU time 0.59 seconds
Started Jan 03 12:27:18 PM PST 24
Finished Jan 03 12:27:23 PM PST 24
Peak memory 183912 kb
Host smart-bcd09435-689c-4c09-aaee-814f9c3a86c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617876974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3617876974
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3393871391
Short name T1227
Test name
Test status
Simulation time 82871493 ps
CPU time 0.74 seconds
Started Jan 03 12:27:26 PM PST 24
Finished Jan 03 12:27:33 PM PST 24
Peak memory 195012 kb
Host smart-1bda7e8d-07fe-4979-9b5b-4a0e76cf3133
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393871391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3393871391
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.575685395
Short name T491
Test name
Test status
Simulation time 69553441 ps
CPU time 1.38 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:29:47 PM PST 24
Peak memory 199788 kb
Host smart-6132f9b8-41b9-4030-b1a9-bb3d88d3bf29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575685395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.575685395
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1370053188
Short name T481
Test name
Test status
Simulation time 45530091 ps
CPU time 0.93 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:02 PM PST 24
Peak memory 198816 kb
Host smart-7be71f51-c656-4e90-a31f-15d4493b75d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370053188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1370053188
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3602514940
Short name T1231
Test name
Test status
Simulation time 18590693 ps
CPU time 0.58 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:18 PM PST 24
Peak memory 184804 kb
Host smart-dc57017d-b2e8-4542-a2bc-f4cdbf5927c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602514940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3602514940
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2366804330
Short name T1271
Test name
Test status
Simulation time 247688055 ps
CPU time 0.57 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:05 PM PST 24
Peak memory 194312 kb
Host smart-9e78cf91-ad7c-40f5-a033-2645e8f37d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366804330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2366804330
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1605620688
Short name T64
Test name
Test status
Simulation time 86152132 ps
CPU time 0.57 seconds
Started Jan 03 12:25:03 PM PST 24
Finished Jan 03 12:25:10 PM PST 24
Peak memory 185208 kb
Host smart-f3d5ae18-d93e-423c-8b43-ac7a8bab8496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605620688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1605620688
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2272294262
Short name T474
Test name
Test status
Simulation time 21674586 ps
CPU time 0.54 seconds
Started Jan 03 12:30:33 PM PST 24
Finished Jan 03 12:31:37 PM PST 24
Peak memory 184788 kb
Host smart-3ad91db6-3aeb-4a47-8726-a95908c30d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272294262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2272294262
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1044920009
Short name T1259
Test name
Test status
Simulation time 23276266 ps
CPU time 0.55 seconds
Started Jan 03 12:30:34 PM PST 24
Finished Jan 03 12:31:35 PM PST 24
Peak memory 194068 kb
Host smart-6cb2fc60-3f1a-48c8-877c-de7573a6bb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044920009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1044920009
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1956734232
Short name T1249
Test name
Test status
Simulation time 15652296 ps
CPU time 0.58 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:19 PM PST 24
Peak memory 184816 kb
Host smart-53c24e10-8cca-4de0-9bc2-49c814ef132d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956734232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1956734232
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3754125007
Short name T484
Test name
Test status
Simulation time 21562264 ps
CPU time 0.57 seconds
Started Jan 03 12:22:43 PM PST 24
Finished Jan 03 12:22:46 PM PST 24
Peak memory 194516 kb
Host smart-004b1fea-b580-499b-921c-3a79fa046a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754125007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3754125007
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.4106022935
Short name T489
Test name
Test status
Simulation time 18916832 ps
CPU time 0.58 seconds
Started Jan 03 12:32:48 PM PST 24
Finished Jan 03 12:34:13 PM PST 24
Peak memory 183516 kb
Host smart-b8fc9e5f-c4dc-4dd4-83bc-58649e5484e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106022935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4106022935
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2105520989
Short name T1
Test name
Test status
Simulation time 34962514 ps
CPU time 0.55 seconds
Started Jan 03 12:45:09 PM PST 24
Finished Jan 03 12:46:44 PM PST 24
Peak memory 194432 kb
Host smart-e0de30d8-9e1b-432a-b401-8ce631cfefc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105520989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2105520989
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.384348111
Short name T488
Test name
Test status
Simulation time 23761588 ps
CPU time 0.67 seconds
Started Jan 03 12:29:55 PM PST 24
Finished Jan 03 12:30:39 PM PST 24
Peak memory 194508 kb
Host smart-101e2497-2a7e-4a06-a8bc-dc19ece562e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384348111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.384348111
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3948578163
Short name T1278
Test name
Test status
Simulation time 533180341 ps
CPU time 2.27 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:11 PM PST 24
Peak memory 195672 kb
Host smart-a4078723-0138-423c-a162-2ab5d6c4aaae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948578163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3948578163
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1255221997
Short name T35
Test name
Test status
Simulation time 12703284 ps
CPU time 0.67 seconds
Started Jan 03 12:28:12 PM PST 24
Finished Jan 03 12:28:21 PM PST 24
Peak memory 194108 kb
Host smart-2c9156db-8b49-4847-bfe9-b80e131b5dea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255221997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1255221997
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3241333026
Short name T65
Test name
Test status
Simulation time 52090680 ps
CPU time 0.65 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:27:30 PM PST 24
Peak memory 197472 kb
Host smart-fa599a02-12a7-4a56-8899-d4f2bab8e6cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241333026 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3241333026
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2687931697
Short name T8
Test name
Test status
Simulation time 62121094 ps
CPU time 0.64 seconds
Started Jan 03 12:28:39 PM PST 24
Finished Jan 03 12:28:56 PM PST 24
Peak memory 195380 kb
Host smart-4a3c3052-75d0-42e8-be0e-2e87440abee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687931697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2687931697
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.758613528
Short name T466
Test name
Test status
Simulation time 12942960 ps
CPU time 0.7 seconds
Started Jan 03 12:27:51 PM PST 24
Finished Jan 03 12:27:56 PM PST 24
Peak memory 185012 kb
Host smart-10da7e5a-d6a0-4864-a47e-8f08299cc937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758613528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.758613528
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3951267436
Short name T1239
Test name
Test status
Simulation time 89476546 ps
CPU time 0.62 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:30:54 PM PST 24
Peak memory 195252 kb
Host smart-5d9821d9-53e8-4919-8288-5d93c67d77ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951267436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3951267436
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1595620909
Short name T38
Test name
Test status
Simulation time 90259133 ps
CPU time 1.05 seconds
Started Jan 03 12:28:12 PM PST 24
Finished Jan 03 12:28:21 PM PST 24
Peak memory 197560 kb
Host smart-5fd0d39b-a663-4401-85ae-b8268138a791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595620909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1595620909
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3035738199
Short name T1264
Test name
Test status
Simulation time 52462245 ps
CPU time 0.56 seconds
Started Jan 03 12:28:14 PM PST 24
Finished Jan 03 12:28:21 PM PST 24
Peak memory 193976 kb
Host smart-c6ccb0ac-670d-4cac-b123-705023d58c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035738199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3035738199
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.433058837
Short name T1285
Test name
Test status
Simulation time 21381613 ps
CPU time 0.54 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:03 PM PST 24
Peak memory 185064 kb
Host smart-758291c3-205e-410f-95ff-dfce59878883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433058837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.433058837
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1565243705
Short name T470
Test name
Test status
Simulation time 163964674 ps
CPU time 0.63 seconds
Started Jan 03 12:28:39 PM PST 24
Finished Jan 03 12:28:56 PM PST 24
Peak memory 194264 kb
Host smart-b9427d6c-eb48-43f9-88ab-375497d010c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565243705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1565243705
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3087301691
Short name T1253
Test name
Test status
Simulation time 21951741 ps
CPU time 0.53 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:29:53 PM PST 24
Peak memory 184868 kb
Host smart-b9498819-2bb8-49e2-9097-b30dc896688e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087301691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3087301691
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1326620328
Short name T465
Test name
Test status
Simulation time 50016196 ps
CPU time 0.55 seconds
Started Jan 03 12:33:49 PM PST 24
Finished Jan 03 12:35:21 PM PST 24
Peak memory 194088 kb
Host smart-ac3663b5-6445-475e-971d-6c4f06753bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326620328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1326620328
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.751508505
Short name T1270
Test name
Test status
Simulation time 15672622 ps
CPU time 0.53 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:29:50 PM PST 24
Peak memory 184872 kb
Host smart-be933902-5c45-4734-8c7b-0ee0f0643ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751508505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.751508505
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1080712169
Short name T464
Test name
Test status
Simulation time 16269580 ps
CPU time 0.6 seconds
Started Jan 03 12:22:42 PM PST 24
Finished Jan 03 12:22:44 PM PST 24
Peak memory 194272 kb
Host smart-b215e6f9-0bb7-4c52-94c2-f786f9fef23d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080712169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1080712169
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3777139866
Short name T473
Test name
Test status
Simulation time 52787749 ps
CPU time 0.55 seconds
Started Jan 03 12:34:46 PM PST 24
Finished Jan 03 12:35:59 PM PST 24
Peak memory 184396 kb
Host smart-842254bd-b0a5-4d74-914a-ad551c507cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777139866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3777139866
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3159174237
Short name T1233
Test name
Test status
Simulation time 41503598 ps
CPU time 0.54 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:30:54 PM PST 24
Peak memory 184860 kb
Host smart-ac1fa742-221f-4769-b3bf-21da89e30e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159174237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3159174237
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1586195692
Short name T404
Test name
Test status
Simulation time 126675842 ps
CPU time 0.62 seconds
Started Jan 03 12:29:45 PM PST 24
Finished Jan 03 12:30:26 PM PST 24
Peak memory 183972 kb
Host smart-11e06911-99d2-4eca-a795-3d6afd3d54da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586195692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1586195692
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4121491323
Short name T56
Test name
Test status
Simulation time 23580592 ps
CPU time 0.64 seconds
Started Jan 03 12:22:43 PM PST 24
Finished Jan 03 12:22:45 PM PST 24
Peak memory 194932 kb
Host smart-c8e369b4-85c6-47bc-877c-30060b350843
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121491323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.4121491323
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1922562520
Short name T73
Test name
Test status
Simulation time 715225477 ps
CPU time 1.61 seconds
Started Jan 03 12:27:59 PM PST 24
Finished Jan 03 12:28:11 PM PST 24
Peak memory 196908 kb
Host smart-a3728616-c191-4333-b360-0526d59ffbb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922562520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1922562520
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2279553033
Short name T482
Test name
Test status
Simulation time 16137174 ps
CPU time 0.59 seconds
Started Jan 03 12:30:22 PM PST 24
Finished Jan 03 12:31:17 PM PST 24
Peak memory 195132 kb
Host smart-2be85c8a-172f-461c-87d5-eaf3e44d6ee5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279553033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2279553033
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3585097365
Short name T1257
Test name
Test status
Simulation time 122354514 ps
CPU time 0.79 seconds
Started Jan 03 12:29:12 PM PST 24
Finished Jan 03 12:29:40 PM PST 24
Peak memory 199092 kb
Host smart-2dc981ce-b4a4-439f-a74a-0ce9e1ba0cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585097365 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3585097365
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3708914099
Short name T478
Test name
Test status
Simulation time 11521371 ps
CPU time 0.61 seconds
Started Jan 03 12:30:37 PM PST 24
Finished Jan 03 12:31:40 PM PST 24
Peak memory 194580 kb
Host smart-0d072d72-fea8-4009-a4a2-a347b33f0951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708914099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3708914099
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2221547340
Short name T479
Test name
Test status
Simulation time 60766062 ps
CPU time 0.56 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:19 PM PST 24
Peak memory 184336 kb
Host smart-799b4830-8ae5-47dc-a75f-8c3ba2c961b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221547340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2221547340
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3545006604
Short name T1245
Test name
Test status
Simulation time 74584640 ps
CPU time 0.63 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 194388 kb
Host smart-fc753c6d-1d50-40d9-a1fd-9d896b8454e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545006604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3545006604
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1536283676
Short name T1244
Test name
Test status
Simulation time 65428894 ps
CPU time 1.54 seconds
Started Jan 03 12:30:09 PM PST 24
Finished Jan 03 12:30:57 PM PST 24
Peak memory 199752 kb
Host smart-478db174-2026-4769-b262-a40c05c9157e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536283676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1536283676
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2204867961
Short name T31
Test name
Test status
Simulation time 1010771870 ps
CPU time 1.38 seconds
Started Jan 03 12:27:35 PM PST 24
Finished Jan 03 12:27:40 PM PST 24
Peak memory 199064 kb
Host smart-bd1839a1-8a7e-4b3c-a8c4-e4c6676b1389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204867961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2204867961
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.294252226
Short name T1258
Test name
Test status
Simulation time 13082434 ps
CPU time 0.55 seconds
Started Jan 03 12:30:05 PM PST 24
Finished Jan 03 12:30:51 PM PST 24
Peak memory 184940 kb
Host smart-815a84d2-827a-4c5d-8bd2-fe6e51f8f63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294252226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.294252226
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1568029553
Short name T1277
Test name
Test status
Simulation time 29680906 ps
CPU time 0.67 seconds
Started Jan 03 12:28:53 PM PST 24
Finished Jan 03 12:29:22 PM PST 24
Peak memory 183040 kb
Host smart-494cbc90-aa56-448e-aed2-ffe38a51083d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568029553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1568029553
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3203417293
Short name T467
Test name
Test status
Simulation time 25487688 ps
CPU time 0.6 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 192908 kb
Host smart-498c966d-67bc-4031-a1ae-7e8dfe9dc813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203417293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3203417293
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3673431858
Short name T462
Test name
Test status
Simulation time 14722085 ps
CPU time 0.53 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 184756 kb
Host smart-9da1f158-8c6b-46e8-9db5-e57a6f6f395c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673431858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3673431858
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.906240681
Short name T463
Test name
Test status
Simulation time 16902126 ps
CPU time 0.53 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 184736 kb
Host smart-35af5d14-e2c6-41c3-8f7e-c864ee8df79a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906240681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.906240681
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3807913871
Short name T472
Test name
Test status
Simulation time 12127993 ps
CPU time 0.54 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:35 PM PST 24
Peak memory 184844 kb
Host smart-ef38fff4-6089-4787-a32b-3a86b13eb015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807913871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3807913871
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3139841465
Short name T1225
Test name
Test status
Simulation time 47171994 ps
CPU time 0.53 seconds
Started Jan 03 12:30:11 PM PST 24
Finished Jan 03 12:30:59 PM PST 24
Peak memory 184848 kb
Host smart-bdc28e00-2abe-47d3-88a3-fa92e89e7ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139841465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3139841465
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.300538141
Short name T51
Test name
Test status
Simulation time 31147059 ps
CPU time 0.54 seconds
Started Jan 03 12:22:38 PM PST 24
Finished Jan 03 12:22:39 PM PST 24
Peak memory 185188 kb
Host smart-6b8e636b-41bc-4135-bac4-b8ac642e0693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300538141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.300538141
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.186904934
Short name T1242
Test name
Test status
Simulation time 32309974 ps
CPU time 1.56 seconds
Started Jan 03 12:30:37 PM PST 24
Finished Jan 03 12:31:41 PM PST 24
Peak memory 199192 kb
Host smart-472a26dc-bc1b-43e1-a575-053000e1f2b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186904934 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.186904934
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1296423900
Short name T1236
Test name
Test status
Simulation time 29152633 ps
CPU time 0.57 seconds
Started Jan 03 12:30:24 PM PST 24
Finished Jan 03 12:31:20 PM PST 24
Peak memory 195060 kb
Host smart-644080ae-0b51-4965-ae4b-b5fde73544a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296423900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1296423900
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3480835047
Short name T1243
Test name
Test status
Simulation time 11574848 ps
CPU time 0.53 seconds
Started Jan 03 12:28:26 PM PST 24
Finished Jan 03 12:28:37 PM PST 24
Peak memory 194232 kb
Host smart-a23cbfe2-467c-473e-b94b-e40bda1cbf5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480835047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3480835047
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.680865325
Short name T1268
Test name
Test status
Simulation time 63768151 ps
CPU time 0.61 seconds
Started Jan 03 12:30:50 PM PST 24
Finished Jan 03 12:31:57 PM PST 24
Peak memory 195508 kb
Host smart-1bea4859-8b94-4097-ab72-f7e9aac743e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680865325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.680865325
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2161436288
Short name T1240
Test name
Test status
Simulation time 267870191 ps
CPU time 1.34 seconds
Started Jan 03 12:28:25 PM PST 24
Finished Jan 03 12:28:33 PM PST 24
Peak memory 199904 kb
Host smart-e82ac10c-70e4-4c7a-a52d-bdafe3440cea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161436288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2161436288
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1194522423
Short name T1280
Test name
Test status
Simulation time 35052513 ps
CPU time 0.64 seconds
Started Jan 03 12:27:58 PM PST 24
Finished Jan 03 12:28:09 PM PST 24
Peak memory 196520 kb
Host smart-5a178467-c848-4fa4-af00-461135caffca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194522423 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1194522423
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1114080776
Short name T60
Test name
Test status
Simulation time 36959495 ps
CPU time 0.54 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:19 PM PST 24
Peak memory 195192 kb
Host smart-8a396da8-bda0-467c-8e1e-d1e336a852c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114080776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1114080776
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3651697205
Short name T1283
Test name
Test status
Simulation time 40219671 ps
CPU time 0.53 seconds
Started Jan 03 12:31:02 PM PST 24
Finished Jan 03 12:32:10 PM PST 24
Peak memory 184812 kb
Host smart-9fc753bd-a068-49c4-88d0-d485e1e696b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651697205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3651697205
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2435316872
Short name T61
Test name
Test status
Simulation time 22396155 ps
CPU time 0.63 seconds
Started Jan 03 12:24:14 PM PST 24
Finished Jan 03 12:24:17 PM PST 24
Peak memory 194624 kb
Host smart-1ad5eef2-b681-49e9-99c6-c19279eda08c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435316872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2435316872
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2457188809
Short name T492
Test name
Test status
Simulation time 42236294 ps
CPU time 2.31 seconds
Started Jan 03 12:23:46 PM PST 24
Finished Jan 03 12:23:49 PM PST 24
Peak memory 200008 kb
Host smart-c2fae546-3eb0-4596-8ba8-58e238b6308e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457188809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2457188809
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4228702403
Short name T54
Test name
Test status
Simulation time 369420799 ps
CPU time 1.3 seconds
Started Jan 03 12:30:35 PM PST 24
Finished Jan 03 12:31:38 PM PST 24
Peak memory 198416 kb
Host smart-f5dff002-f626-4c8d-bfc8-75977d10e4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228702403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4228702403
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.178278770
Short name T1291
Test name
Test status
Simulation time 12196454 ps
CPU time 0.62 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 196076 kb
Host smart-a5536073-f552-477c-ae1b-6d2663f10fec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178278770 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.178278770
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1983767085
Short name T1237
Test name
Test status
Simulation time 49146211 ps
CPU time 0.57 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 195064 kb
Host smart-050fd56b-d363-48d6-b92a-5ac0721de1df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983767085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1983767085
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1401279212
Short name T66
Test name
Test status
Simulation time 64448397 ps
CPU time 0.53 seconds
Started Jan 03 12:29:59 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 184752 kb
Host smart-c4392911-2da9-4945-bbe7-58c4bf44a865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401279212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1401279212
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3306890150
Short name T1275
Test name
Test status
Simulation time 122457890 ps
CPU time 0.69 seconds
Started Jan 03 12:30:49 PM PST 24
Finished Jan 03 12:31:55 PM PST 24
Peak memory 196648 kb
Host smart-1c3dce59-ef56-48a0-8a18-6e204654973b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306890150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3306890150
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1891713606
Short name T44
Test name
Test status
Simulation time 35086999 ps
CPU time 0.9 seconds
Started Jan 03 12:30:56 PM PST 24
Finished Jan 03 12:32:03 PM PST 24
Peak memory 198892 kb
Host smart-ba918e51-c016-4390-8a37-b1919b093b42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891713606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1891713606
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.98647244
Short name T1262
Test name
Test status
Simulation time 47779061 ps
CPU time 0.97 seconds
Started Jan 03 12:25:08 PM PST 24
Finished Jan 03 12:25:11 PM PST 24
Peak memory 198916 kb
Host smart-96e1b277-15cb-4cf4-99da-4e74fb3935d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98647244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.98647244
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2519657185
Short name T1241
Test name
Test status
Simulation time 80696197 ps
CPU time 0.82 seconds
Started Jan 03 12:30:40 PM PST 24
Finished Jan 03 12:31:45 PM PST 24
Peak memory 199520 kb
Host smart-6168ae11-a4cc-41cf-95a3-af3b89a997ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519657185 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2519657185
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.174126870
Short name T1288
Test name
Test status
Simulation time 54765320 ps
CPU time 0.66 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 193580 kb
Host smart-62aa9b11-3f19-4c43-8f61-e6b8999e7225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174126870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.174126870
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3149985623
Short name T1266
Test name
Test status
Simulation time 49846719 ps
CPU time 0.54 seconds
Started Jan 03 12:27:35 PM PST 24
Finished Jan 03 12:27:39 PM PST 24
Peak memory 184996 kb
Host smart-9e1fa5b4-0aeb-49a3-a317-138daa9b64e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149985623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3149985623
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1083271104
Short name T1252
Test name
Test status
Simulation time 16360151 ps
CPU time 0.64 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:19 PM PST 24
Peak memory 194352 kb
Host smart-6ddbc2d8-2165-4394-b4c8-82a21ee69897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083271104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1083271104
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2360770734
Short name T1287
Test name
Test status
Simulation time 207400959 ps
CPU time 1.31 seconds
Started Jan 03 12:28:29 PM PST 24
Finished Jan 03 12:28:44 PM PST 24
Peak memory 199892 kb
Host smart-cdcc1524-56f7-4383-b96f-698019ce5c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360770734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2360770734
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1794836892
Short name T40
Test name
Test status
Simulation time 157100824 ps
CPU time 0.86 seconds
Started Jan 03 12:27:17 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 198316 kb
Host smart-2c0f03a8-47da-4014-b776-7a7dfceadf72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794836892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1794836892
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.64070481
Short name T1263
Test name
Test status
Simulation time 31128309 ps
CPU time 0.68 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 194884 kb
Host smart-ebccd0c5-2eb9-4a03-beb2-46ac18489424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64070481 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.64070481
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2858819753
Short name T1273
Test name
Test status
Simulation time 16373225 ps
CPU time 0.59 seconds
Started Jan 03 12:28:24 PM PST 24
Finished Jan 03 12:28:32 PM PST 24
Peak memory 195504 kb
Host smart-8bada3bd-baed-4c64-8dd5-9534348eac5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858819753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2858819753
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2885584000
Short name T460
Test name
Test status
Simulation time 16793020 ps
CPU time 0.55 seconds
Started Jan 03 12:23:54 PM PST 24
Finished Jan 03 12:23:55 PM PST 24
Peak memory 185040 kb
Host smart-f758438c-415b-4427-b725-0dcb6be1bb71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885584000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2885584000
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4179241976
Short name T50
Test name
Test status
Simulation time 50747308 ps
CPU time 0.69 seconds
Started Jan 03 12:30:39 PM PST 24
Finished Jan 03 12:31:43 PM PST 24
Peak memory 197484 kb
Host smart-9c7c0f37-40f6-4980-8523-3cd229aefe0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179241976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4179241976
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1622707220
Short name T476
Test name
Test status
Simulation time 54597490 ps
CPU time 1.2 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:30:44 PM PST 24
Peak memory 199200 kb
Host smart-861d3249-29ad-4da6-b123-323b621af9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622707220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1622707220
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.402225693
Short name T88
Test name
Test status
Simulation time 102998665 ps
CPU time 0.86 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:30:46 PM PST 24
Peak memory 198332 kb
Host smart-ae48b3dc-cde7-40ef-b930-4fdef83fc728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402225693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.402225693
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1833542590
Short name T424
Test name
Test status
Simulation time 108033810995 ps
CPU time 155.27 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 200144 kb
Host smart-f34f79b2-ee0c-4fd6-8a3e-832ac83558eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833542590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1833542590
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_intr.2551936321
Short name T560
Test name
Test status
Simulation time 1403577325743 ps
CPU time 2178.31 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 01:25:00 PM PST 24
Peak memory 200036 kb
Host smart-b8257372-88ed-4de8-9d3b-364a49a91a51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551936321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2551936321
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1272810415
Short name T1205
Test name
Test status
Simulation time 67222793363 ps
CPU time 542.11 seconds
Started Jan 03 12:48:08 PM PST 24
Finished Jan 03 12:57:39 PM PST 24
Peak memory 200212 kb
Host smart-d01c5e34-460d-49f9-8f5f-23336084762a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272810415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1272810415
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1505457520
Short name T519
Test name
Test status
Simulation time 1210442063 ps
CPU time 2.29 seconds
Started Jan 03 12:48:20 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 197672 kb
Host smart-3e07187c-7ab8-41a1-8a02-12e588a40e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505457520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1505457520
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2438800400
Short name T765
Test name
Test status
Simulation time 17595643210 ps
CPU time 8.09 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 194880 kb
Host smart-5722b7f5-0945-4d86-8639-fd37043834cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438800400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2438800400
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.822094434
Short name T980
Test name
Test status
Simulation time 22201314475 ps
CPU time 406.64 seconds
Started Jan 03 12:48:07 PM PST 24
Finished Jan 03 12:55:23 PM PST 24
Peak memory 200156 kb
Host smart-9096731b-ec08-490d-bfc3-b23069a12cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822094434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.822094434
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3984144107
Short name T632
Test name
Test status
Simulation time 2930933847 ps
CPU time 3.1 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 198636 kb
Host smart-e333569b-0f08-4194-9061-d48c8088eebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984144107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3984144107
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3318796013
Short name T810
Test name
Test status
Simulation time 161045569780 ps
CPU time 112.29 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 200116 kb
Host smart-1cebd39c-3a7f-48a6-be04-f625e4711807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318796013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3318796013
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2933531625
Short name T543
Test name
Test status
Simulation time 55900513986 ps
CPU time 44.18 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:49:29 PM PST 24
Peak memory 195748 kb
Host smart-8bf26611-9bfa-45d7-b2b7-33dc28d872cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933531625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2933531625
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2825517175
Short name T96
Test name
Test status
Simulation time 191820332 ps
CPU time 0.75 seconds
Started Jan 03 12:48:09 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 217736 kb
Host smart-70cc58d7-fc3a-43cd-9d5d-1abf7f6a2c53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825517175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2825517175
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2702507935
Short name T1013
Test name
Test status
Simulation time 109838248 ps
CPU time 0.97 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 198368 kb
Host smart-527714f6-9539-4eba-9f69-d8b529f28793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702507935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2702507935
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1536210835
Short name T457
Test name
Test status
Simulation time 106988135356 ps
CPU time 762.32 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 01:01:25 PM PST 24
Peak memory 214576 kb
Host smart-d8cd2380-751e-432f-a371-388b016b6e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536210835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1536210835
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.286347494
Short name T713
Test name
Test status
Simulation time 7354344862 ps
CPU time 11.29 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:49:10 PM PST 24
Peak memory 199640 kb
Host smart-ae11db71-31fe-492a-bc72-b10c18299440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286347494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.286347494
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.664057556
Short name T1031
Test name
Test status
Simulation time 104217153181 ps
CPU time 70.99 seconds
Started Jan 03 12:48:11 PM PST 24
Finished Jan 03 12:49:49 PM PST 24
Peak memory 200156 kb
Host smart-1164b665-1cb3-464c-ba4b-762327b0a83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664057556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.664057556
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.986809016
Short name T736
Test name
Test status
Simulation time 43946062 ps
CPU time 0.52 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 12:49:03 PM PST 24
Peak memory 195632 kb
Host smart-1321bf8a-fdbe-404f-8f53-84ba96206e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986809016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.986809016
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1955653407
Short name T1098
Test name
Test status
Simulation time 154485289288 ps
CPU time 86.89 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:50:17 PM PST 24
Peak memory 200160 kb
Host smart-2d5b5b8b-ae41-439d-9735-3e0a9a9189f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955653407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1955653407
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2659617970
Short name T740
Test name
Test status
Simulation time 35752191962 ps
CPU time 18.46 seconds
Started Jan 03 12:48:20 PM PST 24
Finished Jan 03 12:49:03 PM PST 24
Peak memory 200136 kb
Host smart-6635c8b2-f7db-4f38-9be1-92b51f47204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659617970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2659617970
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.186379586
Short name T643
Test name
Test status
Simulation time 243623116694 ps
CPU time 407.54 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:55:30 PM PST 24
Peak memory 200068 kb
Host smart-a1f21e3b-9c3e-4ddf-abf2-84b54c66220f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186379586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.186379586
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1995542194
Short name T928
Test name
Test status
Simulation time 94878857208 ps
CPU time 276.48 seconds
Started Jan 03 12:48:04 PM PST 24
Finished Jan 03 12:53:11 PM PST 24
Peak memory 200164 kb
Host smart-b7ac7a01-0628-4faf-bbfc-95ea8a03e699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995542194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1995542194
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.4108841180
Short name T1177
Test name
Test status
Simulation time 1905590008 ps
CPU time 0.98 seconds
Started Jan 03 12:48:09 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 195640 kb
Host smart-de636a92-1607-43f5-88b2-f147b30374a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108841180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.4108841180
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3936079590
Short name T990
Test name
Test status
Simulation time 45995036516 ps
CPU time 81.17 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:50:18 PM PST 24
Peak memory 197668 kb
Host smart-6037c732-9f53-4478-b870-a7d0e3282ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936079590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3936079590
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.3611908795
Short name T756
Test name
Test status
Simulation time 18754311555 ps
CPU time 935.64 seconds
Started Jan 03 12:48:06 PM PST 24
Finished Jan 03 01:04:12 PM PST 24
Peak memory 200172 kb
Host smart-bf151975-c4b1-4465-897f-44bfeed1f25a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611908795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3611908795
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.462866886
Short name T621
Test name
Test status
Simulation time 1339804066 ps
CPU time 2.12 seconds
Started Jan 03 12:48:05 PM PST 24
Finished Jan 03 12:48:38 PM PST 24
Peak memory 198376 kb
Host smart-517a0366-966e-44f7-9a37-4524990697d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462866886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.462866886
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.473838844
Short name T265
Test name
Test status
Simulation time 154287763280 ps
CPU time 33.08 seconds
Started Jan 03 12:48:11 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 199232 kb
Host smart-062a6bc3-54c4-400b-8f47-11cf198ad0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473838844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.473838844
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3985345945
Short name T1193
Test name
Test status
Simulation time 2512067166 ps
CPU time 1.71 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 195704 kb
Host smart-5873cb38-5494-4d3e-a913-ead3f98efd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985345945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3985345945
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3845436707
Short name T95
Test name
Test status
Simulation time 347395694 ps
CPU time 0.72 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:49:10 PM PST 24
Peak memory 217724 kb
Host smart-bba23f43-3a18-42aa-9fc2-c1da62d0a364
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845436707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3845436707
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4175958777
Short name T944
Test name
Test status
Simulation time 446077049 ps
CPU time 2.21 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 197992 kb
Host smart-b436d6f1-2af0-4a32-b1b4-2d750c09dfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175958777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4175958777
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.4160920826
Short name T964
Test name
Test status
Simulation time 433545519649 ps
CPU time 957 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 01:05:05 PM PST 24
Peak memory 200160 kb
Host smart-5d763a52-38d7-4838-820c-a57af5de508e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160920826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4160920826
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.707256896
Short name T801
Test name
Test status
Simulation time 74920804379 ps
CPU time 223.17 seconds
Started Jan 03 12:47:57 PM PST 24
Finished Jan 03 12:52:14 PM PST 24
Peak memory 216908 kb
Host smart-66499edd-8c41-4fed-bca6-de8a967ca8ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707256896 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.707256896
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3702220031
Short name T538
Test name
Test status
Simulation time 214152083 ps
CPU time 1.13 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:48:49 PM PST 24
Peak memory 197044 kb
Host smart-6ed2590f-0734-466b-9d46-c00d542b160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702220031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3702220031
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.305035940
Short name T955
Test name
Test status
Simulation time 38675399459 ps
CPU time 19.27 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:49:00 PM PST 24
Peak memory 200184 kb
Host smart-2be61c8f-f434-4318-90be-15d8b8826960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305035940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.305035940
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2259025639
Short name T561
Test name
Test status
Simulation time 12885902 ps
CPU time 0.53 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 194596 kb
Host smart-39f55ce9-2c1f-420d-9c26-5d81a09c6546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259025639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2259025639
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2603875824
Short name T101
Test name
Test status
Simulation time 29614921526 ps
CPU time 46.31 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:50:03 PM PST 24
Peak memory 200212 kb
Host smart-4cfa3168-964c-4847-a950-4c82655808b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603875824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2603875824
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3887363157
Short name T979
Test name
Test status
Simulation time 36690609047 ps
CPU time 6.86 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 198596 kb
Host smart-c46370cd-c705-4c50-8cff-522e25f9f237
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887363157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3887363157
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_loopback.865572979
Short name T530
Test name
Test status
Simulation time 103822080 ps
CPU time 0.84 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 195844 kb
Host smart-ec5e8ce5-5715-4eba-8975-2a22521100fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865572979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.865572979
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3100388646
Short name T1191
Test name
Test status
Simulation time 69980014318 ps
CPU time 116.69 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 199984 kb
Host smart-a0533aee-a6e6-4967-8886-720331da6bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100388646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3100388646
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.239478044
Short name T809
Test name
Test status
Simulation time 18314438700 ps
CPU time 83.03 seconds
Started Jan 03 12:48:42 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 200084 kb
Host smart-e1846164-dd65-402a-a3d4-12b5c182ad64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=239478044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.239478044
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1361309948
Short name T986
Test name
Test status
Simulation time 1278115454 ps
CPU time 13.03 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:48:54 PM PST 24
Peak memory 198432 kb
Host smart-58df434e-17c0-4041-be7c-5e03c0881b01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361309948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1361309948
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3266638762
Short name T709
Test name
Test status
Simulation time 5007877760 ps
CPU time 8.51 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 195872 kb
Host smart-194b57c7-8fd9-4554-9082-aec1abcacb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266638762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3266638762
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3881493274
Short name T502
Test name
Test status
Simulation time 847295859 ps
CPU time 3.08 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:52 PM PST 24
Peak memory 198540 kb
Host smart-7d213770-e538-4a59-80cc-6825b001727c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881493274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3881493274
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3102625818
Short name T684
Test name
Test status
Simulation time 24582045827 ps
CPU time 285.99 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:53:28 PM PST 24
Peak memory 211428 kb
Host smart-e494db9f-7e8d-4e9a-9693-08a13863e15b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102625818 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3102625818
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2482524952
Short name T526
Test name
Test status
Simulation time 1929079796 ps
CPU time 2.08 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:48:46 PM PST 24
Peak memory 198080 kb
Host smart-b6b23ee0-67d9-49d7-bffc-7e54a5a69b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482524952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2482524952
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2476246609
Short name T448
Test name
Test status
Simulation time 31079978382 ps
CPU time 56.43 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 200260 kb
Host smart-32edc11b-25d4-4987-89fe-73eedb811731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476246609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2476246609
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2415894894
Short name T698
Test name
Test status
Simulation time 113346698918 ps
CPU time 57.21 seconds
Started Jan 03 12:49:23 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 200124 kb
Host smart-3ef9a962-4421-4d6a-8197-bdf4ae73cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415894894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2415894894
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3308863944
Short name T1208
Test name
Test status
Simulation time 19878262218 ps
CPU time 28.35 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:50:04 PM PST 24
Peak memory 200148 kb
Host smart-c2cf33e9-e3b6-4a93-9848-f575a3ba3865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308863944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3308863944
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1651658991
Short name T121
Test name
Test status
Simulation time 131445413434 ps
CPU time 56.15 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 200172 kb
Host smart-ac9321d3-2f88-4d78-b9a8-7da9010d6dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651658991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1651658991
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1030031931
Short name T313
Test name
Test status
Simulation time 14260537352 ps
CPU time 10.91 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 199872 kb
Host smart-36104983-ebe7-4f1b-857a-a0517ec78f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030031931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1030031931
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3483500120
Short name T932
Test name
Test status
Simulation time 48585426 ps
CPU time 0.54 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 195568 kb
Host smart-0eff3219-2282-4f91-8cef-ba4ebcff8941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483500120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3483500120
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2689523666
Short name T705
Test name
Test status
Simulation time 128487729277 ps
CPU time 53.78 seconds
Started Jan 03 12:49:25 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 200144 kb
Host smart-fa9c7c57-012c-42a2-9714-adfef2059bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689523666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2689523666
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1019959440
Short name T997
Test name
Test status
Simulation time 57994620091 ps
CPU time 23.82 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:49:19 PM PST 24
Peak memory 199540 kb
Host smart-a01396cc-e282-4c78-af4b-394760b27f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019959440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1019959440
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3815884511
Short name T946
Test name
Test status
Simulation time 44669847012 ps
CPU time 17.34 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:04 PM PST 24
Peak memory 200116 kb
Host smart-eaa37c7a-d641-4218-8a9a-bdf5a9d90baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815884511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3815884511
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1136747062
Short name T594
Test name
Test status
Simulation time 179322423659 ps
CPU time 487.92 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:57:06 PM PST 24
Peak memory 199948 kb
Host smart-581f5678-80b3-44d7-a1a4-ee60ea2fd6ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136747062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1136747062
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.121174031
Short name T1214
Test name
Test status
Simulation time 214209591412 ps
CPU time 200.14 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:52:33 PM PST 24
Peak memory 200128 kb
Host smart-afc67097-cfee-4145-8aaf-6da8bfb2acc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=121174031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.121174031
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.4250080484
Short name T501
Test name
Test status
Simulation time 4915326069 ps
CPU time 2.86 seconds
Started Jan 03 12:49:11 PM PST 24
Finished Jan 03 12:49:31 PM PST 24
Peak memory 197408 kb
Host smart-b097db56-48fa-436c-a43e-147067aa7599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250080484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.4250080484
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2479457464
Short name T581
Test name
Test status
Simulation time 14808383194 ps
CPU time 20.57 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:49:00 PM PST 24
Peak memory 194944 kb
Host smart-310f9c17-e9bb-4a96-9301-f9ef9bc304dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479457464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2479457464
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3304331431
Short name T283
Test name
Test status
Simulation time 4349813367 ps
CPU time 255.07 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:53:00 PM PST 24
Peak memory 200172 kb
Host smart-a078625f-66c9-41f8-bee8-b627b025a552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3304331431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3304331431
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3612116480
Short name T1188
Test name
Test status
Simulation time 2595030103 ps
CPU time 18.27 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 198148 kb
Host smart-00e33d6d-953c-4aeb-9942-3d0d10dfaf50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3612116480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3612116480
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1000147630
Short name T509
Test name
Test status
Simulation time 139209827722 ps
CPU time 324.29 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:54:19 PM PST 24
Peak memory 200116 kb
Host smart-20ca9c74-17b2-44a1-b5db-32ccbde0fdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000147630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1000147630
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2096089835
Short name T18
Test name
Test status
Simulation time 2239607864 ps
CPU time 3.73 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:48:50 PM PST 24
Peak memory 195728 kb
Host smart-29695342-f3e2-42e7-aac7-603731eff2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096089835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2096089835
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1164653609
Short name T656
Test name
Test status
Simulation time 6202226115 ps
CPU time 12.65 seconds
Started Jan 03 12:48:39 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 199360 kb
Host smart-a540e9dc-7336-46e0-81c4-5957b3bb39ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164653609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1164653609
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.253136205
Short name T76
Test name
Test status
Simulation time 92592528427 ps
CPU time 252.33 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:53:23 PM PST 24
Peak memory 216872 kb
Host smart-b0faf19c-6e58-4533-899c-d24d00bc5626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253136205 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.253136205
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2814780321
Short name T1147
Test name
Test status
Simulation time 1540896377 ps
CPU time 2.49 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:48:48 PM PST 24
Peak memory 198560 kb
Host smart-4faf217f-642d-4e1d-a0b6-f0645694eac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814780321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2814780321
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2677248593
Short name T603
Test name
Test status
Simulation time 11682604042 ps
CPU time 2.44 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 199336 kb
Host smart-97fcee78-b59a-4d32-9605-3114cb4b4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677248593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2677248593
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3442883101
Short name T978
Test name
Test status
Simulation time 32621397757 ps
CPU time 15.37 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 198224 kb
Host smart-a7edc8ef-9072-49b7-8f02-5a595d2a3b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442883101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3442883101
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3277647540
Short name T1152
Test name
Test status
Simulation time 49688138055 ps
CPU time 68.49 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 200056 kb
Host smart-2fd667de-1901-43eb-9ca2-efae09d42776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277647540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3277647540
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3265366783
Short name T1106
Test name
Test status
Simulation time 25964698516 ps
CPU time 43.4 seconds
Started Jan 03 12:49:33 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 199424 kb
Host smart-528435df-a57f-4ea8-90b2-f9bea999b28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265366783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3265366783
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1425263260
Short name T1040
Test name
Test status
Simulation time 14030770188 ps
CPU time 22.17 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:59 PM PST 24
Peak memory 199244 kb
Host smart-d550cee3-dcbe-4b09-83b1-b25e5066f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425263260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1425263260
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2229565717
Short name T1145
Test name
Test status
Simulation time 24972823202 ps
CPU time 11.64 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 200048 kb
Host smart-45066acf-2e0e-4e72-bcb5-e90e8da74a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229565717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2229565717
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.176580538
Short name T252
Test name
Test status
Simulation time 22289838399 ps
CPU time 34.71 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 12:50:19 PM PST 24
Peak memory 200168 kb
Host smart-d2399b51-9c6e-4cfd-a6dd-47469341658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176580538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.176580538
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1358894741
Short name T831
Test name
Test status
Simulation time 50385447003 ps
CPU time 90.65 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:51:36 PM PST 24
Peak memory 200212 kb
Host smart-fd8fe49f-a984-41fd-a794-a233314096c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358894741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1358894741
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.963331307
Short name T1045
Test name
Test status
Simulation time 44072617738 ps
CPU time 80.94 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 199812 kb
Host smart-6e1af0f2-d524-4a28-8426-52b967cb6e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963331307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.963331307
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3321963852
Short name T90
Test name
Test status
Simulation time 45430375 ps
CPU time 0.54 seconds
Started Jan 03 12:49:04 PM PST 24
Finished Jan 03 12:49:24 PM PST 24
Peak memory 195600 kb
Host smart-984d98c0-cf88-4102-a4cb-71daa4bbcaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321963852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3321963852
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.710534994
Short name T752
Test name
Test status
Simulation time 101445135235 ps
CPU time 26.83 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 200112 kb
Host smart-2656b085-eb45-4948-954c-d0a2c9b9ab65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710534994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.710534994
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2356362142
Short name T1166
Test name
Test status
Simulation time 5289224965 ps
CPU time 7.73 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:49:06 PM PST 24
Peak memory 198212 kb
Host smart-e47bf643-8d06-456e-bde0-354b962d42e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356362142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2356362142
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1051861857
Short name T1171
Test name
Test status
Simulation time 1756756925795 ps
CPU time 702.51 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 01:00:52 PM PST 24
Peak memory 198936 kb
Host smart-30fb7834-55a2-40a2-8416-712698d569f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051861857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1051861857
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.181314216
Short name T103
Test name
Test status
Simulation time 369006413967 ps
CPU time 315.22 seconds
Started Jan 03 12:49:01 PM PST 24
Finished Jan 03 12:54:37 PM PST 24
Peak memory 200268 kb
Host smart-03ee6f41-f762-40ac-b45f-8d75b514ea92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181314216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.181314216
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2801713574
Short name T1060
Test name
Test status
Simulation time 1321949169 ps
CPU time 2.34 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 195452 kb
Host smart-38b84c36-c3e7-4348-b311-7e06620b0fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801713574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2801713574
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2452900619
Short name T616
Test name
Test status
Simulation time 149694191632 ps
CPU time 225.93 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 12:53:01 PM PST 24
Peak memory 200068 kb
Host smart-cba6a008-7c87-4eaf-bf0f-46b7a0b8dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452900619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2452900619
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.699822192
Short name T255
Test name
Test status
Simulation time 15874320253 ps
CPU time 114.14 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:50:49 PM PST 24
Peak memory 200208 kb
Host smart-492e7606-7acb-423b-bd3b-ab98a53aa06e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699822192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.699822192
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2987771237
Short name T668
Test name
Test status
Simulation time 126593233 ps
CPU time 0.74 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 195588 kb
Host smart-817a7115-6767-4d43-bc57-32f82206549a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987771237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2987771237
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3850664066
Short name T937
Test name
Test status
Simulation time 2688898823 ps
CPU time 1.82 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:06 PM PST 24
Peak memory 195620 kb
Host smart-c863abe0-6a5f-42c6-b7f8-970635b8959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850664066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3850664066
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3304928393
Short name T689
Test name
Test status
Simulation time 712374858 ps
CPU time 4.13 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:49:15 PM PST 24
Peak memory 198116 kb
Host smart-5e8c40b5-7d2d-4a5e-b756-6a1fc46ab672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304928393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3304928393
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1406570803
Short name T828
Test name
Test status
Simulation time 195975194678 ps
CPU time 1780.19 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 01:18:46 PM PST 24
Peak memory 200204 kb
Host smart-fe17d642-6205-4d44-bb72-d2bef1c4e2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406570803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1406570803
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3430003003
Short name T940
Test name
Test status
Simulation time 87053637485 ps
CPU time 965.03 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 01:05:08 PM PST 24
Peak memory 216704 kb
Host smart-762be3f8-3864-4bd6-9c61-a42e8f79cefe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430003003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3430003003
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.337115832
Short name T631
Test name
Test status
Simulation time 366655902 ps
CPU time 1.56 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:52 PM PST 24
Peak memory 198420 kb
Host smart-d8f7976e-30f2-4541-ae9f-a990df037dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337115832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.337115832
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.175759060
Short name T966
Test name
Test status
Simulation time 65254075863 ps
CPU time 24.93 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:49:20 PM PST 24
Peak memory 197808 kb
Host smart-37c953ff-d318-4906-ba59-7b67d2a05123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175759060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.175759060
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.637674766
Short name T933
Test name
Test status
Simulation time 50120096442 ps
CPU time 36.89 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 198140 kb
Host smart-c76dfc34-fc9f-4a2f-a79d-65e0019869f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637674766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.637674766
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1452085986
Short name T1131
Test name
Test status
Simulation time 96315218133 ps
CPU time 42.31 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 199236 kb
Host smart-7a0fb437-5abb-4f56-a7a2-79a6d4927689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452085986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1452085986
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.352887993
Short name T648
Test name
Test status
Simulation time 90446108887 ps
CPU time 52.6 seconds
Started Jan 03 12:49:21 PM PST 24
Finished Jan 03 12:50:31 PM PST 24
Peak memory 200120 kb
Host smart-1cbda35d-0e52-45d8-8605-83e7c6428825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352887993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.352887993
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1857551143
Short name T872
Test name
Test status
Simulation time 25430443064 ps
CPU time 22.18 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 200072 kb
Host smart-c1d6a508-c6e4-47c3-8e1a-2668615aab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857551143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1857551143
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1753672175
Short name T836
Test name
Test status
Simulation time 218815325762 ps
CPU time 44.55 seconds
Started Jan 03 12:50:04 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 199576 kb
Host smart-3c0ff29a-b962-4329-aaf3-09aadd8bbe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753672175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1753672175
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3207023337
Short name T280
Test name
Test status
Simulation time 33502348758 ps
CPU time 18.52 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 12:50:05 PM PST 24
Peak memory 200228 kb
Host smart-7613360a-5bda-4785-a730-1e2fb51d4470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207023337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3207023337
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1876562982
Short name T182
Test name
Test status
Simulation time 61361967311 ps
CPU time 23.32 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 199968 kb
Host smart-a165b26d-ba1f-46aa-a02a-0b9e3b8ddf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876562982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1876562982
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2054150628
Short name T1081
Test name
Test status
Simulation time 48807001 ps
CPU time 0.53 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:49 PM PST 24
Peak memory 195616 kb
Host smart-d069c25a-65a9-4f8a-8227-853a5720816a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054150628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2054150628
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3137623370
Short name T712
Test name
Test status
Simulation time 73505978597 ps
CPU time 18.34 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:49:24 PM PST 24
Peak memory 199160 kb
Host smart-e893b0cf-7b5f-43ed-a456-90a3d70b6e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137623370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3137623370
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1640524983
Short name T427
Test name
Test status
Simulation time 41449356643 ps
CPU time 36.16 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:41 PM PST 24
Peak memory 200092 kb
Host smart-08a01a45-1a21-4cb2-a7ac-191b6a9409ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640524983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1640524983
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.2375611707
Short name T681
Test name
Test status
Simulation time 825793123509 ps
CPU time 140.93 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:51:21 PM PST 24
Peak memory 199252 kb
Host smart-b479e29c-a38c-48b8-9487-5e9c90c4fc9a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375611707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2375611707
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1985035488
Short name T1220
Test name
Test status
Simulation time 162430493662 ps
CPU time 320.79 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:54:29 PM PST 24
Peak memory 200168 kb
Host smart-60414893-a176-41a5-b477-5498145bc3a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985035488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1985035488
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3156529340
Short name T925
Test name
Test status
Simulation time 2141829062 ps
CPU time 4.37 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:48:59 PM PST 24
Peak memory 197364 kb
Host smart-653ac086-589a-4cc2-a19a-da7f0b3f0f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156529340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3156529340
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.970296478
Short name T1209
Test name
Test status
Simulation time 152324439576 ps
CPU time 37.03 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:49:22 PM PST 24
Peak memory 208680 kb
Host smart-e2965133-099a-49c6-8586-093d6ea19b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970296478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.970296478
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.4207884979
Short name T714
Test name
Test status
Simulation time 12773072231 ps
CPU time 156.24 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:51:23 PM PST 24
Peak memory 200092 kb
Host smart-8a567bca-a036-4694-a51f-84f4065e1a0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207884979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4207884979
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4217846430
Short name T951
Test name
Test status
Simulation time 2525030453 ps
CPU time 4.38 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:53 PM PST 24
Peak memory 198524 kb
Host smart-739bbfd9-c69c-42d1-974d-1e454524cd80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217846430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4217846430
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3499500651
Short name T975
Test name
Test status
Simulation time 65668738488 ps
CPU time 29.98 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:49:23 PM PST 24
Peak memory 200068 kb
Host smart-50eb073c-fd9c-4534-b551-7805015546b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499500651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3499500651
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2860803142
Short name T438
Test name
Test status
Simulation time 41315727912 ps
CPU time 32.56 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:49:19 PM PST 24
Peak memory 195968 kb
Host smart-6572e068-f1a7-4897-bedf-599e4d4d3557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860803142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2860803142
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1541964436
Short name T768
Test name
Test status
Simulation time 5490547409 ps
CPU time 24.92 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 199572 kb
Host smart-0896dd4c-1084-4fe3-afaa-0692e1876c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541964436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1541964436
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1745477992
Short name T853
Test name
Test status
Simulation time 189005735754 ps
CPU time 547.12 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:58:16 PM PST 24
Peak memory 216628 kb
Host smart-4b9b9394-9bc9-402d-9ce2-0d63c213ec5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745477992 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1745477992
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.658593606
Short name T811
Test name
Test status
Simulation time 1175541094 ps
CPU time 1.77 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 198328 kb
Host smart-f17424df-0f9b-4312-94a1-671119828f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658593606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.658593606
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.629772418
Short name T1187
Test name
Test status
Simulation time 40314834491 ps
CPU time 16.86 seconds
Started Jan 03 12:48:52 PM PST 24
Finished Jan 03 12:49:31 PM PST 24
Peak memory 197400 kb
Host smart-073728af-da1b-4c05-ab4e-f9c16506facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629772418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.629772418
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3742960139
Short name T272
Test name
Test status
Simulation time 41463916849 ps
CPU time 65.03 seconds
Started Jan 03 12:49:52 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 200080 kb
Host smart-9134795c-cdd8-459d-8ca8-d73117456c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742960139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3742960139
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2640373122
Short name T144
Test name
Test status
Simulation time 150153134321 ps
CPU time 228.94 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:53:38 PM PST 24
Peak memory 200068 kb
Host smart-8c59d117-e92c-487b-a950-1254d0d47ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640373122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2640373122
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3344201273
Short name T154
Test name
Test status
Simulation time 70487903628 ps
CPU time 53.78 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:51:36 PM PST 24
Peak memory 200092 kb
Host smart-90ef6e6a-747d-44bc-b48b-57109a5dea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344201273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3344201273
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2752182957
Short name T243
Test name
Test status
Simulation time 41003363963 ps
CPU time 16.79 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 199816 kb
Host smart-dee14845-48cb-4ed8-aa78-7ab220f71190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752182957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2752182957
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1652030167
Short name T513
Test name
Test status
Simulation time 158927344164 ps
CPU time 13.64 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 199916 kb
Host smart-a54fdcd9-4073-4ed0-b48f-ec6e3ff19952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652030167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1652030167
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.433285979
Short name T270
Test name
Test status
Simulation time 7251368680 ps
CPU time 11.68 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:04 PM PST 24
Peak memory 198884 kb
Host smart-443ab9d8-0b1a-4742-a72a-129b330b997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433285979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.433285979
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3208507899
Short name T790
Test name
Test status
Simulation time 10948928 ps
CPU time 0.55 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 194736 kb
Host smart-7c3c4187-079d-490f-9ba3-69129e9ad7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208507899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3208507899
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.452210515
Short name T717
Test name
Test status
Simulation time 20895928032 ps
CPU time 17.48 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 12:49:20 PM PST 24
Peak memory 200088 kb
Host smart-242fe555-0c55-42ad-9348-21be6cc26a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452210515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.452210515
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2648556473
Short name T363
Test name
Test status
Simulation time 285830790688 ps
CPU time 173.31 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:51:37 PM PST 24
Peak memory 200116 kb
Host smart-f8abd315-e2a2-45da-b330-88f378731eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648556473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2648556473
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.3785420617
Short name T761
Test name
Test status
Simulation time 41695419006 ps
CPU time 75.14 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:49:56 PM PST 24
Peak memory 198604 kb
Host smart-9ad623e6-c3f7-42dd-badf-50ee92ab5004
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785420617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3785420617
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2838204026
Short name T1120
Test name
Test status
Simulation time 80016862910 ps
CPU time 252.96 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:53:23 PM PST 24
Peak memory 200208 kb
Host smart-906ab1bb-87bb-455f-92c6-2585a0c32948
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838204026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2838204026
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1248414897
Short name T529
Test name
Test status
Simulation time 921491830 ps
CPU time 1.13 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 12:49:24 PM PST 24
Peak memory 197208 kb
Host smart-9fcf3ce0-62a0-4529-becb-6c521a1e642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248414897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1248414897
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.58687763
Short name T887
Test name
Test status
Simulation time 44650358507 ps
CPU time 69.86 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:50:08 PM PST 24
Peak memory 198824 kb
Host smart-211b7b13-ee49-4183-b2fd-5d676374b639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58687763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.58687763
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3555577891
Short name T1050
Test name
Test status
Simulation time 6024299325 ps
CPU time 60.83 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:49:59 PM PST 24
Peak memory 200176 kb
Host smart-7426d9ac-8d03-4014-8135-1b5dad164be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3555577891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3555577891
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4050280978
Short name T1174
Test name
Test status
Simulation time 1375005286 ps
CPU time 5.27 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:48:49 PM PST 24
Peak memory 198396 kb
Host smart-a140ab4f-da42-4904-9468-3d1ce5fd0b21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050280978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4050280978
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2218955667
Short name T1025
Test name
Test status
Simulation time 91170177151 ps
CPU time 136.21 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:51:14 PM PST 24
Peak memory 200072 kb
Host smart-3a29cc36-dcf4-4449-81f9-0ef480561516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218955667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2218955667
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.305974686
Short name T780
Test name
Test status
Simulation time 3505106463 ps
CPU time 2.1 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 12:49:08 PM PST 24
Peak memory 195972 kb
Host smart-5398a8cb-4bad-474d-8f8c-9d64d4b34656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305974686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.305974686
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1002045320
Short name T584
Test name
Test status
Simulation time 702163133 ps
CPU time 1.97 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 198216 kb
Host smart-9bedf3aa-a1d9-48a6-948f-7225856d9463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002045320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1002045320
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.563736053
Short name T1023
Test name
Test status
Simulation time 158496061542 ps
CPU time 90.77 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:50:24 PM PST 24
Peak memory 200460 kb
Host smart-da1478bb-7252-4ece-b351-ec237cbd8a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563736053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.563736053
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4218519000
Short name T29
Test name
Test status
Simulation time 6592000761 ps
CPU time 9.14 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 199404 kb
Host smart-aa5c276b-e510-4c28-974d-d714df39441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218519000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4218519000
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4060863287
Short name T521
Test name
Test status
Simulation time 12921096976 ps
CPU time 5.34 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:48 PM PST 24
Peak memory 199580 kb
Host smart-c0f58897-a04f-4f91-9ecb-18351d0f58b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060863287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4060863287
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.710985300
Short name T320
Test name
Test status
Simulation time 31204868265 ps
CPU time 13.2 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:50:05 PM PST 24
Peak memory 200228 kb
Host smart-4846a4aa-63eb-45d8-858a-18d5bf5f1aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710985300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.710985300
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.316572307
Short name T664
Test name
Test status
Simulation time 27313177685 ps
CPU time 18.46 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 200120 kb
Host smart-f9907114-9d0e-46e7-8852-ddb52bcdbcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316572307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.316572307
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3888090832
Short name T920
Test name
Test status
Simulation time 115773996851 ps
CPU time 94.16 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:51:27 PM PST 24
Peak memory 200052 kb
Host smart-66dfb1f5-7252-4faa-ab14-933f7a63ad57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888090832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3888090832
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2556496970
Short name T116
Test name
Test status
Simulation time 73482923712 ps
CPU time 105.69 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:52:03 PM PST 24
Peak memory 200124 kb
Host smart-aed7516e-2b81-4b3b-b4f7-af101d26c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556496970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2556496970
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2442414974
Short name T353
Test name
Test status
Simulation time 301280701857 ps
CPU time 140.25 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:52:40 PM PST 24
Peak memory 200156 kb
Host smart-ea87d38f-6568-4b62-ab0a-74a693160d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442414974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2442414974
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2966836819
Short name T106
Test name
Test status
Simulation time 209968033969 ps
CPU time 66.93 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 199444 kb
Host smart-bee8bd97-661f-49ac-a378-cfd668247a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966836819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2966836819
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2303412624
Short name T246
Test name
Test status
Simulation time 19075538401 ps
CPU time 34.2 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 200040 kb
Host smart-d733eff1-5d03-4de4-bf63-e02144559096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303412624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2303412624
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2063628764
Short name T1035
Test name
Test status
Simulation time 56429529694 ps
CPU time 127.62 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:52:31 PM PST 24
Peak memory 199992 kb
Host smart-cada1b8b-8840-4f3d-a97c-367a4ce6da20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063628764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2063628764
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4148128517
Short name T316
Test name
Test status
Simulation time 16100970412 ps
CPU time 23.43 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 199828 kb
Host smart-fc2708eb-b726-443a-9f01-4f834daa533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148128517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4148128517
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2547386375
Short name T860
Test name
Test status
Simulation time 13778358 ps
CPU time 0.53 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:48:53 PM PST 24
Peak memory 195588 kb
Host smart-8c03cb6d-4b1e-4207-9cc3-05e15e8472f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547386375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2547386375
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2063879720
Short name T348
Test name
Test status
Simulation time 89531347685 ps
CPU time 12.57 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:49:23 PM PST 24
Peak memory 200220 kb
Host smart-ebe50378-4ce2-4140-804c-db0a40f7745b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063879720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2063879720
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.4022449380
Short name T300
Test name
Test status
Simulation time 122172843383 ps
CPU time 54.35 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:49:55 PM PST 24
Peak memory 200136 kb
Host smart-b474400c-54a4-40d0-aa7c-ce7c1a111def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022449380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4022449380
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.3100769013
Short name T879
Test name
Test status
Simulation time 1624446885422 ps
CPU time 2706.99 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 01:34:30 PM PST 24
Peak memory 199648 kb
Host smart-baaba777-9fbe-405a-a325-9f628b23dbea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100769013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3100769013
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.30634589
Short name T701
Test name
Test status
Simulation time 112585448163 ps
CPU time 306.35 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:54:05 PM PST 24
Peak memory 200200 kb
Host smart-79f57d80-fa0c-418a-a990-d18ffd39fea3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30634589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.30634589
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_noise_filter.677235401
Short name T571
Test name
Test status
Simulation time 99688002931 ps
CPU time 47.11 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:49:53 PM PST 24
Peak memory 208556 kb
Host smart-6065ddfd-f648-4e27-9c7d-271eb33c76f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677235401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.677235401
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3269971948
Short name T110
Test name
Test status
Simulation time 17480611489 ps
CPU time 996.11 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 01:05:46 PM PST 24
Peak memory 200184 kb
Host smart-bfeb3b49-999a-48eb-a20a-69d403e542ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269971948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3269971948
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3134946098
Short name T838
Test name
Test status
Simulation time 5394633671 ps
CPU time 21 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 12:49:24 PM PST 24
Peak memory 198384 kb
Host smart-d8ffe32c-27b7-48a7-af15-dd9fc9922519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134946098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3134946098
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3139050727
Short name T956
Test name
Test status
Simulation time 103513075489 ps
CPU time 81.34 seconds
Started Jan 03 12:48:20 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 200092 kb
Host smart-85a1997e-4021-4f05-b4e5-2f26cc656f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139050727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3139050727
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.4185972903
Short name T1212
Test name
Test status
Simulation time 29730264922 ps
CPU time 10.66 seconds
Started Jan 03 12:48:52 PM PST 24
Finished Jan 03 12:49:25 PM PST 24
Peak memory 195556 kb
Host smart-4d34c0a9-e262-47e1-b591-cb791882f1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185972903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.4185972903
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3530169951
Short name T747
Test name
Test status
Simulation time 441351049 ps
CPU time 1.97 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:48:57 PM PST 24
Peak memory 199104 kb
Host smart-d9266842-4bea-4851-8d45-b0a308f0a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530169951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3530169951
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.226533958
Short name T392
Test name
Test status
Simulation time 233859911295 ps
CPU time 194.92 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:52:27 PM PST 24
Peak memory 200200 kb
Host smart-99801db5-5e9d-4823-adee-6ab954f1fbf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226533958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.226533958
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1945950987
Short name T523
Test name
Test status
Simulation time 663183965 ps
CPU time 1.29 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:49:10 PM PST 24
Peak memory 198276 kb
Host smart-eb987431-0969-418d-b111-53e2cf7510c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945950987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1945950987
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1479612479
Short name T553
Test name
Test status
Simulation time 1829331846 ps
CPU time 0.76 seconds
Started Jan 03 12:48:52 PM PST 24
Finished Jan 03 12:49:14 PM PST 24
Peak memory 195336 kb
Host smart-24d50e92-a151-4179-bac3-dfd11e058c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479612479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1479612479
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3115026029
Short name T358
Test name
Test status
Simulation time 105977615635 ps
CPU time 42.92 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 200100 kb
Host smart-62797481-c34e-4709-a0dc-8eabebf867a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115026029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3115026029
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3365405551
Short name T285
Test name
Test status
Simulation time 39032027663 ps
CPU time 35.15 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:50:02 PM PST 24
Peak memory 200176 kb
Host smart-629839a2-ae7b-4033-9a92-312597461000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365405551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3365405551
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3223378831
Short name T149
Test name
Test status
Simulation time 42068797181 ps
CPU time 22.84 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:50:16 PM PST 24
Peak memory 200060 kb
Host smart-a2a0245a-aa55-4eb1-80ba-548bc6f883e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223378831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3223378831
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.669227781
Short name T852
Test name
Test status
Simulation time 20860360237 ps
CPU time 15.69 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:49:51 PM PST 24
Peak memory 198952 kb
Host smart-d8d2b084-dc81-4c46-925b-9f751ec3636f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669227781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.669227781
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2655658745
Short name T818
Test name
Test status
Simulation time 25360474192 ps
CPU time 11.54 seconds
Started Jan 03 12:49:33 PM PST 24
Finished Jan 03 12:50:00 PM PST 24
Peak memory 199016 kb
Host smart-2262ff9e-f078-41b4-9b4a-cfb5871a9ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655658745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2655658745
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.985294072
Short name T129
Test name
Test status
Simulation time 22697734875 ps
CPU time 45.73 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 200052 kb
Host smart-60422d8d-a712-4a06-bf0c-1be1d97f9be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985294072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.985294072
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2767690366
Short name T767
Test name
Test status
Simulation time 47561014121 ps
CPU time 39.76 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 200160 kb
Host smart-b154be46-64a1-485f-8852-72c34e63c1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767690366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2767690366
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1237730815
Short name T327
Test name
Test status
Simulation time 82916609389 ps
CPU time 11.53 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:50:03 PM PST 24
Peak memory 199692 kb
Host smart-332d60a9-32d6-4aad-9d55-849bb3363a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237730815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1237730815
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1512762519
Short name T739
Test name
Test status
Simulation time 7010682681 ps
CPU time 5.9 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 198748 kb
Host smart-cc5ba4a2-bf71-43f2-8954-c5cb8fafc7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512762519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1512762519
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2816284049
Short name T912
Test name
Test status
Simulation time 37382865 ps
CPU time 0.51 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 194500 kb
Host smart-5bcb6207-14e5-4b6b-bd8f-0b7df6899ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816284049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2816284049
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1122871769
Short name T351
Test name
Test status
Simulation time 31807306486 ps
CPU time 53.99 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:49:39 PM PST 24
Peak memory 200032 kb
Host smart-817cb5e0-4a09-43ac-aba6-0b11eaabeddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122871769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1122871769
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.610070277
Short name T593
Test name
Test status
Simulation time 84199707373 ps
CPU time 137.51 seconds
Started Jan 03 12:48:35 PM PST 24
Finished Jan 03 12:51:18 PM PST 24
Peak memory 199480 kb
Host smart-63ca9a66-7272-46cc-98fe-0357f0873331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610070277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.610070277
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3007977855
Short name T759
Test name
Test status
Simulation time 59566625625 ps
CPU time 51.23 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:49:48 PM PST 24
Peak memory 200124 kb
Host smart-e0668dc0-9c5f-43c6-9212-b4c3a4ec0a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007977855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3007977855
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.522943744
Short name T27
Test name
Test status
Simulation time 305332753570 ps
CPU time 498 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:57:19 PM PST 24
Peak memory 200112 kb
Host smart-83e5d6ad-a95d-44c1-a832-3b8042260b1b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522943744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.522943744
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.303485804
Short name T533
Test name
Test status
Simulation time 104379579842 ps
CPU time 436.91 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:56:03 PM PST 24
Peak memory 200076 kb
Host smart-496e50ac-2bc1-474d-be88-c403fcaa235e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303485804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.303485804
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3055391660
Short name T779
Test name
Test status
Simulation time 5532166997 ps
CPU time 5.66 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:49:19 PM PST 24
Peak memory 197520 kb
Host smart-13e5c0ea-fcb7-4b2a-9d88-0933e4c7420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055391660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3055391660
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2577710770
Short name T934
Test name
Test status
Simulation time 57447600121 ps
CPU time 12.57 seconds
Started Jan 03 12:48:35 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 196696 kb
Host smart-9479d5a9-6686-40b7-b1d7-75add301b050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577710770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2577710770
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3263669332
Short name T540
Test name
Test status
Simulation time 19346062432 ps
CPU time 1050.67 seconds
Started Jan 03 12:48:51 PM PST 24
Finished Jan 03 01:06:44 PM PST 24
Peak memory 200236 kb
Host smart-b966ab9f-9962-48b2-bf49-f803aaf647d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263669332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3263669332
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2031142703
Short name T1039
Test name
Test status
Simulation time 3627641627 ps
CPU time 14.56 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:49:01 PM PST 24
Peak memory 198656 kb
Host smart-de039254-1c75-4946-9a91-984815c5b166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031142703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2031142703
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3358861578
Short name T1083
Test name
Test status
Simulation time 23408747630 ps
CPU time 24.01 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:49:20 PM PST 24
Peak memory 200056 kb
Host smart-b7c454e2-4fc3-4dd4-8ac2-30c9b2043b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358861578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3358861578
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.249902714
Short name T799
Test name
Test status
Simulation time 1470078575 ps
CPU time 1.17 seconds
Started Jan 03 12:48:34 PM PST 24
Finished Jan 03 12:49:01 PM PST 24
Peak memory 195496 kb
Host smart-1536c8d5-20d6-4588-b391-c581c4e75e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249902714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.249902714
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.335734758
Short name T451
Test name
Test status
Simulation time 426282575 ps
CPU time 2.2 seconds
Started Jan 03 12:48:35 PM PST 24
Finished Jan 03 12:49:03 PM PST 24
Peak memory 199520 kb
Host smart-a5262207-749e-414f-8195-fb146a46f8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335734758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.335734758
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1517697045
Short name T753
Test name
Test status
Simulation time 162267359832 ps
CPU time 709.21 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 01:00:32 PM PST 24
Peak memory 200132 kb
Host smart-72bc6de7-2ca0-481d-b3cb-012b85b57b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517697045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1517697045
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3164704837
Short name T692
Test name
Test status
Simulation time 47302923258 ps
CPU time 538.38 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:58:09 PM PST 24
Peak memory 216192 kb
Host smart-68f83e12-0154-44df-aa8b-5c22a640bb6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164704837 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3164704837
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1004280330
Short name T411
Test name
Test status
Simulation time 14404544175 ps
CPU time 19.87 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 199972 kb
Host smart-1019e105-477b-4276-8053-f3c2d3998531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004280330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1004280330
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1551413071
Short name T125
Test name
Test status
Simulation time 100862437349 ps
CPU time 42.6 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 200176 kb
Host smart-13ac90a0-5ae5-43e2-a964-518597d83619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551413071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1551413071
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.263735521
Short name T254
Test name
Test status
Simulation time 61589874560 ps
CPU time 17.69 seconds
Started Jan 03 12:49:29 PM PST 24
Finished Jan 03 12:50:03 PM PST 24
Peak memory 199884 kb
Host smart-cc15b806-d2c9-4c95-862f-73901dda4388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263735521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.263735521
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3397419199
Short name T902
Test name
Test status
Simulation time 115783197018 ps
CPU time 48 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 200216 kb
Host smart-c41e6dab-2982-4497-be00-48ebb551f0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397419199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3397419199
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2327206956
Short name T707
Test name
Test status
Simulation time 58069661809 ps
CPU time 24.34 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:18 PM PST 24
Peak memory 200048 kb
Host smart-48e3f81d-1ad0-4670-9a9f-ef7794036f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327206956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2327206956
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2896294149
Short name T1000
Test name
Test status
Simulation time 38029113241 ps
CPU time 19.34 seconds
Started Jan 03 12:49:28 PM PST 24
Finished Jan 03 12:50:05 PM PST 24
Peak memory 200180 kb
Host smart-089863df-b876-4af2-8551-3b21255b145e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896294149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2896294149
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3166170824
Short name T856
Test name
Test status
Simulation time 113535551064 ps
CPU time 185.86 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:53:05 PM PST 24
Peak memory 200136 kb
Host smart-ac283c6b-fe2b-4a37-914b-f2cdcfe43a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166170824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3166170824
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2100731315
Short name T347
Test name
Test status
Simulation time 36356260370 ps
CPU time 20.95 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:50:33 PM PST 24
Peak memory 198372 kb
Host smart-a4bd2b39-154c-4655-9959-db55f5983c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100731315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2100731315
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4121510493
Short name T112
Test name
Test status
Simulation time 140878121350 ps
CPU time 62.83 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 200124 kb
Host smart-1f751e27-b79a-40b4-83ac-60b578727ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121510493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4121510493
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2647009390
Short name T1037
Test name
Test status
Simulation time 42589527 ps
CPU time 0.53 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 195600 kb
Host smart-ffb43298-4d0c-4f6d-8a6a-a5b7cf806e2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647009390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2647009390
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3099716664
Short name T849
Test name
Test status
Simulation time 16323907160 ps
CPU time 27.84 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 199952 kb
Host smart-b95f5d43-3ce7-461f-8e13-13bf725401b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099716664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3099716664
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2731393616
Short name T346
Test name
Test status
Simulation time 128167365822 ps
CPU time 45 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:49:44 PM PST 24
Peak memory 199960 kb
Host smart-dd058e70-822c-4474-9322-b67dedaa859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731393616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2731393616
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2234594176
Short name T1124
Test name
Test status
Simulation time 79880874680 ps
CPU time 21.02 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:49:01 PM PST 24
Peak memory 200096 kb
Host smart-eedcd585-66d3-460e-9df2-24f9a1d87979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234594176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2234594176
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3878013717
Short name T1140
Test name
Test status
Simulation time 31290377894 ps
CPU time 14.78 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:23 PM PST 24
Peak memory 197404 kb
Host smart-bba46088-7913-4608-a7b3-e46b7fcb48b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878013717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3878013717
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.232532303
Short name T805
Test name
Test status
Simulation time 34804392690 ps
CPU time 89.65 seconds
Started Jan 03 12:48:54 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 200092 kb
Host smart-d70abe72-d0b9-4351-b96e-912482e5ad9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232532303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.232532303
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.512492761
Short name T673
Test name
Test status
Simulation time 666215924 ps
CPU time 0.78 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:50 PM PST 24
Peak memory 195620 kb
Host smart-22ec4826-bdf4-44a8-94d9-13c37b135683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512492761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.512492761
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.819770359
Short name T636
Test name
Test status
Simulation time 83167984654 ps
CPU time 72.64 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 208316 kb
Host smart-19b2abcd-1b55-4f6c-8049-bb5a32776f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819770359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.819770359
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2221773281
Short name T598
Test name
Test status
Simulation time 24388256939 ps
CPU time 549.4 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:57:54 PM PST 24
Peak memory 200044 kb
Host smart-9c9db01c-3c3a-4032-886e-6dae510fa70f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221773281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2221773281
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2603920924
Short name T642
Test name
Test status
Simulation time 36359967411 ps
CPU time 16.29 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:49:02 PM PST 24
Peak memory 199952 kb
Host smart-091ff369-f51c-4f98-8f02-a7b8141da9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603920924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2603920924
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3300511700
Short name T432
Test name
Test status
Simulation time 3845480104 ps
CPU time 2.04 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:49:00 PM PST 24
Peak memory 195988 kb
Host smart-c47ff668-ed79-49e7-83b1-82cdff27947f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300511700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3300511700
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3699769613
Short name T611
Test name
Test status
Simulation time 472690915 ps
CPU time 2.32 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 198408 kb
Host smart-e76f2812-1818-466c-8997-4959f321eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699769613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3699769613
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.239712941
Short name T1055
Test name
Test status
Simulation time 410090855833 ps
CPU time 538.65 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:57:55 PM PST 24
Peak memory 200172 kb
Host smart-e5fdda30-a613-4dda-bd53-899107155261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239712941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.239712941
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1961905254
Short name T1079
Test name
Test status
Simulation time 22739753642 ps
CPU time 193.45 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:52:08 PM PST 24
Peak memory 216164 kb
Host smart-da06c7aa-8e80-4bdb-a9b3-2d345c16c1fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961905254 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1961905254
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.180668066
Short name T873
Test name
Test status
Simulation time 7561475211 ps
CPU time 12.55 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:28 PM PST 24
Peak memory 199704 kb
Host smart-23d0d75f-8c65-4f53-bd73-845422a2b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180668066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.180668066
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1026236384
Short name T676
Test name
Test status
Simulation time 50996331513 ps
CPU time 21.61 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 200176 kb
Host smart-992d296f-d00c-46a8-b3df-fa489e9940b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026236384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1026236384
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1793104666
Short name T1151
Test name
Test status
Simulation time 121722286713 ps
CPU time 98.99 seconds
Started Jan 03 12:49:24 PM PST 24
Finished Jan 03 12:51:21 PM PST 24
Peak memory 199952 kb
Host smart-ed0bea65-b0f2-45fc-8556-2f571c476dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793104666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1793104666
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3172234910
Short name T532
Test name
Test status
Simulation time 54558610114 ps
CPU time 18.88 seconds
Started Jan 03 12:50:03 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 199776 kb
Host smart-dad41713-3e1b-45d4-ac3a-fe684b912e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172234910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3172234910
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.4254188010
Short name T1065
Test name
Test status
Simulation time 41068539943 ps
CPU time 23.8 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:50:23 PM PST 24
Peak memory 200140 kb
Host smart-263e6e25-0a21-4453-b724-0f92f13fcbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254188010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.4254188010
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2578191404
Short name T607
Test name
Test status
Simulation time 252289496365 ps
CPU time 91.49 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 200124 kb
Host smart-850cb037-4e50-424a-95dd-9a0de9e3c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578191404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2578191404
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3979242401
Short name T1222
Test name
Test status
Simulation time 41070676871 ps
CPU time 22.11 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 199756 kb
Host smart-800649f4-938b-4aa0-871d-fb1929330834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979242401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3979242401
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2983503834
Short name T1113
Test name
Test status
Simulation time 7665797388 ps
CPU time 12.85 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 199528 kb
Host smart-ba95fef6-83e3-4a80-b0d6-7813f8be0f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983503834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2983503834
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3107741759
Short name T93
Test name
Test status
Simulation time 12851454 ps
CPU time 0.53 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:48:59 PM PST 24
Peak memory 194652 kb
Host smart-96ceb6fe-5b6f-430b-9f66-f964b29f4918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107741759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3107741759
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.244512457
Short name T748
Test name
Test status
Simulation time 108777412982 ps
CPU time 45.44 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:49:58 PM PST 24
Peak memory 198492 kb
Host smart-4c78df15-88c0-41ca-b148-1b5e79aa3f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244512457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.244512457
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2300900098
Short name T743
Test name
Test status
Simulation time 28971727582 ps
CPU time 45.53 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:41 PM PST 24
Peak memory 199456 kb
Host smart-2934f2e6-4e65-443f-a87a-c7ae3aa06821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300900098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2300900098
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.1640824146
Short name T1012
Test name
Test status
Simulation time 637063794363 ps
CPU time 368.37 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:55:18 PM PST 24
Peak memory 199108 kb
Host smart-759fe235-58c6-42a1-bfe5-65ebf98d9c51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640824146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1640824146
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3574212250
Short name T1165
Test name
Test status
Simulation time 147780982747 ps
CPU time 1138.11 seconds
Started Jan 03 12:48:51 PM PST 24
Finished Jan 03 01:08:12 PM PST 24
Peak memory 200236 kb
Host smart-94d321ac-46da-42be-bdd8-8e4621bf7ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574212250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3574212250
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2514431561
Short name T1016
Test name
Test status
Simulation time 43650322671 ps
CPU time 12.26 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 197816 kb
Host smart-85ab2434-3a69-4a7f-af36-52c1be06a077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514431561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2514431561
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2103203318
Short name T1053
Test name
Test status
Simulation time 11801497350 ps
CPU time 429.84 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:56:32 PM PST 24
Peak memory 200184 kb
Host smart-f0770057-f3d8-4571-9302-8ccf0157b2b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103203318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2103203318
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.776031064
Short name T791
Test name
Test status
Simulation time 610398381 ps
CPU time 1.85 seconds
Started Jan 03 12:48:36 PM PST 24
Finished Jan 03 12:49:03 PM PST 24
Peak memory 198252 kb
Host smart-00cefd8d-f61e-423b-af08-d4c4a9a799d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776031064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.776031064
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.617730399
Short name T11
Test name
Test status
Simulation time 44036844970 ps
CPU time 34.46 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:49:22 PM PST 24
Peak memory 200072 kb
Host smart-d8497c30-0659-4b20-903a-5778765b4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617730399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.617730399
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1579287051
Short name T415
Test name
Test status
Simulation time 40432751676 ps
CPU time 63.38 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:49:53 PM PST 24
Peak memory 196044 kb
Host smart-47288931-71a2-4f28-978e-85250d0b8b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579287051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1579287051
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2354771279
Short name T1167
Test name
Test status
Simulation time 332354989 ps
CPU time 1.07 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:48:58 PM PST 24
Peak memory 198132 kb
Host smart-e517252c-b35a-42f9-adae-81d974c2632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354771279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2354771279
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.244859028
Short name T368
Test name
Test status
Simulation time 391078903988 ps
CPU time 196.63 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:52:33 PM PST 24
Peak memory 208664 kb
Host smart-ee1a64bb-5404-4f86-81d6-de138076843f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244859028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.244859028
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2568156481
Short name T155
Test name
Test status
Simulation time 217420311857 ps
CPU time 476.73 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:56:50 PM PST 24
Peak memory 217032 kb
Host smart-019b7269-185f-4960-91d1-7f6a5cb9799e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568156481 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2568156481
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.260319642
Short name T1134
Test name
Test status
Simulation time 2313367723 ps
CPU time 1.97 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:49:41 PM PST 24
Peak memory 198268 kb
Host smart-1071ee4e-6bd0-4919-bc32-075ff8d5383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260319642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.260319642
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1584669698
Short name T1056
Test name
Test status
Simulation time 41422454419 ps
CPU time 39.04 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 200160 kb
Host smart-bb4ba8db-545e-4548-a264-a34b27366faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584669698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1584669698
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2751245319
Short name T287
Test name
Test status
Simulation time 276830041650 ps
CPU time 416.15 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:56:53 PM PST 24
Peak memory 200048 kb
Host smart-50a3037d-2fa4-4a16-ade3-ad9b6a511da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751245319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2751245319
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3371060391
Short name T808
Test name
Test status
Simulation time 164392031999 ps
CPU time 325.74 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:55:21 PM PST 24
Peak memory 200096 kb
Host smart-d8bc8de5-5069-49e5-abc0-7fb60f43ffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371060391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3371060391
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.280070809
Short name T204
Test name
Test status
Simulation time 50304588609 ps
CPU time 44.29 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:50:56 PM PST 24
Peak memory 200032 kb
Host smart-694c4a1a-8959-45f8-8934-e8ed3e7406c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280070809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.280070809
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2846790460
Short name T124
Test name
Test status
Simulation time 140627626298 ps
CPU time 52.23 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 199668 kb
Host smart-7785a497-52e4-4def-9b24-6b5e98e2efbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846790460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2846790460
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.400523030
Short name T137
Test name
Test status
Simulation time 29549507841 ps
CPU time 45.2 seconds
Started Jan 03 12:50:03 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 200112 kb
Host smart-dd33ea35-c6cb-44f2-a605-7745c2b116e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400523030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.400523030
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1714667874
Short name T968
Test name
Test status
Simulation time 17742396891 ps
CPU time 30.07 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:50:19 PM PST 24
Peak memory 200160 kb
Host smart-d168ac77-775f-4b22-b5c8-355be07df373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714667874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1714667874
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.204405470
Short name T680
Test name
Test status
Simulation time 74027960 ps
CPU time 0.56 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:50 PM PST 24
Peak memory 195536 kb
Host smart-ffa4bde9-e2e8-4d33-b9ba-36af0f29d497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204405470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.204405470
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3030070381
Short name T164
Test name
Test status
Simulation time 61633615788 ps
CPU time 22.85 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 200076 kb
Host smart-55b683a3-a56c-4fec-931d-b9426f1560ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030070381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3030070381
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.509117001
Short name T703
Test name
Test status
Simulation time 51851865227 ps
CPU time 33.07 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:20 PM PST 24
Peak memory 200096 kb
Host smart-a4c96452-0997-4c47-a2c4-4b79351e5979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509117001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.509117001
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2173744519
Short name T804
Test name
Test status
Simulation time 22032568068 ps
CPU time 43.83 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:49:29 PM PST 24
Peak memory 200160 kb
Host smart-64764b6d-a879-4ac5-acd8-62e959ed7b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173744519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2173744519
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3265747512
Short name T688
Test name
Test status
Simulation time 2197797418979 ps
CPU time 3053.15 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 01:39:40 PM PST 24
Peak memory 200072 kb
Host smart-1e615444-5676-4ad7-b249-7bd76eabfb36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265747512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3265747512
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_loopback.3539018113
Short name T507
Test name
Test status
Simulation time 1903711786 ps
CPU time 4.21 seconds
Started Jan 03 12:48:42 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 198184 kb
Host smart-80845c9d-99fb-46e6-bfdc-cf72e4673cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539018113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3539018113
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2367279156
Short name T841
Test name
Test status
Simulation time 116958335379 ps
CPU time 50.91 seconds
Started Jan 03 12:48:08 PM PST 24
Finished Jan 03 12:49:27 PM PST 24
Peak memory 199156 kb
Host smart-1ee82c89-beff-42d0-a955-8178c13e5864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367279156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2367279156
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3410716190
Short name T693
Test name
Test status
Simulation time 18742038653 ps
CPU time 235.96 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:52:42 PM PST 24
Peak memory 200172 kb
Host smart-dc33f034-468d-4789-bc3e-2b46fb238433
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410716190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3410716190
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2671184130
Short name T595
Test name
Test status
Simulation time 4530280099 ps
CPU time 22.62 seconds
Started Jan 03 12:48:34 PM PST 24
Finished Jan 03 12:49:22 PM PST 24
Peak memory 198792 kb
Host smart-80d233e3-ea29-443d-88d6-4d9375cd473d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671184130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2671184130
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2471903402
Short name T952
Test name
Test status
Simulation time 50499278715 ps
CPU time 24.09 seconds
Started Jan 03 12:48:51 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 199448 kb
Host smart-c7e99028-ab2f-4fb0-9b98-e40200dae8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471903402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2471903402
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.255881801
Short name T548
Test name
Test status
Simulation time 2079070317 ps
CPU time 1.52 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:48:56 PM PST 24
Peak memory 195532 kb
Host smart-580bd0d3-20b8-43c3-9b49-65717098e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255881801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.255881801
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2465158879
Short name T1161
Test name
Test status
Simulation time 737024882 ps
CPU time 3.57 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 198616 kb
Host smart-22cbf32d-284d-4bfb-9718-244246d42566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465158879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2465158879
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1841913677
Short name T1062
Test name
Test status
Simulation time 25651068831 ps
CPU time 255.84 seconds
Started Jan 03 12:48:51 PM PST 24
Finished Jan 03 12:53:29 PM PST 24
Peak memory 208340 kb
Host smart-5ff3e127-a87b-4a1d-a5e0-12450e36fffe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841913677 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1841913677
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3272444958
Short name T1181
Test name
Test status
Simulation time 1404971496 ps
CPU time 1.72 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:10 PM PST 24
Peak memory 198652 kb
Host smart-cdd1e2ce-5c19-486b-8492-3b0fd5b2781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272444958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3272444958
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3994452421
Short name T597
Test name
Test status
Simulation time 33398368030 ps
CPU time 66.58 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 200176 kb
Host smart-8ce87e59-631c-45f6-a0c6-e06c64d8ec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994452421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3994452421
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.367431678
Short name T700
Test name
Test status
Simulation time 14965988917 ps
CPU time 13.16 seconds
Started Jan 03 12:50:51 PM PST 24
Finished Jan 03 12:51:26 PM PST 24
Peak memory 199768 kb
Host smart-96d1db50-1937-4d86-b79e-15e6af3546dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367431678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.367431678
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1433846428
Short name T1093
Test name
Test status
Simulation time 92984649926 ps
CPU time 188.35 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:52:58 PM PST 24
Peak memory 200208 kb
Host smart-6e1fac88-54ef-48ac-82c9-d282938f2e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433846428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1433846428
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.13174778
Short name T133
Test name
Test status
Simulation time 16244500170 ps
CPU time 19.03 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:51:50 PM PST 24
Peak memory 199836 kb
Host smart-1eb58f01-f974-4150-9113-84152c97d09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13174778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.13174778
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3512785510
Short name T104
Test name
Test status
Simulation time 38259126675 ps
CPU time 30.44 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:23 PM PST 24
Peak memory 199324 kb
Host smart-68f7599b-a051-44c6-9e2b-7fb2813dba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512785510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3512785510
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3277218580
Short name T746
Test name
Test status
Simulation time 119572642394 ps
CPU time 43.33 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 199616 kb
Host smart-ab9559ee-bf75-40c5-9a9f-a1f059879308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277218580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3277218580
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2618465793
Short name T381
Test name
Test status
Simulation time 77815260430 ps
CPU time 11.24 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 199192 kb
Host smart-66a04399-58a7-4f9e-985a-e3423bb07fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618465793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2618465793
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2095982412
Short name T264
Test name
Test status
Simulation time 35937448898 ps
CPU time 62.72 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:51:22 PM PST 24
Peak memory 199980 kb
Host smart-4296ab9c-7d31-4097-94be-b2d6a4cd1de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095982412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2095982412
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1477616974
Short name T244
Test name
Test status
Simulation time 9268785456 ps
CPU time 14.77 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:19 PM PST 24
Peak memory 199776 kb
Host smart-9f00aaf7-70ba-415a-9d58-a2a08d6b3bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477616974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1477616974
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.334629295
Short name T317
Test name
Test status
Simulation time 24430647522 ps
CPU time 20.79 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:50:17 PM PST 24
Peak memory 200152 kb
Host smart-98e86235-f71b-410f-b500-c005b323ff58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334629295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.334629295
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.244820588
Short name T754
Test name
Test status
Simulation time 46989886889 ps
CPU time 39.12 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 200172 kb
Host smart-132bbc0b-a766-46ea-a5b6-3ec08b2eba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244820588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.244820588
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2614124693
Short name T508
Test name
Test status
Simulation time 10882319 ps
CPU time 0.54 seconds
Started Jan 03 12:48:35 PM PST 24
Finished Jan 03 12:49:01 PM PST 24
Peak memory 194668 kb
Host smart-bb4ba814-d7ce-41d5-8ab6-c53a271d58e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614124693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2614124693
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.670935673
Short name T109
Test name
Test status
Simulation time 65177363073 ps
CPU time 12.2 seconds
Started Jan 03 12:48:39 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 200076 kb
Host smart-3035f5bd-6e6c-4679-97a8-f1749442f657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670935673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.670935673
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2713982300
Short name T1169
Test name
Test status
Simulation time 41806183808 ps
CPU time 18.63 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 199276 kb
Host smart-eff87b1d-fe24-4975-97ef-4a7185d47126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713982300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2713982300
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.275577290
Short name T354
Test name
Test status
Simulation time 36099856124 ps
CPU time 51.81 seconds
Started Jan 03 12:48:56 PM PST 24
Finished Jan 03 12:50:08 PM PST 24
Peak memory 200272 kb
Host smart-c2c0d021-b074-4e14-b77f-92fb9dc145e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275577290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.275577290
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3519769994
Short name T454
Test name
Test status
Simulation time 415258469410 ps
CPU time 285.12 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:53:25 PM PST 24
Peak memory 199228 kb
Host smart-ae41f3fd-acd8-47df-ad04-0d95a9ed576a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519769994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3519769994
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4238692437
Short name T1180
Test name
Test status
Simulation time 133584071659 ps
CPU time 338.36 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:54:20 PM PST 24
Peak memory 200124 kb
Host smart-865f90e1-fb9d-48c2-89de-7ffb43210766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238692437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4238692437
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2005650967
Short name T574
Test name
Test status
Simulation time 8897935470 ps
CPU time 7.62 seconds
Started Jan 03 12:48:10 PM PST 24
Finished Jan 03 12:48:45 PM PST 24
Peak memory 198652 kb
Host smart-a9b3814b-2f8c-47b5-a84b-c0e7db9df286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005650967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2005650967
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.933258539
Short name T1144
Test name
Test status
Simulation time 196917351153 ps
CPU time 23.17 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 200332 kb
Host smart-29a3bfaa-222c-4626-98e9-1868cc3f15b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933258539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.933258539
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2151703463
Short name T660
Test name
Test status
Simulation time 8123030645 ps
CPU time 116.54 seconds
Started Jan 03 12:48:12 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 200228 kb
Host smart-6b94b710-fc05-4c2c-a4fe-36b9c32f0c4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151703463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2151703463
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1451813248
Short name T1115
Test name
Test status
Simulation time 2533706028 ps
CPU time 8.12 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 198156 kb
Host smart-3395de1a-da35-41b7-a683-37b43d26bc93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451813248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1451813248
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2204335778
Short name T1072
Test name
Test status
Simulation time 28965379359 ps
CPU time 22.77 seconds
Started Jan 03 12:48:42 PM PST 24
Finished Jan 03 12:49:30 PM PST 24
Peak memory 198768 kb
Host smart-d2bc9e43-968e-4628-8839-bb3269087b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204335778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2204335778
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.921837564
Short name T670
Test name
Test status
Simulation time 1535151712 ps
CPU time 2.91 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:53 PM PST 24
Peak memory 195520 kb
Host smart-b7566a71-94a9-409b-828f-e3dfdcea42cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921837564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.921837564
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.1045478693
Short name T792
Test name
Test status
Simulation time 863845068 ps
CPU time 1.87 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:50 PM PST 24
Peak memory 198152 kb
Host smart-11148aa6-2a87-4581-93a6-6a0af397da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045478693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1045478693
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.4122547226
Short name T248
Test name
Test status
Simulation time 19859953682 ps
CPU time 623.87 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:59:04 PM PST 24
Peak memory 200344 kb
Host smart-e950f3a9-0962-47fc-a4a7-6e8d1f31cb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122547226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4122547226
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3509466275
Short name T866
Test name
Test status
Simulation time 81228343042 ps
CPU time 731.99 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 01:00:55 PM PST 24
Peak memory 225128 kb
Host smart-540f06a0-b49e-4e7c-90c3-2cdcecc8e56b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509466275 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3509466275
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1929899656
Short name T564
Test name
Test status
Simulation time 6018249871 ps
CPU time 21.22 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:49:16 PM PST 24
Peak memory 199628 kb
Host smart-60d01d43-c876-4115-af50-85c61b5acc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929899656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1929899656
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2426930595
Short name T119
Test name
Test status
Simulation time 32452537533 ps
CPU time 12.86 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 199120 kb
Host smart-ba156b8e-51e8-4ee6-900e-bc7b76d882ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426930595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2426930595
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1555903100
Short name T94
Test name
Test status
Simulation time 38187067 ps
CPU time 0.54 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 194632 kb
Host smart-2c2d0e6a-84b7-4075-b36e-ed552774be96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555903100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1555903100
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2948828412
Short name T1051
Test name
Test status
Simulation time 505048220253 ps
CPU time 53.39 seconds
Started Jan 03 12:48:20 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 200096 kb
Host smart-ca262357-49c9-4f0f-aa22-eef966fb3fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948828412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2948828412
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3435395936
Short name T1049
Test name
Test status
Simulation time 141898063061 ps
CPU time 174.61 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:52:09 PM PST 24
Peak memory 198964 kb
Host smart-4bc36b01-7593-4c0e-bbd7-3ad44f8ed426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435395936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3435395936
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.444244967
Short name T1170
Test name
Test status
Simulation time 91827893563 ps
CPU time 37.63 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 199608 kb
Host smart-74fdb4c4-817a-4cd6-ab09-ad231b5b7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444244967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.444244967
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.497912314
Short name T859
Test name
Test status
Simulation time 432547941289 ps
CPU time 678.1 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 01:00:17 PM PST 24
Peak memory 200220 kb
Host smart-a43a4488-bb67-404c-8dd4-d1f7d445ee5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497912314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.497912314
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3354885185
Short name T961
Test name
Test status
Simulation time 57118554863 ps
CPU time 141.3 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 12:51:33 PM PST 24
Peak memory 200120 kb
Host smart-25f704f6-53c3-4d0e-a646-eca43cddfa03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354885185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3354885185
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3190819152
Short name T958
Test name
Test status
Simulation time 107922852620 ps
CPU time 101.87 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 208636 kb
Host smart-5a4cf011-b182-44b2-a6bb-1e02994c6894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190819152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3190819152
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3836359332
Short name T545
Test name
Test status
Simulation time 5782545165 ps
CPU time 154.33 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 200208 kb
Host smart-4d4ce728-db60-40e2-9983-96c1324e6ce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836359332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3836359332
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3690326196
Short name T654
Test name
Test status
Simulation time 2015992154 ps
CPU time 9.16 seconds
Started Jan 03 12:48:34 PM PST 24
Finished Jan 03 12:49:08 PM PST 24
Peak memory 197792 kb
Host smart-1eea6de4-8ddc-4370-8f0b-b382f6b4ac8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3690326196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3690326196
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.334438971
Short name T737
Test name
Test status
Simulation time 210442981789 ps
CPU time 399.02 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:55:27 PM PST 24
Peak memory 200276 kb
Host smart-9c092699-89f9-41e0-ba07-b56591ae934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334438971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.334438971
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4248916752
Short name T678
Test name
Test status
Simulation time 4959330706 ps
CPU time 1.71 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:48:49 PM PST 24
Peak memory 195908 kb
Host smart-9cfc3570-9c4b-4a77-b79b-46b5701286b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248916752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4248916752
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1324684199
Short name T930
Test name
Test status
Simulation time 6272362191 ps
CPU time 8.24 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 199512 kb
Host smart-704c0285-fedd-42a9-aa4d-12a7639b46f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324684199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1324684199
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.765003037
Short name T865
Test name
Test status
Simulation time 62298333478 ps
CPU time 100.11 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:50:28 PM PST 24
Peak memory 200076 kb
Host smart-b9f3e921-21e3-4996-b6d4-4ebb63f6f4ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765003037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.765003037
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2230574553
Short name T1073
Test name
Test status
Simulation time 37125938950 ps
CPU time 217.37 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:52:28 PM PST 24
Peak memory 215664 kb
Host smart-db25587d-5c7c-4ec7-822b-83e2c09afb90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230574553 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2230574553
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2622456825
Short name T527
Test name
Test status
Simulation time 8574323042 ps
CPU time 7.17 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:48:52 PM PST 24
Peak memory 199312 kb
Host smart-215ab181-3c8f-46c0-a581-79023ff396f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622456825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2622456825
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2898205726
Short name T766
Test name
Test status
Simulation time 19242558418 ps
CPU time 27.67 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:49:23 PM PST 24
Peak memory 196548 kb
Host smart-365eb1fa-c216-4b84-8f0b-cbea953b07b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898205726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2898205726
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2854498548
Short name T178
Test name
Test status
Simulation time 16425780084 ps
CPU time 28.66 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:47 PM PST 24
Peak memory 200044 kb
Host smart-1fc539e3-7bf6-4424-8a8c-93229eadebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854498548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2854498548
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3547145309
Short name T904
Test name
Test status
Simulation time 128115988244 ps
CPU time 27.55 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 199628 kb
Host smart-251ca842-1ffa-4790-9cbe-231bce0396ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547145309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3547145309
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4162910639
Short name T787
Test name
Test status
Simulation time 174162563243 ps
CPU time 66.7 seconds
Started Jan 03 12:50:05 PM PST 24
Finished Jan 03 12:51:36 PM PST 24
Peak memory 200168 kb
Host smart-b521550e-ef3d-45ad-8d1f-d8c41173727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162910639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4162910639
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1735522786
Short name T1160
Test name
Test status
Simulation time 48935528556 ps
CPU time 76.56 seconds
Started Jan 03 12:50:34 PM PST 24
Finished Jan 03 12:52:14 PM PST 24
Peak memory 200060 kb
Host smart-9229910e-5976-4afd-a926-859d16169b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735522786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1735522786
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1031432870
Short name T220
Test name
Test status
Simulation time 28118747808 ps
CPU time 46.1 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:51:35 PM PST 24
Peak memory 200120 kb
Host smart-132a4367-831e-45a8-a21b-fd886a2bbf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031432870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1031432870
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2558241402
Short name T114
Test name
Test status
Simulation time 42024681927 ps
CPU time 27.52 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 199388 kb
Host smart-5dc97e99-51db-4e47-aca3-f59e5e25b4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558241402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2558241402
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3751247706
Short name T138
Test name
Test status
Simulation time 9180160954 ps
CPU time 16.75 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:50:14 PM PST 24
Peak memory 200132 kb
Host smart-56e41162-e9ec-47e9-852e-56b364ffbec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751247706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3751247706
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2165300912
Short name T1182
Test name
Test status
Simulation time 18728735363 ps
CPU time 32.73 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 200068 kb
Host smart-820d8c29-568a-4774-8fed-07c04da18ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165300912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2165300912
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.965495045
Short name T1087
Test name
Test status
Simulation time 39722539082 ps
CPU time 26.81 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:50:20 PM PST 24
Peak memory 200212 kb
Host smart-aa20535a-141c-4ac4-858c-2fb772a380a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965495045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.965495045
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2841154806
Short name T566
Test name
Test status
Simulation time 63112286129 ps
CPU time 92.73 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:52:08 PM PST 24
Peak memory 200208 kb
Host smart-27bac576-0658-4ee4-b724-185ebed812ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841154806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2841154806
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1085531304
Short name T695
Test name
Test status
Simulation time 23850386 ps
CPU time 0.53 seconds
Started Jan 03 12:49:00 PM PST 24
Finished Jan 03 12:49:21 PM PST 24
Peak memory 195588 kb
Host smart-a4049c1e-d0ae-462b-bc89-894c60f0325d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085531304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1085531304
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3094832743
Short name T446
Test name
Test status
Simulation time 94749617795 ps
CPU time 39.45 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:43 PM PST 24
Peak memory 200068 kb
Host smart-e4e797a6-61f7-4a77-8105-8101c697f222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094832743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3094832743
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2094299535
Short name T757
Test name
Test status
Simulation time 25340822503 ps
CPU time 42.55 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:49:28 PM PST 24
Peak memory 200036 kb
Host smart-d408d944-17bb-4e62-a056-d1fcc9ba3ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094299535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2094299535
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2107570931
Short name T1118
Test name
Test status
Simulation time 660667035929 ps
CPU time 1035.32 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 01:06:20 PM PST 24
Peak memory 198436 kb
Host smart-b22cf1e8-8a08-4f3c-bc52-26639779327e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107570931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2107570931
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.747945228
Short name T579
Test name
Test status
Simulation time 189643363472 ps
CPU time 1337.84 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 01:11:32 PM PST 24
Peak memory 200164 kb
Host smart-b22b4f13-ee51-4b53-9404-59bb064c6b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=747945228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.747945228
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3821016322
Short name T877
Test name
Test status
Simulation time 5385437795 ps
CPU time 6.24 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:49:04 PM PST 24
Peak memory 199484 kb
Host smart-9b559190-6e52-41e1-bb8a-a96b0495b101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821016322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3821016322
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.688526791
Short name T522
Test name
Test status
Simulation time 121298217599 ps
CPU time 117.47 seconds
Started Jan 03 12:48:34 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 208528 kb
Host smart-d2b1c574-0117-4839-a083-b02cb2c26f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688526791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.688526791
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.719940294
Short name T971
Test name
Test status
Simulation time 35361959010 ps
CPU time 548.87 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:58:07 PM PST 24
Peak memory 200120 kb
Host smart-592f665e-4278-467a-a6a8-b36a125a3b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719940294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.719940294
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2281576043
Short name T789
Test name
Test status
Simulation time 4042394130 ps
CPU time 8.77 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 198252 kb
Host smart-c5d688e4-6510-40e8-9d3f-0990bc84dc36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281576043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2281576043
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3574312443
Short name T362
Test name
Test status
Simulation time 48990100429 ps
CPU time 48.78 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:36 PM PST 24
Peak memory 200196 kb
Host smart-6668c8cc-6727-4e27-9944-506589a39a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574312443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3574312443
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2292475856
Short name T609
Test name
Test status
Simulation time 3503885627 ps
CPU time 6.41 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:14 PM PST 24
Peak memory 195944 kb
Host smart-9d4fb7d1-642d-4630-a028-7710f7944297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292475856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2292475856
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2772714335
Short name T1153
Test name
Test status
Simulation time 5680674221 ps
CPU time 7.62 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 199664 kb
Host smart-43324a83-fc1b-492a-8b01-683c2c3dc0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772714335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2772714335
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.150147923
Short name T1183
Test name
Test status
Simulation time 318051870326 ps
CPU time 822.7 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 01:02:54 PM PST 24
Peak memory 225116 kb
Host smart-06b56156-6b95-4625-9047-757da6dcca41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150147923 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.150147923
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4003526727
Short name T696
Test name
Test status
Simulation time 7185813958 ps
CPU time 8.46 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:16 PM PST 24
Peak memory 199748 kb
Host smart-ba2e54a9-157a-48ef-a5a6-df71b099f698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003526727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4003526727
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3141069994
Short name T213
Test name
Test status
Simulation time 67264000760 ps
CPU time 118.17 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:51:08 PM PST 24
Peak memory 200148 kb
Host smart-d6c167bd-ba95-4a01-88b9-2fa499d70bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141069994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3141069994
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2211624280
Short name T620
Test name
Test status
Simulation time 151317805831 ps
CPU time 27.75 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 199744 kb
Host smart-f8294912-fa74-4bb8-899c-4d72872c5d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211624280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2211624280
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3038466344
Short name T314
Test name
Test status
Simulation time 138816196378 ps
CPU time 125.42 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:53:27 PM PST 24
Peak memory 199076 kb
Host smart-4c689c7b-ee81-4a88-9cd8-d6e25f332c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038466344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3038466344
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.343440271
Short name T167
Test name
Test status
Simulation time 56886616504 ps
CPU time 50.33 seconds
Started Jan 03 12:50:02 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 200100 kb
Host smart-a6b2d2e5-1143-46d2-b5f0-15accc673d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343440271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.343440271
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1197631943
Short name T921
Test name
Test status
Simulation time 71256859745 ps
CPU time 122.83 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:53:19 PM PST 24
Peak memory 199600 kb
Host smart-5368256f-cccf-44c3-9bc5-69266012e343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197631943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1197631943
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.18782162
Short name T240
Test name
Test status
Simulation time 65538139150 ps
CPU time 25.51 seconds
Started Jan 03 12:51:07 PM PST 24
Finished Jan 03 12:51:51 PM PST 24
Peak memory 199748 kb
Host smart-c76bc95d-f0cd-4e5d-aa06-e68ad95445f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18782162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.18782162
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1969034850
Short name T972
Test name
Test status
Simulation time 18357719529 ps
CPU time 16.35 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 199836 kb
Host smart-3930036c-8157-4967-bd73-f0b279cfc306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969034850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1969034850
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3600515141
Short name T646
Test name
Test status
Simulation time 31373244 ps
CPU time 0.53 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 12:49:03 PM PST 24
Peak memory 194596 kb
Host smart-754e8d7a-b187-4c48-8d07-42e7046cac29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600515141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3600515141
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3698881216
Short name T365
Test name
Test status
Simulation time 102982012118 ps
CPU time 39.85 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:36 PM PST 24
Peak memory 199504 kb
Host smart-c356751d-c4f1-45ab-9f64-9f0c8fe9774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698881216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3698881216
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2345851672
Short name T355
Test name
Test status
Simulation time 249071232652 ps
CPU time 500.94 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:57:17 PM PST 24
Peak memory 200136 kb
Host smart-bc3547cf-3faa-4f17-b4e4-6ce6edd1ba7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345851672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2345851672
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.3781416854
Short name T1125
Test name
Test status
Simulation time 376284111866 ps
CPU time 646.89 seconds
Started Jan 03 12:48:39 PM PST 24
Finished Jan 03 12:59:52 PM PST 24
Peak memory 200180 kb
Host smart-198cc25a-167f-4c80-a0e1-d4ce6b8ec8e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781416854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3781416854
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3145124961
Short name T585
Test name
Test status
Simulation time 76163456246 ps
CPU time 394.56 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:55:40 PM PST 24
Peak memory 200164 kb
Host smart-14c1a92d-4648-4590-b744-534c165e3415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145124961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3145124961
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.570466488
Short name T1086
Test name
Test status
Simulation time 8680376661 ps
CPU time 17.23 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:48:58 PM PST 24
Peak memory 198700 kb
Host smart-0b1a7638-f9ca-4e16-9c8f-ebe0fdd887ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570466488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.570466488
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2267142071
Short name T160
Test name
Test status
Simulation time 357126172029 ps
CPU time 61.75 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:49:50 PM PST 24
Peak memory 200308 kb
Host smart-5eb958ca-058e-48e4-97e4-d080fe629e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267142071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2267142071
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2102187593
Short name T999
Test name
Test status
Simulation time 43304637970 ps
CPU time 373.21 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:54:53 PM PST 24
Peak memory 200220 kb
Host smart-0b2fb645-dcc7-4ed8-ab36-2dc920e18339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102187593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2102187593
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.4101851937
Short name T1102
Test name
Test status
Simulation time 409773792 ps
CPU time 2.56 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 198368 kb
Host smart-32c5e4e4-6434-4d25-9891-739e85e2c40e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101851937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4101851937
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.428626616
Short name T1216
Test name
Test status
Simulation time 128512665091 ps
CPU time 220.33 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:52:20 PM PST 24
Peak memory 200080 kb
Host smart-a7497f90-c472-41ab-a007-ac87aa9af2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428626616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.428626616
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1336343190
Short name T922
Test name
Test status
Simulation time 35983114540 ps
CPU time 14.73 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:02 PM PST 24
Peak memory 195480 kb
Host smart-19975437-3afd-44da-8c51-a2d4b1c6ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336343190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1336343190
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3498296627
Short name T666
Test name
Test status
Simulation time 247976254 ps
CPU time 1.39 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:49:10 PM PST 24
Peak memory 198316 kb
Host smart-28e6e2aa-dd61-40b2-becc-7bdfb0c1907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498296627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3498296627
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.331267437
Short name T807
Test name
Test status
Simulation time 240832127092 ps
CPU time 56.18 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 216808 kb
Host smart-c3fd5a82-f420-4379-a89c-5f47841e0995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331267437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.331267437
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1199210406
Short name T75
Test name
Test status
Simulation time 270949246515 ps
CPU time 500.73 seconds
Started Jan 03 12:48:39 PM PST 24
Finished Jan 03 12:57:26 PM PST 24
Peak memory 216600 kb
Host smart-fa32a582-a8c2-4df2-b035-3f63f3e14043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199210406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1199210406
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.440316617
Short name T22
Test name
Test status
Simulation time 437219110 ps
CPU time 1.66 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 198416 kb
Host smart-1127797f-b2cf-4fce-95ff-b6ce51515224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440316617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.440316617
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.360338004
Short name T1004
Test name
Test status
Simulation time 172419213428 ps
CPU time 72.81 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:50:08 PM PST 24
Peak memory 200196 kb
Host smart-8a037de2-5892-4d3c-841f-52565a081fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360338004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.360338004
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.561857396
Short name T194
Test name
Test status
Simulation time 51466108477 ps
CPU time 82.87 seconds
Started Jan 03 12:50:23 PM PST 24
Finished Jan 03 12:52:15 PM PST 24
Peak memory 200180 kb
Host smart-cbd937a4-44a2-4408-b899-fa37520064ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561857396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.561857396
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1306943608
Short name T173
Test name
Test status
Simulation time 169604145284 ps
CPU time 24.5 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 198412 kb
Host smart-13c52e5f-9667-4309-a1dd-bc729b84f13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306943608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1306943608
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3504912403
Short name T162
Test name
Test status
Simulation time 63023402116 ps
CPU time 20.5 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 199388 kb
Host smart-0a41f51f-04ad-478f-8dcb-0845fe2628b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504912403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3504912403
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3433093903
Short name T588
Test name
Test status
Simulation time 20629782195 ps
CPU time 29.65 seconds
Started Jan 03 12:50:30 PM PST 24
Finished Jan 03 12:51:23 PM PST 24
Peak memory 200016 kb
Host smart-f6408c93-ee5d-4d31-89c9-c1eea1fa7f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433093903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3433093903
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.973078752
Short name T749
Test name
Test status
Simulation time 7115565869 ps
CPU time 13.38 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:50:26 PM PST 24
Peak memory 200152 kb
Host smart-d4bfcfc7-56d6-4796-85be-58e7a9ad237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973078752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.973078752
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.392756710
Short name T1156
Test name
Test status
Simulation time 26888282820 ps
CPU time 12.19 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 200104 kb
Host smart-79709337-7ea0-4006-8680-37b7a35766a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392756710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.392756710
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3597105255
Short name T1018
Test name
Test status
Simulation time 24083891694 ps
CPU time 37.72 seconds
Started Jan 03 12:51:26 PM PST 24
Finished Jan 03 12:52:18 PM PST 24
Peak memory 199792 kb
Host smart-fa5605f9-9ae8-4260-9b58-022429198906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597105255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3597105255
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1500688096
Short name T169
Test name
Test status
Simulation time 78655723851 ps
CPU time 112.84 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:52:15 PM PST 24
Peak memory 200184 kb
Host smart-b101b43c-8c8b-4c3e-9067-dc5e7de5061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500688096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1500688096
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3326710551
Short name T396
Test name
Test status
Simulation time 61780447650 ps
CPU time 44.76 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 200172 kb
Host smart-73f5e63b-edc3-4bce-8a79-7c452af5700f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326710551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3326710551
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3084289711
Short name T639
Test name
Test status
Simulation time 20100327 ps
CPU time 0.53 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:49:13 PM PST 24
Peak memory 195524 kb
Host smart-68cde055-b35e-47ba-b7ba-ad1dfecef638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084289711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3084289711
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3017262135
Short name T1054
Test name
Test status
Simulation time 162963841248 ps
CPU time 68 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:49:59 PM PST 24
Peak memory 199968 kb
Host smart-73fcc103-3c63-42a5-ae58-410932526baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017262135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3017262135
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.104898397
Short name T725
Test name
Test status
Simulation time 10108623698 ps
CPU time 18.45 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:49:29 PM PST 24
Peak memory 197832 kb
Host smart-d104866d-2766-4ac9-9f29-35c020ee83cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104898397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.104898397
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.3453825357
Short name T1192
Test name
Test status
Simulation time 12865108043 ps
CPU time 21.01 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:49:16 PM PST 24
Peak memory 196564 kb
Host smart-73229d6c-5234-4afe-814a-6dc949caf263
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453825357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3453825357
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1171949367
Short name T987
Test name
Test status
Simulation time 100572366638 ps
CPU time 386.3 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:55:13 PM PST 24
Peak memory 200044 kb
Host smart-50994274-3be8-45d6-8588-f28fee175c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171949367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1171949367
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.986529533
Short name T974
Test name
Test status
Simulation time 3216980677 ps
CPU time 5.67 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:48:53 PM PST 24
Peak memory 198252 kb
Host smart-31606d67-eac9-4c5b-bd97-31bbacc1d2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986529533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.986529533
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2470653467
Short name T835
Test name
Test status
Simulation time 3396963049 ps
CPU time 6.43 seconds
Started Jan 03 12:48:34 PM PST 24
Finished Jan 03 12:49:06 PM PST 24
Peak memory 193960 kb
Host smart-89adb388-3b1c-4eea-bafa-722f848c072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470653467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2470653467
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1019745423
Short name T973
Test name
Test status
Simulation time 24656425375 ps
CPU time 159.4 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 200036 kb
Host smart-de81e769-759b-4d6d-b687-911528af3ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019745423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1019745423
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1774915876
Short name T20
Test name
Test status
Simulation time 1820010215 ps
CPU time 2.07 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 198032 kb
Host smart-c44e8ddb-d394-42e7-9756-d17b7a8e3fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774915876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1774915876
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2257157555
Short name T794
Test name
Test status
Simulation time 50324410847 ps
CPU time 30.32 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:49:46 PM PST 24
Peak memory 200148 kb
Host smart-2754b637-7612-4d3c-abb9-264107a6dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257157555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2257157555
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1210753123
Short name T423
Test name
Test status
Simulation time 46467399595 ps
CPU time 35.91 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 195840 kb
Host smart-11419b57-f3fd-4ec1-b450-a593d91adcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210753123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1210753123
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2287706723
Short name T659
Test name
Test status
Simulation time 857772611 ps
CPU time 2.36 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 198484 kb
Host smart-39f6ef28-7800-4727-80a1-160f9be73a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287706723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2287706723
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2380854789
Short name T1005
Test name
Test status
Simulation time 51333555624 ps
CPU time 27.25 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 200132 kb
Host smart-db85d489-9b77-4e15-b961-70e1b0ecbd81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380854789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2380854789
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3512117513
Short name T518
Test name
Test status
Simulation time 9063526833 ps
CPU time 11.25 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:49:15 PM PST 24
Peak memory 199596 kb
Host smart-a8d8df74-2f0d-4c07-8f3f-c53d9e854e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512117513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3512117513
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1230851383
Short name T1007
Test name
Test status
Simulation time 49392132234 ps
CPU time 19.45 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:49:31 PM PST 24
Peak memory 200040 kb
Host smart-9c6c0cda-2ef2-4b95-ab24-69cc14688a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230851383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1230851383
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1970519901
Short name T289
Test name
Test status
Simulation time 100915427842 ps
CPU time 184.96 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:53:02 PM PST 24
Peak memory 200092 kb
Host smart-a29acc0e-d94b-4897-801f-df6b71d3baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970519901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1970519901
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2429472254
Short name T202
Test name
Test status
Simulation time 46383498533 ps
CPU time 63.24 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 200112 kb
Host smart-6a37612e-6c5d-4bdf-b59c-4056d8c84619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429472254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2429472254
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1671548353
Short name T165
Test name
Test status
Simulation time 230797030642 ps
CPU time 369.4 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:56:39 PM PST 24
Peak memory 200192 kb
Host smart-630f6163-5a29-48f2-a560-b9249bf99299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671548353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1671548353
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3216711776
Short name T199
Test name
Test status
Simulation time 285247951181 ps
CPU time 103.7 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:52:19 PM PST 24
Peak memory 200116 kb
Host smart-d51c0941-465e-4e74-a9aa-a23a4239d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216711776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3216711776
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1747914098
Short name T644
Test name
Test status
Simulation time 33362830132 ps
CPU time 25.85 seconds
Started Jan 03 12:50:18 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 200128 kb
Host smart-3e90631d-e785-40bb-a5b3-ec2936a1c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747914098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1747914098
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1173337880
Short name T634
Test name
Test status
Simulation time 133931603597 ps
CPU time 49.39 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 200176 kb
Host smart-0f137904-1dea-4735-a67d-24975764a086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173337880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1173337880
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2778068892
Short name T190
Test name
Test status
Simulation time 238177818610 ps
CPU time 91.85 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 200068 kb
Host smart-62c855ee-8c04-4278-a9de-77993aa85b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778068892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2778068892
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1728813678
Short name T198
Test name
Test status
Simulation time 61644401648 ps
CPU time 26.85 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 12:50:59 PM PST 24
Peak memory 200132 kb
Host smart-1ddaaa5b-4397-43af-8fb3-269043744e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728813678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1728813678
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.771575903
Short name T1011
Test name
Test status
Simulation time 11742348 ps
CPU time 0.54 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 195596 kb
Host smart-d76443aa-b9eb-4e4e-99cd-7acebebd6f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771575903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.771575903
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2928008438
Short name T282
Test name
Test status
Simulation time 86825861585 ps
CPU time 37.34 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 200092 kb
Host smart-1d79d4f8-e88c-48eb-af7f-31776fb4833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928008438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2928008438
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1892460652
Short name T1141
Test name
Test status
Simulation time 88842125780 ps
CPU time 37.61 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:49 PM PST 24
Peak memory 200052 kb
Host smart-f7b2ee47-9129-4eed-ac56-3ae483393b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892460652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1892460652
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.524616811
Short name T277
Test name
Test status
Simulation time 44907875112 ps
CPU time 79.82 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 199988 kb
Host smart-47bf4afe-4461-465d-8e33-c9fa9b62930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524616811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.524616811
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2993566208
Short name T635
Test name
Test status
Simulation time 1040003925669 ps
CPU time 650.46 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 01:00:17 PM PST 24
Peak memory 200236 kb
Host smart-0f2b906f-7b43-4ac6-af98-39e45456053b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993566208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2993566208
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4083807650
Short name T741
Test name
Test status
Simulation time 100117496836 ps
CPU time 248.52 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:53:16 PM PST 24
Peak memory 200168 kb
Host smart-24bdb664-5fbb-42dd-beb9-09a69130618f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083807650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4083807650
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1798812388
Short name T534
Test name
Test status
Simulation time 6616729834 ps
CPU time 5.23 seconds
Started Jan 03 12:48:54 PM PST 24
Finished Jan 03 12:49:20 PM PST 24
Peak memory 198056 kb
Host smart-3475f501-b37b-4438-9622-a7a1488bbca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798812388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1798812388
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1189955025
Short name T802
Test name
Test status
Simulation time 254573884285 ps
CPU time 45.41 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 12:50:00 PM PST 24
Peak memory 208660 kb
Host smart-41b018b5-b3b6-49c3-bd23-8b092c2cf94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189955025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1189955025
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3493381508
Short name T762
Test name
Test status
Simulation time 21459947971 ps
CPU time 236.21 seconds
Started Jan 03 12:49:00 PM PST 24
Finished Jan 03 12:53:17 PM PST 24
Peak memory 200176 kb
Host smart-26e3b9cb-0745-4853-b426-3f60e8e26c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493381508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3493381508
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.428177801
Short name T710
Test name
Test status
Simulation time 3428811986 ps
CPU time 25.54 seconds
Started Jan 03 12:48:52 PM PST 24
Finished Jan 03 12:49:39 PM PST 24
Peak memory 198228 kb
Host smart-e7f570bd-9e18-4d74-8658-467c50eec2bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428177801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.428177801
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1562854813
Short name T948
Test name
Test status
Simulation time 30067653538 ps
CPU time 48.19 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:50:00 PM PST 24
Peak memory 199448 kb
Host smart-3b5c2dc6-1887-44b3-b73e-ccf28c0fdfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562854813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1562854813
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1001112951
Short name T425
Test name
Test status
Simulation time 1353631184 ps
CPU time 2.45 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 195524 kb
Host smart-7efb7f63-43c3-409b-870b-6c2d24ad9996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001112951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1001112951
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2620700255
Short name T994
Test name
Test status
Simulation time 675640112 ps
CPU time 1.33 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 197992 kb
Host smart-7b02fa7e-4e68-4785-b862-a39261c4f8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620700255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2620700255
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2307707256
Short name T1143
Test name
Test status
Simulation time 155462005220 ps
CPU time 879.84 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 01:03:35 PM PST 24
Peak memory 216660 kb
Host smart-d4c34a78-d316-422a-92fd-68ab74df624d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307707256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2307707256
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2969450889
Short name T1184
Test name
Test status
Simulation time 840750472 ps
CPU time 2.32 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 198600 kb
Host smart-734e4198-94ba-4fef-a1e1-e9ff0c96a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969450889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2969450889
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2348862337
Short name T943
Test name
Test status
Simulation time 7610385337 ps
CPU time 9.81 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:48:56 PM PST 24
Peak memory 198544 kb
Host smart-0d46b610-f518-4dbf-b927-33a42a8a89e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348862337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2348862337
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.786652289
Short name T359
Test name
Test status
Simulation time 386519883818 ps
CPU time 93.14 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 12:52:09 PM PST 24
Peak memory 199856 kb
Host smart-f30c858f-e0f9-48fa-ad8a-527fac716c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786652289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.786652289
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3713532415
Short name T279
Test name
Test status
Simulation time 29576562828 ps
CPU time 50 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 200180 kb
Host smart-8091d941-5acf-4031-98e2-b7ea375d76e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713532415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3713532415
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.4188838700
Short name T1064
Test name
Test status
Simulation time 76051396678 ps
CPU time 34.94 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 200056 kb
Host smart-cd03926d-cd08-4f19-aaf0-95ccc22b5223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188838700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4188838700
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2652636034
Short name T349
Test name
Test status
Simulation time 145631996683 ps
CPU time 37.47 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 200148 kb
Host smart-a40922ca-477e-4250-a311-1c8cfacd844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652636034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2652636034
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2902456510
Short name T1139
Test name
Test status
Simulation time 43656675744 ps
CPU time 17.62 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 200020 kb
Host smart-e004475d-eaa9-4137-a6d2-17e6c3ca4332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902456510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2902456510
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2512796795
Short name T721
Test name
Test status
Simulation time 260526552918 ps
CPU time 73.08 seconds
Started Jan 03 12:50:31 PM PST 24
Finished Jan 03 12:52:08 PM PST 24
Peak memory 200188 kb
Host smart-b2a11dc2-f97d-40da-9ceb-66271545a73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512796795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2512796795
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2546625593
Short name T577
Test name
Test status
Simulation time 11878978329 ps
CPU time 6.21 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:20 PM PST 24
Peak memory 199864 kb
Host smart-ded23f00-a83f-4a47-8e71-81f3c759d559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546625593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2546625593
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2632799062
Short name T221
Test name
Test status
Simulation time 24732351921 ps
CPU time 7.48 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:50:03 PM PST 24
Peak memory 199900 kb
Host smart-a0f3b418-fdfe-47a9-a83b-6c9851588a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632799062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2632799062
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.309467527
Short name T196
Test name
Test status
Simulation time 47595626440 ps
CPU time 79.06 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 199992 kb
Host smart-140886a1-e84c-47b0-b21b-111f0e6aae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309467527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.309467527
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3460866243
Short name T497
Test name
Test status
Simulation time 44968773 ps
CPU time 0.53 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 195652 kb
Host smart-73b2c884-c689-444f-baa6-1c656f91d8f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460866243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3460866243
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.640687546
Short name T419
Test name
Test status
Simulation time 57519922505 ps
CPU time 89.12 seconds
Started Jan 03 12:48:33 PM PST 24
Finished Jan 03 12:50:28 PM PST 24
Peak memory 200232 kb
Host smart-fb676e72-1661-4cc0-9c88-e127711e16d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640687546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.640687546
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1674758603
Short name T720
Test name
Test status
Simulation time 193230951847 ps
CPU time 43.18 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:49:29 PM PST 24
Peak memory 200160 kb
Host smart-cac2baf7-e800-4813-b18e-7a63bb9f0df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674758603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1674758603
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2825772753
Short name T663
Test name
Test status
Simulation time 253374612317 ps
CPU time 139.31 seconds
Started Jan 03 12:48:39 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 199876 kb
Host smart-a2fafc16-b023-44de-b59e-d3edc5f8ec8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825772753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2825772753
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_loopback.223091282
Short name T870
Test name
Test status
Simulation time 5789764617 ps
CPU time 1.31 seconds
Started Jan 03 12:49:08 PM PST 24
Finished Jan 03 12:49:27 PM PST 24
Peak memory 197768 kb
Host smart-86ec775a-4852-4e9c-ad9f-2f3e3a6807d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223091282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.223091282
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1312837227
Short name T822
Test name
Test status
Simulation time 60825023331 ps
CPU time 140.22 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:51:18 PM PST 24
Peak memory 199964 kb
Host smart-c65167ca-860f-491e-9b3e-d577d1ba47a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312837227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1312837227
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2198619860
Short name T1111
Test name
Test status
Simulation time 5766886700 ps
CPU time 282.16 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:53:50 PM PST 24
Peak memory 200160 kb
Host smart-b976568a-0242-411b-b2f4-dcf11258b153
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198619860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2198619860
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2790827076
Short name T589
Test name
Test status
Simulation time 1916952005 ps
CPU time 2.78 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:49:19 PM PST 24
Peak memory 198156 kb
Host smart-992cf70e-e83b-4ccf-999b-28b465b42c16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790827076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2790827076
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3078791828
Short name T1148
Test name
Test status
Simulation time 15073741684 ps
CPU time 17.76 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 200224 kb
Host smart-813135fd-7563-4d70-ac92-838f531c0c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078791828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3078791828
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.4124228617
Short name T515
Test name
Test status
Simulation time 1957094367 ps
CPU time 2.02 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:49:08 PM PST 24
Peak memory 195520 kb
Host smart-4a92d894-fe6f-4c00-8c72-5bd482ec9059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124228617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4124228617
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1049380289
Short name T776
Test name
Test status
Simulation time 648342278 ps
CPU time 2.09 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:49:14 PM PST 24
Peak memory 197992 kb
Host smart-b24c65a7-6084-4efd-a46d-8b5ccea1e6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049380289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1049380289
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2290312671
Short name T685
Test name
Test status
Simulation time 227736363168 ps
CPU time 197.84 seconds
Started Jan 03 12:48:42 PM PST 24
Finished Jan 03 12:52:25 PM PST 24
Peak memory 200164 kb
Host smart-82e7d76c-84b2-417e-b61f-899e5fb3c835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290312671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2290312671
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3069552401
Short name T929
Test name
Test status
Simulation time 124750575888 ps
CPU time 1505.17 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 01:14:17 PM PST 24
Peak memory 226380 kb
Host smart-a613221e-91c9-43b0-b6c6-da3fc6e3eeee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069552401 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3069552401
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.48732090
Short name T573
Test name
Test status
Simulation time 849565368 ps
CPU time 2.68 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:49:16 PM PST 24
Peak memory 198208 kb
Host smart-a9d193af-e3f0-4af2-8cab-0ad0e40c15ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48732090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.48732090
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3871684232
Short name T147
Test name
Test status
Simulation time 58211876949 ps
CPU time 27.51 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:49:34 PM PST 24
Peak memory 200176 kb
Host smart-4ad33f25-b617-442e-9b07-65cfd7478e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871684232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3871684232
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2703375626
Short name T266
Test name
Test status
Simulation time 16205615258 ps
CPU time 24.97 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:50:17 PM PST 24
Peak memory 200148 kb
Host smart-40e03d96-f17a-41c2-8576-76c30e4f165b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703375626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2703375626
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.468654528
Short name T126
Test name
Test status
Simulation time 133354768558 ps
CPU time 115.86 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 12:52:35 PM PST 24
Peak memory 200192 kb
Host smart-7d074ed1-e3cd-4740-a457-8088f47aa20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468654528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.468654528
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3808319318
Short name T935
Test name
Test status
Simulation time 35745942509 ps
CPU time 54.46 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 12:51:31 PM PST 24
Peak memory 200152 kb
Host smart-f49833ca-8535-4baa-9c9e-b345bf80facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808319318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3808319318
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1101910896
Short name T156
Test name
Test status
Simulation time 127637021972 ps
CPU time 238.34 seconds
Started Jan 03 12:49:48 PM PST 24
Finished Jan 03 12:53:58 PM PST 24
Peak memory 200172 kb
Host smart-d4f5425a-215b-4caa-9691-7f674a19dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101910896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1101910896
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.320557260
Short name T1197
Test name
Test status
Simulation time 77700312391 ps
CPU time 137.21 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 200268 kb
Host smart-9b4c8130-31f8-49a2-862e-4ca81caa2629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320557260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.320557260
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2178397381
Short name T230
Test name
Test status
Simulation time 27354493415 ps
CPU time 37.5 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 200160 kb
Host smart-4514e800-3bc0-4e84-a96a-ce50f9ad82a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178397381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2178397381
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3711666176
Short name T367
Test name
Test status
Simulation time 198110103858 ps
CPU time 71.24 seconds
Started Jan 03 12:50:05 PM PST 24
Finished Jan 03 12:51:45 PM PST 24
Peak memory 199932 kb
Host smart-297cc2fe-4421-4879-b715-7213090e6642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711666176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3711666176
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1718122049
Short name T118
Test name
Test status
Simulation time 86555060616 ps
CPU time 41.77 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 200260 kb
Host smart-8b59ea82-f373-4e04-9a49-a268d35363d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718122049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1718122049
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.332752932
Short name T1048
Test name
Test status
Simulation time 23302168 ps
CPU time 0.55 seconds
Started Jan 03 12:48:56 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 195576 kb
Host smart-d4a0369b-ca7c-49c8-ac46-af4aaf2025fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332752932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.332752932
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.446425462
Short name T606
Test name
Test status
Simulation time 61505997763 ps
CPU time 49.68 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 200136 kb
Host smart-d25f8ce2-e05c-4671-a7a6-df66667e7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446425462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.446425462
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2869700817
Short name T336
Test name
Test status
Simulation time 115311685431 ps
CPU time 45.26 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:53 PM PST 24
Peak memory 200060 kb
Host smart-abc8c444-e429-491b-88b2-d10b44443c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869700817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2869700817
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1448833276
Short name T661
Test name
Test status
Simulation time 17734113782 ps
CPU time 12.64 seconds
Started Jan 03 12:49:12 PM PST 24
Finished Jan 03 12:49:42 PM PST 24
Peak memory 199908 kb
Host smart-dc63fff7-0e72-417f-93c5-ca3acac7a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448833276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1448833276
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1099618554
Short name T1046
Test name
Test status
Simulation time 177144039952 ps
CPU time 1029.25 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 01:06:44 PM PST 24
Peak memory 200120 kb
Host smart-120d7f9e-fc89-4101-82e4-3b60455f7c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099618554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1099618554
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_noise_filter.574188981
Short name T1155
Test name
Test status
Simulation time 23249469172 ps
CPU time 36.32 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:44 PM PST 24
Peak memory 198768 kb
Host smart-d44c2452-49ba-436b-8317-136975fbcb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574188981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.574188981
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.102849369
Short name T203
Test name
Test status
Simulation time 8986675362 ps
CPU time 254.44 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:53:19 PM PST 24
Peak memory 200168 kb
Host smart-7452fee8-078b-4fe5-a7cb-0a95f2ed03dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102849369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.102849369
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1444165823
Short name T871
Test name
Test status
Simulation time 3373736979 ps
CPU time 6.72 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:15 PM PST 24
Peak memory 198076 kb
Host smart-b9016192-44bc-4b01-927e-f0659caeb878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444165823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1444165823
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.12177167
Short name T142
Test name
Test status
Simulation time 249399425770 ps
CPU time 34.65 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:49:49 PM PST 24
Peak memory 199240 kb
Host smart-8f27ef6b-b5df-48e7-b649-55d5bfd7f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12177167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.12177167
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.459567234
Short name T449
Test name
Test status
Simulation time 3168835988 ps
CPU time 1.8 seconds
Started Jan 03 12:48:35 PM PST 24
Finished Jan 03 12:49:02 PM PST 24
Peak memory 195600 kb
Host smart-d882fb02-ae38-4eb8-b2ee-9ccf9594b278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459567234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.459567234
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.328251227
Short name T516
Test name
Test status
Simulation time 5559876654 ps
CPU time 9.79 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:49:02 PM PST 24
Peak memory 198928 kb
Host smart-29b5d7d9-e433-45fa-bb3f-953b81ba3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328251227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.328251227
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1784888586
Short name T441
Test name
Test status
Simulation time 126368545468 ps
CPU time 459.68 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:56:56 PM PST 24
Peak memory 215948 kb
Host smart-0ca73cd9-2fd7-492d-a5b4-d67a4f6dc237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784888586 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1784888586
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3979677564
Short name T572
Test name
Test status
Simulation time 1371585502 ps
CPU time 2.94 seconds
Started Jan 03 12:48:56 PM PST 24
Finished Jan 03 12:49:20 PM PST 24
Peak memory 198716 kb
Host smart-b21f8c73-f74a-4e29-8222-63471a5c15b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979677564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3979677564
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.4149402424
Short name T814
Test name
Test status
Simulation time 83977221617 ps
CPU time 59.87 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:49:55 PM PST 24
Peak memory 200108 kb
Host smart-b56c1013-3586-45cd-8485-89a948c8c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149402424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.4149402424
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3999361499
Short name T844
Test name
Test status
Simulation time 50788745334 ps
CPU time 42.89 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 200156 kb
Host smart-10771f1f-8929-4d5b-913e-c86c9b31d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999361499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3999361499
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1882675293
Short name T318
Test name
Test status
Simulation time 13864371099 ps
CPU time 21.75 seconds
Started Jan 03 12:50:05 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 200184 kb
Host smart-ba2a908d-c81a-4bba-ae85-a3bdb9854d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882675293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1882675293
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3083705723
Short name T854
Test name
Test status
Simulation time 29788441549 ps
CPU time 13.16 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 199892 kb
Host smart-01ce10e1-dc3e-4b23-9543-20b19c0954b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083705723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3083705723
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3183337255
Short name T909
Test name
Test status
Simulation time 39009859889 ps
CPU time 14.55 seconds
Started Jan 03 12:51:22 PM PST 24
Finished Jan 03 12:51:52 PM PST 24
Peak memory 199768 kb
Host smart-28f7fec8-5d24-4c80-98ee-c4315c758606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183337255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3183337255
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2708429772
Short name T157
Test name
Test status
Simulation time 15618825866 ps
CPU time 22.92 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 199424 kb
Host smart-402156bf-2dcd-450f-a65d-a8847f706050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708429772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2708429772
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.277769296
Short name T250
Test name
Test status
Simulation time 8050472449 ps
CPU time 11.85 seconds
Started Jan 03 12:49:48 PM PST 24
Finished Jan 03 12:50:13 PM PST 24
Peak memory 198256 kb
Host smart-49fa7877-f8f1-4bbf-bb60-dff44a9b3d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277769296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.277769296
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3037452025
Short name T185
Test name
Test status
Simulation time 115010762798 ps
CPU time 48.09 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:50:50 PM PST 24
Peak memory 200096 kb
Host smart-9fdc9b49-eee0-4fd5-987c-e99ebba6f643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037452025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3037452025
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1299132205
Short name T505
Test name
Test status
Simulation time 23653191 ps
CPU time 0.62 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:49:23 PM PST 24
Peak memory 195560 kb
Host smart-d7d492e8-a6aa-4be5-baa2-f2c58308f03f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299132205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1299132205
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3610891234
Short name T1100
Test name
Test status
Simulation time 164966240377 ps
CPU time 77.37 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:50:26 PM PST 24
Peak memory 200052 kb
Host smart-7ede993d-3d67-42fe-82da-779de05fdcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610891234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3610891234
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1718902305
Short name T1085
Test name
Test status
Simulation time 36118040907 ps
CPU time 16.6 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:49:15 PM PST 24
Peak memory 198524 kb
Host smart-eec16735-dcaf-4bb6-97dc-0de3c0bd9235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718902305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1718902305
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.2335320612
Short name T837
Test name
Test status
Simulation time 202306463381 ps
CPU time 197.31 seconds
Started Jan 03 12:48:59 PM PST 24
Finished Jan 03 12:52:36 PM PST 24
Peak memory 200156 kb
Host smart-a7b9ced1-6dcf-408f-94a6-3cfbef43d26f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335320612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2335320612
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1352394064
Short name T677
Test name
Test status
Simulation time 77106194898 ps
CPU time 253.95 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:53:20 PM PST 24
Peak memory 200188 kb
Host smart-4f083f48-859a-4ff7-997e-c4dbdae9848e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352394064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1352394064
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.907859994
Short name T883
Test name
Test status
Simulation time 4222906016 ps
CPU time 8.28 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 198348 kb
Host smart-24555fd5-425c-48bc-8c33-e121721e41c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907859994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.907859994
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.4289646622
Short name T1103
Test name
Test status
Simulation time 34091537978 ps
CPU time 52.02 seconds
Started Jan 03 12:48:54 PM PST 24
Finished Jan 03 12:50:08 PM PST 24
Peak memory 198888 kb
Host smart-61d61d05-a870-4f2f-83f0-4cd7f829557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289646622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.4289646622
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2439831933
Short name T535
Test name
Test status
Simulation time 16336028736 ps
CPU time 221.75 seconds
Started Jan 03 12:48:56 PM PST 24
Finished Jan 03 12:52:59 PM PST 24
Peak memory 200128 kb
Host smart-a9b88e31-886e-44d9-bf4b-2ae04f9191dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439831933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2439831933
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3251809485
Short name T827
Test name
Test status
Simulation time 2989246268 ps
CPU time 13.37 seconds
Started Jan 03 12:48:42 PM PST 24
Finished Jan 03 12:49:21 PM PST 24
Peak memory 198608 kb
Host smart-8f4f6011-faf0-423a-8b58-406a35f5df11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3251809485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3251809485
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2151802284
Short name T1117
Test name
Test status
Simulation time 140709599990 ps
CPU time 228.77 seconds
Started Jan 03 12:48:59 PM PST 24
Finished Jan 03 12:53:08 PM PST 24
Peak memory 200136 kb
Host smart-332cb422-7b86-4416-91ea-f9938501bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151802284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2151802284
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2073961015
Short name T1133
Test name
Test status
Simulation time 1599683207 ps
CPU time 1.72 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 195560 kb
Host smart-99a0e4c8-c648-49e3-999b-671fc1dfa59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073961015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2073961015
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.174246002
Short name T524
Test name
Test status
Simulation time 285087653 ps
CPU time 1.44 seconds
Started Jan 03 12:49:08 PM PST 24
Finished Jan 03 12:49:27 PM PST 24
Peak memory 198660 kb
Host smart-8758d568-43a8-4a3d-9860-bcfa163f7c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174246002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.174246002
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.331312262
Short name T393
Test name
Test status
Simulation time 193021341851 ps
CPU time 711.85 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 01:01:10 PM PST 24
Peak memory 226440 kb
Host smart-d3862642-4be3-4f2b-a61b-859eb0b1efcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331312262 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.331312262
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.95748133
Short name T557
Test name
Test status
Simulation time 996993832 ps
CPU time 2.99 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 198020 kb
Host smart-10c751c6-9bff-49d6-b6ec-7bb51ae52b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95748133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.95748133
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2710977221
Short name T189
Test name
Test status
Simulation time 57283490331 ps
CPU time 27.53 seconds
Started Jan 03 12:48:59 PM PST 24
Finished Jan 03 12:49:46 PM PST 24
Peak memory 200136 kb
Host smart-6d69112b-4bf2-4369-a128-ca3c652bf223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710977221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2710977221
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1993591097
Short name T380
Test name
Test status
Simulation time 130139419958 ps
CPU time 30.69 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 200048 kb
Host smart-70c9530c-793d-499b-ae39-b4b2eb3831bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993591097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1993591097
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3046140161
Short name T332
Test name
Test status
Simulation time 43663757242 ps
CPU time 35.4 seconds
Started Jan 03 12:50:23 PM PST 24
Finished Jan 03 12:51:21 PM PST 24
Peak memory 200252 kb
Host smart-4fa438c8-d7b9-4609-aaa6-89fc66f57faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046140161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3046140161
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2980696670
Short name T1128
Test name
Test status
Simulation time 47237757146 ps
CPU time 20.99 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 12:51:58 PM PST 24
Peak memory 199288 kb
Host smart-3b8ac7fd-af81-4d87-949c-4e91a9017d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980696670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2980696670
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1068516191
Short name T645
Test name
Test status
Simulation time 7877612224 ps
CPU time 12.23 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 199988 kb
Host smart-b96043d2-1968-4236-a7a5-a4d698b3cfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068516191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1068516191
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3789497604
Short name T197
Test name
Test status
Simulation time 170837702024 ps
CPU time 72.23 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:51:31 PM PST 24
Peak memory 200240 kb
Host smart-c5112a2b-78fb-486d-99f0-6cdb2bed7bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789497604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3789497604
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3747009361
Short name T614
Test name
Test status
Simulation time 194257496403 ps
CPU time 86.32 seconds
Started Jan 03 12:49:52 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 199672 kb
Host smart-25a10450-3cb0-48b3-bd0c-fa84c8ca9805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747009361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3747009361
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3018080035
Short name T323
Test name
Test status
Simulation time 70500511779 ps
CPU time 31.23 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:51:27 PM PST 24
Peak memory 200196 kb
Host smart-6f048828-f5ea-45fc-9643-cbda7d3701dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018080035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3018080035
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.4134353477
Short name T638
Test name
Test status
Simulation time 13174205 ps
CPU time 0.55 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:49:35 PM PST 24
Peak memory 194668 kb
Host smart-6b145260-f52d-4126-9022-da272a0422ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134353477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.4134353477
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.262803008
Short name T426
Test name
Test status
Simulation time 60742953279 ps
CPU time 87.45 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 200204 kb
Host smart-f225134b-3b15-4daf-b8ca-54bdd8163040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262803008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.262803008
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3735395749
Short name T210
Test name
Test status
Simulation time 109825501617 ps
CPU time 66.23 seconds
Started Jan 03 12:48:46 PM PST 24
Finished Jan 03 12:50:16 PM PST 24
Peak memory 200212 kb
Host smart-15083a89-da5b-4f8f-b155-440d3085b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735395749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3735395749
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1606665318
Short name T942
Test name
Test status
Simulation time 2139766764796 ps
CPU time 1440.57 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 01:13:33 PM PST 24
Peak memory 199804 kb
Host smart-cec21e3a-0dc2-43e0-8567-5ef4f7c0a4ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606665318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1606665318
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2612899904
Short name T111
Test name
Test status
Simulation time 96491611347 ps
CPU time 696.85 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 01:00:53 PM PST 24
Peak memory 200160 kb
Host smart-7ce534a0-e28b-477f-b956-9bf9c49f2d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612899904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2612899904
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.578305635
Short name T21
Test name
Test status
Simulation time 10156088127 ps
CPU time 19.25 seconds
Started Jan 03 12:49:00 PM PST 24
Finished Jan 03 12:49:39 PM PST 24
Peak memory 198604 kb
Host smart-f258f030-b837-429b-9f9e-c9802c3591d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578305635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.578305635
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1147515870
Short name T795
Test name
Test status
Simulation time 104660154539 ps
CPU time 44.1 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 197220 kb
Host smart-2541914d-138d-4ad7-9762-170f83dc6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147515870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1147515870
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.776873730
Short name T1198
Test name
Test status
Simulation time 9580898790 ps
CPU time 235.43 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 12:53:39 PM PST 24
Peak memory 200172 kb
Host smart-15fa7405-e238-4b72-bd15-18ba30bffbf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776873730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.776873730
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.166526270
Short name T957
Test name
Test status
Simulation time 4038657060 ps
CPU time 30.94 seconds
Started Jan 03 12:49:07 PM PST 24
Finished Jan 03 12:49:56 PM PST 24
Peak memory 198572 kb
Host smart-3e9cf639-8062-413e-ba7a-d22d72dc7519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166526270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.166526270
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3081676467
Short name T830
Test name
Test status
Simulation time 13530011061 ps
CPU time 12.19 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 200112 kb
Host smart-85e4ad62-c938-4780-a107-b4733409dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081676467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3081676467
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3033467275
Short name T541
Test name
Test status
Simulation time 33596294434 ps
CPU time 28.52 seconds
Started Jan 03 12:48:49 PM PST 24
Finished Jan 03 12:49:40 PM PST 24
Peak memory 195652 kb
Host smart-d6e3206e-8515-41f3-bcc6-d3fcf354ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033467275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3033467275
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1002975250
Short name T868
Test name
Test status
Simulation time 5353676860 ps
CPU time 11.94 seconds
Started Jan 03 12:49:01 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 199576 kb
Host smart-ae5a3f3d-4552-403d-9036-ab66bff12d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002975250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1002975250
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3158371917
Short name T399
Test name
Test status
Simulation time 736412471299 ps
CPU time 387.98 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:56:13 PM PST 24
Peak memory 211904 kb
Host smart-ffce5935-3635-4b16-bf27-f4a9f7302d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158371917 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3158371917
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.858756812
Short name T686
Test name
Test status
Simulation time 1312874220 ps
CPU time 4.36 seconds
Started Jan 03 12:49:19 PM PST 24
Finished Jan 03 12:49:41 PM PST 24
Peak memory 198680 kb
Host smart-35fd80b4-9b29-4964-bac5-1603208bb6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858756812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.858756812
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3218005824
Short name T422
Test name
Test status
Simulation time 16647619703 ps
CPU time 15.31 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:23 PM PST 24
Peak memory 200284 kb
Host smart-c01b6740-816a-4d49-b5e4-d8b89abd26c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218005824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3218005824
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2746987515
Short name T242
Test name
Test status
Simulation time 27608761797 ps
CPU time 15.48 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:25 PM PST 24
Peak memory 199812 kb
Host smart-50bda89c-a7f1-4476-8929-871e25742759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746987515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2746987515
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3201662659
Short name T983
Test name
Test status
Simulation time 47416681875 ps
CPU time 44.94 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 200252 kb
Host smart-1a0c9b75-80cf-4bbc-ad80-a1d8ff9f5fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201662659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3201662659
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.950633441
Short name T1146
Test name
Test status
Simulation time 123856604784 ps
CPU time 255.08 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:54:50 PM PST 24
Peak memory 200220 kb
Host smart-abebac9f-58d3-44de-8592-15866953fa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950633441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.950633441
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3696830844
Short name T233
Test name
Test status
Simulation time 309392664444 ps
CPU time 52.34 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:50:47 PM PST 24
Peak memory 200200 kb
Host smart-a02f8f71-4cea-431e-8d7f-372c2b8b6fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696830844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3696830844
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4069520548
Short name T170
Test name
Test status
Simulation time 310453408853 ps
CPU time 135.21 seconds
Started Jan 03 12:50:01 PM PST 24
Finished Jan 03 12:52:40 PM PST 24
Peak memory 200252 kb
Host smart-cd2294be-64a8-42c9-be2e-a2e85cfb284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069520548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4069520548
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3367802363
Short name T357
Test name
Test status
Simulation time 36761214573 ps
CPU time 18.31 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 200148 kb
Host smart-23c89f24-8a4b-4fb8-9df5-0a1dd4df7451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367802363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3367802363
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2240217191
Short name T690
Test name
Test status
Simulation time 24791937620 ps
CPU time 37.06 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 199856 kb
Host smart-4350f040-24b0-4cc8-bc09-4defd800b564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240217191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2240217191
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3079794672
Short name T1095
Test name
Test status
Simulation time 7297669769 ps
CPU time 11.94 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:50:29 PM PST 24
Peak memory 199532 kb
Host smart-1ef2b24a-536a-438f-a50c-22eba2f3e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079794672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3079794672
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.211396030
Short name T191
Test name
Test status
Simulation time 25196509974 ps
CPU time 44.27 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 200088 kb
Host smart-706e7b99-e403-451d-9446-16b35839684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211396030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.211396030
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4091307827
Short name T715
Test name
Test status
Simulation time 13971809 ps
CPU time 0.52 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 194508 kb
Host smart-340cbeae-34f2-4f55-8b83-620ce69997ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091307827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4091307827
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2152774037
Short name T544
Test name
Test status
Simulation time 88284571673 ps
CPU time 42.12 seconds
Started Jan 03 12:49:13 PM PST 24
Finished Jan 03 12:50:14 PM PST 24
Peak memory 200116 kb
Host smart-291cbe33-9ac1-4ca0-a176-af61c7f7b15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152774037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2152774037
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.4287177294
Short name T377
Test name
Test status
Simulation time 26673148947 ps
CPU time 47.3 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:50:14 PM PST 24
Peak memory 200164 kb
Host smart-4fb18a3f-9c20-4312-8847-0388f9339457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287177294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4287177294
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.894076312
Short name T232
Test name
Test status
Simulation time 46919523903 ps
CPU time 14.79 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:49:41 PM PST 24
Peak memory 200212 kb
Host smart-8e2eaf86-4b3b-4f57-a816-d509ffbb0a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894076312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.894076312
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1152106097
Short name T665
Test name
Test status
Simulation time 84800047270 ps
CPU time 59.41 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 198188 kb
Host smart-be1fec31-e8de-4914-b5aa-4e848223ac8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152106097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1152106097
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1059612429
Short name T926
Test name
Test status
Simulation time 87892759181 ps
CPU time 422.32 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:56:39 PM PST 24
Peak memory 200220 kb
Host smart-87971f84-4282-448b-b061-e437a3241291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059612429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1059612429
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4065903358
Short name T556
Test name
Test status
Simulation time 8813685366 ps
CPU time 14.06 seconds
Started Jan 03 12:49:24 PM PST 24
Finished Jan 03 12:49:56 PM PST 24
Peak memory 199432 kb
Host smart-2276be7e-81dd-44a1-a24e-00018f5c14d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065903358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4065903358
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.912066905
Short name T885
Test name
Test status
Simulation time 49420893735 ps
CPU time 76.55 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 200056 kb
Host smart-fc22c454-bce9-4e34-b33e-dba67c8c3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912066905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.912066905
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1026384220
Short name T711
Test name
Test status
Simulation time 5482011562 ps
CPU time 152.88 seconds
Started Jan 03 12:49:04 PM PST 24
Finished Jan 03 12:51:56 PM PST 24
Peak memory 200136 kb
Host smart-e15e9382-998c-4584-8dd2-e040ff12781a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026384220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1026384220
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2764110495
Short name T1179
Test name
Test status
Simulation time 921002398 ps
CPU time 2.56 seconds
Started Jan 03 12:49:32 PM PST 24
Finished Jan 03 12:49:50 PM PST 24
Peak memory 198324 kb
Host smart-83a75cf5-8995-4d50-9a1d-38f8c9844dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2764110495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2764110495
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3642343655
Short name T823
Test name
Test status
Simulation time 87528564373 ps
CPU time 34.31 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:50:14 PM PST 24
Peak memory 199852 kb
Host smart-cc85fff2-62f9-4569-8799-2261e658791a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642343655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3642343655
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2409643720
Short name T504
Test name
Test status
Simulation time 1886962239 ps
CPU time 2.78 seconds
Started Jan 03 12:49:24 PM PST 24
Finished Jan 03 12:49:44 PM PST 24
Peak memory 195548 kb
Host smart-ce64a701-ef39-47ff-9557-13b59dba0710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409643720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2409643720
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3772099847
Short name T1130
Test name
Test status
Simulation time 5719300008 ps
CPU time 8.54 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 12:49:32 PM PST 24
Peak memory 199012 kb
Host smart-c4e3564f-72eb-4de1-ade2-eb1001753f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772099847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3772099847
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.734691201
Short name T704
Test name
Test status
Simulation time 80007429245 ps
CPU time 84.1 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 200120 kb
Host smart-e88ed784-77e5-45f1-a377-e1be0b0599d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734691201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.734691201
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.4060689892
Short name T820
Test name
Test status
Simulation time 839171931 ps
CPU time 2.74 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 198168 kb
Host smart-1f8da761-c183-4a4a-90e8-50def32e5c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060689892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.4060689892
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2948554020
Short name T1185
Test name
Test status
Simulation time 85101207639 ps
CPU time 39.22 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:50:01 PM PST 24
Peak memory 200088 kb
Host smart-bd5c8656-23cf-4fb6-8930-45fed0f714b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948554020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2948554020
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2991911951
Short name T275
Test name
Test status
Simulation time 28270641208 ps
CPU time 44.7 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 199608 kb
Host smart-7f322488-6716-49b8-9ed8-257a8a18db8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991911951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2991911951
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.181733848
Short name T400
Test name
Test status
Simulation time 73051304371 ps
CPU time 128.18 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:52:01 PM PST 24
Peak memory 199900 kb
Host smart-bc44d828-8b00-421d-8ea1-1df5da3a92fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181733848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.181733848
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3303997880
Short name T893
Test name
Test status
Simulation time 13194187830 ps
CPU time 23.37 seconds
Started Jan 03 12:50:08 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 200132 kb
Host smart-93649534-e02c-4958-931d-803ecf2d4529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303997880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3303997880
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2715335986
Short name T257
Test name
Test status
Simulation time 12369713297 ps
CPU time 28.1 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:50:35 PM PST 24
Peak memory 200196 kb
Host smart-a9a08c8f-3f03-4b53-be45-9f551f8ef805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715335986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2715335986
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.148689090
Short name T1107
Test name
Test status
Simulation time 67155493929 ps
CPU time 51.48 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 200228 kb
Host smart-a1d32def-859e-4bae-9fe1-8acd5bcbedbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148689090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.148689090
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.397564478
Short name T311
Test name
Test status
Simulation time 21524243817 ps
CPU time 22.87 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:15 PM PST 24
Peak memory 200192 kb
Host smart-dd18415d-d099-498b-b986-68fae04e5f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397564478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.397564478
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2936866155
Short name T1097
Test name
Test status
Simulation time 20117372978 ps
CPU time 17.54 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 199716 kb
Host smart-367fadfc-1866-4d4e-888c-51fb9c672d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936866155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2936866155
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1683243378
Short name T329
Test name
Test status
Simulation time 22539354467 ps
CPU time 36.31 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 12:50:23 PM PST 24
Peak memory 200044 kb
Host smart-48894bfd-40ef-479e-8ca9-d9e2b36d981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683243378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1683243378
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1791268584
Short name T825
Test name
Test status
Simulation time 12264522 ps
CPU time 0.57 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 195592 kb
Host smart-2d2fad42-04ab-4a7e-b8f6-6fe48d9fe08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791268584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1791268584
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.4023153420
Short name T1027
Test name
Test status
Simulation time 160913215606 ps
CPU time 267.28 seconds
Started Jan 03 12:48:07 PM PST 24
Finished Jan 03 12:53:04 PM PST 24
Peak memory 200192 kb
Host smart-e5554802-728a-49f4-b8ff-236dd5f8f4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023153420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4023153420
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.382233603
Short name T334
Test name
Test status
Simulation time 51432240898 ps
CPU time 45.43 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:49:25 PM PST 24
Peak memory 199424 kb
Host smart-c695f461-19e3-4453-8bb6-9fc83fa1913b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382233603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.382233603
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1428492149
Short name T604
Test name
Test status
Simulation time 280091532264 ps
CPU time 106.07 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 200124 kb
Host smart-9584bf76-f09f-4ad6-af7f-188506279e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428492149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1428492149
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.4032933031
Short name T699
Test name
Test status
Simulation time 122371986951 ps
CPU time 321.16 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:54:01 PM PST 24
Peak memory 200232 kb
Host smart-a10b48aa-b360-4227-80ce-e7e3d1d901ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032933031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.4032933031
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3508517194
Short name T1017
Test name
Test status
Simulation time 10538642123 ps
CPU time 6.13 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:55 PM PST 24
Peak memory 199252 kb
Host smart-5d221e00-dfd2-4bc0-8b9f-6b5e20392f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508517194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3508517194
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2178186131
Short name T180
Test name
Test status
Simulation time 27746513834 ps
CPU time 25.95 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 199428 kb
Host smart-3536b6d1-c7f3-4687-8110-01c8db9a05eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178186131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2178186131
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1419542583
Short name T612
Test name
Test status
Simulation time 7472000958 ps
CPU time 157.86 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 200304 kb
Host smart-5ef88fc9-342b-45c9-8617-30a393360075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419542583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1419542583
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3372636593
Short name T407
Test name
Test status
Simulation time 156058953273 ps
CPU time 206.56 seconds
Started Jan 03 12:47:55 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 199368 kb
Host smart-84853e70-5a55-4a89-afd1-4e3450952986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372636593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3372636593
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2981387221
Short name T742
Test name
Test status
Simulation time 3941628381 ps
CPU time 1.96 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 196048 kb
Host smart-c75a0f70-7744-4835-9eb7-90d71affac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981387221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2981387221
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1081775120
Short name T84
Test name
Test status
Simulation time 37737043 ps
CPU time 0.8 seconds
Started Jan 03 12:48:43 PM PST 24
Finished Jan 03 12:49:08 PM PST 24
Peak memory 217672 kb
Host smart-086f4ae6-39b7-4b1b-821b-d889e40d41e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081775120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1081775120
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.941123217
Short name T1195
Test name
Test status
Simulation time 497680548 ps
CPU time 2.52 seconds
Started Jan 03 12:48:28 PM PST 24
Finished Jan 03 12:49:01 PM PST 24
Peak memory 198496 kb
Host smart-c06ac70d-3ecb-4521-8335-5613bbbf8e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941123217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.941123217
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3684974846
Short name T1006
Test name
Test status
Simulation time 617620499554 ps
CPU time 443.42 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:56:07 PM PST 24
Peak memory 200128 kb
Host smart-3df72c5b-e443-46ab-8a57-49342ea6e909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684974846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3684974846
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1102933885
Short name T731
Test name
Test status
Simulation time 56078163574 ps
CPU time 335.07 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:54:21 PM PST 24
Peak memory 215816 kb
Host smart-5c8825ea-8f3d-493d-8ffc-a6daec232b9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102933885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1102933885
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2497899400
Short name T671
Test name
Test status
Simulation time 7101732040 ps
CPU time 21.43 seconds
Started Jan 03 12:48:31 PM PST 24
Finished Jan 03 12:49:18 PM PST 24
Peak memory 199544 kb
Host smart-df5af0bc-a6b9-46b9-9b27-46b2c3941785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497899400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2497899400
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.684671156
Short name T962
Test name
Test status
Simulation time 133282437024 ps
CPU time 53.05 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:49:34 PM PST 24
Peak memory 200112 kb
Host smart-9c7991d4-a872-49d9-9951-add28962293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684671156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.684671156
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2493344098
Short name T640
Test name
Test status
Simulation time 15257422 ps
CPU time 0.54 seconds
Started Jan 03 12:48:44 PM PST 24
Finished Jan 03 12:49:16 PM PST 24
Peak memory 195560 kb
Host smart-d1df6a2b-8a02-4713-a966-17443cd06e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493344098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2493344098
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1463906997
Short name T440
Test name
Test status
Simulation time 201906982497 ps
CPU time 84.08 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:50:33 PM PST 24
Peak memory 200112 kb
Host smart-82cf7169-7b2c-4114-a633-2b62552f04ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463906997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1463906997
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.46181537
Short name T371
Test name
Test status
Simulation time 69461264533 ps
CPU time 30.3 seconds
Started Jan 03 12:48:57 PM PST 24
Finished Jan 03 12:49:51 PM PST 24
Peak memory 200228 kb
Host smart-3c220344-9a46-4334-8179-e7c7733187f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46181537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.46181537
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3449452424
Short name T229
Test name
Test status
Simulation time 13232176289 ps
CPU time 22.14 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 12:49:40 PM PST 24
Peak memory 200164 kb
Host smart-877207be-20cf-4c16-b977-6e7f503405cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449452424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3449452424
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.1052100961
Short name T842
Test name
Test status
Simulation time 187718261212 ps
CPU time 100.29 seconds
Started Jan 03 12:49:13 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 200160 kb
Host smart-9756c1c1-7ecd-4ce5-b84b-5bff7b382547
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052100961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1052100961
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3428348463
Short name T826
Test name
Test status
Simulation time 126596485492 ps
CPU time 503.66 seconds
Started Jan 03 12:49:11 PM PST 24
Finished Jan 03 12:57:52 PM PST 24
Peak memory 200264 kb
Host smart-150516c4-19af-4bd1-a50d-160fa52f52d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428348463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3428348463
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2536840646
Short name T716
Test name
Test status
Simulation time 6075899672 ps
CPU time 18.16 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:49:24 PM PST 24
Peak memory 198812 kb
Host smart-ea83400d-3438-469f-bcbe-2e6b7bfcd40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536840646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2536840646
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1332626510
Short name T653
Test name
Test status
Simulation time 134251394180 ps
CPU time 77.09 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 200408 kb
Host smart-1beec179-4a05-461a-968d-be80b5d0e0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332626510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1332626510
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1823250344
Short name T901
Test name
Test status
Simulation time 21830228093 ps
CPU time 340.11 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 12:54:55 PM PST 24
Peak memory 200048 kb
Host smart-cd0f3e75-6588-459f-85a7-6ae93f972bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823250344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1823250344
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3932701740
Short name T1043
Test name
Test status
Simulation time 55425485529 ps
CPU time 93.33 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 200044 kb
Host smart-7961b792-8a2f-4503-89a5-0795ee7c2062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932701740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3932701740
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3314850378
Short name T421
Test name
Test status
Simulation time 32922902252 ps
CPU time 13.42 seconds
Started Jan 03 12:49:01 PM PST 24
Finished Jan 03 12:49:35 PM PST 24
Peak memory 195964 kb
Host smart-567fcd2f-8994-4512-b2b7-34aa78b24f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314850378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3314850378
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3156096185
Short name T829
Test name
Test status
Simulation time 525098623 ps
CPU time 0.84 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 198300 kb
Host smart-381588d9-d713-4adc-9021-ba8c9716833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156096185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3156096185
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.218077151
Short name T245
Test name
Test status
Simulation time 564892534160 ps
CPU time 468.37 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:56:59 PM PST 24
Peak memory 227628 kb
Host smart-1c7bfaa0-4844-45ba-88da-6454287e19d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218077151 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.218077151
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3632736286
Short name T991
Test name
Test status
Simulation time 456371154 ps
CPU time 1.65 seconds
Started Jan 03 12:49:01 PM PST 24
Finished Jan 03 12:49:24 PM PST 24
Peak memory 198028 kb
Host smart-210f6450-0ffe-4341-808a-94e9be14dcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632736286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3632736286
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_alert_test.422889020
Short name T554
Test name
Test status
Simulation time 35956633 ps
CPU time 0.54 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 195648 kb
Host smart-da5401b7-b03a-4b2e-9acd-e045147572ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422889020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.422889020
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2269354363
Short name T600
Test name
Test status
Simulation time 104641772107 ps
CPU time 150.05 seconds
Started Jan 03 12:49:06 PM PST 24
Finished Jan 03 12:51:54 PM PST 24
Peak memory 200136 kb
Host smart-aacbfe60-679c-402a-b3a6-40c4d4c74f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269354363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2269354363
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3031860452
Short name T655
Test name
Test status
Simulation time 199126550097 ps
CPU time 80.39 seconds
Started Jan 03 12:49:19 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 200060 kb
Host smart-56d29938-1b22-4835-8c35-95fbd4dc179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031860452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3031860452
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.122064259
Short name T225
Test name
Test status
Simulation time 52380133240 ps
CPU time 22.05 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:49:57 PM PST 24
Peak memory 200132 kb
Host smart-6b91b1e6-9165-42e5-84cc-ae378073f668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122064259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.122064259
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2575202079
Short name T755
Test name
Test status
Simulation time 122523041656 ps
CPU time 171.72 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:52:18 PM PST 24
Peak memory 200144 kb
Host smart-7bb67b08-d749-4910-a5c0-d4d733fe6f8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575202079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2575202079
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2225725074
Short name T931
Test name
Test status
Simulation time 132725582741 ps
CPU time 572.15 seconds
Started Jan 03 12:49:07 PM PST 24
Finished Jan 03 12:58:57 PM PST 24
Peak memory 200132 kb
Host smart-64d4f5a5-a255-41c9-8b0d-d3f61b2866e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225725074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2225725074
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.906101335
Short name T949
Test name
Test status
Simulation time 2819956966 ps
CPU time 2.02 seconds
Started Jan 03 12:49:05 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 195860 kb
Host smart-996a9324-a64d-4d45-8d3b-a45723e6975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906101335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.906101335
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1250693854
Short name T1078
Test name
Test status
Simulation time 125249876626 ps
CPU time 222.87 seconds
Started Jan 03 12:48:57 PM PST 24
Finished Jan 03 12:53:00 PM PST 24
Peak memory 200220 kb
Host smart-dc0817ef-f7ac-4f47-aac9-2376ca443c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250693854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1250693854
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.660236283
Short name T575
Test name
Test status
Simulation time 9722257066 ps
CPU time 217.04 seconds
Started Jan 03 12:49:04 PM PST 24
Finished Jan 03 12:53:00 PM PST 24
Peak memory 200136 kb
Host smart-c40a262e-176e-45f1-9ab0-d4d6d4b15704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660236283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.660236283
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2033066889
Short name T1089
Test name
Test status
Simulation time 1262795875 ps
CPU time 11.75 seconds
Started Jan 03 12:49:07 PM PST 24
Finished Jan 03 12:49:36 PM PST 24
Peak memory 198460 kb
Host smart-13914fd4-6386-4907-b875-1d869cc10dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033066889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2033066889
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2176035468
Short name T903
Test name
Test status
Simulation time 3697313305 ps
CPU time 3.62 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 195864 kb
Host smart-1f9e7145-6d92-45a4-8983-6489f1187586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176035468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2176035468
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4073595781
Short name T785
Test name
Test status
Simulation time 672124184 ps
CPU time 2.77 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 199432 kb
Host smart-ff5a88bf-477f-4a16-801e-c5257c348dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073595781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4073595781
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3857117766
Short name T630
Test name
Test status
Simulation time 535094954540 ps
CPU time 2106.32 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 01:24:12 PM PST 24
Peak memory 209476 kb
Host smart-e665e81f-9c87-4770-93f6-9b18c06fe0a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857117766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3857117766
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1427416826
Short name T1202
Test name
Test status
Simulation time 34354204538 ps
CPU time 424 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:56:27 PM PST 24
Peak memory 208456 kb
Host smart-a55fe99c-dec9-4d5b-a0f5-1439d5fb1493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427416826 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1427416826
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1759329125
Short name T744
Test name
Test status
Simulation time 1270546244 ps
CPU time 1.39 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 12:49:45 PM PST 24
Peak memory 198348 kb
Host smart-9df4ac2e-bfbf-4777-9b84-d8c6bcbcff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759329125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1759329125
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2982269665
Short name T773
Test name
Test status
Simulation time 7192787235 ps
CPU time 11.63 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 12:49:30 PM PST 24
Peak memory 198372 kb
Host smart-910ca051-a50e-4d5e-9ba0-8f7f2fb6386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982269665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2982269665
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2923426095
Short name T1164
Test name
Test status
Simulation time 23192533 ps
CPU time 0.52 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:49:27 PM PST 24
Peak memory 194552 kb
Host smart-9e7a73f6-4092-472b-9a1d-cd6064a84050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923426095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2923426095
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.987878747
Short name T939
Test name
Test status
Simulation time 112651601011 ps
CPU time 41.14 seconds
Started Jan 03 12:49:23 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 200232 kb
Host smart-a1410053-ea16-4b5a-9cea-b1efbe944857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987878747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.987878747
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.746825977
Short name T775
Test name
Test status
Simulation time 337394842898 ps
CPU time 142.86 seconds
Started Jan 03 12:49:04 PM PST 24
Finished Jan 03 12:51:46 PM PST 24
Peak memory 200068 kb
Host smart-246561f3-bb3a-47e6-951f-2817300d8b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746825977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.746825977
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_intr.4063316432
Short name T179
Test name
Test status
Simulation time 294178448443 ps
CPU time 448.04 seconds
Started Jan 03 12:48:59 PM PST 24
Finished Jan 03 12:56:47 PM PST 24
Peak memory 199568 kb
Host smart-5c1d85fc-c2d7-4067-aad4-76a1e2f60073
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063316432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4063316432
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1524194122
Short name T735
Test name
Test status
Simulation time 53481817756 ps
CPU time 89.35 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 200164 kb
Host smart-2854a8e6-bfbf-475d-8b73-8980d39ca4f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524194122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1524194122
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1098007341
Short name T496
Test name
Test status
Simulation time 7166080939 ps
CPU time 13.95 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:49:27 PM PST 24
Peak memory 197484 kb
Host smart-586336a7-6838-433c-9567-8080e3aac180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098007341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1098007341
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1837122423
Short name T559
Test name
Test status
Simulation time 108205989705 ps
CPU time 102.87 seconds
Started Jan 03 12:49:21 PM PST 24
Finished Jan 03 12:51:21 PM PST 24
Peak memory 208592 kb
Host smart-9b8bb008-3daa-4081-b77f-ebfca40191c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837122423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1837122423
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1229793934
Short name T622
Test name
Test status
Simulation time 18517555318 ps
CPU time 769.59 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 199860 kb
Host smart-e8484488-4f2c-47f3-b4b9-eb633c513ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229793934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1229793934
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1233001858
Short name T1114
Test name
Test status
Simulation time 47649910597 ps
CPU time 91.94 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 199008 kb
Host smart-c03056e5-2a6a-47ec-a662-74bf00979f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233001858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1233001858
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3218510303
Short name T627
Test name
Test status
Simulation time 38263232610 ps
CPU time 59.53 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 195584 kb
Host smart-426cfb29-a8d3-4cba-b68d-ff8b8641d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218510303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3218510303
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2185370811
Short name T452
Test name
Test status
Simulation time 473295036 ps
CPU time 1.96 seconds
Started Jan 03 12:49:13 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 199044 kb
Host smart-f7869bd8-b610-4b5f-ab08-fdd07f560742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185370811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2185370811
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2953912673
Short name T555
Test name
Test status
Simulation time 82377664536 ps
CPU time 35.87 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 12:49:54 PM PST 24
Peak memory 200120 kb
Host smart-ce4c4855-5b2e-4d5d-8b44-ca2bf7ad9758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953912673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2953912673
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3354844595
Short name T453
Test name
Test status
Simulation time 1075486606 ps
CPU time 1.8 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 198044 kb
Host smart-8df6070f-9357-480b-b272-77ade7d61f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354844595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3354844595
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1934988816
Short name T551
Test name
Test status
Simulation time 225246468103 ps
CPU time 125.45 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:51:37 PM PST 24
Peak memory 200128 kb
Host smart-6ed056d8-f12a-44fd-94a4-95be0724861c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934988816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1934988816
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.877380597
Short name T911
Test name
Test status
Simulation time 16798100 ps
CPU time 0.55 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 12:49:24 PM PST 24
Peak memory 195604 kb
Host smart-2b81536c-1ab0-4d1b-8962-271de782fa67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877380597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.877380597
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1249570888
Short name T1094
Test name
Test status
Simulation time 182226369697 ps
CPU time 50.76 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 200260 kb
Host smart-3bc4668f-8d1c-4d98-87bd-d2c00e4492b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249570888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1249570888
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4211004080
Short name T378
Test name
Test status
Simulation time 143697432812 ps
CPU time 61.73 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 200028 kb
Host smart-3ad5e1c3-7439-4887-bc1f-393d893207a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211004080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4211004080
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1659715876
Short name T900
Test name
Test status
Simulation time 25905555347 ps
CPU time 46.5 seconds
Started Jan 03 12:48:54 PM PST 24
Finished Jan 03 12:50:02 PM PST 24
Peak memory 200124 kb
Host smart-da066f8c-1980-4165-ba86-6e5c5ec400d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659715876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1659715876
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.741932271
Short name T1129
Test name
Test status
Simulation time 65221254043 ps
CPU time 42.52 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 200248 kb
Host smart-1fb937f7-8a7f-43b8-9cab-5291fe3747cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741932271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.741932271
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1961052502
Short name T816
Test name
Test status
Simulation time 88264099312 ps
CPU time 213 seconds
Started Jan 03 12:49:07 PM PST 24
Finished Jan 03 12:52:58 PM PST 24
Peak memory 200228 kb
Host smart-0d5c74f8-4e77-461a-96eb-a7dbb03e01f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961052502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1961052502
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2909425190
Short name T528
Test name
Test status
Simulation time 1407691165 ps
CPU time 2.72 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:49:51 PM PST 24
Peak memory 196712 kb
Host smart-97b5b9b1-9d00-4797-9877-e246978ae692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909425190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2909425190
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.3426666524
Short name T107
Test name
Test status
Simulation time 24955445487 ps
CPU time 1293.07 seconds
Started Jan 03 12:49:07 PM PST 24
Finished Jan 03 01:10:58 PM PST 24
Peak memory 200136 kb
Host smart-0ef67c3b-86dc-44a1-a4d7-0a9876359cf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426666524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3426666524
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.4088261244
Short name T898
Test name
Test status
Simulation time 1481026118 ps
CPU time 0.69 seconds
Started Jan 03 12:49:07 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 195604 kb
Host smart-7a149c99-738c-4e76-90aa-7b43f54f5dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088261244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.4088261244
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2501684336
Short name T590
Test name
Test status
Simulation time 468528846 ps
CPU time 1.06 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 195496 kb
Host smart-6bf32ffe-bec8-41f2-89d8-bacb392d594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501684336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2501684336
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1195353855
Short name T863
Test name
Test status
Simulation time 506315748 ps
CPU time 1.28 seconds
Started Jan 03 12:48:57 PM PST 24
Finished Jan 03 12:49:19 PM PST 24
Peak memory 198296 kb
Host smart-048ca655-5c72-4576-8af6-1e60cc8683ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195353855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1195353855
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2401333972
Short name T889
Test name
Test status
Simulation time 281658039 ps
CPU time 1.28 seconds
Started Jan 03 12:49:19 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 196828 kb
Host smart-3c3cf6c8-372f-4273-aab4-c8731ccd8b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401333972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2401333972
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3748131747
Short name T1108
Test name
Test status
Simulation time 35036017510 ps
CPU time 65.81 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 200208 kb
Host smart-c02970eb-30d0-4579-b56b-e04cde70c385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748131747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3748131747
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2964560368
Short name T798
Test name
Test status
Simulation time 22107123 ps
CPU time 0.54 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:49:17 PM PST 24
Peak memory 195552 kb
Host smart-7da7adfe-7b74-4e80-856c-b9a0e949030f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964560368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2964560368
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2976988483
Short name T372
Test name
Test status
Simulation time 49234025894 ps
CPU time 20.71 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:49:56 PM PST 24
Peak memory 199364 kb
Host smart-4545e08f-e5e0-4f15-9bba-01056f254b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976988483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2976988483
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.904367941
Short name T1162
Test name
Test status
Simulation time 134112256625 ps
CPU time 29.64 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 12:49:53 PM PST 24
Peak memory 199152 kb
Host smart-c2408502-5ff3-43ce-9f60-9cffc0f07270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904367941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.904367941
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.951074049
Short name T697
Test name
Test status
Simulation time 2816454833384 ps
CPU time 1166.68 seconds
Started Jan 03 12:49:03 PM PST 24
Finished Jan 03 01:08:50 PM PST 24
Peak memory 200168 kb
Host smart-f42933b7-f92d-48e5-b13b-7d106668e0f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951074049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.951074049
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.4086602035
Short name T896
Test name
Test status
Simulation time 117557811262 ps
CPU time 896.82 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 01:04:46 PM PST 24
Peak memory 200140 kb
Host smart-0d3d6e3a-fb56-4342-8e61-4f10d8b9b846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4086602035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.4086602035
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2494069489
Short name T1101
Test name
Test status
Simulation time 7466959221 ps
CPU time 2.81 seconds
Started Jan 03 12:49:05 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 199240 kb
Host smart-e4e5760f-5eb0-40f1-980f-bcdc3e890b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494069489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2494069489
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3341831441
Short name T1019
Test name
Test status
Simulation time 24012773680 ps
CPU time 36.3 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:50:28 PM PST 24
Peak memory 199068 kb
Host smart-2dc4b516-03f6-4e85-a887-3c7b4aac823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341831441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3341831441
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.375447344
Short name T295
Test name
Test status
Simulation time 6662258586 ps
CPU time 94.95 seconds
Started Jan 03 12:48:59 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 200088 kb
Host smart-10ed5620-4f01-40d7-8575-94a4f0ed2582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375447344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.375447344
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1749300417
Short name T1020
Test name
Test status
Simulation time 1187255996 ps
CPU time 1.03 seconds
Started Jan 03 12:49:13 PM PST 24
Finished Jan 03 12:49:32 PM PST 24
Peak memory 195484 kb
Host smart-95418c62-705a-4e1c-8c25-c87bef5b205a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749300417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1749300417
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1402240105
Short name T293
Test name
Test status
Simulation time 69820305642 ps
CPU time 47.11 seconds
Started Jan 03 12:49:12 PM PST 24
Finished Jan 03 12:50:18 PM PST 24
Peak memory 200144 kb
Host smart-3ee9c486-a512-4222-92fd-f067ea640790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402240105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1402240105
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1889764899
Short name T617
Test name
Test status
Simulation time 46219134292 ps
CPU time 19.46 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 12:49:55 PM PST 24
Peak memory 195660 kb
Host smart-012b8b6b-3113-4152-983c-37e4b619bba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889764899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1889764899
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.505871581
Short name T723
Test name
Test status
Simulation time 931589069 ps
CPU time 4.26 seconds
Started Jan 03 12:49:05 PM PST 24
Finished Jan 03 12:49:28 PM PST 24
Peak memory 198916 kb
Host smart-bdef02c0-5921-4ca3-80ee-227d1ae2810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505871581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.505871581
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2701016207
Short name T100
Test name
Test status
Simulation time 179339320813 ps
CPU time 1523.58 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 01:14:58 PM PST 24
Peak memory 200168 kb
Host smart-acfa8a6e-1b66-4ce6-ba21-ce0787679e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701016207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2701016207
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1840965981
Short name T224
Test name
Test status
Simulation time 295013867122 ps
CPU time 719.27 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 01:01:27 PM PST 24
Peak memory 216684 kb
Host smart-1a8be1f2-d363-4581-aa1a-1c1cbf16eb3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840965981 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1840965981
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.4105854067
Short name T923
Test name
Test status
Simulation time 5240281825 ps
CPU time 1.29 seconds
Started Jan 03 12:49:33 PM PST 24
Finished Jan 03 12:49:50 PM PST 24
Peak memory 199004 kb
Host smart-24bbeea0-43d7-4eba-b7e6-b8413d622e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105854067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.4105854067
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3015686969
Short name T444
Test name
Test status
Simulation time 9144308577 ps
CPU time 15.5 seconds
Started Jan 03 12:49:01 PM PST 24
Finished Jan 03 12:49:36 PM PST 24
Peak memory 200068 kb
Host smart-22a1b5d7-4959-4be7-a1ac-eb15525b12e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015686969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3015686969
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1101874887
Short name T884
Test name
Test status
Simulation time 52087504 ps
CPU time 0.55 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:49:27 PM PST 24
Peak memory 195544 kb
Host smart-838637e8-227e-4475-b92e-c7542da0cb3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101874887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1101874887
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2056495956
Short name T322
Test name
Test status
Simulation time 151502898052 ps
CPU time 62.22 seconds
Started Jan 03 12:49:28 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 200108 kb
Host smart-e0470e61-c157-42ad-b0d8-ed244611d4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056495956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2056495956
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2914080537
Short name T201
Test name
Test status
Simulation time 111591112983 ps
CPU time 47.49 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 197952 kb
Host smart-38369f77-762a-4ee7-9e91-be635780321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914080537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2914080537
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1686673533
Short name T312
Test name
Test status
Simulation time 34115546892 ps
CPU time 31.81 seconds
Started Jan 03 12:49:19 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 200100 kb
Host smart-7c496223-bd5f-4dda-8514-f492a35898dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686673533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1686673533
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2097887343
Short name T886
Test name
Test status
Simulation time 629003068935 ps
CPU time 400.86 seconds
Started Jan 03 12:49:00 PM PST 24
Finished Jan 03 12:56:05 PM PST 24
Peak memory 200108 kb
Host smart-8055893a-aa99-4775-8d15-6c53cdb840bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097887343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2097887343
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2874776285
Short name T682
Test name
Test status
Simulation time 149979274745 ps
CPU time 169.41 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:52:16 PM PST 24
Peak memory 200164 kb
Host smart-74949fe0-0901-4054-ab1f-841a0d0ff75e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2874776285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2874776285
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1129788693
Short name T28
Test name
Test status
Simulation time 946898835 ps
CPU time 1.43 seconds
Started Jan 03 12:49:06 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 196808 kb
Host smart-f4a25c45-252c-492c-a37c-804db21d859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129788693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1129788693
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3379642838
Short name T781
Test name
Test status
Simulation time 184182010484 ps
CPU time 86.3 seconds
Started Jan 03 12:49:32 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 200356 kb
Host smart-d8d0e2db-4229-4b38-a3a0-96d15d402006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379642838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3379642838
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1547110274
Short name T599
Test name
Test status
Simulation time 34754006873 ps
CPU time 297.67 seconds
Started Jan 03 12:49:19 PM PST 24
Finished Jan 03 12:54:34 PM PST 24
Peak memory 200024 kb
Host smart-e83aca8c-8c48-41b3-865d-cf3e246dc4d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547110274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1547110274
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3629801522
Short name T652
Test name
Test status
Simulation time 1955106675 ps
CPU time 19.68 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 12:49:26 PM PST 24
Peak memory 198184 kb
Host smart-705b77f6-2271-480e-be02-b9e2d12fde39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629801522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3629801522
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1973014251
Short name T862
Test name
Test status
Simulation time 94512907314 ps
CPU time 41.71 seconds
Started Jan 03 12:49:23 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 200100 kb
Host smart-35db6571-11f0-4e53-a2cc-6cac74ccfe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973014251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1973014251
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3600987471
Short name T102
Test name
Test status
Simulation time 1823847312 ps
CPU time 3.23 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:33 PM PST 24
Peak memory 195496 kb
Host smart-de7a299d-c0ed-426a-98ab-d63531d78bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600987471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3600987471
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2081074024
Short name T1172
Test name
Test status
Simulation time 933075379 ps
CPU time 2.93 seconds
Started Jan 03 12:48:50 PM PST 24
Finished Jan 03 12:49:16 PM PST 24
Peak memory 199036 kb
Host smart-8b28684b-0dae-4209-9849-ee0c2ce4a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081074024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2081074024
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.586245147
Short name T970
Test name
Test status
Simulation time 234896661761 ps
CPU time 372.64 seconds
Started Jan 03 12:50:02 PM PST 24
Finished Jan 03 12:56:39 PM PST 24
Peak memory 200104 kb
Host smart-7d814d7f-18fe-4e07-be74-b793c0c0387b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586245147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.586245147
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1466399965
Short name T1105
Test name
Test status
Simulation time 12149442253 ps
CPU time 142.53 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:51:49 PM PST 24
Peak memory 208508 kb
Host smart-145ddbd0-9034-4eae-824e-2ac374e2dd7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466399965 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1466399965
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2660431989
Short name T965
Test name
Test status
Simulation time 520440453 ps
CPU time 1.86 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 198108 kb
Host smart-7b83dd95-b9d1-419a-842c-37e08154de40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660431989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2660431989
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2158609022
Short name T127
Test name
Test status
Simulation time 108542025313 ps
CPU time 74.96 seconds
Started Jan 03 12:48:52 PM PST 24
Finished Jan 03 12:50:29 PM PST 24
Peak memory 200208 kb
Host smart-196b80b3-dfbe-41ee-8d0b-3bc8f2f2b915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158609022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2158609022
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.4093377446
Short name T764
Test name
Test status
Simulation time 110602099 ps
CPU time 0.53 seconds
Started Jan 03 12:49:19 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 195504 kb
Host smart-e31da9bf-98e4-4825-88c8-596dc4b3bc3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093377446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.4093377446
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3805684730
Short name T163
Test name
Test status
Simulation time 85749826535 ps
CPU time 10.49 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:49:43 PM PST 24
Peak memory 199780 kb
Host smart-88b4cf6b-5c04-43ef-9968-75ff3ed0a268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805684730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3805684730
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1389624030
Short name T385
Test name
Test status
Simulation time 136729739719 ps
CPU time 48.86 seconds
Started Jan 03 12:48:58 PM PST 24
Finished Jan 03 12:50:07 PM PST 24
Peak memory 199408 kb
Host smart-5ca21a5b-d2fb-4554-94ae-d11d5a0d9ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389624030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1389624030
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1281826916
Short name T985
Test name
Test status
Simulation time 49687683299 ps
CPU time 13.51 seconds
Started Jan 03 12:49:21 PM PST 24
Finished Jan 03 12:49:52 PM PST 24
Peak memory 200192 kb
Host smart-ab53be55-09a1-41d4-8de1-b100975c5368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281826916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1281826916
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3956966773
Short name T1042
Test name
Test status
Simulation time 566943646177 ps
CPU time 150.91 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 12:52:15 PM PST 24
Peak memory 200156 kb
Host smart-e7f8493d-1904-42d0-9680-ecdd2e23b2b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956966773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3956966773
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3899648528
Short name T542
Test name
Test status
Simulation time 46827334916 ps
CPU time 229.85 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:53:49 PM PST 24
Peak memory 200188 kb
Host smart-ad96c9d4-d95d-44de-a0ee-c8b99e3759e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899648528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3899648528
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2217417459
Short name T1163
Test name
Test status
Simulation time 4809486456 ps
CPU time 9.87 seconds
Started Jan 03 12:49:25 PM PST 24
Finished Jan 03 12:49:53 PM PST 24
Peak memory 199672 kb
Host smart-b88b3be3-190f-4a87-8278-84f0147e2746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217417459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2217417459
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.762830103
Short name T305
Test name
Test status
Simulation time 166592098463 ps
CPU time 215.25 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:53:54 PM PST 24
Peak memory 200480 kb
Host smart-f73ad52e-f8ea-42cf-b986-e4904c1fc9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762830103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.762830103
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1793502603
Short name T108
Test name
Test status
Simulation time 11573505544 ps
CPU time 155.69 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:52:24 PM PST 24
Peak memory 200176 kb
Host smart-d937e24c-2ea4-41e4-81db-b16ce8cea4c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793502603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1793502603
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.744703737
Short name T861
Test name
Test status
Simulation time 3064767265 ps
CPU time 2.93 seconds
Started Jan 03 12:49:11 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 198200 kb
Host smart-d00b1a1a-c82b-4df0-91a9-55caaf3e1fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744703737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.744703737
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1715292216
Short name T1126
Test name
Test status
Simulation time 25198635482 ps
CPU time 34.65 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:49:57 PM PST 24
Peak memory 199436 kb
Host smart-c2ef0a2e-d588-41fa-b161-de059a262b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715292216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1715292216
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2149061885
Short name T1067
Test name
Test status
Simulation time 38840554595 ps
CPU time 34.98 seconds
Started Jan 03 12:49:23 PM PST 24
Finished Jan 03 12:50:16 PM PST 24
Peak memory 195684 kb
Host smart-c564c7fa-1320-452e-8994-cf0b15846f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149061885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2149061885
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3272556986
Short name T869
Test name
Test status
Simulation time 112101587 ps
CPU time 0.74 seconds
Started Jan 03 12:49:15 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 196772 kb
Host smart-cf6df8b1-58d9-4441-b6cd-5ee74ebf092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272556986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3272556986
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1595887878
Short name T388
Test name
Test status
Simulation time 38494151111 ps
CPU time 404.36 seconds
Started Jan 03 12:49:01 PM PST 24
Finished Jan 03 12:56:06 PM PST 24
Peak memory 216652 kb
Host smart-50d4ec19-a99b-43fb-8c35-ac8b94509a00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595887878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1595887878
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.955069994
Short name T910
Test name
Test status
Simulation time 10279108299 ps
CPU time 8.32 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:49:48 PM PST 24
Peak memory 199748 kb
Host smart-39040e3e-2b7d-47dd-a382-d9c5d2aa2861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955069994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.955069994
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4138401820
Short name T891
Test name
Test status
Simulation time 42893473715 ps
CPU time 61.82 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:50:29 PM PST 24
Peak memory 200176 kb
Host smart-326ad600-64a5-4050-9870-fba77a525d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138401820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4138401820
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.790475651
Short name T981
Test name
Test status
Simulation time 13603788 ps
CPU time 0.54 seconds
Started Jan 03 12:49:48 PM PST 24
Finished Jan 03 12:50:01 PM PST 24
Peak memory 195540 kb
Host smart-bf082dbe-ea74-4fe2-9fcc-d18044cd34fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790475651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.790475651
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.657497031
Short name T1132
Test name
Test status
Simulation time 60954722770 ps
CPU time 52.52 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 200052 kb
Host smart-5a30fc8d-ea3e-46fb-b9f1-8aee9968a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657497031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.657497031
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3263720987
Short name T1084
Test name
Test status
Simulation time 43394107614 ps
CPU time 42.09 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:50:35 PM PST 24
Peak memory 199276 kb
Host smart-b2ecf9bb-d96d-47eb-99a6-d12a0bfc4171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263720987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3263720987
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1969357643
Short name T260
Test name
Test status
Simulation time 78905180236 ps
CPU time 27.29 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:50:18 PM PST 24
Peak memory 200128 kb
Host smart-0a2f0bf6-7e82-4237-b498-9d653690dc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969357643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1969357643
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1545565006
Short name T793
Test name
Test status
Simulation time 282233444986 ps
CPU time 175.49 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:52:47 PM PST 24
Peak memory 199876 kb
Host smart-f90c4557-0ecf-4520-9c0a-662bebe3e11e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545565006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1545565006
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.188142498
Short name T874
Test name
Test status
Simulation time 175296137761 ps
CPU time 188.3 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:53:42 PM PST 24
Peak memory 200160 kb
Host smart-e259d1fd-bf74-4369-90ed-48b06b4f131a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188142498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.188142498
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1376039878
Short name T728
Test name
Test status
Simulation time 4694633874 ps
CPU time 4.32 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:49:55 PM PST 24
Peak memory 198152 kb
Host smart-8b5795f6-1d18-4024-a467-c472f09e8837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376039878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1376039878
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1979444575
Short name T839
Test name
Test status
Simulation time 16299841566 ps
CPU time 20.06 seconds
Started Jan 03 12:49:21 PM PST 24
Finished Jan 03 12:50:07 PM PST 24
Peak memory 197368 kb
Host smart-6e6870ca-d70e-4bfa-acc1-b60b4dc2e194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979444575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1979444575
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2197494851
Short name T832
Test name
Test status
Simulation time 7763763188 ps
CPU time 348.31 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:55:44 PM PST 24
Peak memory 200164 kb
Host smart-0b875ed9-5472-4a9e-ac96-6d9ad1b15583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2197494851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2197494851
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.560502917
Short name T1069
Test name
Test status
Simulation time 499935849 ps
CPU time 4.53 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:50:04 PM PST 24
Peak memory 198108 kb
Host smart-c9d59129-0775-48c6-b9fe-f3a39d5aed5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560502917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.560502917
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1733404947
Short name T310
Test name
Test status
Simulation time 67441248899 ps
CPU time 31.95 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:50:47 PM PST 24
Peak memory 200140 kb
Host smart-d0f9ac3a-6560-4293-b63d-a812d0088048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733404947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1733404947
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3399978920
Short name T669
Test name
Test status
Simulation time 746770360 ps
CPU time 1.25 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 12:49:47 PM PST 24
Peak memory 195492 kb
Host smart-13c42651-2504-40a8-99db-17b89bd19c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399978920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3399978920
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3183540843
Short name T1002
Test name
Test status
Simulation time 5367990324 ps
CPU time 20.75 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:14 PM PST 24
Peak memory 199076 kb
Host smart-9627f522-1c3d-4936-acb3-356ed9fe8542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183540843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3183540843
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1367019815
Short name T913
Test name
Test status
Simulation time 256097920150 ps
CPU time 433.62 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:57:43 PM PST 24
Peak memory 200232 kb
Host smart-3d32de1e-a0c0-48ba-bd69-bdd32fd179b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367019815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1367019815
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3798616775
Short name T989
Test name
Test status
Simulation time 131108464370 ps
CPU time 543.62 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:59:26 PM PST 24
Peak memory 226008 kb
Host smart-ea297daf-219a-4db2-a180-5cbf8051100d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798616775 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3798616775
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2581140380
Short name T512
Test name
Test status
Simulation time 8809185809 ps
CPU time 8.87 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:50:00 PM PST 24
Peak memory 198844 kb
Host smart-c2a7d540-9b39-4e75-ab6e-fbddd66e639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581140380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2581140380
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2113423760
Short name T418
Test name
Test status
Simulation time 15758555967 ps
CPU time 18.62 seconds
Started Jan 03 12:49:15 PM PST 24
Finished Jan 03 12:49:51 PM PST 24
Peak memory 200108 kb
Host smart-6f0770de-234d-4b5d-82e9-2c9f1ecdc71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113423760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2113423760
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3865309769
Short name T1112
Test name
Test status
Simulation time 24305787 ps
CPU time 0.56 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:49:46 PM PST 24
Peak memory 195596 kb
Host smart-3c7067f5-7faf-4c5d-9138-b1f44a989b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865309769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3865309769
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3701084148
Short name T209
Test name
Test status
Simulation time 209936206553 ps
CPU time 71.89 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 200136 kb
Host smart-7604d780-4379-4fe4-bde8-9da86ea8f5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701084148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3701084148
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1654124515
Short name T1090
Test name
Test status
Simulation time 118957622720 ps
CPU time 177.94 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:53:34 PM PST 24
Peak memory 199340 kb
Host smart-b2654be3-aeb3-4e4e-99e2-f56a94e815af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654124515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1654124515
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3266577736
Short name T304
Test name
Test status
Simulation time 33438059245 ps
CPU time 22.86 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:50:17 PM PST 24
Peak memory 200144 kb
Host smart-44efeccb-ca36-4add-89ff-e737fbbfbad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266577736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3266577736
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1340322432
Short name T239
Test name
Test status
Simulation time 356587321991 ps
CPU time 274.25 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 200088 kb
Host smart-bf1caf71-33dd-4c50-9bfd-6629c33df5fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340322432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1340322432
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2306570996
Short name T514
Test name
Test status
Simulation time 126937506011 ps
CPU time 1046.72 seconds
Started Jan 03 12:49:18 PM PST 24
Finished Jan 03 01:07:03 PM PST 24
Peak memory 200088 kb
Host smart-05a48875-0c61-46cd-871a-53d3fea03630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306570996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2306570996
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2339428719
Short name T628
Test name
Test status
Simulation time 11380918097 ps
CPU time 12.43 seconds
Started Jan 03 12:49:19 PM PST 24
Finished Jan 03 12:49:49 PM PST 24
Peak memory 198548 kb
Host smart-1f72be9d-1161-470f-8abe-3d1220296ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339428719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2339428719
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.416110186
Short name T539
Test name
Test status
Simulation time 41246577561 ps
CPU time 38.6 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 200160 kb
Host smart-ce7a936d-37b3-474d-832c-f6e1ca6a22e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416110186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.416110186
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2971989780
Short name T414
Test name
Test status
Simulation time 13978623381 ps
CPU time 298.63 seconds
Started Jan 03 12:49:25 PM PST 24
Finished Jan 03 12:54:42 PM PST 24
Peak memory 200040 kb
Host smart-f4c48519-f8cc-48f0-9b2e-057644d4b590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971989780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2971989780
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4288148350
Short name T113
Test name
Test status
Simulation time 23125080468 ps
CPU time 34.51 seconds
Started Jan 03 12:50:17 PM PST 24
Finished Jan 03 12:51:14 PM PST 24
Peak memory 200112 kb
Host smart-725e2fbf-eabf-4296-9b42-7a0d1e6117dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288148350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4288148350
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3358113874
Short name T442
Test name
Test status
Simulation time 6149605224 ps
CPU time 8.45 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:01 PM PST 24
Peak memory 195920 kb
Host smart-446f2d5c-5e00-4f9b-9005-b3fcc651a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358113874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3358113874
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1027156812
Short name T641
Test name
Test status
Simulation time 994690926 ps
CPU time 1.79 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 198480 kb
Host smart-3c1ff48c-3de8-4da1-aaca-0c775ff3a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027156812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1027156812
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1957105879
Short name T1136
Test name
Test status
Simulation time 406410059827 ps
CPU time 992.55 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 01:06:23 PM PST 24
Peak memory 200204 kb
Host smart-9d25a1c2-f9e9-4fb1-a6e7-013495420bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957105879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1957105879
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3809644461
Short name T1173
Test name
Test status
Simulation time 89107802298 ps
CPU time 1132.25 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 01:08:46 PM PST 24
Peak memory 225020 kb
Host smart-6be59ab5-f43a-4f57-bb22-438235592c24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809644461 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3809644461
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1773798920
Short name T1142
Test name
Test status
Simulation time 544669215 ps
CPU time 2.06 seconds
Started Jan 03 12:50:28 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 198196 kb
Host smart-295d502f-db54-4abf-8872-05d26d0fcc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773798920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1773798920
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3498492067
Short name T146
Test name
Test status
Simulation time 124746479076 ps
CPU time 118.52 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:51:58 PM PST 24
Peak memory 200144 kb
Host smart-53c1c825-6405-461b-8fc2-5540e8ba3e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498492067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3498492067
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.530701429
Short name T510
Test name
Test status
Simulation time 17123806 ps
CPU time 0.53 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 194572 kb
Host smart-46541601-44b4-46b4-8bbb-b695c1291f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530701429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.530701429
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.519695851
Short name T1059
Test name
Test status
Simulation time 38056365268 ps
CPU time 29.65 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:49:45 PM PST 24
Peak memory 200140 kb
Host smart-1ec196a9-652d-4987-ad94-5a72569199f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519695851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.519695851
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1780991759
Short name T342
Test name
Test status
Simulation time 30746861893 ps
CPU time 13.61 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 197892 kb
Host smart-91288755-7b38-4864-918d-7344857e91b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780991759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1780991759
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.357578900
Short name T993
Test name
Test status
Simulation time 434547848035 ps
CPU time 468.18 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:57:33 PM PST 24
Peak memory 198928 kb
Host smart-a4988dac-3af6-496c-82df-d0f4737cfb8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357578900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.357578900
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2492640568
Short name T563
Test name
Test status
Simulation time 43808089737 ps
CPU time 82.47 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:51:58 PM PST 24
Peak memory 200236 kb
Host smart-3ac52e80-f17e-4a3c-b70e-708589c6dc66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492640568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2492640568
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2364957641
Short name T813
Test name
Test status
Simulation time 4737440635 ps
CPU time 4.4 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:49:42 PM PST 24
Peak memory 198620 kb
Host smart-f4d71030-26ff-4dfb-9b98-b58a6676e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364957641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2364957641
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3514512156
Short name T412
Test name
Test status
Simulation time 91189123664 ps
CPU time 35.69 seconds
Started Jan 03 12:49:12 PM PST 24
Finished Jan 03 12:50:05 PM PST 24
Peak memory 208704 kb
Host smart-5715386f-d058-49b6-a31a-3f0a60053676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514512156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3514512156
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2621343098
Short name T436
Test name
Test status
Simulation time 18570915280 ps
CPU time 820.76 seconds
Started Jan 03 12:49:06 PM PST 24
Finished Jan 03 01:03:05 PM PST 24
Peak memory 200020 kb
Host smart-d2077e52-dad2-412a-b3e3-c0f251326ede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621343098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2621343098
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2298095005
Short name T784
Test name
Test status
Simulation time 51998925732 ps
CPU time 69.7 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:51:01 PM PST 24
Peak memory 199276 kb
Host smart-c3044107-d3a6-4c5d-ad0d-dc6ee436b579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298095005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2298095005
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2106534890
Short name T1026
Test name
Test status
Simulation time 3080424502 ps
CPU time 1.28 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:49:50 PM PST 24
Peak memory 195580 kb
Host smart-e7009b36-6091-4e9d-8b73-57496eca4694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106534890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2106534890
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3970608201
Short name T567
Test name
Test status
Simulation time 583742645 ps
CPU time 1.36 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 198588 kb
Host smart-7721f18a-672a-41f7-b200-2fb0ba4d6a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970608201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3970608201
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.169466708
Short name T1092
Test name
Test status
Simulation time 98077727719 ps
CPU time 190.34 seconds
Started Jan 03 12:49:12 PM PST 24
Finished Jan 03 12:52:40 PM PST 24
Peak memory 200152 kb
Host smart-7d896eb0-be09-4f41-bab2-782944bb65ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169466708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.169466708
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4162851923
Short name T1157
Test name
Test status
Simulation time 131518634822 ps
CPU time 564 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:58:59 PM PST 24
Peak memory 225128 kb
Host smart-105ca4aa-368b-4e0c-8829-cf9718b9dc51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162851923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4162851923
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2428776680
Short name T30
Test name
Test status
Simulation time 596019633 ps
CPU time 1.31 seconds
Started Jan 03 12:49:32 PM PST 24
Finished Jan 03 12:49:49 PM PST 24
Peak memory 198316 kb
Host smart-44f21282-c19b-4c14-a656-1c5080751aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428776680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2428776680
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1611392105
Short name T458
Test name
Test status
Simulation time 64634370101 ps
CPU time 25.06 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:49:52 PM PST 24
Peak memory 200196 kb
Host smart-48043bd5-031a-4792-acfd-6dacb93e4813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611392105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1611392105
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.479175405
Short name T91
Test name
Test status
Simulation time 43447228 ps
CPU time 0.54 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 195552 kb
Host smart-59c8c614-db47-48e8-a770-983663ae16a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479175405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.479175405
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1259536852
Short name T290
Test name
Test status
Simulation time 59887739538 ps
CPU time 48.93 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 200088 kb
Host smart-a321e125-be2d-47f8-b904-8e37c2064f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259536852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1259536852
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2229799574
Short name T1203
Test name
Test status
Simulation time 70968681726 ps
CPU time 114.01 seconds
Started Jan 03 12:48:07 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 200172 kb
Host smart-2e42315c-526d-408c-a274-87d9d33cb257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229799574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2229799574
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2348072919
Short name T183
Test name
Test status
Simulation time 23283227046 ps
CPU time 43.41 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:49:25 PM PST 24
Peak memory 200076 kb
Host smart-34542021-05f9-4feb-826f-a84fa67b39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348072919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2348072919
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3999631015
Short name T626
Test name
Test status
Simulation time 1803524829503 ps
CPU time 2884.28 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 01:36:50 PM PST 24
Peak memory 200100 kb
Host smart-5baaebf2-3344-465c-8fbd-6a8e3ca0e0a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999631015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3999631015
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1153851483
Short name T408
Test name
Test status
Simulation time 57164751273 ps
CPU time 218.31 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:52:21 PM PST 24
Peak memory 200160 kb
Host smart-dd05f726-6671-4905-a3b0-86d6cdacf7d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153851483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1153851483
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3994933050
Short name T570
Test name
Test status
Simulation time 4090657915 ps
CPU time 3.22 seconds
Started Jan 03 12:48:39 PM PST 24
Finished Jan 03 12:49:09 PM PST 24
Peak memory 199440 kb
Host smart-f187f5c1-67e5-4d30-9f63-77a5dbe0fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994933050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3994933050
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1290647242
Short name T726
Test name
Test status
Simulation time 20118672473 ps
CPU time 16.27 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:49:01 PM PST 24
Peak memory 195840 kb
Host smart-a1f36f26-f742-40f8-974f-fdbc67eae5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290647242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1290647242
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3946603190
Short name T511
Test name
Test status
Simulation time 6716168782 ps
CPU time 278.23 seconds
Started Jan 03 12:48:26 PM PST 24
Finished Jan 03 12:53:27 PM PST 24
Peak memory 200200 kb
Host smart-8f4cb749-4bd4-4328-930a-374d001a30e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3946603190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3946603190
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2354420916
Short name T774
Test name
Test status
Simulation time 154395972044 ps
CPU time 125.96 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:50:50 PM PST 24
Peak memory 200212 kb
Host smart-bb5675c1-fd51-4bd5-8816-813b1634ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354420916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2354420916
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2592739070
Short name T984
Test name
Test status
Simulation time 1773840067 ps
CPU time 3.51 seconds
Started Jan 03 12:48:12 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 195492 kb
Host smart-0ff1d2d4-406e-459a-8537-54f044089a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592739070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2592739070
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3509800950
Short name T83
Test name
Test status
Simulation time 153881089 ps
CPU time 0.75 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:48:49 PM PST 24
Peak memory 217764 kb
Host smart-23430c8b-1f93-4ae8-917b-3f90cbe375e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509800950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3509800950
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3423233570
Short name T938
Test name
Test status
Simulation time 5438153497 ps
CPU time 10.82 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:48:57 PM PST 24
Peak memory 199000 kb
Host smart-6c5ff5c5-9bd1-4d54-83c6-5085e5cab9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423233570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3423233570
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.4120188449
Short name T1032
Test name
Test status
Simulation time 416545051128 ps
CPU time 608 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:58:51 PM PST 24
Peak memory 200244 kb
Host smart-1eebc140-e86b-4854-b02d-59cd400ba899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120188449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.4120188449
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2535987645
Short name T992
Test name
Test status
Simulation time 441028302 ps
CPU time 1.7 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:48:45 PM PST 24
Peak memory 198476 kb
Host smart-f84d4d2a-9e94-4296-8c9a-7663bee29a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535987645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2535987645
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.4223728048
Short name T905
Test name
Test status
Simulation time 45404629146 ps
CPU time 13.87 seconds
Started Jan 03 12:48:12 PM PST 24
Finished Jan 03 12:48:53 PM PST 24
Peak memory 200204 kb
Host smart-0b8f09aa-ea5b-4e97-abc0-ebc12dba6a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223728048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.4223728048
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.404563234
Short name T786
Test name
Test status
Simulation time 13312944 ps
CPU time 0.54 seconds
Started Jan 03 12:49:25 PM PST 24
Finished Jan 03 12:49:43 PM PST 24
Peak memory 194700 kb
Host smart-d1c0625a-63f2-4fca-953c-08328a114d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404563234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.404563234
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3422842868
Short name T687
Test name
Test status
Simulation time 48639292402 ps
CPU time 76.16 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 200152 kb
Host smart-296da1ca-8bee-497e-83c2-268285fe101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422842868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3422842868
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3633203895
Short name T727
Test name
Test status
Simulation time 81298137207 ps
CPU time 68.98 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 199832 kb
Host smart-7911aaf3-9010-4a70-b506-f8e126f3495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633203895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3633203895
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.4196310755
Short name T343
Test name
Test status
Simulation time 101052487206 ps
CPU time 130.92 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:51:46 PM PST 24
Peak memory 200164 kb
Host smart-8d34822e-c1d3-4318-a058-655567b14211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196310755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.4196310755
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3324349004
Short name T1022
Test name
Test status
Simulation time 38558413435 ps
CPU time 72.81 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 199680 kb
Host smart-8d32e617-797b-4408-a30c-9b0e130c2755
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324349004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3324349004
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2045421501
Short name T817
Test name
Test status
Simulation time 136862754297 ps
CPU time 985.77 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 01:06:10 PM PST 24
Peak memory 200188 kb
Host smart-84aff514-b07e-4752-b8bf-aa8c568006df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045421501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2045421501
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3554068316
Short name T517
Test name
Test status
Simulation time 793130152 ps
CPU time 0.75 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:49:51 PM PST 24
Peak memory 195600 kb
Host smart-cc2c443f-aa88-468e-a08f-075e8c917e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554068316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3554068316
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2322874995
Short name T148
Test name
Test status
Simulation time 209777858900 ps
CPU time 72.86 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 12:50:59 PM PST 24
Peak memory 199716 kb
Host smart-944be873-6923-4019-908c-fe88a8978225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322874995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2322874995
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2874453976
Short name T450
Test name
Test status
Simulation time 13940266136 ps
CPU time 240.2 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:53:55 PM PST 24
Peak memory 200096 kb
Host smart-c845d639-177a-4789-8ad9-96dfb81fb8f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2874453976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2874453976
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1653594938
Short name T503
Test name
Test status
Simulation time 5396673862 ps
CPU time 12.63 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:49:52 PM PST 24
Peak memory 198548 kb
Host smart-fe01a9f3-bd86-41a3-86ae-5c8260577f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653594938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1653594938
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1550615562
Short name T880
Test name
Test status
Simulation time 35067164770 ps
CPU time 50.53 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 200144 kb
Host smart-a6197375-2f73-45dd-8900-a7f4cdae6b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550615562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1550615562
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.483233078
Short name T531
Test name
Test status
Simulation time 2670931050 ps
CPU time 1 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:49:58 PM PST 24
Peak memory 195668 kb
Host smart-53282bd5-6ec8-43c7-8696-3dbb5609a359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483233078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.483233078
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2682455533
Short name T1175
Test name
Test status
Simulation time 6084151145 ps
CPU time 8.47 seconds
Started Jan 03 12:49:11 PM PST 24
Finished Jan 03 12:49:37 PM PST 24
Peak memory 199132 kb
Host smart-da62ff8c-1a30-4e26-a338-4142f3eab473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682455533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2682455533
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3345005710
Short name T895
Test name
Test status
Simulation time 152409677017 ps
CPU time 645.54 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 01:00:23 PM PST 24
Peak memory 200144 kb
Host smart-e4fcfeeb-de07-4c25-a1c6-ef61e73288dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345005710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3345005710
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.4211077825
Short name T959
Test name
Test status
Simulation time 109604851196 ps
CPU time 670.93 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 01:00:46 PM PST 24
Peak memory 229344 kb
Host smart-07367304-28ba-4f8a-8e2d-bc05271127dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211077825 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.4211077825
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.639138081
Short name T724
Test name
Test status
Simulation time 1277818467 ps
CPU time 5.15 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:49:58 PM PST 24
Peak memory 198800 kb
Host smart-581ad238-bfa6-4680-a620-976f0b83b1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639138081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.639138081
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.486215666
Short name T734
Test name
Test status
Simulation time 78182685154 ps
CPU time 55.88 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:50:28 PM PST 24
Peak memory 200156 kb
Host smart-8c562153-ae14-4ef2-9e77-bcde47012aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486215666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.486215666
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2200494742
Short name T924
Test name
Test status
Simulation time 34619258 ps
CPU time 0.54 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:49:38 PM PST 24
Peak memory 195532 kb
Host smart-ee206b65-cdbf-4d53-b321-a666cda8c121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200494742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2200494742
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2680885932
Short name T401
Test name
Test status
Simulation time 151538518547 ps
CPU time 124.13 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:52:28 PM PST 24
Peak memory 200088 kb
Host smart-45b011c9-16d8-4455-bd27-85cf2600c81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680885932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2680885932
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2639685430
Short name T941
Test name
Test status
Simulation time 74485136658 ps
CPU time 121.08 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:51:58 PM PST 24
Peak memory 200148 kb
Host smart-02b88579-399b-4009-8a55-c3c08d49a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639685430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2639685430
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3006502925
Short name T806
Test name
Test status
Simulation time 29069211432 ps
CPU time 52.13 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 200120 kb
Host smart-7df254fe-7ccb-41fa-b1e2-b753a4f8d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006502925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3006502925
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.992747527
Short name T14
Test name
Test status
Simulation time 139467601309 ps
CPU time 134.95 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:52:39 PM PST 24
Peak memory 199364 kb
Host smart-5c64cae1-f9e3-47d4-9455-965331a831fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992747527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.992747527
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1580597948
Short name T413
Test name
Test status
Simulation time 118704233738 ps
CPU time 587.43 seconds
Started Jan 03 12:48:54 PM PST 24
Finished Jan 03 12:59:03 PM PST 24
Peak memory 200112 kb
Host smart-9457619a-570e-4e4a-ae21-f9e825652669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580597948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1580597948
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1472802898
Short name T19
Test name
Test status
Simulation time 4229489355 ps
CPU time 7.99 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 198320 kb
Host smart-87141783-c81c-4fea-a844-edfe6cbb99ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472802898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1472802898
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2956238053
Short name T733
Test name
Test status
Simulation time 46814794586 ps
CPU time 38.83 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 200236 kb
Host smart-4c50b5df-fbd3-4f27-9224-0a71c8982896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956238053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2956238053
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.832538324
Short name T592
Test name
Test status
Simulation time 13587702288 ps
CPU time 120.15 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:51:37 PM PST 24
Peak memory 200088 kb
Host smart-35cb657f-ee54-4637-9f2b-2103ea726f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832538324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.832538324
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2614656379
Short name T500
Test name
Test status
Simulation time 2632740472 ps
CPU time 24.69 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:28 PM PST 24
Peak memory 198672 kb
Host smart-ed2c2e31-2b31-47e3-9c8d-4eb39c7ecb7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614656379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2614656379
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3199018753
Short name T625
Test name
Test status
Simulation time 29370052432 ps
CPU time 27.79 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 200056 kb
Host smart-93308345-0dae-4252-9b91-064999b34034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199018753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3199018753
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3781476820
Short name T547
Test name
Test status
Simulation time 4400893388 ps
CPU time 8.01 seconds
Started Jan 03 12:50:08 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 195856 kb
Host smart-7a3cdf56-a998-4736-b87a-9e6fef91a440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781476820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3781476820
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.18141660
Short name T651
Test name
Test status
Simulation time 462014379 ps
CPU time 3.23 seconds
Started Jan 03 12:50:19 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 198132 kb
Host smart-e95f798f-834f-4dd0-9390-6297b776b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18141660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.18141660
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2886757343
Short name T376
Test name
Test status
Simulation time 152183156408 ps
CPU time 55.97 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:50:31 PM PST 24
Peak memory 200268 kb
Host smart-e57a2b07-8216-4bf0-a816-1c09f8d809b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886757343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2886757343
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1929904021
Short name T168
Test name
Test status
Simulation time 258870233483 ps
CPU time 759.5 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 231432 kb
Host smart-79cf5fd4-36d2-4b36-b579-02e4ffd85bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929904021 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1929904021
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3132845357
Short name T586
Test name
Test status
Simulation time 5955776861 ps
CPU time 39.84 seconds
Started Jan 03 12:49:29 PM PST 24
Finished Jan 03 12:50:29 PM PST 24
Peak memory 199644 kb
Host smart-60cbe697-58bf-469c-9cb4-193f78e0ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132845357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3132845357
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1449848448
Short name T745
Test name
Test status
Simulation time 272449421985 ps
CPU time 94.71 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 200188 kb
Host smart-efb948ac-546f-4d60-a3ab-92ad28e371bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449848448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1449848448
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1931947248
Short name T918
Test name
Test status
Simulation time 22957378 ps
CPU time 0.53 seconds
Started Jan 03 12:49:29 PM PST 24
Finished Jan 03 12:49:46 PM PST 24
Peak memory 194592 kb
Host smart-f19c39bf-d357-4532-97b2-b590f920da1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931947248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1931947248
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.4291804837
Short name T845
Test name
Test status
Simulation time 229325259076 ps
CPU time 232.32 seconds
Started Jan 03 12:49:10 PM PST 24
Finished Jan 03 12:53:20 PM PST 24
Peak memory 200096 kb
Host smart-adf0b756-93b8-499b-a7dd-ff6d216a9363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291804837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.4291804837
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1839074158
Short name T927
Test name
Test status
Simulation time 86561464044 ps
CPU time 121.86 seconds
Started Jan 03 12:49:28 PM PST 24
Finished Jan 03 12:51:47 PM PST 24
Peak memory 199180 kb
Host smart-8601a537-338b-412f-be9e-01500646ea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839074158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1839074158
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1984504138
Short name T691
Test name
Test status
Simulation time 66504099327 ps
CPU time 15.91 seconds
Started Jan 03 12:49:05 PM PST 24
Finished Jan 03 12:49:40 PM PST 24
Peak memory 199824 kb
Host smart-21d6c850-2848-4b34-9eed-08ce26b3352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984504138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1984504138
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.4287240345
Short name T917
Test name
Test status
Simulation time 311898956636 ps
CPU time 809.19 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 01:03:15 PM PST 24
Peak memory 200180 kb
Host smart-454eda77-f360-46c5-b1a7-13b66b66b990
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287240345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.4287240345
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1404001839
Short name T916
Test name
Test status
Simulation time 128071493959 ps
CPU time 505.64 seconds
Started Jan 03 12:49:21 PM PST 24
Finished Jan 03 12:58:04 PM PST 24
Peak memory 200064 kb
Host smart-6d1b2b1f-57e6-45d4-b812-20e13c93cad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404001839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1404001839
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.790459867
Short name T751
Test name
Test status
Simulation time 4832756935 ps
CPU time 3.54 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:14 PM PST 24
Peak memory 198900 kb
Host smart-93cc1dbc-2c1c-4b54-9cfc-86c45f74a872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790459867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.790459867
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.4116289000
Short name T718
Test name
Test status
Simulation time 140487359825 ps
CPU time 149.31 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:52:27 PM PST 24
Peak memory 200444 kb
Host smart-00ba090b-5b32-4f09-b910-15919d5e4c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116289000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.4116289000
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.4202674018
Short name T568
Test name
Test status
Simulation time 23690981491 ps
CPU time 158.55 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:52:45 PM PST 24
Peak memory 200100 kb
Host smart-0aa02410-4ed6-4be8-b241-15b1e9ae1c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202674018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4202674018
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3134784252
Short name T506
Test name
Test status
Simulation time 463840756 ps
CPU time 1.66 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:49:55 PM PST 24
Peak memory 198420 kb
Host smart-5c1533d8-9d76-4e2f-9081-8123a44c7b0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134784252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3134784252
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1040954591
Short name T963
Test name
Test status
Simulation time 155702720748 ps
CPU time 163.62 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:52:18 PM PST 24
Peak memory 200172 kb
Host smart-8e903845-f8df-4fb4-bbc2-b9a1a2ab11a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040954591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1040954591
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4191131204
Short name T824
Test name
Test status
Simulation time 25118322669 ps
CPU time 9.39 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:49:47 PM PST 24
Peak memory 195744 kb
Host smart-3b4e6620-0a56-4b4f-a924-541bd7e97e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191131204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4191131204
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2953329114
Short name T833
Test name
Test status
Simulation time 715366294 ps
CPU time 1.61 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:49:47 PM PST 24
Peak memory 197992 kb
Host smart-e1a5e63f-45d0-422b-9a14-c40188c91036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953329114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2953329114
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2160398459
Short name T674
Test name
Test status
Simulation time 1561232666660 ps
CPU time 2716.53 seconds
Started Jan 03 12:49:31 PM PST 24
Finished Jan 03 01:35:04 PM PST 24
Peak memory 200184 kb
Host smart-df4ade66-9512-4cf7-a7cb-a1fae6cc85b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160398459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2160398459
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2088529738
Short name T915
Test name
Test status
Simulation time 70286936084 ps
CPU time 785.08 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 01:03:05 PM PST 24
Peak memory 216532 kb
Host smart-97f93d3d-043f-4435-9db0-8b3685c2cc6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088529738 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2088529738
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3901415969
Short name T662
Test name
Test status
Simulation time 1874021403 ps
CPU time 1.94 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:49:57 PM PST 24
Peak memory 198100 kb
Host smart-ae83d1e6-39ea-43be-90fb-a75ba3ba4592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901415969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3901415969
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1878202213
Short name T1024
Test name
Test status
Simulation time 40557552421 ps
CPU time 9.34 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 198052 kb
Host smart-2158a7bb-1720-4744-b573-7c4b9e6b71d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878202213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1878202213
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3851121814
Short name T969
Test name
Test status
Simulation time 10578645 ps
CPU time 0.52 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:05 PM PST 24
Peak memory 194544 kb
Host smart-e53803e4-7780-4777-bf54-461fe743732d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851121814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3851121814
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.773990083
Short name T1190
Test name
Test status
Simulation time 109828719605 ps
CPU time 172.16 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:53:22 PM PST 24
Peak memory 200084 kb
Host smart-361af70e-af46-4c12-a4a9-6bde77b482f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773990083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.773990083
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.429935265
Short name T1213
Test name
Test status
Simulation time 129122066427 ps
CPU time 51.67 seconds
Started Jan 03 12:50:02 PM PST 24
Finished Jan 03 12:51:18 PM PST 24
Peak memory 199952 kb
Host smart-655add94-9e5e-418e-9fb8-79e4666e5bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429935265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.429935265
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.509650008
Short name T777
Test name
Test status
Simulation time 188955877058 ps
CPU time 362.68 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:56:06 PM PST 24
Peak memory 200116 kb
Host smart-5fd04b32-8391-4493-9601-14556bec0cd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509650008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.509650008
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1018147002
Short name T858
Test name
Test status
Simulation time 6616606941 ps
CPU time 4.38 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:03 PM PST 24
Peak memory 198632 kb
Host smart-e9651db4-b9c6-405d-88fd-587970d38d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018147002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1018147002
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3212141693
Short name T890
Test name
Test status
Simulation time 99181209526 ps
CPU time 177.14 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:53:03 PM PST 24
Peak memory 208660 kb
Host smart-0346989b-f1ab-43bf-a77b-3a5d032764a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212141693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3212141693
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.880608725
Short name T899
Test name
Test status
Simulation time 1154775112 ps
CPU time 1.64 seconds
Started Jan 03 12:49:25 PM PST 24
Finished Jan 03 12:49:47 PM PST 24
Peak memory 197932 kb
Host smart-bbf6e967-2589-4ab8-b393-d0772342c09b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=880608725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.880608725
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.833947650
Short name T136
Test name
Test status
Simulation time 62602671246 ps
CPU time 49.54 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 200200 kb
Host smart-1e19c0c2-2e37-491d-aeac-00dabb067d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833947650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.833947650
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3681193523
Short name T729
Test name
Test status
Simulation time 3789476810 ps
CPU time 0.99 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:50:03 PM PST 24
Peak memory 195200 kb
Host smart-893ce2e8-1a91-46bc-bf1c-f64389666dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681193523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3681193523
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1566144817
Short name T1204
Test name
Test status
Simulation time 123337028 ps
CPU time 1.06 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 198232 kb
Host smart-03eb1019-dbf5-4bf0-bd0a-badffc0d0962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566144817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1566144817
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2233715204
Short name T977
Test name
Test status
Simulation time 191297461716 ps
CPU time 905.98 seconds
Started Jan 03 12:49:31 PM PST 24
Finished Jan 03 01:04:53 PM PST 24
Peak memory 225148 kb
Host smart-9e40ed91-1967-4f8d-941c-a951907a0409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233715204 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2233715204
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1039247076
Short name T550
Test name
Test status
Simulation time 973713996 ps
CPU time 4.23 seconds
Started Jan 03 12:49:48 PM PST 24
Finished Jan 03 12:50:04 PM PST 24
Peak memory 198060 kb
Host smart-c2cbbb17-562d-458c-823c-eb5495b24084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039247076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1039247076
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.245734675
Short name T770
Test name
Test status
Simulation time 13745865894 ps
CPU time 24.55 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 200172 kb
Host smart-489efd60-f678-41d9-bf06-c8c4fb7b6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245734675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.245734675
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.313077085
Short name T878
Test name
Test status
Simulation time 13898476 ps
CPU time 0.53 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:49:57 PM PST 24
Peak memory 194560 kb
Host smart-cc2855d2-b343-486b-b19b-30e1f8f367c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313077085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.313077085
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1318053377
Short name T857
Test name
Test status
Simulation time 146982397129 ps
CPU time 55.43 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 199924 kb
Host smart-42e8bb53-17a7-4033-a644-80ce061d303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318053377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1318053377
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2308549991
Short name T1044
Test name
Test status
Simulation time 51195861352 ps
CPU time 45.86 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 200008 kb
Host smart-992f18dd-5604-4374-bed2-c12a4f391b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308549991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2308549991
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.599025132
Short name T908
Test name
Test status
Simulation time 131229105876 ps
CPU time 191.35 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:53:04 PM PST 24
Peak memory 200152 kb
Host smart-d5875732-ce01-4a76-a391-d8d13e62b35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599025132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.599025132
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3661146218
Short name T565
Test name
Test status
Simulation time 425759765152 ps
CPU time 151.16 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:53:15 PM PST 24
Peak memory 200012 kb
Host smart-c8cb7db1-de66-4bc2-b813-5a2ca141a014
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661146218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3661146218
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1260218717
Short name T1041
Test name
Test status
Simulation time 85198186286 ps
CPU time 396.26 seconds
Started Jan 03 12:49:02 PM PST 24
Finished Jan 03 12:55:59 PM PST 24
Peak memory 200144 kb
Host smart-3610ced5-f38e-4237-a9c9-ee7f6102549d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260218717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1260218717
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2773657047
Short name T1099
Test name
Test status
Simulation time 7254010458 ps
CPU time 15.34 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:50:30 PM PST 24
Peak memory 199476 kb
Host smart-541dedb8-5f57-47d6-8380-d8ab8508d8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773657047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2773657047
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1111205036
Short name T1211
Test name
Test status
Simulation time 35362976436 ps
CPU time 18.9 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:50:09 PM PST 24
Peak memory 200464 kb
Host smart-40795e0f-7bfe-439f-9151-82d0e16e6df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111205036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1111205036
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2355840690
Short name T821
Test name
Test status
Simulation time 6531520057 ps
CPU time 154.66 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:52:26 PM PST 24
Peak memory 200120 kb
Host smart-187158e3-9c01-4430-bd4e-5c0073923bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355840690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2355840690
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1344221259
Short name T498
Test name
Test status
Simulation time 1696954214 ps
CPU time 2.72 seconds
Started Jan 03 12:50:02 PM PST 24
Finished Jan 03 12:50:29 PM PST 24
Peak memory 198332 kb
Host smart-2759d482-d35a-459d-a6e5-514a47528df4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344221259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1344221259
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.228205763
Short name T1070
Test name
Test status
Simulation time 18489390454 ps
CPU time 31.86 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:50:47 PM PST 24
Peak memory 200104 kb
Host smart-9529fb7c-325d-41a8-88d3-8f0a7306887f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228205763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.228205763
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1932787067
Short name T434
Test name
Test status
Simulation time 766266522 ps
CPU time 1.89 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:49:28 PM PST 24
Peak memory 195532 kb
Host smart-4d98cd80-24bb-4fb6-a772-183e449bea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932787067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1932787067
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3784091149
Short name T430
Test name
Test status
Simulation time 5510492784 ps
CPU time 9.76 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 198848 kb
Host smart-e0ac9819-f520-414b-9634-9d5cb21e904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784091149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3784091149
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1347156909
Short name T750
Test name
Test status
Simulation time 1050774377916 ps
CPU time 586.18 seconds
Started Jan 03 12:49:33 PM PST 24
Finished Jan 03 12:59:34 PM PST 24
Peak memory 200104 kb
Host smart-319c1407-b700-492e-96e6-5e7c047c5f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347156909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1347156909
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2160422003
Short name T945
Test name
Test status
Simulation time 122866880579 ps
CPU time 525.2 seconds
Started Jan 03 12:48:55 PM PST 24
Finished Jan 03 12:58:01 PM PST 24
Peak memory 216848 kb
Host smart-c10f3da6-2021-42e7-bdfb-3c86497f0871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160422003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2160422003
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3659889118
Short name T1186
Test name
Test status
Simulation time 7038141934 ps
CPU time 8.77 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:01 PM PST 24
Peak memory 199124 kb
Host smart-1ee03c7e-6e91-4a9c-afea-448a4f78b01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659889118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3659889118
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1838063054
Short name T706
Test name
Test status
Simulation time 67988546182 ps
CPU time 29.3 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 200148 kb
Host smart-9ead6fb4-a5c6-44d4-8d64-3280775abc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838063054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1838063054
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2657380107
Short name T876
Test name
Test status
Simulation time 13339690 ps
CPU time 0.57 seconds
Started Jan 03 12:49:09 PM PST 24
Finished Jan 03 12:49:27 PM PST 24
Peak memory 195612 kb
Host smart-2553258a-f9a6-44c2-937a-be341c680a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657380107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2657380107
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1898835029
Short name T288
Test name
Test status
Simulation time 255171720882 ps
CPU time 84.66 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 200112 kb
Host smart-7a2f1fff-06a2-492c-9cbd-8d6fc4526c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898835029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1898835029
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3330280152
Short name T1215
Test name
Test status
Simulation time 203842181239 ps
CPU time 518 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:58:36 PM PST 24
Peak memory 200124 kb
Host smart-e1515b7c-3d1d-4ae2-8d28-07214ec1cee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330280152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3330280152
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2643324118
Short name T26
Test name
Test status
Simulation time 200362043552 ps
CPU time 331.83 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:55:26 PM PST 24
Peak memory 200124 kb
Host smart-b837224c-09e0-42a8-b44c-d474888ec9a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643324118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2643324118
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.978809722
Short name T914
Test name
Test status
Simulation time 94962497218 ps
CPU time 168.75 seconds
Started Jan 03 12:50:04 PM PST 24
Finished Jan 03 12:53:17 PM PST 24
Peak memory 200156 kb
Host smart-12232241-48a9-4ab2-98c8-9f5b4fb67fe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978809722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.978809722
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3026418387
Short name T1001
Test name
Test status
Simulation time 5210513804 ps
CPU time 3.58 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 197852 kb
Host smart-eac8a071-489d-49e5-89b4-b97e74a50f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026418387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3026418387
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1109393592
Short name T730
Test name
Test status
Simulation time 272268981350 ps
CPU time 218.96 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:54:35 PM PST 24
Peak memory 200440 kb
Host smart-58d67d36-ba14-42ca-bf4e-38e9ecfccc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109393592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1109393592
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2703089045
Short name T840
Test name
Test status
Simulation time 16548949033 ps
CPU time 235.96 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:54:12 PM PST 24
Peak memory 200176 kb
Host smart-84575ba1-328d-4a96-adf2-7c520abbde44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703089045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2703089045
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.593383004
Short name T772
Test name
Test status
Simulation time 1364251879 ps
CPU time 3.74 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:50:15 PM PST 24
Peak memory 198320 kb
Host smart-86955fca-d578-45ae-87b3-f2c1235e06e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593383004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.593383004
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.270530267
Short name T1127
Test name
Test status
Simulation time 51070497744 ps
CPU time 21.87 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:50:07 PM PST 24
Peak memory 196000 kb
Host smart-0c3e8cf5-acda-452d-bb96-01af33147b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270530267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.270530267
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3637590340
Short name T613
Test name
Test status
Simulation time 123794094 ps
CPU time 1.11 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:49:55 PM PST 24
Peak memory 198348 kb
Host smart-4825fb3a-8d38-4e53-aa61-36ffe7d1c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637590340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3637590340
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1632589779
Short name T238
Test name
Test status
Simulation time 212623930941 ps
CPU time 805.65 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 01:03:36 PM PST 24
Peak memory 200060 kb
Host smart-10962f82-6350-45b2-9846-577c9140f32a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632589779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1632589779
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.4109675432
Short name T271
Test name
Test status
Simulation time 119264938271 ps
CPU time 664.47 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 01:00:51 PM PST 24
Peak memory 225008 kb
Host smart-b8bc2a82-d4bb-41ab-b520-7debe846a2e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109675432 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.4109675432
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.351276429
Short name T907
Test name
Test status
Simulation time 9017570408 ps
CPU time 7.44 seconds
Started Jan 03 12:49:17 PM PST 24
Finished Jan 03 12:49:42 PM PST 24
Peak memory 199156 kb
Host smart-6811c7f2-167e-4275-aa48-186dbbcfc3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351276429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.351276429
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3561830023
Short name T1066
Test name
Test status
Simulation time 58536653175 ps
CPU time 25.06 seconds
Started Jan 03 12:50:05 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 197032 kb
Host smart-03579d3f-298a-44b0-b63e-ca726669f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561830023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3561830023
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1564651146
Short name T667
Test name
Test status
Simulation time 12529079 ps
CPU time 0.53 seconds
Started Jan 03 12:49:22 PM PST 24
Finished Jan 03 12:49:40 PM PST 24
Peak memory 194680 kb
Host smart-f958ef40-0952-4189-9f97-57b38b687695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564651146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1564651146
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.564545320
Short name T708
Test name
Test status
Simulation time 30433971925 ps
CPU time 44.49 seconds
Started Jan 03 12:49:33 PM PST 24
Finished Jan 03 12:50:33 PM PST 24
Peak memory 200144 kb
Host smart-b996b3be-a057-45ad-888a-71e67a5b642f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564545320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.564545320
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3804172651
Short name T1178
Test name
Test status
Simulation time 232818166851 ps
CPU time 95.58 seconds
Started Jan 03 12:49:48 PM PST 24
Finished Jan 03 12:51:35 PM PST 24
Peak memory 199200 kb
Host smart-1327bf78-44d1-458b-a1a3-119ddde90f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804172651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3804172651
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1381430706
Short name T331
Test name
Test status
Simulation time 81502011903 ps
CPU time 141.26 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:52:20 PM PST 24
Peak memory 199468 kb
Host smart-f47e5eed-3751-4b6b-a8e7-e272a7546a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381430706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1381430706
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2216658838
Short name T897
Test name
Test status
Simulation time 72098655727 ps
CPU time 37.21 seconds
Started Jan 03 12:49:30 PM PST 24
Finished Jan 03 12:50:23 PM PST 24
Peak memory 200132 kb
Host smart-aa763c2b-20f2-4809-83b3-bb5eb0d8e9fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216658838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2216658838
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2355641651
Short name T846
Test name
Test status
Simulation time 51280380318 ps
CPU time 430.79 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 200084 kb
Host smart-dfe7d78f-1f3b-4f76-8628-68202bba7e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355641651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2355641651
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2025443288
Short name T619
Test name
Test status
Simulation time 9659310256 ps
CPU time 14.39 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:50:21 PM PST 24
Peak memory 198516 kb
Host smart-6c703564-e4ae-4266-ac2b-b9e7ca39281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025443288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2025443288
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1235583728
Short name T409
Test name
Test status
Simulation time 53482410514 ps
CPU time 86.05 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 198296 kb
Host smart-4f342dcf-cb03-4e31-8f5b-f87ee909657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235583728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1235583728
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3224241174
Short name T1138
Test name
Test status
Simulation time 25609007474 ps
CPU time 1545.32 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 01:16:21 PM PST 24
Peak memory 200252 kb
Host smart-020dd20e-9c7f-4071-a4ab-dabded562a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224241174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3224241174
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3986629971
Short name T439
Test name
Test status
Simulation time 221859725452 ps
CPU time 190.96 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:53:03 PM PST 24
Peak memory 199364 kb
Host smart-5af7909e-18a1-44a8-9552-711fd9d304c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986629971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3986629971
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3826304431
Short name T98
Test name
Test status
Simulation time 2366042806 ps
CPU time 3.92 seconds
Started Jan 03 12:49:14 PM PST 24
Finished Jan 03 12:49:36 PM PST 24
Peak memory 195592 kb
Host smart-ca6f47f4-bafc-4992-9e63-aa34ed3d9f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826304431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3826304431
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.719831823
Short name T848
Test name
Test status
Simulation time 801968303 ps
CPU time 3.31 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:50:23 PM PST 24
Peak memory 199452 kb
Host smart-dad18f30-bfdd-4ddd-b0d6-90fe395712e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719831823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.719831823
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2375632390
Short name T602
Test name
Test status
Simulation time 31007091613 ps
CPU time 317.1 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:55:16 PM PST 24
Peak memory 216880 kb
Host smart-25d65c2b-584e-4947-bf8f-08a5acc9dc06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375632390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2375632390
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.922368022
Short name T1008
Test name
Test status
Simulation time 623299448 ps
CPU time 2.14 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:49:39 PM PST 24
Peak memory 198036 kb
Host smart-9496e75b-df64-4cc3-89cf-0b42fe3cfa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922368022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.922368022
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.748813305
Short name T657
Test name
Test status
Simulation time 94226299338 ps
CPU time 80.45 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:51:47 PM PST 24
Peak memory 200320 kb
Host smart-a13dd823-6601-4fa5-b51a-c08adaede53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748813305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.748813305
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1057083524
Short name T1047
Test name
Test status
Simulation time 12298546 ps
CPU time 0.58 seconds
Started Jan 03 12:49:42 PM PST 24
Finished Jan 03 12:49:54 PM PST 24
Peak memory 194744 kb
Host smart-06cd7833-b3c7-4886-8833-114155b84792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057083524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1057083524
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.397606933
Short name T1168
Test name
Test status
Simulation time 36841511394 ps
CPU time 17.31 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:16 PM PST 24
Peak memory 199480 kb
Host smart-57812f86-cb1f-4ef3-8aad-5107e1a23546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397606933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.397606933
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2314584618
Short name T882
Test name
Test status
Simulation time 40618346751 ps
CPU time 61.33 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 199976 kb
Host smart-6124a9ef-037f-45f9-a7ff-e037c673f6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314584618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2314584618
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2807081435
Short name T184
Test name
Test status
Simulation time 16750384115 ps
CPU time 33.39 seconds
Started Jan 03 12:49:20 PM PST 24
Finished Jan 03 12:50:11 PM PST 24
Peak memory 200008 kb
Host smart-8d71a3ec-6ec4-435f-a6eb-39ad4867a7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807081435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2807081435
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3061634974
Short name T1219
Test name
Test status
Simulation time 270160156214 ps
CPU time 108.39 seconds
Started Jan 03 12:49:41 PM PST 24
Finished Jan 03 12:51:42 PM PST 24
Peak memory 200176 kb
Host smart-b7c1f886-6abd-49cf-8cea-537c0e83084c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061634974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3061634974
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2100867701
Short name T633
Test name
Test status
Simulation time 189901814326 ps
CPU time 178.99 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:52:57 PM PST 24
Peak memory 200088 kb
Host smart-01e76099-bf2c-4581-9412-70464abd04d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100867701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2100867701
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1871000923
Short name T499
Test name
Test status
Simulation time 4001978198 ps
CPU time 7.91 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:49:56 PM PST 24
Peak memory 198948 kb
Host smart-eb95cd24-aa05-410f-bfee-9840e6e4367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871000923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1871000923
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.868879546
Short name T99
Test name
Test status
Simulation time 44159558758 ps
CPU time 17.47 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:16 PM PST 24
Peak memory 195076 kb
Host smart-95f4e7c5-1e50-487d-9c11-9fe0e0b88e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868879546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.868879546
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2496684561
Short name T995
Test name
Test status
Simulation time 2477113413 ps
CPU time 134.97 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:52:50 PM PST 24
Peak memory 200056 kb
Host smart-f40effa0-64f8-4356-8e7f-789321cd2a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496684561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2496684561
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3833296931
Short name T658
Test name
Test status
Simulation time 2792162576 ps
CPU time 5.73 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:50:23 PM PST 24
Peak memory 198800 kb
Host smart-213ff243-af35-444e-86b9-c8c88964a990
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833296931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3833296931
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1269173891
Short name T1218
Test name
Test status
Simulation time 34514609248 ps
CPU time 50.73 seconds
Started Jan 03 12:50:16 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 200196 kb
Host smart-61bc37af-e777-467e-b00f-0e842e03890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269173891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1269173891
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4182082675
Short name T1009
Test name
Test status
Simulation time 5302350812 ps
CPU time 8.08 seconds
Started Jan 03 12:49:27 PM PST 24
Finished Jan 03 12:49:53 PM PST 24
Peak memory 196008 kb
Host smart-3c9bf713-3e8d-4111-89a4-76d47cf80367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182082675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4182082675
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4032950996
Short name T410
Test name
Test status
Simulation time 307112178 ps
CPU time 1.39 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 12:49:52 PM PST 24
Peak memory 197940 kb
Host smart-aab3133d-7f9b-44a5-975d-165dff089985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032950996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4032950996
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2809016446
Short name T333
Test name
Test status
Simulation time 109516485123 ps
CPU time 217.7 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:53:52 PM PST 24
Peak memory 200164 kb
Host smart-4c60e226-fae0-42e0-b89c-6ddc98cc9eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809016446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2809016446
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2067403532
Short name T558
Test name
Test status
Simulation time 1525019582 ps
CPU time 1.93 seconds
Started Jan 03 12:50:19 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 198696 kb
Host smart-ecd8d221-77de-4c92-81b9-bad002bf2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067403532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2067403532
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3545008334
Short name T1109
Test name
Test status
Simulation time 35966548671 ps
CPU time 23.04 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 200116 kb
Host smart-1220aca1-b47d-4b4b-80f9-6153fb852023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545008334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3545008334
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.4177690253
Short name T694
Test name
Test status
Simulation time 23703376 ps
CPU time 0.55 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:11 PM PST 24
Peak memory 194680 kb
Host smart-d946d25d-6d76-4793-a7a8-e1227818a27c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177690253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.4177690253
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1095552649
Short name T1063
Test name
Test status
Simulation time 31459729327 ps
CPU time 51.98 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:51:27 PM PST 24
Peak memory 200148 kb
Host smart-daba659a-393c-483d-8e1c-a43f565d1235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095552649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1095552649
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3258395732
Short name T569
Test name
Test status
Simulation time 64727305912 ps
CPU time 100.49 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:51:31 PM PST 24
Peak memory 199856 kb
Host smart-47346b71-2537-4f7f-900f-39d0ad3dcc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258395732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3258395732
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1870855247
Short name T151
Test name
Test status
Simulation time 155566394297 ps
CPU time 55.71 seconds
Started Jan 03 12:49:29 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 200132 kb
Host smart-adeef157-9db8-4ced-b789-2b4c0eb8c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870855247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1870855247
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.412427743
Short name T128
Test name
Test status
Simulation time 2285355111340 ps
CPU time 2137.87 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 01:25:31 PM PST 24
Peak memory 200212 kb
Host smart-3c19e904-cec3-447e-b379-94c94ae8f8e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412427743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.412427743
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1928886157
Short name T803
Test name
Test status
Simulation time 103765925313 ps
CPU time 234.83 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:54:08 PM PST 24
Peak memory 200132 kb
Host smart-cb227a74-5d74-4962-9421-f67d30ca9363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928886157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1928886157
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.429314673
Short name T782
Test name
Test status
Simulation time 11241626496 ps
CPU time 6.29 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:41 PM PST 24
Peak memory 198904 kb
Host smart-d91733c6-02ef-4fbe-88db-0b4d0e262cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429314673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.429314673
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2600597796
Short name T207
Test name
Test status
Simulation time 81534508132 ps
CPU time 32.57 seconds
Started Jan 03 12:49:53 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 200312 kb
Host smart-039a0cf3-201b-46b1-9b73-bac5e401c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600597796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2600597796
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3821978363
Short name T417
Test name
Test status
Simulation time 12905856672 ps
CPU time 537.06 seconds
Started Jan 03 12:49:57 PM PST 24
Finished Jan 03 12:59:16 PM PST 24
Peak memory 200208 kb
Host smart-f656fc40-f0a5-466a-82de-9d946aa131f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821978363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3821978363
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3225496159
Short name T967
Test name
Test status
Simulation time 4039858440 ps
CPU time 7.72 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:50:42 PM PST 24
Peak memory 198580 kb
Host smart-293c702c-c54c-45bb-af74-a7593a4813f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225496159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3225496159
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3404250615
Short name T615
Test name
Test status
Simulation time 60421195575 ps
CPU time 26.48 seconds
Started Jan 03 12:49:52 PM PST 24
Finished Jan 03 12:50:34 PM PST 24
Peak memory 200060 kb
Host smart-723962fb-87dc-452b-8551-33ac385895b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404250615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3404250615
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3614721429
Short name T1036
Test name
Test status
Simulation time 2905033539 ps
CPU time 1.73 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 12:50:35 PM PST 24
Peak memory 195768 kb
Host smart-c5def3b7-bb33-4c03-9180-f488be02af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614721429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3614721429
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3014690546
Short name T758
Test name
Test status
Simulation time 499155387 ps
CPU time 1.49 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:49:54 PM PST 24
Peak memory 198540 kb
Host smart-388d42f1-b46a-41e8-8f4d-edc407f58004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014690546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3014690546
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2436388836
Short name T562
Test name
Test status
Simulation time 30012786887 ps
CPU time 54.49 seconds
Started Jan 03 12:49:45 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 200128 kb
Host smart-ad59523d-831c-4d79-a0c1-0e088c372e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436388836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2436388836
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3970401229
Short name T435
Test name
Test status
Simulation time 391144743262 ps
CPU time 365.88 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:56:49 PM PST 24
Peak memory 208640 kb
Host smart-6f3d507a-15f8-4afb-9786-919c9ec0c4ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970401229 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3970401229
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.612028601
Short name T719
Test name
Test status
Simulation time 6962189636 ps
CPU time 29.13 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:29 PM PST 24
Peak memory 200120 kb
Host smart-8bb2c2da-d736-48eb-a6ca-efcb59390b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612028601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.612028601
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2285119560
Short name T892
Test name
Test status
Simulation time 31559484043 ps
CPU time 19.82 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 200096 kb
Host smart-54debc5a-f9eb-47b0-93a4-0c241e6f069c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285119560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2285119560
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.250440026
Short name T998
Test name
Test status
Simulation time 15250540 ps
CPU time 0.54 seconds
Started Jan 03 12:49:23 PM PST 24
Finished Jan 03 12:49:42 PM PST 24
Peak memory 195544 kb
Host smart-44a24059-ff32-4479-92a9-14e414142156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250440026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.250440026
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2979151946
Short name T864
Test name
Test status
Simulation time 104046388536 ps
CPU time 35.86 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:50:50 PM PST 24
Peak memory 200160 kb
Host smart-1b95959e-db03-41a0-8d78-50c72720287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979151946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2979151946
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2921832918
Short name T796
Test name
Test status
Simulation time 89867592113 ps
CPU time 124.45 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:51:58 PM PST 24
Peak memory 199336 kb
Host smart-40949e34-f786-4b49-bede-86d0a2d44127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921832918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2921832918
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.494195138
Short name T582
Test name
Test status
Simulation time 43340012258 ps
CPU time 18.7 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:51:01 PM PST 24
Peak memory 200132 kb
Host smart-4a6a9448-1c95-46af-b75c-c6bf10403e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494195138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.494195138
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3488849466
Short name T1091
Test name
Test status
Simulation time 27812126614 ps
CPU time 115.56 seconds
Started Jan 03 12:50:18 PM PST 24
Finished Jan 03 12:52:36 PM PST 24
Peak memory 200108 kb
Host smart-3cb05280-4c76-461e-893f-d39bbed8b619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488849466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3488849466
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1267203506
Short name T1082
Test name
Test status
Simulation time 13784378511 ps
CPU time 23.9 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:46 PM PST 24
Peak memory 199384 kb
Host smart-541fc4cd-5dc1-4ba6-a19c-562b803b50d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267203506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1267203506
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2374080033
Short name T214
Test name
Test status
Simulation time 117637785994 ps
CPU time 180.51 seconds
Started Jan 03 12:50:18 PM PST 24
Finished Jan 03 12:53:41 PM PST 24
Peak memory 199544 kb
Host smart-8e1f13dc-aa23-4743-889d-605c3a2793df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374080033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2374080033
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1623628764
Short name T1199
Test name
Test status
Simulation time 11269654404 ps
CPU time 513.78 seconds
Started Jan 03 12:49:52 PM PST 24
Finished Jan 03 12:58:41 PM PST 24
Peak memory 200060 kb
Host smart-22ea0184-b00a-45a1-b7e1-2941e28973e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1623628764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1623628764
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2731681459
Short name T1137
Test name
Test status
Simulation time 1376119291 ps
CPU time 5.53 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:49:55 PM PST 24
Peak memory 197660 kb
Host smart-d014d6aa-0267-408a-a8ff-f3adc24e5961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731681459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2731681459
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.4162258159
Short name T732
Test name
Test status
Simulation time 33333007006 ps
CPU time 14.01 seconds
Started Jan 03 12:50:16 PM PST 24
Finished Jan 03 12:50:52 PM PST 24
Peak memory 195920 kb
Host smart-840e65d6-fd99-4e6b-9570-aebe7ec9f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162258159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.4162258159
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.914378679
Short name T549
Test name
Test status
Simulation time 512369677 ps
CPU time 1.37 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:06 PM PST 24
Peak memory 198236 kb
Host smart-770a347b-f827-411f-962c-648a4816f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914378679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.914378679
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1344128908
Short name T722
Test name
Test status
Simulation time 65725657085 ps
CPU time 70.75 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:52:26 PM PST 24
Peak memory 199588 kb
Host smart-ee201974-1c27-430c-a5a0-8c58591abc13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344128908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1344128908
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.3461634992
Short name T960
Test name
Test status
Simulation time 27687116495 ps
CPU time 304.65 seconds
Started Jan 03 12:49:51 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 216492 kb
Host smart-9973f2c7-d4f0-419d-bfd5-e184831e0374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461634992 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.3461634992
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3171825852
Short name T433
Test name
Test status
Simulation time 2970729892 ps
CPU time 2.18 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:51:33 PM PST 24
Peak memory 198408 kb
Host smart-f796a60a-5c29-4321-9a5c-682c15391517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171825852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3171825852
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2505963313
Short name T919
Test name
Test status
Simulation time 67440784806 ps
CPU time 64.52 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 200028 kb
Host smart-ba292e48-17f5-4a1d-9d34-f1ee338c127b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505963313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2505963313
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.108646270
Short name T605
Test name
Test status
Simulation time 12979626 ps
CPU time 0.54 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 195612 kb
Host smart-345b100d-98cd-4fac-a73d-51c317c0b995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108646270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.108646270
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3660618643
Short name T1194
Test name
Test status
Simulation time 246610386399 ps
CPU time 100.69 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:50:39 PM PST 24
Peak memory 200100 kb
Host smart-187b1735-f220-4391-80d5-bfd7ae81708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660618643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3660618643
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2247780309
Short name T1206
Test name
Test status
Simulation time 156007502519 ps
CPU time 76.79 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:50:12 PM PST 24
Peak memory 199656 kb
Host smart-da713f8b-9d9a-4b37-b52c-baa7e5dd2ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247780309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2247780309
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3907403217
Short name T1061
Test name
Test status
Simulation time 35577290940 ps
CPU time 32.04 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 200236 kb
Host smart-14082b03-a2ef-4555-bfd8-eecb8257edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907403217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3907403217
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3001034702
Short name T988
Test name
Test status
Simulation time 472295002531 ps
CPU time 694.7 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 01:00:16 PM PST 24
Peak memory 200044 kb
Host smart-cd6536e4-2ee1-4064-9218-77806066f288
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001034702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3001034702
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.743100500
Short name T1068
Test name
Test status
Simulation time 131832613343 ps
CPU time 181.52 seconds
Started Jan 03 12:48:10 PM PST 24
Finished Jan 03 12:51:39 PM PST 24
Peak memory 200160 kb
Host smart-1d6c769f-d51b-4e57-ad83-b5a395ce07f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743100500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.743100500
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1883714652
Short name T537
Test name
Test status
Simulation time 4717248242 ps
CPU time 9.54 seconds
Started Jan 03 12:48:11 PM PST 24
Finished Jan 03 12:48:48 PM PST 24
Peak memory 199196 kb
Host smart-f2a92563-0d0f-4413-9772-1aa7d92bce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883714652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1883714652
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.416096124
Short name T954
Test name
Test status
Simulation time 189299763277 ps
CPU time 51.26 seconds
Started Jan 03 12:48:12 PM PST 24
Finished Jan 03 12:49:30 PM PST 24
Peak memory 208380 kb
Host smart-d0da4a49-5845-47ab-b036-2fc5adfc810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416096124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.416096124
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.737671713
Short name T1029
Test name
Test status
Simulation time 11585534764 ps
CPU time 636.08 seconds
Started Jan 03 12:48:34 PM PST 24
Finished Jan 03 12:59:35 PM PST 24
Peak memory 200236 kb
Host smart-a793ab78-4855-4843-bced-5f9b25ba8918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737671713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.737671713
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2087326365
Short name T906
Test name
Test status
Simulation time 2118795215 ps
CPU time 11.39 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 197732 kb
Host smart-18a8804f-099f-4824-a956-b075a2f34cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087326365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2087326365
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3582186099
Short name T97
Test name
Test status
Simulation time 149479196370 ps
CPU time 103.64 seconds
Started Jan 03 12:47:56 PM PST 24
Finished Jan 03 12:50:15 PM PST 24
Peak memory 200124 kb
Host smart-b6ed038c-f672-40f1-a069-87f20879fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582186099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3582186099
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1029129347
Short name T815
Test name
Test status
Simulation time 1567480060 ps
CPU time 1.23 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:48:46 PM PST 24
Peak memory 195644 kb
Host smart-8c4c2409-8bda-40ea-a3a2-9183f0022baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029129347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1029129347
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.200918657
Short name T618
Test name
Test status
Simulation time 451410893 ps
CPU time 2.18 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:48:48 PM PST 24
Peak memory 198128 kb
Host smart-0beeb470-03a4-4829-a55b-0f7a20c04d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200918657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.200918657
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.4686309
Short name T702
Test name
Test status
Simulation time 497133857141 ps
CPU time 623.15 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:59:09 PM PST 24
Peak memory 200188 kb
Host smart-536c4cbd-0d8d-45c3-8c8d-11d4937cd131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4686309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.4686309
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1755405290
Short name T1015
Test name
Test status
Simulation time 46972641107 ps
CPU time 108.63 seconds
Started Jan 03 12:48:09 PM PST 24
Finished Jan 03 12:50:25 PM PST 24
Peak memory 216556 kb
Host smart-50586634-c5bf-4695-b4f2-ae3a10de177f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755405290 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1755405290
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.4035346932
Short name T459
Test name
Test status
Simulation time 1290690630 ps
CPU time 2.04 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 198116 kb
Host smart-019743cc-5d15-40ef-9b33-9c9a0164233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035346932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4035346932
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3979120078
Short name T309
Test name
Test status
Simulation time 130451588632 ps
CPU time 139.29 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 200232 kb
Host smart-592ca3a9-672f-413b-a7f2-439c2ed5efa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979120078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3979120078
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1356257
Short name T123
Test name
Test status
Simulation time 24587492844 ps
CPU time 55.55 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:51:00 PM PST 24
Peak memory 200152 kb
Host smart-720e633e-12eb-4f98-91e6-856e314ad6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1356257
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4118341480
Short name T456
Test name
Test status
Simulation time 13444908492 ps
CPU time 197.66 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:53:10 PM PST 24
Peak memory 215732 kb
Host smart-c2922493-b8e3-4a9a-ae7f-fa8c09f0e783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118341480 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4118341480
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3012795905
Short name T819
Test name
Test status
Simulation time 82865736376 ps
CPU time 357.87 seconds
Started Jan 03 12:49:31 PM PST 24
Finished Jan 03 12:55:45 PM PST 24
Peak memory 216848 kb
Host smart-d1811d84-4d24-4ff0-80f8-5b1d34737075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012795905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3012795905
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1049000751
Short name T236
Test name
Test status
Simulation time 39912796375 ps
CPU time 67.96 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:51:25 PM PST 24
Peak memory 200208 kb
Host smart-71ffcf59-3dcb-493a-b0fb-38a5a28eb455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049000751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1049000751
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1890847074
Short name T345
Test name
Test status
Simulation time 31183717684 ps
CPU time 14.69 seconds
Started Jan 03 12:50:06 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 199512 kb
Host smart-b50eb454-efe2-44ef-8c19-01155fec53ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890847074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1890847074
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1486938843
Short name T536
Test name
Test status
Simulation time 20978367823 ps
CPU time 347.3 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:55:59 PM PST 24
Peak memory 215748 kb
Host smart-6c19a57a-cce1-43dd-9c01-c84cebb2b4d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486938843 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1486938843
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2533724647
Short name T834
Test name
Test status
Simulation time 12645588825 ps
CPU time 21.34 seconds
Started Jan 03 12:49:29 PM PST 24
Finished Jan 03 12:50:07 PM PST 24
Peak memory 199788 kb
Host smart-b52886fd-fa5a-4751-897a-43593c23dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533724647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2533724647
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.567550930
Short name T291
Test name
Test status
Simulation time 55205324050 ps
CPU time 216.27 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:53:29 PM PST 24
Peak memory 208476 kb
Host smart-bfe9cc32-5616-4f8b-9a14-bb61c940b3b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567550930 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.567550930
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3751732014
Short name T1201
Test name
Test status
Simulation time 158595970994 ps
CPU time 566.03 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:59:31 PM PST 24
Peak memory 216644 kb
Host smart-7aa1b070-6d4b-46a8-93ee-9f07b57aa4f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751732014 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3751732014
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.17066728
Short name T1052
Test name
Test status
Simulation time 83840303106 ps
CPU time 40.32 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:50:53 PM PST 24
Peak memory 200064 kb
Host smart-1eafe7eb-358e-4607-a2de-fc8339e5bcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17066728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.17066728
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1831548447
Short name T797
Test name
Test status
Simulation time 89953921633 ps
CPU time 662.83 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 01:01:25 PM PST 24
Peak memory 225028 kb
Host smart-451399e6-e228-4add-b5a1-97e0bc7a6c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831548447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1831548447
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2183423897
Short name T306
Test name
Test status
Simulation time 129618427764 ps
CPU time 133.78 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:53:05 PM PST 24
Peak memory 200112 kb
Host smart-e03f32c7-4518-45bf-99d0-82c8f84f62e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183423897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2183423897
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2470345385
Short name T1030
Test name
Test status
Simulation time 57670051450 ps
CPU time 845.65 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 01:04:41 PM PST 24
Peak memory 216936 kb
Host smart-badb71a5-df1d-48bf-a805-a75f4ab4888a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470345385 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2470345385
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.762792733
Short name T950
Test name
Test status
Simulation time 11565644763 ps
CPU time 23.1 seconds
Started Jan 03 12:50:01 PM PST 24
Finished Jan 03 12:50:49 PM PST 24
Peak memory 200228 kb
Host smart-f5c4a17f-66af-409c-827d-faa904409790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762792733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.762792733
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.4137826768
Short name T953
Test name
Test status
Simulation time 73886640788 ps
CPU time 269.13 seconds
Started Jan 03 12:50:11 PM PST 24
Finished Jan 03 12:55:03 PM PST 24
Peak memory 216340 kb
Host smart-71be6809-d26f-44db-86dd-b903a25d9fb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137826768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.4137826768
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.4002313825
Short name T601
Test name
Test status
Simulation time 10672575322 ps
CPU time 17.16 seconds
Started Jan 03 12:49:21 PM PST 24
Finished Jan 03 12:49:56 PM PST 24
Peak memory 198444 kb
Host smart-1daf67e2-0b16-4702-a293-93c76ed3f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002313825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4002313825
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2027886993
Short name T1074
Test name
Test status
Simulation time 67975557710 ps
CPU time 762.73 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 01:02:45 PM PST 24
Peak memory 216628 kb
Host smart-799d3a07-b636-4c2a-a804-5859861d7c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027886993 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2027886993
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.764030052
Short name T881
Test name
Test status
Simulation time 17712166 ps
CPU time 0.56 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:43 PM PST 24
Peak memory 195616 kb
Host smart-dd59fc79-5973-44b7-b9fa-de2195e8d29d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764030052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.764030052
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3678581059
Short name T850
Test name
Test status
Simulation time 157596126074 ps
CPU time 520.3 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:57:24 PM PST 24
Peak memory 200168 kb
Host smart-0108df8a-a9e5-4b85-938a-9f742ce8feb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678581059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3678581059
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2356589303
Short name T428
Test name
Test status
Simulation time 114621038085 ps
CPU time 44.87 seconds
Started Jan 03 12:48:09 PM PST 24
Finished Jan 03 12:49:22 PM PST 24
Peak memory 199372 kb
Host smart-b52f79a1-8fa9-4587-8232-efe64a3b3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356589303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2356589303
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1167491731
Short name T624
Test name
Test status
Simulation time 124426292026 ps
CPU time 45.03 seconds
Started Jan 03 12:48:48 PM PST 24
Finished Jan 03 12:49:56 PM PST 24
Peak memory 200232 kb
Host smart-8239694e-f586-42d3-b27e-83359e43fca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167491731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1167491731
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4177193686
Short name T1207
Test name
Test status
Simulation time 73181838254 ps
CPU time 147.8 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 200144 kb
Host smart-a9da2cf5-9df0-4129-b6c9-820c0f7b4eb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177193686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4177193686
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.690853716
Short name T1021
Test name
Test status
Simulation time 3893265921 ps
CPU time 1.93 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:48:48 PM PST 24
Peak memory 199072 kb
Host smart-20e635f1-9a39-4495-8f82-8c8541c11e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690853716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.690853716
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.4011246074
Short name T1159
Test name
Test status
Simulation time 364460197819 ps
CPU time 76.34 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:49:57 PM PST 24
Peak memory 208448 kb
Host smart-8f4fa7c3-c5ff-41fc-9437-b3a815e90094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011246074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.4011246074
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.776572354
Short name T1034
Test name
Test status
Simulation time 23847460736 ps
CPU time 332.2 seconds
Started Jan 03 12:48:41 PM PST 24
Finished Jan 03 12:54:39 PM PST 24
Peak memory 200232 kb
Host smart-46e36e30-47df-4f9e-9cd7-3ab7725eda58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776572354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.776572354
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1286207192
Short name T675
Test name
Test status
Simulation time 820931762 ps
CPU time 4.74 seconds
Started Jan 03 12:48:08 PM PST 24
Finished Jan 03 12:48:41 PM PST 24
Peak memory 197992 kb
Host smart-dabeaed0-2f31-40d7-9fa7-fc0a8002ce16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1286207192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1286207192
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3221740800
Short name T578
Test name
Test status
Simulation time 78648433586 ps
CPU time 19.52 seconds
Started Jan 03 12:48:12 PM PST 24
Finished Jan 03 12:48:58 PM PST 24
Peak memory 200160 kb
Host smart-9e153968-e4e4-42e2-bba4-ba66249b1806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221740800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3221740800
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3027383543
Short name T847
Test name
Test status
Simulation time 57712481869 ps
CPU time 9.06 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:48:54 PM PST 24
Peak memory 195844 kb
Host smart-f1cc4708-3140-4064-8302-c14ea5a32566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027383543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3027383543
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4004634789
Short name T623
Test name
Test status
Simulation time 579007587 ps
CPU time 1.47 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:44 PM PST 24
Peak memory 198040 kb
Host smart-4c54e23a-9352-43e0-88ad-40ad69dd7f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004634789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4004634789
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3320820821
Short name T760
Test name
Test status
Simulation time 99798512323 ps
CPU time 104.07 seconds
Started Jan 03 12:48:07 PM PST 24
Finished Jan 03 12:50:20 PM PST 24
Peak memory 200084 kb
Host smart-8c3ae865-727b-4d8c-858f-0f39984f281f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320820821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3320820821
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1044769122
Short name T1057
Test name
Test status
Simulation time 7686155093 ps
CPU time 8.53 seconds
Started Jan 03 12:48:17 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 199688 kb
Host smart-94a4616c-51a9-424d-89b2-add331358a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044769122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1044769122
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2476694165
Short name T1003
Test name
Test status
Simulation time 29066577680 ps
CPU time 39.67 seconds
Started Jan 03 12:48:14 PM PST 24
Finished Jan 03 12:49:20 PM PST 24
Peak memory 200184 kb
Host smart-7517b157-387e-4186-9150-20ac45cdb514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476694165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2476694165
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3499640436
Short name T1150
Test name
Test status
Simulation time 52266511776 ps
CPU time 98.21 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:51:27 PM PST 24
Peak memory 200068 kb
Host smart-38b4b1db-d555-40f7-bccc-96efe4574353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499640436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3499640436
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1065833140
Short name T328
Test name
Test status
Simulation time 33098270943 ps
CPU time 28.87 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:50:22 PM PST 24
Peak memory 200048 kb
Host smart-1816b8cd-7f1c-4ae2-9bc7-02cc4e29e6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065833140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1065833140
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2522169942
Short name T455
Test name
Test status
Simulation time 41226500028 ps
CPU time 381.84 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:56:18 PM PST 24
Peak memory 216656 kb
Host smart-bebee115-aaa9-4494-b58d-be5af49b59e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522169942 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2522169942
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3251232967
Short name T888
Test name
Test status
Simulation time 39102925809 ps
CPU time 38.75 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:50:38 PM PST 24
Peak memory 200108 kb
Host smart-1d8ca747-f679-42ba-b920-8ab1009c702d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251232967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3251232967
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.858065905
Short name T552
Test name
Test status
Simulation time 21965977214 ps
CPU time 643.38 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 01:00:49 PM PST 24
Peak memory 216028 kb
Host smart-4627509e-638b-4151-8a07-b90560e9c74d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858065905 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.858065905
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2131651972
Short name T172
Test name
Test status
Simulation time 81229299885 ps
CPU time 44.75 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:51:00 PM PST 24
Peak memory 200096 kb
Host smart-40285090-2b3a-45d3-bfbe-b8c1605aa6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131651972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2131651972
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.75459295
Short name T1033
Test name
Test status
Simulation time 45984896208 ps
CPU time 141.32 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:52:16 PM PST 24
Peak memory 215808 kb
Host smart-13e3567b-8d9d-4162-9bc6-03b90ff57bc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75459295 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.75459295
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3375966634
Short name T177
Test name
Test status
Simulation time 56733340507 ps
CPU time 39.2 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:51:15 PM PST 24
Peak memory 200052 kb
Host smart-4a2eba20-54b1-47e6-a198-43bf02ade352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375966634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3375966634
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3888620345
Short name T269
Test name
Test status
Simulation time 20537773443 ps
CPU time 27.78 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 200100 kb
Host smart-729f30b6-b809-458f-a02b-b2271e50386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888620345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3888620345
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3507176845
Short name T397
Test name
Test status
Simulation time 462043597118 ps
CPU time 976.19 seconds
Started Jan 03 12:49:23 PM PST 24
Finished Jan 03 01:05:57 PM PST 24
Peak memory 225172 kb
Host smart-e09164c5-ceba-4822-ab34-9b9943e0f023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507176845 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3507176845
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.813468830
Short name T1028
Test name
Test status
Simulation time 100419150838 ps
CPU time 16.68 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:50:13 PM PST 24
Peak memory 200140 kb
Host smart-03f1513a-c745-483e-8933-96f899ff8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813468830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.813468830
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.4100288720
Short name T778
Test name
Test status
Simulation time 128322952454 ps
CPU time 1863.28 seconds
Started Jan 03 12:50:02 PM PST 24
Finished Jan 03 01:21:30 PM PST 24
Peak memory 216832 kb
Host smart-c9107df1-7128-42c2-ada4-d5c995d43807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100288720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4100288720
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.981118771
Short name T1110
Test name
Test status
Simulation time 106261502725 ps
CPU time 176.48 seconds
Started Jan 03 12:50:24 PM PST 24
Finished Jan 03 12:53:42 PM PST 24
Peak memory 200088 kb
Host smart-ca4cfca8-2af3-4589-8452-7c12113fe1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981118771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.981118771
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1725562550
Short name T996
Test name
Test status
Simulation time 84240660384 ps
CPU time 1351.78 seconds
Started Jan 03 12:50:23 PM PST 24
Finished Jan 03 01:13:17 PM PST 24
Peak memory 225144 kb
Host smart-f05199e4-f93c-4d47-a8e5-ae8e9a1786ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725562550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1725562550
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3896683099
Short name T241
Test name
Test status
Simulation time 42622786476 ps
CPU time 18.55 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:50:07 PM PST 24
Peak memory 200124 kb
Host smart-d0b30b76-a77b-4a82-b478-f94fe2d58fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896683099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3896683099
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.27868321
Short name T1071
Test name
Test status
Simulation time 98355422788 ps
CPU time 691.03 seconds
Started Jan 03 12:50:14 PM PST 24
Finished Jan 03 01:02:07 PM PST 24
Peak memory 216572 kb
Host smart-47761efd-248f-4d77-838b-7a8844d15926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27868321 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.27868321
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1238380632
Short name T273
Test name
Test status
Simulation time 50994475153 ps
CPU time 24.5 seconds
Started Jan 03 12:50:07 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 200240 kb
Host smart-cf1dcded-7bf4-4029-903e-cb4561e545b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238380632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1238380632
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2159743732
Short name T783
Test name
Test status
Simulation time 86083323442 ps
CPU time 803.21 seconds
Started Jan 03 12:50:22 PM PST 24
Finished Jan 03 01:04:08 PM PST 24
Peak memory 225132 kb
Host smart-21310975-4424-422e-8fdd-9d6951b86eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159743732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2159743732
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2604164394
Short name T1223
Test name
Test status
Simulation time 18799095 ps
CPU time 0.52 seconds
Started Jan 03 12:48:53 PM PST 24
Finished Jan 03 12:49:15 PM PST 24
Peak memory 194568 kb
Host smart-3d24a8fb-4492-4058-a17e-dc7bee797070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604164394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2604164394
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2312338365
Short name T1119
Test name
Test status
Simulation time 37114179967 ps
CPU time 15.31 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:49:03 PM PST 24
Peak memory 200096 kb
Host smart-5e94cdea-85a9-4d0a-86fb-b8ea24c3c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312338365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2312338365
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1517116966
Short name T683
Test name
Test status
Simulation time 101253866786 ps
CPU time 95.7 seconds
Started Jan 03 12:48:04 PM PST 24
Finished Jan 03 12:50:11 PM PST 24
Peak memory 200112 kb
Host smart-3f431102-dc5e-49f9-acd6-d14d10e72757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517116966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1517116966
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.675196217
Short name T976
Test name
Test status
Simulation time 920650319308 ps
CPU time 363.23 seconds
Started Jan 03 12:48:25 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 200020 kb
Host smart-a4363473-9c03-4cb0-ba86-a20dc36378f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675196217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.675196217
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3927213814
Short name T406
Test name
Test status
Simulation time 65167793717 ps
CPU time 152.41 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 12:51:19 PM PST 24
Peak memory 200104 kb
Host smart-3babab27-249e-411c-8e2e-71676e9f0df1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927213814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3927213814
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1929034472
Short name T1121
Test name
Test status
Simulation time 54629062 ps
CPU time 0.55 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:05 PM PST 24
Peak memory 195524 kb
Host smart-d53ea329-ff94-4312-9dd4-ba867f46a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929034472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1929034472
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.850046765
Short name T1080
Test name
Test status
Simulation time 38681421257 ps
CPU time 66.34 seconds
Started Jan 03 12:48:20 PM PST 24
Finished Jan 03 12:49:51 PM PST 24
Peak memory 200092 kb
Host smart-05a524db-795c-4adf-a67b-f64352e776fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850046765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.850046765
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1277712373
Short name T267
Test name
Test status
Simulation time 5428107803 ps
CPU time 150.18 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 200124 kb
Host smart-bf3d9c24-0677-486d-b0aa-b93ef2e5100f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1277712373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1277712373
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3651475513
Short name T1076
Test name
Test status
Simulation time 3758599052 ps
CPU time 13.47 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:00 PM PST 24
Peak memory 198224 kb
Host smart-287fb6b1-b40d-4da8-bfa5-d94a4abe61ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651475513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3651475513
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.790979041
Short name T302
Test name
Test status
Simulation time 103292074628 ps
CPU time 36.35 seconds
Started Jan 03 12:48:24 PM PST 24
Finished Jan 03 12:49:23 PM PST 24
Peak memory 200068 kb
Host smart-94774627-cf21-4dd3-bae0-10e633cdf943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790979041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.790979041
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4119949452
Short name T851
Test name
Test status
Simulation time 3154470878 ps
CPU time 3.36 seconds
Started Jan 03 12:48:20 PM PST 24
Finished Jan 03 12:48:48 PM PST 24
Peak memory 195880 kb
Host smart-8dd2f880-7ce7-408f-b113-1f2de185fe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119949452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4119949452
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1295061784
Short name T982
Test name
Test status
Simulation time 5446058393 ps
CPU time 8.63 seconds
Started Jan 03 12:48:16 PM PST 24
Finished Jan 03 12:48:51 PM PST 24
Peak memory 199664 kb
Host smart-2dc090ec-af60-4a14-b236-973ae60d7314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295061784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1295061784
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1100775623
Short name T610
Test name
Test status
Simulation time 124865557998 ps
CPU time 52.36 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:49:35 PM PST 24
Peak memory 200140 kb
Host smart-a83a6440-643c-4fef-ab20-117855289d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100775623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1100775623
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.313911599
Short name T86
Test name
Test status
Simulation time 189013835715 ps
CPU time 639.44 seconds
Started Jan 03 12:48:39 PM PST 24
Finished Jan 03 12:59:45 PM PST 24
Peak memory 216592 kb
Host smart-291d9cf9-4e87-49ad-929f-0ce3641d8d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313911599 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.313911599
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.543127394
Short name T520
Test name
Test status
Simulation time 1152415610 ps
CPU time 3.95 seconds
Started Jan 03 12:48:27 PM PST 24
Finished Jan 03 12:48:57 PM PST 24
Peak memory 198208 kb
Host smart-de9bf037-631a-471e-951a-be12c1ac7314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543127394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.543127394
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2391498223
Short name T576
Test name
Test status
Simulation time 25894145607 ps
CPU time 10.58 seconds
Started Jan 03 12:48:09 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 195916 kb
Host smart-4a78b145-8078-475d-b6a3-3de83f83282e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391498223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2391498223
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2303872297
Short name T259
Test name
Test status
Simulation time 100290593245 ps
CPU time 85.91 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 12:51:46 PM PST 24
Peak memory 199748 kb
Host smart-746f35ff-a51c-4a75-97f5-af6e7a777f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303872297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2303872297
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1534498871
Short name T763
Test name
Test status
Simulation time 153750424866 ps
CPU time 814.01 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 01:04:25 PM PST 24
Peak memory 215416 kb
Host smart-49c84067-1e07-4432-bea2-4c2e5bce0e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534498871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1534498871
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2337179795
Short name T1088
Test name
Test status
Simulation time 42460462831 ps
CPU time 29.53 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 12:52:06 PM PST 24
Peak memory 199784 kb
Host smart-588db402-b769-4232-8c20-ce75f8bd7838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337179795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2337179795
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2490425496
Short name T339
Test name
Test status
Simulation time 62367345883 ps
CPU time 136.89 seconds
Started Jan 03 12:49:52 PM PST 24
Finished Jan 03 12:52:25 PM PST 24
Peak memory 212808 kb
Host smart-f4783c10-5ca7-4ff9-bafd-19cf2ea44b4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490425496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2490425496
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1479066619
Short name T800
Test name
Test status
Simulation time 58017535933 ps
CPU time 78.37 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 200084 kb
Host smart-50760a61-e438-43ab-95a1-0e1b2b08bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479066619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1479066619
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2194557083
Short name T176
Test name
Test status
Simulation time 168655135807 ps
CPU time 127.57 seconds
Started Jan 03 12:51:05 PM PST 24
Finished Jan 03 12:53:32 PM PST 24
Peak memory 199520 kb
Host smart-fd73fecc-8059-4c3c-8579-fb88870a3c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194557083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2194557083
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3987695975
Short name T416
Test name
Test status
Simulation time 33500960552 ps
CPU time 189.24 seconds
Started Jan 03 12:51:09 PM PST 24
Finished Jan 03 12:54:36 PM PST 24
Peak memory 199812 kb
Host smart-41a82b8e-efc4-4889-9879-3327effcffc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987695975 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3987695975
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1294103140
Short name T235
Test name
Test status
Simulation time 70840400992 ps
CPU time 65.38 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 200212 kb
Host smart-00972399-354e-4eed-8f3b-4ec98f37a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294103140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1294103140
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1819726879
Short name T843
Test name
Test status
Simulation time 35093552967 ps
CPU time 533.67 seconds
Started Jan 03 12:49:56 PM PST 24
Finished Jan 03 12:59:11 PM PST 24
Peak memory 216848 kb
Host smart-58ef40e8-88fc-41d2-9bcc-bd5a9430ac6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819726879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1819726879
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3945738395
Short name T1077
Test name
Test status
Simulation time 364855454578 ps
CPU time 51.89 seconds
Started Jan 03 12:49:55 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 199684 kb
Host smart-4ee4a904-f79a-4c22-bd2b-ea3544c05928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945738395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3945738395
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2261546989
Short name T1217
Test name
Test status
Simulation time 67087643439 ps
CPU time 131.56 seconds
Started Jan 03 12:49:54 PM PST 24
Finished Jan 03 12:52:25 PM PST 24
Peak memory 208412 kb
Host smart-05f73958-b0cd-44ed-9d1a-16ca15c6bb56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261546989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2261546989
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4008605883
Short name T212
Test name
Test status
Simulation time 31267558001 ps
CPU time 16.31 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:14 PM PST 24
Peak memory 200060 kb
Host smart-05454f37-2a0c-49a3-a575-e9cbc8acaded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008605883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4008605883
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.912315187
Short name T1010
Test name
Test status
Simulation time 137212809071 ps
CPU time 304.61 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:54:57 PM PST 24
Peak memory 216864 kb
Host smart-c6771f74-f4d6-46e0-a7a3-ad5167307ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912315187 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.912315187
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.504938727
Short name T120
Test name
Test status
Simulation time 24714205920 ps
CPU time 44.8 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 200180 kb
Host smart-61c947d2-7076-43d6-a613-3245536f8d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504938727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.504938727
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3144889716
Short name T193
Test name
Test status
Simulation time 227114727450 ps
CPU time 604.25 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 01:00:00 PM PST 24
Peak memory 225020 kb
Host smart-f2609df9-9652-4f7a-aa60-7f0094fa68f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144889716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3144889716
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2922533809
Short name T679
Test name
Test status
Simulation time 25656312575 ps
CPU time 43.88 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:51:08 PM PST 24
Peak memory 200084 kb
Host smart-81b12af8-88d9-4778-9ce3-7b67a57b6e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922533809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2922533809
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1050430505
Short name T87
Test name
Test status
Simulation time 19499659869 ps
CPU time 225.57 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:53:44 PM PST 24
Peak memory 208396 kb
Host smart-822db0ab-5396-4d5e-a155-025c08628fd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050430505 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1050430505
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4013312695
Short name T867
Test name
Test status
Simulation time 37195336 ps
CPU time 0.56 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 195688 kb
Host smart-bd268667-7e8b-4f4f-a683-cb678b4e9b37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013312695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4013312695
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1809524263
Short name T647
Test name
Test status
Simulation time 27448640669 ps
CPU time 40.99 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:49:39 PM PST 24
Peak memory 200088 kb
Host smart-fcbc08af-01a6-4663-ad0e-40adcbbebace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809524263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1809524263
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.936597529
Short name T1158
Test name
Test status
Simulation time 38149809107 ps
CPU time 67.52 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:49:50 PM PST 24
Peak memory 200216 kb
Host smart-8ae2318d-5932-4cac-880f-a46ec6e9d10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936597529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.936597529
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2817181201
Short name T226
Test name
Test status
Simulation time 20827398977 ps
CPU time 37.99 seconds
Started Jan 03 12:48:54 PM PST 24
Finished Jan 03 12:49:54 PM PST 24
Peak memory 200092 kb
Host smart-aedeb788-71b7-4d1a-96d1-39b4f8474dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817181201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2817181201
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1526108089
Short name T608
Test name
Test status
Simulation time 467084107956 ps
CPU time 787.74 seconds
Started Jan 03 12:48:23 PM PST 24
Finished Jan 03 01:01:54 PM PST 24
Peak memory 200192 kb
Host smart-f66c9d41-fa23-42dd-88d3-a8a566d865ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526108089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1526108089
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3291674317
Short name T429
Test name
Test status
Simulation time 71735676989 ps
CPU time 356.7 seconds
Started Jan 03 12:48:20 PM PST 24
Finished Jan 03 12:54:42 PM PST 24
Peak memory 200096 kb
Host smart-39d852e5-481a-45b7-b372-6406ae556a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291674317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3291674317
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2465221365
Short name T637
Test name
Test status
Simulation time 154927173587 ps
CPU time 88.38 seconds
Started Jan 03 12:48:45 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 200488 kb
Host smart-4a34b90f-5892-40bd-af6d-a0ddeb9bd673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465221365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2465221365
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3455465251
Short name T580
Test name
Test status
Simulation time 5767852301 ps
CPU time 77.33 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:50:02 PM PST 24
Peak memory 200232 kb
Host smart-d66ec311-7b85-4ade-8215-4ba09a478aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455465251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3455465251
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4060153255
Short name T936
Test name
Test status
Simulation time 50635876553 ps
CPU time 38.08 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:49:31 PM PST 24
Peak memory 199912 kb
Host smart-a28ac1af-4af0-4064-be15-62b5c9c52b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060153255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4060153255
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1083686091
Short name T437
Test name
Test status
Simulation time 539861654 ps
CPU time 1.52 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:49:12 PM PST 24
Peak memory 195532 kb
Host smart-a5cbb505-336b-4bd2-86df-a6094c575af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083686091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1083686091
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1572203694
Short name T591
Test name
Test status
Simulation time 5754244399 ps
CPU time 12.66 seconds
Started Jan 03 12:48:10 PM PST 24
Finished Jan 03 12:48:56 PM PST 24
Peak memory 199680 kb
Host smart-9874a482-85c4-407c-b189-8979e815c3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572203694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1572203694
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1987465900
Short name T219
Test name
Test status
Simulation time 512318611994 ps
CPU time 1701.26 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 01:17:27 PM PST 24
Peak memory 200240 kb
Host smart-1469bc46-39a7-455b-b82a-fb7513bfdedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987465900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1987465900
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.104234694
Short name T1122
Test name
Test status
Simulation time 25549757513 ps
CPU time 223.8 seconds
Started Jan 03 12:48:47 PM PST 24
Finished Jan 03 12:52:54 PM PST 24
Peak memory 208404 kb
Host smart-de0a661c-238d-44be-8b71-df2124179099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104234694 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.104234694
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3269803175
Short name T525
Test name
Test status
Simulation time 1220599010 ps
CPU time 3.8 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:48:47 PM PST 24
Peak memory 199188 kb
Host smart-65d13513-81a7-4296-947a-08b9b419904c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269803175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3269803175
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.4031362773
Short name T130
Test name
Test status
Simulation time 22988069772 ps
CPU time 3.32 seconds
Started Jan 03 12:48:36 PM PST 24
Finished Jan 03 12:49:05 PM PST 24
Peak memory 197268 kb
Host smart-62a06a02-4df8-42a7-9652-ef0f705aa0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031362773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4031362773
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.783429589
Short name T769
Test name
Test status
Simulation time 120995567177 ps
CPU time 57.11 seconds
Started Jan 03 12:49:29 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 200156 kb
Host smart-bb87ea8e-d5b5-4264-97fc-4ba914d639ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783429589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.783429589
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2210473697
Short name T1210
Test name
Test status
Simulation time 153951720399 ps
CPU time 548.05 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:59:11 PM PST 24
Peak memory 216624 kb
Host smart-f7cf8299-61bc-4dde-bc14-fb29d0baa15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210473697 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2210473697
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.304960645
Short name T122
Test name
Test status
Simulation time 86136282010 ps
CPU time 114.27 seconds
Started Jan 03 12:49:40 PM PST 24
Finished Jan 03 12:51:47 PM PST 24
Peak memory 199984 kb
Host smart-22d30b01-71e4-4652-adbb-33163eb1b2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304960645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.304960645
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3631106874
Short name T1123
Test name
Test status
Simulation time 57840775422 ps
CPU time 399.89 seconds
Started Jan 03 12:50:05 PM PST 24
Finished Jan 03 12:57:09 PM PST 24
Peak memory 216800 kb
Host smart-eb8ebacf-36b1-4f27-8e5e-5f793bb2ea4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631106874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3631106874
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3896250113
Short name T1200
Test name
Test status
Simulation time 58617811988 ps
CPU time 40.53 seconds
Started Jan 03 12:49:50 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 200136 kb
Host smart-f93a9bf0-524e-4a07-b9af-1571647005b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896250113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3896250113
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.868020849
Short name T330
Test name
Test status
Simulation time 49257994317 ps
CPU time 312.56 seconds
Started Jan 03 12:49:35 PM PST 24
Finished Jan 03 12:55:02 PM PST 24
Peak memory 216136 kb
Host smart-c6c6ad59-b1e4-40b7-ad81-15284a639c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868020849 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.868020849
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.735084156
Short name T175
Test name
Test status
Simulation time 133823160148 ps
CPU time 73.81 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:52:04 PM PST 24
Peak memory 200128 kb
Host smart-8cc5dd27-ed80-4574-a632-98a7dc42bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735084156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.735084156
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1449009422
Short name T383
Test name
Test status
Simulation time 54526055104 ps
CPU time 669.58 seconds
Started Jan 03 12:49:37 PM PST 24
Finished Jan 03 01:01:01 PM PST 24
Peak memory 225064 kb
Host smart-fc4533b0-359b-4a64-b977-3fa47c5c30ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449009422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1449009422
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.697173713
Short name T321
Test name
Test status
Simulation time 146938013756 ps
CPU time 17.54 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 200168 kb
Host smart-06a9f950-62f5-42b9-ac5e-d652bf903db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697173713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.697173713
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2749569106
Short name T812
Test name
Test status
Simulation time 46794089116 ps
CPU time 13.11 seconds
Started Jan 03 12:49:43 PM PST 24
Finished Jan 03 12:50:11 PM PST 24
Peak memory 200052 kb
Host smart-6e680e61-6dfd-44f5-a5e6-e50e5263d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749569106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2749569106
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3564830210
Short name T583
Test name
Test status
Simulation time 64546324338 ps
CPU time 623.21 seconds
Started Jan 03 12:49:33 PM PST 24
Finished Jan 03 01:00:12 PM PST 24
Peak memory 216812 kb
Host smart-8f19c80a-b400-42bb-9b90-3ebfd207e46a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564830210 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3564830210
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3485839714
Short name T1221
Test name
Test status
Simulation time 53983633559 ps
CPU time 786.02 seconds
Started Jan 03 12:49:58 PM PST 24
Finished Jan 03 01:03:27 PM PST 24
Peak memory 216744 kb
Host smart-4874dd9c-08d4-47f5-bbcc-73b6fe080918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485839714 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3485839714
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3233981586
Short name T1196
Test name
Test status
Simulation time 59860484398 ps
CPU time 100.59 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:52:15 PM PST 24
Peak memory 200116 kb
Host smart-7ef4d1bc-9de8-452b-af3f-7988ef4cbb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233981586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3233981586
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3635293190
Short name T402
Test name
Test status
Simulation time 216998839658 ps
CPU time 1274.98 seconds
Started Jan 03 12:49:39 PM PST 24
Finished Jan 03 01:11:08 PM PST 24
Peak memory 225020 kb
Host smart-451bc6c8-5e42-4195-8f07-03f14d8bcdd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635293190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3635293190
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3016758116
Short name T324
Test name
Test status
Simulation time 158881375833 ps
CPU time 42.36 seconds
Started Jan 03 12:50:03 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 200168 kb
Host smart-0a3adb41-432b-4093-a472-c24480a95180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016758116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3016758116
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.4280825954
Short name T596
Test name
Test status
Simulation time 24548322163 ps
CPU time 217.61 seconds
Started Jan 03 12:50:23 PM PST 24
Finished Jan 03 12:54:23 PM PST 24
Peak memory 212132 kb
Host smart-bf32e9d6-4b14-4878-a834-9cb472310394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280825954 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.4280825954
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1927078619
Short name T206
Test name
Test status
Simulation time 250721540612 ps
CPU time 103.51 seconds
Started Jan 03 12:49:34 PM PST 24
Finished Jan 03 12:51:37 PM PST 24
Peak memory 199956 kb
Host smart-c4163452-ee1e-43c3-a2f9-c79085d03499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927078619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1927078619
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1901829976
Short name T1189
Test name
Test status
Simulation time 18869954200 ps
CPU time 210.76 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:53:23 PM PST 24
Peak memory 216240 kb
Host smart-df881ce3-8d60-4c78-a111-fce681143648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901829976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1901829976
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1734254193
Short name T738
Test name
Test status
Simulation time 40361448 ps
CPU time 0.52 seconds
Started Jan 03 12:48:22 PM PST 24
Finished Jan 03 12:48:46 PM PST 24
Peak memory 195640 kb
Host smart-352055e1-10a9-4ef2-b3c9-7e831cef3d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734254193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1734254193
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2368589042
Short name T894
Test name
Test status
Simulation time 89384196071 ps
CPU time 35.16 seconds
Started Jan 03 12:48:19 PM PST 24
Finished Jan 03 12:49:19 PM PST 24
Peak memory 199500 kb
Host smart-0fa1fab3-a68e-468e-80bb-2dd382e3d561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368589042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2368589042
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.271503634
Short name T117
Test name
Test status
Simulation time 221742366288 ps
CPU time 100.14 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:50:36 PM PST 24
Peak memory 199240 kb
Host smart-d70630c8-6b60-434d-8741-274c72298de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271503634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.271503634
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.533095729
Short name T1014
Test name
Test status
Simulation time 89149276639 ps
CPU time 153.87 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 200112 kb
Host smart-f6e6a6d7-b32c-47c9-b376-c72db33d7de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533095729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.533095729
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.164842152
Short name T629
Test name
Test status
Simulation time 29135846347 ps
CPU time 13.03 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:53 PM PST 24
Peak memory 197928 kb
Host smart-40ddf783-afd8-4bf7-8e12-1b38029d31f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164842152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.164842152
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4002784941
Short name T947
Test name
Test status
Simulation time 59909424671 ps
CPU time 185.16 seconds
Started Jan 03 12:48:32 PM PST 24
Finished Jan 03 12:52:04 PM PST 24
Peak memory 200216 kb
Host smart-5e425de6-6c9d-4874-8a14-273e65903d87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002784941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4002784941
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2573534073
Short name T1176
Test name
Test status
Simulation time 7440454098 ps
CPU time 12.5 seconds
Started Jan 03 12:48:29 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 197992 kb
Host smart-a7a2415f-d19d-4002-8073-3dea918d5cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573534073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2573534073
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3479379221
Short name T587
Test name
Test status
Simulation time 129888757127 ps
CPU time 64.64 seconds
Started Jan 03 12:48:40 PM PST 24
Finished Jan 03 12:50:10 PM PST 24
Peak memory 208188 kb
Host smart-4e2269fb-14e9-492e-90be-3f0f2674aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479379221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3479379221
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.885361333
Short name T195
Test name
Test status
Simulation time 31896572046 ps
CPU time 296.58 seconds
Started Jan 03 12:48:15 PM PST 24
Finished Jan 03 12:53:38 PM PST 24
Peak memory 200180 kb
Host smart-1c1f6941-579b-4db2-8d92-807789478c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885361333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.885361333
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1091358965
Short name T875
Test name
Test status
Simulation time 2885858495 ps
CPU time 14.23 seconds
Started Jan 03 12:48:13 PM PST 24
Finished Jan 03 12:48:54 PM PST 24
Peak memory 198560 kb
Host smart-128850c1-9008-4c10-afca-98c5c15f00fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091358965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1091358965
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1363004604
Short name T546
Test name
Test status
Simulation time 28389147215 ps
CPU time 39.18 seconds
Started Jan 03 12:48:37 PM PST 24
Finished Jan 03 12:49:42 PM PST 24
Peak memory 199472 kb
Host smart-b4588b01-fe98-4d14-9c95-b3c216bcba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363004604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1363004604
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1087810009
Short name T788
Test name
Test status
Simulation time 4463495453 ps
CPU time 4.33 seconds
Started Jan 03 12:48:11 PM PST 24
Finished Jan 03 12:48:42 PM PST 24
Peak memory 196000 kb
Host smart-34ff9d0c-204d-4047-a36a-c6ff6067e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087810009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1087810009
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2385328540
Short name T445
Test name
Test status
Simulation time 11063928360 ps
CPU time 22.13 seconds
Started Jan 03 12:48:21 PM PST 24
Finished Jan 03 12:49:07 PM PST 24
Peak memory 199904 kb
Host smart-5d800b0a-966a-4269-8942-3e7198b4ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385328540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2385328540
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3031386284
Short name T256
Test name
Test status
Simulation time 660374206062 ps
CPU time 481.2 seconds
Started Jan 03 12:48:56 PM PST 24
Finished Jan 03 12:57:18 PM PST 24
Peak memory 200084 kb
Host smart-99ff554f-7b9b-4473-afb0-8a9d2f0c7496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031386284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3031386284
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3907515278
Short name T85
Test name
Test status
Simulation time 143346225957 ps
CPU time 315.98 seconds
Started Jan 03 12:48:30 PM PST 24
Finished Jan 03 12:54:12 PM PST 24
Peak memory 216660 kb
Host smart-dc7aa45c-b8fc-4f00-9230-a39f419336e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907515278 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3907515278
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2392847032
Short name T855
Test name
Test status
Simulation time 8003053344 ps
CPU time 10.35 seconds
Started Jan 03 12:48:38 PM PST 24
Finished Jan 03 12:49:15 PM PST 24
Peak memory 199532 kb
Host smart-a11565df-26b7-45dc-ba8b-4cd22031cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392847032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2392847032
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.436612428
Short name T1096
Test name
Test status
Simulation time 32911287918 ps
CPU time 28.16 seconds
Started Jan 03 12:48:18 PM PST 24
Finished Jan 03 12:49:11 PM PST 24
Peak memory 199744 kb
Host smart-4309bdac-1e7d-4499-bb62-86bc0a5028d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436612428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.436612428
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.89608234
Short name T1154
Test name
Test status
Simulation time 475267576523 ps
CPU time 40.65 seconds
Started Jan 03 12:49:44 PM PST 24
Finished Jan 03 12:50:37 PM PST 24
Peak memory 200024 kb
Host smart-cc0dab1d-8ab7-4b83-95da-684c11555e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89608234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.89608234
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1572358064
Short name T211
Test name
Test status
Simulation time 97738617225 ps
CPU time 743.54 seconds
Started Jan 03 12:50:02 PM PST 24
Finished Jan 03 01:02:50 PM PST 24
Peak memory 225112 kb
Host smart-918a3321-c779-4bc9-996e-db3f8a00bc0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572358064 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1572358064
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.285696573
Short name T1104
Test name
Test status
Simulation time 96572149729 ps
CPU time 17.24 seconds
Started Jan 03 12:49:52 PM PST 24
Finished Jan 03 12:50:24 PM PST 24
Peak memory 200012 kb
Host smart-5bbfc5b1-17ba-449a-894e-904e11410f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285696573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.285696573
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2033913603
Short name T140
Test name
Test status
Simulation time 66600586456 ps
CPU time 1197.82 seconds
Started Jan 03 12:50:09 PM PST 24
Finished Jan 03 01:10:31 PM PST 24
Peak memory 216852 kb
Host smart-177ae2ac-4bf1-4227-b629-36cc80e224e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033913603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2033913603
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2897030486
Short name T141
Test name
Test status
Simulation time 11695016192 ps
CPU time 17.77 seconds
Started Jan 03 12:49:59 PM PST 24
Finished Jan 03 12:50:40 PM PST 24
Peak memory 200168 kb
Host smart-41f87725-5de7-41b3-94cc-480b5a9a7138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897030486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2897030486
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.4029730033
Short name T262
Test name
Test status
Simulation time 84396111326 ps
CPU time 223.28 seconds
Started Jan 03 12:49:38 PM PST 24
Finished Jan 03 12:53:35 PM PST 24
Peak memory 208352 kb
Host smart-e999a5f2-bacc-40d5-a185-9ce4a3a564ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029730033 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.4029730033
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2799545395
Short name T159
Test name
Test status
Simulation time 111858989727 ps
CPU time 45.12 seconds
Started Jan 03 12:50:08 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 199676 kb
Host smart-7bc78a05-f0e2-4596-b693-3692e4befd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799545395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2799545395
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3118807832
Short name T771
Test name
Test status
Simulation time 62944979853 ps
CPU time 137.26 seconds
Started Jan 03 12:49:46 PM PST 24
Finished Jan 03 12:52:15 PM PST 24
Peak memory 216320 kb
Host smart-e32f0715-fe39-44eb-abf6-6a35818e83d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118807832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3118807832
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2755007117
Short name T1116
Test name
Test status
Simulation time 118509726866 ps
CPU time 1236.8 seconds
Started Jan 03 12:50:30 PM PST 24
Finished Jan 03 01:11:31 PM PST 24
Peak memory 230052 kb
Host smart-08ca5988-77af-4ea1-8ebb-61f07b9320f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755007117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2755007117
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3879677643
Short name T352
Test name
Test status
Simulation time 127247921480 ps
CPU time 234.43 seconds
Started Jan 03 12:50:13 PM PST 24
Finished Jan 03 12:54:30 PM PST 24
Peak memory 208348 kb
Host smart-00790c16-ca76-4e23-8daa-d89c6cb1f268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879677643 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3879677643
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2086466331
Short name T227
Test name
Test status
Simulation time 61788037897 ps
CPU time 26.06 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 12:51:16 PM PST 24
Peak memory 199444 kb
Host smart-0ea1eb66-c584-42e3-b4de-54cf0da535ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086466331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2086466331
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1068889009
Short name T650
Test name
Test status
Simulation time 29259193399 ps
CPU time 318.47 seconds
Started Jan 03 12:49:47 PM PST 24
Finished Jan 03 12:55:18 PM PST 24
Peak memory 213228 kb
Host smart-c004ee19-4765-480d-aa14-274f66dd7d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068889009 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1068889009
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1181644588
Short name T649
Test name
Test status
Simulation time 25730953239 ps
CPU time 42.5 seconds
Started Jan 03 12:49:36 PM PST 24
Finished Jan 03 12:50:32 PM PST 24
Peak memory 199936 kb
Host smart-9948ff46-5d83-4962-9f6b-6bdb168db5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181644588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1181644588
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2353781783
Short name T325
Test name
Test status
Simulation time 59608293136 ps
CPU time 43.33 seconds
Started Jan 03 12:49:49 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 200156 kb
Host smart-1244ff6e-a247-4ad0-94df-ba3dba8024e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353781783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2353781783
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.23453863
Short name T1075
Test name
Test status
Simulation time 152225980543 ps
CPU time 1068.99 seconds
Started Jan 03 12:51:21 PM PST 24
Finished Jan 03 01:09:26 PM PST 24
Peak memory 216148 kb
Host smart-600ee70c-c58a-4e1d-a9ac-c813e378ebee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23453863 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.23453863
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4133957637
Short name T1149
Test name
Test status
Simulation time 116652819146 ps
CPU time 165.17 seconds
Started Jan 03 12:50:00 PM PST 24
Finished Jan 03 12:53:10 PM PST 24
Peak memory 200244 kb
Host smart-e2d93a68-2cb8-44ac-b031-adb062059b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133957637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4133957637
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1820008943
Short name T286
Test name
Test status
Simulation time 29106309548 ps
CPU time 482.49 seconds
Started Jan 03 12:49:26 PM PST 24
Finished Jan 03 12:57:49 PM PST 24
Peak memory 214064 kb
Host smart-8e7680ac-8977-4308-8ecc-902d0fa95353
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820008943 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1820008943
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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