Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	104191	1			T1	150		T2	2		T3	53
all_values[1]	104191	1			T1	150		T2	2		T3	53
all_values[2]	104191	1			T1	150		T2	2		T3	53
all_values[3]	104191	1			T1	150		T2	2		T3	53
all_values[4]	104191	1			T1	150		T2	2		T3	53
all_values[5]	104191	1			T1	150		T2	2		T3	53
all_values[6]	104191	1			T1	150		T2	2		T3	53
all_values[7]	104191	1			T1	150		T2	2		T3	53

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

425050

1

T1

782

T2

10

T3

270

auto[1]

408478

1

T1

418

T2

6

T3

154

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

820621

1

T1

1144

T2

14

T3

415

auto[1]

12907

1

T1

56

T2

2

T3

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	53596	1			T1	126		T3	28		T4	14
all_values[0]	auto[0]	auto[1]	2069	1			T1	11		T3	1		T4	2
all_values[0]	auto[1]	auto[0]	46720	1			T1	11		T2	1		T3	22
all_values[0]	auto[1]	auto[1]	1806	1			T1	2		T2	1		T3	2
all_values[1]	auto[0]	auto[0]	50362	1			T1	38		T3	33		T4	19
all_values[1]	auto[0]	auto[1]	1708	1			T1	20		T3	1		T4	3
all_values[1]	auto[1]	auto[0]	50613	1			T1	75		T2	2		T3	18
all_values[1]	auto[1]	auto[1]	1508	1			T1	17		T3	1		T8	1
all_values[2]	auto[0]	auto[0]	47586	1			T1	102		T2	1		T3	20
all_values[2]	auto[0]	auto[1]	1968	1			T1	1		T2	1		T3	4
all_values[2]	auto[1]	auto[0]	52750	1			T1	42		T3	29		T4	23
all_values[2]	auto[1]	auto[1]	1887	1			T1	5		T4	3		T8	5
all_values[3]	auto[0]	auto[0]	56136	1			T1	121		T2	2		T3	32
all_values[3]	auto[0]	auto[1]	155	1			T11	1		T12	1		T20	1
all_values[3]	auto[1]	auto[0]	47733	1			T1	29		T3	21		T4	40
all_values[3]	auto[1]	auto[1]	167	1			T13	2		T11	2		T12	2
all_values[4]	auto[0]	auto[0]	51805	1			T1	4		T3	5		T4	16
all_values[4]	auto[0]	auto[1]	354	1			T11	8		T12	1		T15	1
all_values[4]	auto[1]	auto[0]	51729	1			T1	146		T2	2		T3	48
all_values[4]	auto[1]	auto[1]	303	1			T11	3		T17	6		T12	7
all_values[5]	auto[0]	auto[0]	54174	1			T1	120		T2	2		T3	48
all_values[5]	auto[0]	auto[1]	135	1			T12	2		T32	2		T33	2
all_values[5]	auto[1]	auto[0]	49767	1			T1	30		T3	5		T4	5
all_values[5]	auto[1]	auto[1]	115	1			T13	3		T11	1		T12	1
all_values[6]	auto[0]	auto[0]	54282	1			T1	104		T2	2		T3	45
all_values[6]	auto[0]	auto[1]	119	1			T11	2		T32	6		T100	1
all_values[6]	auto[1]	auto[0]	49662	1			T1	46		T3	8		T4	5
all_values[6]	auto[1]	auto[1]	128	1			T13	1		T11	2		T12	5
all_values[7]	auto[0]	auto[0]	50374	1			T1	135		T2	2		T3	53
all_values[7]	auto[0]	auto[1]	227	1			T6	9		T14	1		T20	2
all_values[7]	auto[1]	auto[0]	53332	1			T1	15		T4	23		T5	1
all_values[7]	auto[1]	auto[1]	258	1			T11	6		T12	3		T20	1