Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1536	1			T1	4		T3	2		T4	2
auto[BaudRate115200]	1736	1			T1	1		T2	1		T6	1
auto[BaudRate230400]	1503	1			T1	1		T3	2		T4	2
auto[BaudRate128Kbps]	1493	1			T1	1		T2	2		T5	9
auto[BaudRate256Kbps]	1799	1			T2	1		T3	2		T5	3
auto[BaudRate1Mbps]	1407	1			T2	1		T4	2		T6	1
auto[BaudRate1p5Mbps]	1021	1			T1	3		T3	1		T4	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1239	1			T22	19		T12	17		T39	8
freqs[25]	1157	1			T15	11		T96	8		T95	8
freqs[48]	338	1			T6	6		T368	2		T283	6
freqs[50]	324	1			T172	10		T141	10		T127	2
freqs[100]	629	1			T3	7		T4	8		T14	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	162	1			T22	1		T12	4		T349	1
auto[BaudRate9600]	freqs[25]	177	1			T15	5		T96	1		T398	3
auto[BaudRate9600]	freqs[48]	38	1			T6	2		T399	4		T394	1
auto[BaudRate9600]	freqs[50]	49	1			T172	5		T347	2		T168	3
auto[BaudRate9600]	freqs[100]	92	1			T3	2		T4	2		T14	2
auto[BaudRate115200]	freqs[24]	201	1			T22	2		T12	1		T39	2
auto[BaudRate115200]	freqs[25]	183	1			T15	2		T96	2		T33	16
auto[BaudRate115200]	freqs[48]	67	1			T6	1		T399	1		T394	4
auto[BaudRate115200]	freqs[50]	54	1			T172	1		T141	2		T400	2
auto[BaudRate115200]	freqs[100]	95	1			T14	1		T111	1		T97	1
auto[BaudRate230400]	freqs[24]	199	1			T22	5		T12	5		T39	1
auto[BaudRate230400]	freqs[25]	159	1			T15	2		T96	1		T95	1
auto[BaudRate230400]	freqs[48]	52	1			T283	1		T143	2		T133	2
auto[BaudRate230400]	freqs[50]	30	1			T172	1		T141	1		T401	5
auto[BaudRate230400]	freqs[100]	69	1			T3	2		T4	2		T14	1
auto[BaudRate128Kbps]	freqs[24]	189	1			T22	1		T39	2		T261	1
auto[BaudRate128Kbps]	freqs[25]	186	1			T15	1		T96	3		T95	3
auto[BaudRate128Kbps]	freqs[48]	42	1			T368	1		T283	1		T394	2
auto[BaudRate128Kbps]	freqs[50]	41	1			T172	1		T141	2		T127	2
auto[BaudRate128Kbps]	freqs[100]	71	1			T14	1		T97	1		T34	10
auto[BaudRate256Kbps]	freqs[24]	202	1			T22	4		T12	3		T39	2
auto[BaudRate256Kbps]	freqs[25]	182	1			T95	2		T362	1		T33	20
auto[BaudRate256Kbps]	freqs[48]	43	1			T6	2		T283	1		T394	3
auto[BaudRate256Kbps]	freqs[50]	46	1			T141	1		T361	1		T168	1
auto[BaudRate256Kbps]	freqs[100]	112	1			T3	2		T14	1		T34	13
auto[BaudRate1Mbps]	freqs[24]	201	1			T22	3		T12	3		T39	1
auto[BaudRate1Mbps]	freqs[25]	179	1			T96	1		T95	1		T398	3
auto[BaudRate1Mbps]	freqs[48]	44	1			T6	1		T394	3		T182	1
auto[BaudRate1Mbps]	freqs[50]	42	1			T172	1		T361	3		T400	1
auto[BaudRate1Mbps]	freqs[100]	92	1			T4	2		T14	1		T97	1
auto[BaudRate1p5Mbps]	freqs[25]	91	1			T15	1		T95	1		T33	4
auto[BaudRate1p5Mbps]	freqs[48]	52	1			T368	1		T283	3		T394	4
auto[BaudRate1p5Mbps]	freqs[50]	62	1			T172	1		T141	4		T361	1
auto[BaudRate1p5Mbps]	freqs[100]	98	1			T3	1		T4	2		T14	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded