Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1386 1 T1 18 T3 1 T10 1
all_levels[1] 273 1 T1 16 T3 1 T13 5
all_levels[2] 305 1 T14 2 T116 2 T16 7
all_levels[3] 267 1 T11 3 T94 1 T39 4
all_levels[4] 223 1 T1 1 T4 3 T13 2
all_levels[5] 166 1 T11 1 T12 5 T112 1
all_levels[6] 432 1 T1 1 T8 1 T30 1
all_levels[7] 159 1 T1 1 T94 1 T101 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%