Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	104191	1			T1	150		T2	2		T3	53
all_pins[1]	104191	1			T1	150		T2	2		T3	53
all_pins[2]	104191	1			T1	150		T2	2		T3	53
all_pins[3]	104191	1			T1	150		T2	2		T3	53
all_pins[4]	104191	1			T1	150		T2	2		T3	53
all_pins[5]	104191	1			T1	150		T2	2		T3	53
all_pins[6]	104191	1			T1	150		T2	2		T3	53
all_pins[7]	104191	1			T1	150		T2	2		T3	53

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	826704	1			T1	1176		T2	15		T3	421
values[0x1]	6824	1			T1	24		T2	1		T3	3
transitions[0x0=>0x1]	6204	1			T1	23		T2	1		T3	2
transitions[0x1=>0x0]	6216	1			T1	23		T2	1		T3	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102329	1			T1	148		T2	1		T3	51
all_pins[0]	values[0x1]	1862	1			T1	2		T2	1		T3	2
all_pins[0]	transitions[0x0=>0x1]	1670	1			T1	2		T2	1		T3	1
all_pins[0]	transitions[0x1=>0x0]	1312	1			T1	17		T8	1		T13	6
all_pins[1]	values[0x0]	102687	1			T1	133		T2	2		T3	52
all_pins[1]	values[0x1]	1504	1			T1	17		T3	1		T8	1
all_pins[1]	transitions[0x0=>0x1]	1286	1			T1	16		T3	1		T8	1
all_pins[1]	transitions[0x1=>0x0]	1719	1			T1	4		T4	3		T8	5
all_pins[2]	values[0x0]	102254	1			T1	145		T2	2		T3	53
all_pins[2]	values[0x1]	1937	1			T1	5		T4	3		T8	5
all_pins[2]	transitions[0x0=>0x1]	1908	1			T1	5		T4	3		T8	5
all_pins[2]	transitions[0x1=>0x0]	138	1			T13	2		T12	1		T15	2
all_pins[3]	values[0x0]	104024	1			T1	150		T2	2		T3	53
all_pins[3]	values[0x1]	167	1			T13	2		T11	2		T12	2
all_pins[3]	transitions[0x0=>0x1]	134	1			T13	2		T11	1		T12	2
all_pins[3]	transitions[0x1=>0x0]	270	1			T11	2		T17	6		T12	7
all_pins[4]	values[0x0]	103888	1			T1	150		T2	2		T3	53
all_pins[4]	values[0x1]	303	1			T11	3		T17	6		T12	7
all_pins[4]	transitions[0x0=>0x1]	267	1			T11	3		T17	6		T12	6
all_pins[4]	transitions[0x1=>0x0]	107	1			T13	3		T11	1		T12	1
all_pins[5]	values[0x0]	104048	1			T1	150		T2	2		T3	53
all_pins[5]	values[0x1]	143	1			T13	3		T11	1		T12	2
all_pins[5]	transitions[0x0=>0x1]	119	1			T13	2		T11	1		T12	1
all_pins[5]	transitions[0x1=>0x0]	626	1			T8	1		T22	1		T30	1
all_pins[6]	values[0x0]	103541	1			T1	150		T2	2		T3	53
all_pins[6]	values[0x1]	650	1			T8	1		T13	1		T22	1
all_pins[6]	transitions[0x0=>0x1]	613	1			T8	1		T13	1		T22	1
all_pins[6]	transitions[0x1=>0x0]	221	1			T11	6		T12	2		T20	1
all_pins[7]	values[0x0]	103933	1			T1	150		T2	2		T3	53
all_pins[7]	values[0x1]	258	1			T11	6		T12	3		T20	1
all_pins[7]	transitions[0x0=>0x1]	207	1			T11	6		T12	2		T20	1
all_pins[7]	transitions[0x1=>0x0]	1823	1			T1	2		T2	1		T3	2