Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	585	1			T13	4		T11	7		T12	7
all_values[1]	585	1			T13	4		T11	7		T12	7
all_values[2]	585	1			T13	4		T11	7		T12	7
all_values[3]	585	1			T13	4		T11	7		T12	7
all_values[4]	585	1			T13	4		T11	7		T12	7
all_values[5]	585	1			T13	4		T11	7		T12	7
all_values[6]	585	1			T13	4		T11	7		T12	7
all_values[7]	585	1			T13	4		T11	7		T12	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T13

11

T11

23

T12

31

auto[1]

2255

1

T13

21

T11

33

T12

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1965

1

T13

20

T11

27

T12

24

auto[1]

2715

1

T13

12

T11

29

T12

32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2818

1

T13

23

T11

33

T12

35

auto[1]

1862

1

T13

9

T11

23

T12

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	135	1			T11	3		T12	3		T32	5
all_values[0]	auto[0]	auto[0]	auto[1]	55	1			T34	1		T35	1		T49	2
all_values[0]	auto[0]	auto[1]	auto[0]	111	1			T11	1		T20	1		T32	4
all_values[0]	auto[0]	auto[1]	auto[1]	55	1			T13	1		T32	1		T33	2
all_values[0]	auto[1]	auto[0]	auto[1]	117	1			T13	1		T11	1		T12	4
all_values[0]	auto[1]	auto[1]	auto[1]	112	1			T13	2		T11	2		T32	3
all_values[1]	auto[0]	auto[0]	auto[0]	149	1			T13	2		T11	1		T12	2
all_values[1]	auto[0]	auto[0]	auto[1]	51	1			T11	1		T12	2		T32	1
all_values[1]	auto[0]	auto[1]	auto[0]	112	1			T13	2		T11	2		T20	1
all_values[1]	auto[0]	auto[1]	auto[1]	50	1			T12	1		T32	1		T33	1
all_values[1]	auto[1]	auto[0]	auto[1]	115	1			T11	3		T12	1		T34	2
all_values[1]	auto[1]	auto[1]	auto[1]	108	1			T12	1		T32	3		T33	2
all_values[2]	auto[0]	auto[0]	auto[0]	119	1			T13	2		T12	2		T20	1
all_values[2]	auto[0]	auto[0]	auto[1]	67	1			T11	2		T20	1		T32	3
all_values[2]	auto[0]	auto[1]	auto[0]	111	1			T13	1		T11	1		T12	2
all_values[2]	auto[0]	auto[1]	auto[1]	47	1			T11	1		T12	1		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	134	1			T13	1		T12	1		T32	2
all_values[2]	auto[1]	auto[1]	auto[1]	107	1			T11	3		T12	1		T20	1
all_values[3]	auto[0]	auto[0]	auto[0]	135	1			T11	2		T12	3		T32	1
all_values[3]	auto[0]	auto[0]	auto[1]	38	1			T32	1		T343	1		T344	1
all_values[3]	auto[0]	auto[1]	auto[0]	128	1			T13	2		T11	2		T20	2
all_values[3]	auto[0]	auto[1]	auto[1]	58	1			T12	1		T33	1		T34	1
all_values[3]	auto[1]	auto[0]	auto[1]	107	1			T13	1		T11	1		T12	1
all_values[3]	auto[1]	auto[1]	auto[1]	119	1			T13	1		T11	2		T12	2
all_values[4]	auto[0]	auto[0]	auto[0]	112	1			T11	1		T12	1		T20	3
all_values[4]	auto[0]	auto[0]	auto[1]	62	1			T11	1		T32	4		T35	3
all_values[4]	auto[0]	auto[1]	auto[0]	109	1			T13	3		T12	3		T20	1
all_values[4]	auto[0]	auto[1]	auto[1]	63	1			T11	1		T12	1		T32	1
all_values[4]	auto[1]	auto[0]	auto[1]	121	1			T13	1		T11	2		T12	1
all_values[4]	auto[1]	auto[1]	auto[1]	118	1			T11	2		T12	1		T32	2
all_values[5]	auto[0]	auto[0]	auto[0]	137	1			T13	1		T11	3		T12	3
all_values[5]	auto[0]	auto[0]	auto[1]	50	1			T33	1		T345	1		T343	2
all_values[5]	auto[0]	auto[1]	auto[0]	107	1			T11	3		T20	1		T32	4
all_values[5]	auto[0]	auto[1]	auto[1]	52	1			T13	2		T12	1		T32	1
all_values[5]	auto[1]	auto[0]	auto[1]	139	1			T11	1		T12	2		T20	1
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T13	1		T12	1		T20	2
all_values[6]	auto[0]	auto[0]	auto[0]	126	1			T13	1		T12	2		T20	1
all_values[6]	auto[0]	auto[0]	auto[1]	44	1			T32	3		T346	1		T345	1
all_values[6]	auto[0]	auto[1]	auto[0]	117	1			T13	2		T11	2		T20	1
all_values[6]	auto[0]	auto[1]	auto[1]	56	1			T12	3		T100	1		T35	2
all_values[6]	auto[1]	auto[0]	auto[1]	120	1			T11	1		T32	1		T100	1
all_values[6]	auto[1]	auto[1]	auto[1]	122	1			T13	1		T11	4		T12	2
all_values[7]	auto[0]	auto[0]	auto[0]	126	1			T13	1		T12	2		T20	1
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T20	1		T32	1		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	131	1			T13	3		T11	6		T12	1
all_values[7]	auto[0]	auto[1]	auto[1]	60	1			T12	1		T32	1		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	121	1			T12	1		T20	2		T32	3
all_values[7]	auto[1]	auto[1]	auto[1]	102	1			T11	1		T12	2		T32	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal