Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.23 99.79 98.45 100.00 99.76 100.00 97.38


Total test records in report: 1045
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T1006 /workspace/coverage/default/14.uart_rx_oversample.2562721810 Jan 07 12:53:07 PM PST 24 Jan 07 12:54:33 PM PST 24 3610205330 ps
T1007 /workspace/coverage/default/15.uart_long_xfer_wo_dly.3627380617 Jan 07 12:53:37 PM PST 24 Jan 07 01:08:39 PM PST 24 99163266392 ps
T1008 /workspace/coverage/default/44.uart_tx_ovrd.1870145586 Jan 07 12:55:04 PM PST 24 Jan 07 12:56:29 PM PST 24 1124054978 ps
T1009 /workspace/coverage/default/28.uart_tx_ovrd.4266230598 Jan 07 12:54:35 PM PST 24 Jan 07 12:56:18 PM PST 24 698263057 ps
T1010 /workspace/coverage/default/13.uart_perf.453923832 Jan 07 12:53:45 PM PST 24 Jan 07 01:03:43 PM PST 24 20258335153 ps
T1011 /workspace/coverage/default/276.uart_fifo_reset.1520291737 Jan 07 12:55:54 PM PST 24 Jan 07 12:58:17 PM PST 24 69388145378 ps
T1012 /workspace/coverage/default/20.uart_rx_parity_err.4215201366 Jan 07 12:53:52 PM PST 24 Jan 07 12:59:22 PM PST 24 154073618159 ps
T1013 /workspace/coverage/default/157.uart_fifo_reset.2191449537 Jan 07 12:55:35 PM PST 24 Jan 07 12:57:38 PM PST 24 59370792891 ps
T1014 /workspace/coverage/default/36.uart_rx_parity_err.2010223635 Jan 07 12:54:16 PM PST 24 Jan 07 12:56:38 PM PST 24 39051860125 ps
T307 /workspace/coverage/default/31.uart_fifo_full.1648128073 Jan 07 12:54:23 PM PST 24 Jan 07 12:56:47 PM PST 24 462422097455 ps
T1015 /workspace/coverage/default/17.uart_stress_all.2782682511 Jan 07 12:53:12 PM PST 24 Jan 07 01:10:07 PM PST 24 945773870061 ps
T1016 /workspace/coverage/default/20.uart_long_xfer_wo_dly.1985634549 Jan 07 12:53:31 PM PST 24 Jan 07 01:00:09 PM PST 24 98060585274 ps
T1017 /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2697486672 Jan 07 12:54:07 PM PST 24 Jan 07 01:01:12 PM PST 24 115769241746 ps
T258 /workspace/coverage/default/231.uart_fifo_reset.3858497363 Jan 07 12:55:22 PM PST 24 Jan 07 12:57:10 PM PST 24 27601508709 ps
T1018 /workspace/coverage/default/234.uart_fifo_reset.3861922114 Jan 07 12:55:52 PM PST 24 Jan 07 12:57:38 PM PST 24 6395159296 ps
T181 /workspace/coverage/default/233.uart_fifo_reset.4265970000 Jan 07 12:55:12 PM PST 24 Jan 07 12:57:38 PM PST 24 31758354543 ps
T1019 /workspace/coverage/default/3.uart_loopback.950739217 Jan 07 12:53:25 PM PST 24 Jan 07 12:54:42 PM PST 24 10274397552 ps
T1020 /workspace/coverage/default/11.uart_rx_start_bit_filter.721432847 Jan 07 12:53:11 PM PST 24 Jan 07 12:55:09 PM PST 24 42712705064 ps
T1021 /workspace/coverage/default/32.uart_fifo_full.2629089147 Jan 07 12:54:32 PM PST 24 Jan 07 12:57:19 PM PST 24 224926828983 ps
T1022 /workspace/coverage/default/41.uart_tx_rx.2614535674 Jan 07 12:54:14 PM PST 24 Jan 07 12:56:50 PM PST 24 55160436195 ps
T1023 /workspace/coverage/default/15.uart_alert_test.363748865 Jan 07 12:53:56 PM PST 24 Jan 07 12:55:30 PM PST 24 11627883 ps
T1024 /workspace/coverage/default/45.uart_intr.1774452731 Jan 07 12:55:07 PM PST 24 Jan 07 12:59:21 PM PST 24 110725039332 ps
T1025 /workspace/coverage/default/14.uart_fifo_full.3520290566 Jan 07 12:53:46 PM PST 24 Jan 07 12:56:15 PM PST 24 132165604889 ps
T1026 /workspace/coverage/default/26.uart_fifo_overflow.4252393740 Jan 07 12:53:57 PM PST 24 Jan 07 12:55:59 PM PST 24 11566480291 ps
T1027 /workspace/coverage/default/26.uart_intr.857567317 Jan 07 12:53:58 PM PST 24 Jan 07 12:56:12 PM PST 24 35432991231 ps
T1028 /workspace/coverage/default/174.uart_fifo_reset.1261904081 Jan 07 12:55:05 PM PST 24 Jan 07 12:58:14 PM PST 24 54419528323 ps
T1029 /workspace/coverage/default/266.uart_fifo_reset.3890743703 Jan 07 12:55:18 PM PST 24 Jan 07 12:57:34 PM PST 24 20467465165 ps
T1030 /workspace/coverage/default/162.uart_fifo_reset.856678225 Jan 07 12:55:00 PM PST 24 Jan 07 12:57:01 PM PST 24 41703318178 ps
T1031 /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1622356979 Jan 07 12:54:51 PM PST 24 Jan 07 01:07:10 PM PST 24 20310715285 ps
T1032 /workspace/coverage/default/18.uart_perf.3990752861 Jan 07 12:53:23 PM PST 24 Jan 07 12:57:53 PM PST 24 24673728057 ps
T276 /workspace/coverage/default/65.uart_fifo_reset.2582497094 Jan 07 12:55:09 PM PST 24 Jan 07 12:57:44 PM PST 24 100669427297 ps
T1033 /workspace/coverage/default/3.uart_long_xfer_wo_dly.2691143534 Jan 07 12:53:21 PM PST 24 Jan 07 01:09:52 PM PST 24 132758824474 ps
T1034 /workspace/coverage/default/15.uart_intr.396451684 Jan 07 12:53:20 PM PST 24 Jan 07 01:10:34 PM PST 24 498499994900 ps
T1035 /workspace/coverage/default/10.uart_loopback.3447687376 Jan 07 12:53:47 PM PST 24 Jan 07 12:55:35 PM PST 24 12593470356 ps
T1036 /workspace/coverage/default/10.uart_smoke.3142470226 Jan 07 12:53:44 PM PST 24 Jan 07 12:55:06 PM PST 24 500367191 ps
T1037 /workspace/coverage/default/28.uart_fifo_reset.3366733870 Jan 07 12:54:29 PM PST 24 Jan 07 12:57:22 PM PST 24 50408956230 ps
T1038 /workspace/coverage/default/75.uart_stress_all_with_rand_reset.531264568 Jan 07 12:54:57 PM PST 24 Jan 07 01:05:38 PM PST 24 200058866860 ps
T334 /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2661582191 Jan 07 12:55:00 PM PST 24 Jan 07 01:03:45 PM PST 24 46427242861 ps
T1039 /workspace/coverage/default/29.uart_rx_oversample.3815754379 Jan 07 12:54:13 PM PST 24 Jan 07 12:55:48 PM PST 24 3738580606 ps
T1040 /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1849504365 Jan 07 12:55:00 PM PST 24 Jan 07 01:02:17 PM PST 24 62129124098 ps
T1041 /workspace/coverage/default/14.uart_rx_parity_err.3495392536 Jan 07 12:53:37 PM PST 24 Jan 07 12:55:18 PM PST 24 65384868141 ps
T1042 /workspace/coverage/default/31.uart_tx_rx.2664422952 Jan 07 12:54:37 PM PST 24 Jan 07 12:56:33 PM PST 24 55113143620 ps
T1043 /workspace/coverage/default/29.uart_alert_test.2715422543 Jan 07 12:54:19 PM PST 24 Jan 07 12:55:49 PM PST 24 35289493 ps
T1044 /workspace/coverage/default/40.uart_perf.1536812137 Jan 07 12:54:10 PM PST 24 Jan 07 01:01:59 PM PST 24 15955384690 ps
T1045 /workspace/coverage/default/26.uart_rx_parity_err.2849166356 Jan 07 12:53:53 PM PST 24 Jan 07 12:55:44 PM PST 24 9436652676 ps

Test location /workspace/coverage/default/30.uart_fifo_full.3596307685
Short name T1
Test name
Test status
Simulation time 260735368178 ps
CPU time 412.61 seconds
Started Jan 07 12:54:09 PM PST 24
Finished Jan 07 01:02:18 PM PST 24
Peak memory 200128 kb
Host smart-dba8dcea-326c-4165-b1fa-d0682dacad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596307685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3596307685
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1113593903
Short name T11
Test name
Test status
Simulation time 1046783922846 ps
CPU time 560.54 seconds
Started Jan 07 12:55:16 PM PST 24
Finished Jan 07 01:05:55 PM PST 24
Peak memory 216584 kb
Host smart-c07aead1-7986-4738-9ccf-b7f3987fe2c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113593903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1113593903
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.361257802
Short name T103
Test name
Test status
Simulation time 852594655364 ps
CPU time 2012.94 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 01:29:41 PM PST 24
Peak memory 200212 kb
Host smart-83810aa8-c18e-42af-bce4-da8776edafa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361257802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.361257802
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3046197029
Short name T33
Test name
Test status
Simulation time 234984157889 ps
CPU time 802.41 seconds
Started Jan 07 12:54:04 PM PST 24
Finished Jan 07 01:08:50 PM PST 24
Peak memory 230836 kb
Host smart-00930a44-7af1-4b4d-a672-7d64f372ccec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046197029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3046197029
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2654910681
Short name T35
Test name
Test status
Simulation time 455358430702 ps
CPU time 1280.88 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 01:15:54 PM PST 24
Peak memory 228124 kb
Host smart-292c72e5-3a4d-4689-b622-ee6970a93c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654910681 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2654910681
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2226051541
Short name T166
Test name
Test status
Simulation time 1341327505021 ps
CPU time 773.44 seconds
Started Jan 07 12:55:26 PM PST 24
Finished Jan 07 01:09:48 PM PST 24
Peak memory 216704 kb
Host smart-dea5124d-7951-4c5b-965e-51c7e2dccd1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226051541 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2226051541
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1452982
Short name T31
Test name
Test status
Simulation time 108621557709 ps
CPU time 864.83 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 01:11:17 PM PST 24
Peak memory 225808 kb
Host smart-0875237b-bdc9-4748-a6bf-dfeae04bf4de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452982 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1452982
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.126322964
Short name T78
Test name
Test status
Simulation time 648566529 ps
CPU time 1.24 seconds
Started Jan 07 12:25:30 PM PST 24
Finished Jan 07 12:26:33 PM PST 24
Peak memory 199076 kb
Host smart-68b0af52-b72a-4f57-ba25-284cf7e5e3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126322964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.126322964
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_alert_test.3195002619
Short name T403
Test name
Test status
Simulation time 64673564 ps
CPU time 0.52 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 12:55:24 PM PST 24
Peak memory 195548 kb
Host smart-91635eba-849d-4c67-8cd0-081ec545387f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195002619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3195002619
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_stress_all.2140365767
Short name T564
Test name
Test status
Simulation time 1599395904694 ps
CPU time 1364.47 seconds
Started Jan 07 12:54:22 PM PST 24
Finished Jan 07 01:18:32 PM PST 24
Peak memory 200140 kb
Host smart-d8c78a74-ea13-45ad-9783-dac21fa5ed04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140365767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2140365767
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.4142060737
Short name T12
Test name
Test status
Simulation time 88957259174 ps
CPU time 271.51 seconds
Started Jan 07 12:54:47 PM PST 24
Finished Jan 07 01:00:43 PM PST 24
Peak memory 208900 kb
Host smart-3bf66d57-ea53-4328-80da-b94738efb83a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142060737 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4142060737
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1370529236
Short name T34
Test name
Test status
Simulation time 87326735265 ps
CPU time 1022.76 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 01:13:09 PM PST 24
Peak memory 225008 kb
Host smart-846e8120-bc29-4975-b968-053a4b5f3ee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370529236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1370529236
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3609891327
Short name T101
Test name
Test status
Simulation time 98806247334 ps
CPU time 58.91 seconds
Started Jan 07 12:55:24 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 200096 kb
Host smart-341ef225-711b-4644-8412-2f9fe285448a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609891327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3609891327
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1141747611
Short name T81
Test name
Test status
Simulation time 144806927 ps
CPU time 0.8 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:54:50 PM PST 24
Peak memory 217668 kb
Host smart-41dcab2e-bee0-4cf6-a4a8-32b2e3218f9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141747611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1141747611
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/35.uart_stress_all.2713004405
Short name T137
Test name
Test status
Simulation time 699929832342 ps
CPU time 1634.23 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 01:22:53 PM PST 24
Peak memory 200200 kb
Host smart-5fd3d1a2-ad5b-42f7-8806-4a3afe21b316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713004405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2713004405
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.903121602
Short name T90
Test name
Test status
Simulation time 452588517533 ps
CPU time 416.74 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 01:03:40 PM PST 24
Peak memory 215912 kb
Host smart-ff64a8ad-237c-4d80-93a9-ea4606ed6189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903121602 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.903121602
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all.236884003
Short name T109
Test name
Test status
Simulation time 107297680214 ps
CPU time 118.22 seconds
Started Jan 07 12:55:17 PM PST 24
Finished Jan 07 12:58:32 PM PST 24
Peak memory 200136 kb
Host smart-27abb09e-0b03-4839-be3a-26d2fcdcddbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236884003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.236884003
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all.3389122571
Short name T107
Test name
Test status
Simulation time 420419878219 ps
CPU time 1169.33 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 01:14:31 PM PST 24
Peak memory 200080 kb
Host smart-e2631f06-1ac7-4316-b363-067b0c1752cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389122571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3389122571
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.520711406
Short name T6
Test name
Test status
Simulation time 118917329952 ps
CPU time 87.61 seconds
Started Jan 07 12:53:37 PM PST 24
Finished Jan 07 12:56:50 PM PST 24
Peak memory 199296 kb
Host smart-85748873-de45-4af0-9d51-f3f58be2d297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520711406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.520711406
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1529635540
Short name T43
Test name
Test status
Simulation time 30488231 ps
CPU time 0.75 seconds
Started Jan 07 12:30:16 PM PST 24
Finished Jan 07 12:31:59 PM PST 24
Peak memory 196208 kb
Host smart-9125cbb8-5f93-4436-bd43-225974d95deb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529635540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1529635540
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2798119562
Short name T41
Test name
Test status
Simulation time 44077584 ps
CPU time 0.57 seconds
Started Jan 07 12:34:19 PM PST 24
Finished Jan 07 12:36:00 PM PST 24
Peak memory 195128 kb
Host smart-7919d278-f75a-4a7a-bb36-c413623e9ace
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798119562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2798119562
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4153075758
Short name T75
Test name
Test status
Simulation time 116321959 ps
CPU time 1.26 seconds
Started Jan 07 12:29:17 PM PST 24
Finished Jan 07 12:30:34 PM PST 24
Peak memory 198032 kb
Host smart-591bcdb5-56e6-41f6-b733-33b6df4f51c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153075758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4153075758
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2371391545
Short name T117
Test name
Test status
Simulation time 182083856075 ps
CPU time 157.08 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:59:10 PM PST 24
Peak memory 200088 kb
Host smart-e7967f5f-3d99-4c72-8468-663b6d8b4c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371391545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2371391545
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3783729465
Short name T116
Test name
Test status
Simulation time 31967623002 ps
CPU time 12.67 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:55:31 PM PST 24
Peak memory 200176 kb
Host smart-d23b4841-4fdd-4c0f-8603-fdc06d352136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783729465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3783729465
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1705839189
Short name T114
Test name
Test status
Simulation time 15780688609 ps
CPU time 30.62 seconds
Started Jan 07 12:55:37 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 200140 kb
Host smart-b504a79b-c0a7-409d-b1c9-bdf9a28cac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705839189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1705839189
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.325096743
Short name T134
Test name
Test status
Simulation time 174618523001 ps
CPU time 50.67 seconds
Started Jan 07 12:54:30 PM PST 24
Finished Jan 07 12:56:44 PM PST 24
Peak memory 199820 kb
Host smart-3861723f-c161-4817-8382-3c06e4d2e36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325096743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.325096743
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.2151143126
Short name T100
Test name
Test status
Simulation time 94098093348 ps
CPU time 795.96 seconds
Started Jan 07 12:55:03 PM PST 24
Finished Jan 07 01:09:38 PM PST 24
Peak memory 200244 kb
Host smart-11d8109d-e510-4161-b487-5926563ff7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151143126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2151143126
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1872701767
Short name T120
Test name
Test status
Simulation time 48681264381 ps
CPU time 45.9 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 200140 kb
Host smart-063fadc6-23d4-473a-99b9-451f9a3c7975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872701767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1872701767
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2823862557
Short name T300
Test name
Test status
Simulation time 201066805671 ps
CPU time 521.4 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 01:05:02 PM PST 24
Peak memory 225052 kb
Host smart-7d59775d-b783-4f12-9efa-d373092e4d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823862557 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2823862557
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.404595225
Short name T133
Test name
Test status
Simulation time 71275055725 ps
CPU time 54.93 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:58:09 PM PST 24
Peak memory 200108 kb
Host smart-2b0f6254-81ca-447e-8e84-40a3d65d3299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404595225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.404595225
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1916989765
Short name T39
Test name
Test status
Simulation time 58120948984 ps
CPU time 21.99 seconds
Started Jan 07 12:54:56 PM PST 24
Finished Jan 07 12:56:47 PM PST 24
Peak memory 200016 kb
Host smart-0d7512ee-5f83-4534-b01e-e93b9724ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916989765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1916989765
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1706468426
Short name T314
Test name
Test status
Simulation time 59186085699 ps
CPU time 57.54 seconds
Started Jan 07 12:53:12 PM PST 24
Finished Jan 07 12:55:27 PM PST 24
Peak memory 200168 kb
Host smart-15cc74b2-9553-4e29-8c27-d4c458bb3655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706468426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1706468426
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2627007714
Short name T199
Test name
Test status
Simulation time 186377041978 ps
CPU time 409.64 seconds
Started Jan 07 12:55:09 PM PST 24
Finished Jan 07 01:03:18 PM PST 24
Peak memory 200212 kb
Host smart-fc9c0b49-35a2-4203-8ec9-1bf5c6cda68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627007714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2627007714
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.195558126
Short name T8
Test name
Test status
Simulation time 37990107452 ps
CPU time 64.83 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:57:23 PM PST 24
Peak memory 200176 kb
Host smart-8f3af9d4-d617-413f-90aa-0642c3076650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195558126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.195558126
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.34899634
Short name T83
Test name
Test status
Simulation time 32933711887 ps
CPU time 84.58 seconds
Started Jan 07 12:55:45 PM PST 24
Finished Jan 07 12:58:57 PM PST 24
Peak memory 200108 kb
Host smart-21df17c3-32cc-4c24-aed7-1a28ec5835e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34899634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.34899634
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3284487256
Short name T190
Test name
Test status
Simulation time 69163492513 ps
CPU time 56.54 seconds
Started Jan 07 12:53:59 PM PST 24
Finished Jan 07 12:56:07 PM PST 24
Peak memory 200224 kb
Host smart-a268abb6-f962-4702-b433-9f82564d6f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284487256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3284487256
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.5756827
Short name T131
Test name
Test status
Simulation time 17503301645 ps
CPU time 15.15 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:55:46 PM PST 24
Peak memory 199744 kb
Host smart-fca66f54-a449-4b66-ab4b-1624307e2092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5756827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.5756827
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all.3979509110
Short name T108
Test name
Test status
Simulation time 373112583461 ps
CPU time 118.59 seconds
Started Jan 07 12:54:35 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 200216 kb
Host smart-5df46624-0996-4a05-8c35-6f7aa28f6c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979509110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3979509110
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2997805561
Short name T94
Test name
Test status
Simulation time 104018994672 ps
CPU time 198.86 seconds
Started Jan 07 12:55:12 PM PST 24
Finished Jan 07 01:00:11 PM PST 24
Peak memory 200228 kb
Host smart-c88b750a-d19b-4e8d-b17c-ba8c04a86189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997805561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2997805561
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.4070166243
Short name T194
Test name
Test status
Simulation time 59519128706 ps
CPU time 200.14 seconds
Started Jan 07 12:54:42 PM PST 24
Finished Jan 07 12:59:32 PM PST 24
Peak memory 214224 kb
Host smart-d542304b-603c-4d1c-a54f-6fb51ae82316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070166243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4070166243
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2921466407
Short name T328
Test name
Test status
Simulation time 329829278044 ps
CPU time 695.54 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 01:08:13 PM PST 24
Peak memory 227024 kb
Host smart-f64a210e-f197-4370-903f-2dfa5e3814e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921466407 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2921466407
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_full.741514763
Short name T265
Test name
Test status
Simulation time 138632914207 ps
CPU time 28.88 seconds
Started Jan 07 12:53:07 PM PST 24
Finished Jan 07 12:54:56 PM PST 24
Peak memory 200132 kb
Host smart-88db31a2-02bf-4f5c-a6f5-637a2c462688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741514763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.741514763
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2347212415
Short name T241
Test name
Test status
Simulation time 51294503420 ps
CPU time 39.72 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 199748 kb
Host smart-7b4b7e00-39a8-4c88-a50c-70d548e846d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347212415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2347212415
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1602934078
Short name T149
Test name
Test status
Simulation time 27139612311 ps
CPU time 46.79 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:57:49 PM PST 24
Peak memory 200236 kb
Host smart-037285ad-09f9-4336-aaa4-5c0622f20c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602934078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1602934078
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1897759715
Short name T305
Test name
Test status
Simulation time 86728053894 ps
CPU time 18.34 seconds
Started Jan 07 12:55:36 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 200084 kb
Host smart-32df9adb-b500-4e09-a58f-7fd5e64dc7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897759715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1897759715
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1176119161
Short name T287
Test name
Test status
Simulation time 96621031773 ps
CPU time 33.64 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:57:16 PM PST 24
Peak memory 200204 kb
Host smart-5edd93bb-9ee5-4a83-9b11-5e281929653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176119161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1176119161
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1770201237
Short name T261
Test name
Test status
Simulation time 74915366777 ps
CPU time 50.44 seconds
Started Jan 07 12:55:27 PM PST 24
Finished Jan 07 12:57:59 PM PST 24
Peak memory 199912 kb
Host smart-2f9231f2-16cf-43c3-bba8-4e50dc0d33e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770201237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1770201237
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.4018941723
Short name T200
Test name
Test status
Simulation time 91331239083 ps
CPU time 43.29 seconds
Started Jan 07 12:55:17 PM PST 24
Finished Jan 07 12:57:31 PM PST 24
Peak memory 200100 kb
Host smart-81368355-14c8-47d5-b9b4-bd572dcc8bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018941723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4018941723
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_full.4031646757
Short name T322
Test name
Test status
Simulation time 365251184699 ps
CPU time 72.88 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:55 PM PST 24
Peak memory 200136 kb
Host smart-0e34b563-972f-4db7-8356-a14c5c3c95bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031646757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4031646757
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3817306196
Short name T32
Test name
Test status
Simulation time 95197040083 ps
CPU time 549.43 seconds
Started Jan 07 12:55:06 PM PST 24
Finished Jan 07 01:05:41 PM PST 24
Peak memory 225848 kb
Host smart-08012b9f-0386-41bf-9aa2-cf04957ed548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817306196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3817306196
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.69732733
Short name T51
Test name
Test status
Simulation time 79871727 ps
CPU time 0.89 seconds
Started Jan 07 12:29:49 PM PST 24
Finished Jan 07 12:31:45 PM PST 24
Peak memory 198612 kb
Host smart-88c1e479-3577-4b84-925a-cd2b67ba02cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69732733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.69732733
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_stress_all.2676132794
Short name T213
Test name
Test status
Simulation time 720737341463 ps
CPU time 515.12 seconds
Started Jan 07 12:54:05 PM PST 24
Finished Jan 07 01:03:58 PM PST 24
Peak memory 208536 kb
Host smart-60e8c55c-2eed-4874-9d45-d82a10a99164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676132794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2676132794
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3753099397
Short name T168
Test name
Test status
Simulation time 107729088751 ps
CPU time 87.2 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:58:39 PM PST 24
Peak memory 200204 kb
Host smart-b622652a-c7f0-40a7-8353-b5ea7d804141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753099397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3753099397
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3486073738
Short name T340
Test name
Test status
Simulation time 56177354966 ps
CPU time 14.8 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 200152 kb
Host smart-a4dd84be-bbdf-4420-b33c-fab7b6723550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486073738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3486073738
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_perf.2221921063
Short name T95
Test name
Test status
Simulation time 17479065583 ps
CPU time 220.7 seconds
Started Jan 07 12:53:14 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 200204 kb
Host smart-a95924ef-0b3c-4792-98bd-4820a0875fd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2221921063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2221921063
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2479853590
Short name T151
Test name
Test status
Simulation time 20172789387 ps
CPU time 11.72 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:56:57 PM PST 24
Peak memory 200256 kb
Host smart-7088f137-82eb-4e1d-a2b6-7423c0bbcb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479853590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2479853590
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.906022243
Short name T210
Test name
Test status
Simulation time 212171488858 ps
CPU time 34.17 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:57:30 PM PST 24
Peak memory 200220 kb
Host smart-2101ce54-a361-4382-aacd-c3d9c4cb973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906022243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.906022243
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.189222783
Short name T289
Test name
Test status
Simulation time 32924331286 ps
CPU time 29.12 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:57:35 PM PST 24
Peak memory 200128 kb
Host smart-7e27f7cb-e5f7-4d56-babb-6208114adcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189222783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.189222783
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2456703367
Short name T191
Test name
Test status
Simulation time 137965929322 ps
CPU time 20.58 seconds
Started Jan 07 12:55:32 PM PST 24
Finished Jan 07 12:57:35 PM PST 24
Peak memory 200124 kb
Host smart-7178ef8d-39b0-422c-adce-ec6d021c464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456703367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2456703367
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3706718814
Short name T226
Test name
Test status
Simulation time 115299613787 ps
CPU time 32.34 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 12:57:05 PM PST 24
Peak memory 199740 kb
Host smart-dccef5b9-aae7-40f0-8cb2-e9ab06ab54b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706718814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3706718814
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2287930805
Short name T257
Test name
Test status
Simulation time 178006863207 ps
CPU time 307.97 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 01:01:45 PM PST 24
Peak memory 200128 kb
Host smart-bf8d9b47-3805-4fb8-825f-670623583069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287930805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2287930805
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2798545383
Short name T218
Test name
Test status
Simulation time 121054850035 ps
CPU time 23.73 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 200116 kb
Host smart-21bb0512-b3a0-461b-a978-e5392f7d77e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798545383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2798545383
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3362173748
Short name T524
Test name
Test status
Simulation time 131073034102 ps
CPU time 62.44 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 200220 kb
Host smart-0723ed0a-c336-4e33-b184-130cc401922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362173748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3362173748
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4205558005
Short name T156
Test name
Test status
Simulation time 108146321033 ps
CPU time 40.31 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 199964 kb
Host smart-d4b4f8c3-864f-4a24-8512-6da3d7ba1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205558005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4205558005
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2352595957
Short name T337
Test name
Test status
Simulation time 144108580379 ps
CPU time 57.78 seconds
Started Jan 07 12:55:44 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 200104 kb
Host smart-840942d5-30d9-4811-98a3-2c945f52e72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352595957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2352595957
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2768284631
Short name T209
Test name
Test status
Simulation time 73116673996 ps
CPU time 122.8 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:59:08 PM PST 24
Peak memory 200060 kb
Host smart-9feca34c-a571-449e-b6e8-e5763607204c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768284631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2768284631
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3858497363
Short name T258
Test name
Test status
Simulation time 27601508709 ps
CPU time 23.55 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 200040 kb
Host smart-a9e55a57-fa90-4d71-a1d1-dbf10abdbea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858497363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3858497363
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3503791910
Short name T97
Test name
Test status
Simulation time 35028054942 ps
CPU time 60.8 seconds
Started Jan 07 12:55:16 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 200128 kb
Host smart-760ca8d0-fcaf-4910-9880-e8ba7455cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503791910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3503791910
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2484498531
Short name T228
Test name
Test status
Simulation time 5864419685 ps
CPU time 12.73 seconds
Started Jan 07 12:55:37 PM PST 24
Finished Jan 07 12:57:23 PM PST 24
Peak memory 200152 kb
Host smart-f1315636-7f20-409c-aff9-fe88c561620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484498531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2484498531
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.794889670
Short name T233
Test name
Test status
Simulation time 27060926262 ps
CPU time 21.18 seconds
Started Jan 07 12:55:36 PM PST 24
Finished Jan 07 12:57:43 PM PST 24
Peak memory 199628 kb
Host smart-885857eb-5c45-4af1-88a3-49dcea92f969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794889670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.794889670
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.305637798
Short name T266
Test name
Test status
Simulation time 37033827690 ps
CPU time 438.97 seconds
Started Jan 07 12:55:28 PM PST 24
Finished Jan 07 01:04:06 PM PST 24
Peak memory 216656 kb
Host smart-64ca2f8a-6a07-4a1b-9042-5421ce9c14f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305637798 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.305637798
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2222301876
Short name T219
Test name
Test status
Simulation time 169868752884 ps
CPU time 307.68 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 01:00:45 PM PST 24
Peak memory 200128 kb
Host smart-de1f55c7-1336-4b02-a578-6335e7832804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222301876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2222301876
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3009400779
Short name T275
Test name
Test status
Simulation time 93026299109 ps
CPU time 592.67 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 01:04:24 PM PST 24
Peak memory 216624 kb
Host smart-7ed27fe1-5022-456a-ab4b-f334c312842e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009400779 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3009400779
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_rx.797558710
Short name T230
Test name
Test status
Simulation time 51472356317 ps
CPU time 168.95 seconds
Started Jan 07 12:52:57 PM PST 24
Finished Jan 07 12:56:56 PM PST 24
Peak memory 200120 kb
Host smart-bfc1bcb7-205d-462a-9fdb-d3b664d8ceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797558710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.797558710
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1759594108
Short name T247
Test name
Test status
Simulation time 173233143507 ps
CPU time 300.36 seconds
Started Jan 07 12:53:48 PM PST 24
Finished Jan 07 01:00:06 PM PST 24
Peak memory 200188 kb
Host smart-6b0946f2-6d20-4a12-bce6-2b0d6998b142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759594108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1759594108
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3539472119
Short name T284
Test name
Test status
Simulation time 169671443067 ps
CPU time 77.77 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:56:22 PM PST 24
Peak memory 200180 kb
Host smart-5c3d7419-1655-46f7-bc9f-8f7baf36d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539472119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3539472119
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2257798110
Short name T251
Test name
Test status
Simulation time 129607226594 ps
CPU time 109.31 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 12:57:11 PM PST 24
Peak memory 199752 kb
Host smart-80cb026a-2314-45e4-b8e2-c651b6127b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257798110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2257798110
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.455752
Short name T326
Test name
Test status
Simulation time 172075345531 ps
CPU time 74.97 seconds
Started Jan 07 12:54:22 PM PST 24
Finished Jan 07 12:57:05 PM PST 24
Peak memory 199984 kb
Host smart-7942fa6c-a1bd-46c4-bea4-bf9e556516d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.455752
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.490027535
Short name T195
Test name
Test status
Simulation time 60911967999 ps
CPU time 23.58 seconds
Started Jan 07 12:55:35 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 200032 kb
Host smart-3bd1204f-5992-4a7b-8cbf-29b6fa3a9846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490027535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.490027535
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1066893457
Short name T235
Test name
Test status
Simulation time 29395665829 ps
CPU time 49.13 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:57:22 PM PST 24
Peak memory 200068 kb
Host smart-c943b329-4a4a-4165-9236-e1bac22cb7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066893457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1066893457
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.3226335808
Short name T201
Test name
Test status
Simulation time 395641730913 ps
CPU time 208.85 seconds
Started Jan 07 12:52:59 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 200492 kb
Host smart-8638dafc-71cb-49a1-88c8-facfbf7c5c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226335808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3226335808
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1316048883
Short name T220
Test name
Test status
Simulation time 296753318488 ps
CPU time 108.54 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:58:18 PM PST 24
Peak memory 199672 kb
Host smart-a8f05dd2-8019-40b5-aead-caba5fe02d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316048883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1316048883
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1950286546
Short name T169
Test name
Test status
Simulation time 105023437062 ps
CPU time 165.81 seconds
Started Jan 07 12:55:21 PM PST 24
Finished Jan 07 12:59:53 PM PST 24
Peak memory 200112 kb
Host smart-dc606c28-0a9e-4a62-bd33-97aa6d317677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950286546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1950286546
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.705771056
Short name T180
Test name
Test status
Simulation time 46355478206 ps
CPU time 14.78 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:56:56 PM PST 24
Peak memory 200192 kb
Host smart-c4e25f10-4262-4c70-a3ab-0f86c4132a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705771056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.705771056
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1434229497
Short name T212
Test name
Test status
Simulation time 122740251958 ps
CPU time 87.42 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:58:26 PM PST 24
Peak memory 200196 kb
Host smart-518c5d91-0d62-4f4a-b989-5f10fabac4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434229497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1434229497
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3817342999
Short name T205
Test name
Test status
Simulation time 26634374586 ps
CPU time 8.52 seconds
Started Jan 07 12:55:34 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 200160 kb
Host smart-493d7afd-b332-4a4b-940a-d33930761eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817342999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3817342999
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3790104991
Short name T288
Test name
Test status
Simulation time 74945282065 ps
CPU time 32.44 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 200284 kb
Host smart-22dcd921-8a18-4a85-be83-37266b5bd5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790104991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3790104991
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1261904081
Short name T1028
Test name
Test status
Simulation time 54419528323 ps
CPU time 84.37 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:58:14 PM PST 24
Peak memory 199800 kb
Host smart-69034969-e7da-412b-98a6-131d1cffab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261904081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1261904081
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1848326869
Short name T271
Test name
Test status
Simulation time 76702798326 ps
CPU time 116.51 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:58:28 PM PST 24
Peak memory 200116 kb
Host smart-31ff22d3-0ed9-400a-ba02-690e817cfcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848326869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1848326869
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1425041796
Short name T292
Test name
Test status
Simulation time 63863829667 ps
CPU time 27.6 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:14 PM PST 24
Peak memory 200124 kb
Host smart-1ef304ac-9d73-4a52-a5b9-a72869589772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425041796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1425041796
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2804932542
Short name T281
Test name
Test status
Simulation time 65870758048 ps
CPU time 20.16 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 12:56:21 PM PST 24
Peak memory 200188 kb
Host smart-5062069b-f0ee-4db2-ae2b-2ec5fe9bf54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804932542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2804932542
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4029542428
Short name T174
Test name
Test status
Simulation time 36315319531 ps
CPU time 58.57 seconds
Started Jan 07 12:55:49 PM PST 24
Finished Jan 07 12:58:24 PM PST 24
Peak memory 200280 kb
Host smart-c562d2c4-ec85-4ad2-a3c4-81c6b8754b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029542428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4029542428
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.979535373
Short name T303
Test name
Test status
Simulation time 84418334577 ps
CPU time 36.09 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:56 PM PST 24
Peak memory 200160 kb
Host smart-ec31ae57-c8fb-4200-925b-08d824b2c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979535373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.979535373
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4019632624
Short name T298
Test name
Test status
Simulation time 68872088482 ps
CPU time 30.7 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:55 PM PST 24
Peak memory 200132 kb
Host smart-1861f3fe-1f4f-4cf6-b239-037a63e12fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019632624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4019632624
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.992430103
Short name T104
Test name
Test status
Simulation time 80416077274 ps
CPU time 34.77 seconds
Started Jan 07 12:55:21 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 199928 kb
Host smart-75d570fc-aeb4-4aa9-9a65-1114d9304477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992430103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.992430103
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3194816736
Short name T310
Test name
Test status
Simulation time 142160258547 ps
CPU time 70.57 seconds
Started Jan 07 12:54:09 PM PST 24
Finished Jan 07 12:56:39 PM PST 24
Peak memory 200128 kb
Host smart-9b4af748-c964-4db4-81ae-29c1b4be9553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194816736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3194816736
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1869180246
Short name T259
Test name
Test status
Simulation time 35594278387 ps
CPU time 1212.14 seconds
Started Jan 07 12:54:24 PM PST 24
Finished Jan 07 01:16:13 PM PST 24
Peak memory 216624 kb
Host smart-1aa1180e-6057-4cc1-a213-c8f5353f7f55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869180246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1869180246
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.603367991
Short name T333
Test name
Test status
Simulation time 90566120724 ps
CPU time 72.06 seconds
Started Jan 07 12:54:50 PM PST 24
Finished Jan 07 12:57:36 PM PST 24
Peak memory 200176 kb
Host smart-a89889f1-ecf4-4cfa-8847-407475e7b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603367991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.603367991
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.422035320
Short name T260
Test name
Test status
Simulation time 166403572359 ps
CPU time 73.46 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 12:57:07 PM PST 24
Peak memory 199844 kb
Host smart-e285aaab-1079-4d5b-b55f-6aca1c4f9133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422035320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.422035320
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2789543102
Short name T182
Test name
Test status
Simulation time 33813120058 ps
CPU time 28.02 seconds
Started Jan 07 12:55:57 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 198932 kb
Host smart-7a59612a-9165-47a4-b9da-6cca0f0f7bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789543102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2789543102
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_stress_all.4115073843
Short name T324
Test name
Test status
Simulation time 389379771789 ps
CPU time 766.48 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 01:09:02 PM PST 24
Peak memory 200164 kb
Host smart-911a0605-4cd6-4b7e-bc37-60f4d32e565e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115073843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.4115073843
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3898961179
Short name T336
Test name
Test status
Simulation time 383778836233 ps
CPU time 117.54 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 12:58:14 PM PST 24
Peak memory 200156 kb
Host smart-82bb403d-0407-44f4-abdb-6c36d9158cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898961179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3898961179
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2830364567
Short name T341
Test name
Test status
Simulation time 48076673855 ps
CPU time 39.34 seconds
Started Jan 07 12:54:42 PM PST 24
Finished Jan 07 12:56:52 PM PST 24
Peak memory 200196 kb
Host smart-cce61408-48f4-4393-8197-14c23f042610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830364567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2830364567
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_full.136358934
Short name T318
Test name
Test status
Simulation time 149750694668 ps
CPU time 27.87 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:17 PM PST 24
Peak memory 200148 kb
Host smart-b552af9f-f557-4d2e-acf4-007943ffb776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136358934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.136358934
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1471520976
Short name T4
Test name
Test status
Simulation time 25447686090 ps
CPU time 43.71 seconds
Started Jan 07 12:54:54 PM PST 24
Finished Jan 07 12:57:09 PM PST 24
Peak memory 200056 kb
Host smart-231b906e-4858-418f-bcfa-76ba1cb963c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471520976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1471520976
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1025811418
Short name T312
Test name
Test status
Simulation time 496215380435 ps
CPU time 964.41 seconds
Started Jan 07 12:55:09 PM PST 24
Finished Jan 07 01:13:03 PM PST 24
Peak memory 216832 kb
Host smart-f86eb1be-1333-44fc-9b02-c5eb1ea308a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025811418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1025811418
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.361139039
Short name T222
Test name
Test status
Simulation time 120293481965 ps
CPU time 177.02 seconds
Started Jan 07 12:55:12 PM PST 24
Finished Jan 07 12:59:55 PM PST 24
Peak memory 200200 kb
Host smart-d79f969b-0199-4ff2-ba17-163b6327efa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361139039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.361139039
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1395592767
Short name T262
Test name
Test status
Simulation time 28547164067 ps
CPU time 49.28 seconds
Started Jan 07 12:53:26 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 200212 kb
Host smart-ba016651-4755-4f29-80c7-6cea874b3ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395592767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1395592767
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1145034873
Short name T264
Test name
Test status
Simulation time 95948255731 ps
CPU time 10.76 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:56:46 PM PST 24
Peak memory 199876 kb
Host smart-d0a48b77-48b8-430c-81a3-452f29caa745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145034873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1145034873
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1403564700
Short name T299
Test name
Test status
Simulation time 226616377277 ps
CPU time 21.31 seconds
Started Jan 07 12:55:28 PM PST 24
Finished Jan 07 12:57:09 PM PST 24
Peak memory 200148 kb
Host smart-20bcf9b8-aa23-4b3a-80fe-c28aae433707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403564700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1403564700
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.984031830
Short name T165
Test name
Test status
Simulation time 425327561267 ps
CPU time 474.12 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 01:02:41 PM PST 24
Peak memory 200220 kb
Host smart-9e9faaec-ed80-47ca-a61c-9177d127a87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984031830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.984031830
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1073422657
Short name T55
Test name
Test status
Simulation time 221575872 ps
CPU time 2.14 seconds
Started Jan 07 12:31:18 PM PST 24
Finished Jan 07 12:32:54 PM PST 24
Peak memory 196816 kb
Host smart-1b6b49f3-730a-4bb2-9b05-860cceafcb7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073422657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1073422657
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1177363294
Short name T453
Test name
Test status
Simulation time 54260682 ps
CPU time 0.6 seconds
Started Jan 07 12:24:07 PM PST 24
Finished Jan 07 12:24:24 PM PST 24
Peak memory 195132 kb
Host smart-21826909-5d02-4602-b515-04a170eadb59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177363294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1177363294
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.869978867
Short name T495
Test name
Test status
Simulation time 23958409 ps
CPU time 0.67 seconds
Started Jan 07 12:30:59 PM PST 24
Finished Jan 07 12:33:27 PM PST 24
Peak memory 195668 kb
Host smart-6f92f828-fc64-4b43-a8a2-edd556135a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869978867 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.869978867
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3174540516
Short name T46
Test name
Test status
Simulation time 15867570 ps
CPU time 0.63 seconds
Started Jan 07 12:35:49 PM PST 24
Finished Jan 07 12:37:12 PM PST 24
Peak memory 194692 kb
Host smart-61f2e5e4-7c3c-4f74-9f15-42c110d81280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174540516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3174540516
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1873912883
Short name T459
Test name
Test status
Simulation time 39396733 ps
CPU time 0.55 seconds
Started Jan 07 12:26:06 PM PST 24
Finished Jan 07 12:27:08 PM PST 24
Peak memory 184836 kb
Host smart-368aa47f-7cdc-48e0-9b78-d0c15bc899fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873912883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1873912883
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3207878603
Short name T477
Test name
Test status
Simulation time 18611594 ps
CPU time 0.68 seconds
Started Jan 07 12:29:47 PM PST 24
Finished Jan 07 12:31:19 PM PST 24
Peak memory 196936 kb
Host smart-2399d9ba-8e5f-4a82-928e-8b25bf0a1990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207878603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3207878603
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.457856506
Short name T53
Test name
Test status
Simulation time 51843131 ps
CPU time 1.09 seconds
Started Jan 07 12:30:29 PM PST 24
Finished Jan 07 12:32:00 PM PST 24
Peak memory 199040 kb
Host smart-e8aaeb33-f60a-47e7-b09d-e16be69571d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457856506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.457856506
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.240969884
Short name T79
Test name
Test status
Simulation time 51591696 ps
CPU time 0.94 seconds
Started Jan 07 12:31:19 PM PST 24
Finished Jan 07 12:33:48 PM PST 24
Peak memory 198628 kb
Host smart-5aa34cd2-ada4-4b36-9b25-e5b89989a5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240969884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.240969884
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1482683270
Short name T438
Test name
Test status
Simulation time 33165062 ps
CPU time 0.76 seconds
Started Jan 07 12:30:55 PM PST 24
Finished Jan 07 12:32:23 PM PST 24
Peak memory 196740 kb
Host smart-f6462394-b8a5-44d2-8588-0e5b6827516d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482683270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1482683270
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3126716844
Short name T420
Test name
Test status
Simulation time 57629794 ps
CPU time 2.14 seconds
Started Jan 07 12:29:56 PM PST 24
Finished Jan 07 12:31:51 PM PST 24
Peak memory 197724 kb
Host smart-f5293c5f-89ea-45b2-aa56-10cd57f85b88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126716844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3126716844
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.4225859089
Short name T62
Test name
Test status
Simulation time 21080117 ps
CPU time 0.6 seconds
Started Jan 07 12:30:28 PM PST 24
Finished Jan 07 12:32:03 PM PST 24
Peak memory 195404 kb
Host smart-11ca067c-32cc-4bd8-b82d-9d8a0ae4f2a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225859089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.4225859089
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.49824004
Short name T436
Test name
Test status
Simulation time 34680841 ps
CPU time 0.91 seconds
Started Jan 07 12:31:52 PM PST 24
Finished Jan 07 12:33:23 PM PST 24
Peak memory 199556 kb
Host smart-94368707-aa83-4ae1-b0d3-a55f893f79b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49824004 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.49824004
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.362104415
Short name T419
Test name
Test status
Simulation time 16579389 ps
CPU time 0.59 seconds
Started Jan 07 12:29:45 PM PST 24
Finished Jan 07 12:31:25 PM PST 24
Peak memory 184276 kb
Host smart-cff5b56e-e144-4abc-9ca3-b3e89e90bb73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362104415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.362104415
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3948254263
Short name T60
Test name
Test status
Simulation time 26662796 ps
CPU time 0.64 seconds
Started Jan 07 12:41:38 PM PST 24
Finished Jan 07 12:43:10 PM PST 24
Peak memory 195804 kb
Host smart-ca5fe6c1-962b-4ae6-a2a0-f95bbe90a9cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948254263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3948254263
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2232626758
Short name T417
Test name
Test status
Simulation time 79666369 ps
CPU time 1.69 seconds
Started Jan 07 12:30:41 PM PST 24
Finished Jan 07 12:32:14 PM PST 24
Peak memory 199700 kb
Host smart-68680287-002e-4d1c-8e75-3954686f4059
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232626758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2232626758
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1233998311
Short name T63
Test name
Test status
Simulation time 16941128 ps
CPU time 0.66 seconds
Started Jan 07 12:23:50 PM PST 24
Finished Jan 07 12:24:01 PM PST 24
Peak memory 196552 kb
Host smart-3c9a3ca7-331d-4340-b62f-ebe4b81eec56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233998311 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1233998311
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.611344599
Short name T470
Test name
Test status
Simulation time 21114208 ps
CPU time 0.57 seconds
Started Jan 07 12:29:36 PM PST 24
Finished Jan 07 12:31:12 PM PST 24
Peak memory 195172 kb
Host smart-bdc07284-828f-4e35-901f-0eee0924173f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611344599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.611344599
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.991719612
Short name T343
Test name
Test status
Simulation time 144778378 ps
CPU time 0.61 seconds
Started Jan 07 12:29:17 PM PST 24
Finished Jan 07 12:30:34 PM PST 24
Peak memory 193152 kb
Host smart-64cc9e12-f583-45d6-a3b6-ae3aec130899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991719612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.991719612
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3761602390
Short name T50
Test name
Test status
Simulation time 229050523 ps
CPU time 0.97 seconds
Started Jan 07 12:29:09 PM PST 24
Finished Jan 07 12:30:32 PM PST 24
Peak memory 199452 kb
Host smart-708d81dd-f7c8-4243-8dbf-c3eb2944d666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761602390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3761602390
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3265934734
Short name T479
Test name
Test status
Simulation time 94447354 ps
CPU time 0.8 seconds
Started Jan 07 12:26:52 PM PST 24
Finished Jan 07 12:28:09 PM PST 24
Peak memory 198940 kb
Host smart-6a7c71b0-4c7f-4645-98f9-7cbcc2b2ff9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265934734 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3265934734
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1305903591
Short name T58
Test name
Test status
Simulation time 177898911 ps
CPU time 0.56 seconds
Started Jan 07 12:29:53 PM PST 24
Finished Jan 07 12:33:34 PM PST 24
Peak memory 195116 kb
Host smart-5e094861-c190-4e2d-b78e-d649b892bac9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305903591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1305903591
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2652085679
Short name T476
Test name
Test status
Simulation time 40786602 ps
CPU time 0.63 seconds
Started Jan 07 12:29:45 PM PST 24
Finished Jan 07 12:31:19 PM PST 24
Peak memory 194800 kb
Host smart-0a6007cc-1c01-4ae7-8174-99a3b6542754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652085679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2652085679
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3038586120
Short name T430
Test name
Test status
Simulation time 323280816 ps
CPU time 1.6 seconds
Started Jan 07 12:26:21 PM PST 24
Finished Jan 07 12:27:26 PM PST 24
Peak memory 199728 kb
Host smart-6cee4d62-d46c-4567-80af-ac4490e1b7bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038586120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3038586120
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.324859873
Short name T28
Test name
Test status
Simulation time 93605074 ps
CPU time 1.22 seconds
Started Jan 07 12:26:22 PM PST 24
Finished Jan 07 12:27:27 PM PST 24
Peak memory 198676 kb
Host smart-b192a59e-dbee-498f-a7d5-2fdd2b599094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324859873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.324859873
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.986530307
Short name T414
Test name
Test status
Simulation time 31485985 ps
CPU time 0.8 seconds
Started Jan 07 12:29:51 PM PST 24
Finished Jan 07 12:31:36 PM PST 24
Peak memory 198844 kb
Host smart-f2db3385-6909-4970-98ff-6e79935c851b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986530307 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.986530307
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3110029221
Short name T471
Test name
Test status
Simulation time 23825374 ps
CPU time 0.57 seconds
Started Jan 07 12:30:32 PM PST 24
Finished Jan 07 12:31:55 PM PST 24
Peak memory 195248 kb
Host smart-4715e555-8637-4077-9319-bbe49cbb55fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110029221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3110029221
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3575080841
Short name T444
Test name
Test status
Simulation time 23695319 ps
CPU time 0.6 seconds
Started Jan 07 12:26:04 PM PST 24
Finished Jan 07 12:27:03 PM PST 24
Peak memory 184252 kb
Host smart-934a7c53-2063-49f4-b48e-6ec665e12eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575080841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3575080841
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1854715140
Short name T66
Test name
Test status
Simulation time 81220580 ps
CPU time 0.59 seconds
Started Jan 07 12:26:14 PM PST 24
Finished Jan 07 12:27:16 PM PST 24
Peak memory 194196 kb
Host smart-ea7d41b2-9c2e-445a-8455-0dd4b4870e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854715140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1854715140
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2274003183
Short name T449
Test name
Test status
Simulation time 103375946 ps
CPU time 1.82 seconds
Started Jan 07 12:29:45 PM PST 24
Finished Jan 07 12:31:22 PM PST 24
Peak memory 199636 kb
Host smart-eee77637-1360-4cf4-bea1-57da2302a08f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274003183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2274003183
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1687110908
Short name T77
Test name
Test status
Simulation time 649937484 ps
CPU time 1.2 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:15 PM PST 24
Peak memory 198068 kb
Host smart-ba30c5e6-af6b-42d0-b673-7ca9b3af75df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687110908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1687110908
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3234967395
Short name T457
Test name
Test status
Simulation time 25526400 ps
CPU time 0.79 seconds
Started Jan 07 12:25:24 PM PST 24
Finished Jan 07 12:26:28 PM PST 24
Peak memory 199100 kb
Host smart-ec71fc93-62ca-41ab-b2e2-365413878009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234967395 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3234967395
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2711523843
Short name T47
Test name
Test status
Simulation time 120571328 ps
CPU time 0.58 seconds
Started Jan 07 12:26:29 PM PST 24
Finished Jan 07 12:27:38 PM PST 24
Peak memory 195160 kb
Host smart-de07f537-8d32-41c4-9487-6b27c9467d16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711523843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2711523843
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2285883755
Short name T345
Test name
Test status
Simulation time 70095172 ps
CPU time 0.57 seconds
Started Jan 07 12:25:30 PM PST 24
Finished Jan 07 12:26:32 PM PST 24
Peak memory 185076 kb
Host smart-f3267866-48c9-4aef-ac29-91e5908ae499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285883755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2285883755
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4164929356
Short name T454
Test name
Test status
Simulation time 64019401 ps
CPU time 0.65 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:39 PM PST 24
Peak memory 196576 kb
Host smart-1751a543-3590-4793-94e2-b569b9d6346c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164929356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4164929356
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1694929553
Short name T475
Test name
Test status
Simulation time 50476214 ps
CPU time 1.12 seconds
Started Jan 07 12:26:05 PM PST 24
Finished Jan 07 12:27:07 PM PST 24
Peak memory 199592 kb
Host smart-ee36a2e5-c891-448f-8cde-83bd91fae6fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694929553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1694929553
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3522488169
Short name T494
Test name
Test status
Simulation time 336224572 ps
CPU time 0.87 seconds
Started Jan 07 12:26:17 PM PST 24
Finished Jan 07 12:27:20 PM PST 24
Peak memory 198616 kb
Host smart-226d49c4-db7a-481d-ae93-85f9eee30701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522488169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3522488169
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4037021302
Short name T412
Test name
Test status
Simulation time 21809957 ps
CPU time 0.95 seconds
Started Jan 07 12:26:32 PM PST 24
Finished Jan 07 12:27:44 PM PST 24
Peak memory 199452 kb
Host smart-13e1e602-9173-412a-96e1-a86102d31628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037021302 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4037021302
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3618203039
Short name T466
Test name
Test status
Simulation time 13362875 ps
CPU time 0.55 seconds
Started Jan 07 12:31:32 PM PST 24
Finished Jan 07 12:33:21 PM PST 24
Peak memory 195224 kb
Host smart-6b30e22f-f60e-465c-9fe8-0b67b1c44938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618203039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3618203039
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2142773708
Short name T498
Test name
Test status
Simulation time 45747530 ps
CPU time 0.68 seconds
Started Jan 07 12:41:33 PM PST 24
Finished Jan 07 12:43:23 PM PST 24
Peak memory 196964 kb
Host smart-1b4ef048-64d9-4ccf-928e-8377d1e88688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142773708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2142773708
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2798571209
Short name T493
Test name
Test status
Simulation time 388513011 ps
CPU time 1.28 seconds
Started Jan 07 12:31:45 PM PST 24
Finished Jan 07 12:33:32 PM PST 24
Peak memory 199092 kb
Host smart-446c7297-266c-4025-be38-bd9e87cb2412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798571209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2798571209
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.548725141
Short name T441
Test name
Test status
Simulation time 109909892 ps
CPU time 1.24 seconds
Started Jan 07 12:26:32 PM PST 24
Finished Jan 07 12:27:45 PM PST 24
Peak memory 199616 kb
Host smart-0218d06c-3b8c-4a3b-a51e-38a3bc65566f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548725141 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.548725141
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.695313005
Short name T45
Test name
Test status
Simulation time 55889275 ps
CPU time 0.61 seconds
Started Jan 07 12:31:27 PM PST 24
Finished Jan 07 12:33:05 PM PST 24
Peak memory 194620 kb
Host smart-d596a112-18b5-433b-99fb-0c9f941d13a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695313005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.695313005
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.224507489
Short name T489
Test name
Test status
Simulation time 19014407 ps
CPU time 0.57 seconds
Started Jan 07 12:28:53 PM PST 24
Finished Jan 07 12:29:59 PM PST 24
Peak memory 184404 kb
Host smart-4425ec1f-dd24-4c12-b3e8-87ffa9650ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224507489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.224507489
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3065494502
Short name T69
Test name
Test status
Simulation time 21648323 ps
CPU time 0.61 seconds
Started Jan 07 12:25:52 PM PST 24
Finished Jan 07 12:26:55 PM PST 24
Peak memory 194212 kb
Host smart-af91f964-2c17-4c2b-a36c-c6766217ad83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065494502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3065494502
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1604113043
Short name T483
Test name
Test status
Simulation time 497464292 ps
CPU time 2.09 seconds
Started Jan 07 12:25:38 PM PST 24
Finished Jan 07 12:26:40 PM PST 24
Peak memory 199588 kb
Host smart-4fe4c349-c017-4e89-b91f-6ba62ace7514
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604113043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1604113043
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2369299279
Short name T26
Test name
Test status
Simulation time 180479932 ps
CPU time 1.29 seconds
Started Jan 07 12:30:26 PM PST 24
Finished Jan 07 12:32:05 PM PST 24
Peak memory 198552 kb
Host smart-817f5342-35f4-4ca0-9a87-3f4b5aa27172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369299279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2369299279
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2673440842
Short name T61
Test name
Test status
Simulation time 62620751 ps
CPU time 0.74 seconds
Started Jan 07 12:29:37 PM PST 24
Finished Jan 07 12:31:02 PM PST 24
Peak memory 197932 kb
Host smart-afe3a7b8-9dd8-490c-8805-36534ba19a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673440842 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2673440842
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2836075321
Short name T56
Test name
Test status
Simulation time 58118634 ps
CPU time 0.58 seconds
Started Jan 07 12:33:01 PM PST 24
Finished Jan 07 12:34:40 PM PST 24
Peak memory 195216 kb
Host smart-0b01a871-4121-4649-b2ce-b8e96386fb62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836075321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2836075321
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.780427685
Short name T416
Test name
Test status
Simulation time 22736896 ps
CPU time 0.54 seconds
Started Jan 07 12:31:19 PM PST 24
Finished Jan 07 12:32:53 PM PST 24
Peak memory 194028 kb
Host smart-f5601576-9f6d-457c-9633-d4d2d42d5bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780427685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.780427685
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1609988075
Short name T492
Test name
Test status
Simulation time 96792274 ps
CPU time 1.99 seconds
Started Jan 07 12:34:16 PM PST 24
Finished Jan 07 12:35:56 PM PST 24
Peak memory 199804 kb
Host smart-7eb193ca-52d6-42ec-87d1-5ce15fd2f4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609988075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1609988075
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1809971776
Short name T481
Test name
Test status
Simulation time 73889183 ps
CPU time 1.3 seconds
Started Jan 07 12:24:10 PM PST 24
Finished Jan 07 12:24:29 PM PST 24
Peak memory 199160 kb
Host smart-82f30dd8-53ad-4028-99d8-abd2323bf0c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809971776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1809971776
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3941850224
Short name T344
Test name
Test status
Simulation time 16228679 ps
CPU time 0.58 seconds
Started Jan 07 12:24:26 PM PST 24
Finished Jan 07 12:24:59 PM PST 24
Peak memory 194316 kb
Host smart-d52ecbc6-ca6d-4e85-9700-9d3040d02c70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941850224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3941850224
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2552341104
Short name T468
Test name
Test status
Simulation time 27979323 ps
CPU time 0.73 seconds
Started Jan 07 12:23:50 PM PST 24
Finished Jan 07 12:24:02 PM PST 24
Peak memory 195872 kb
Host smart-e8b68806-93cb-4408-ae13-0659e6c271bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552341104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2552341104
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3878999638
Short name T486
Test name
Test status
Simulation time 53031828 ps
CPU time 0.95 seconds
Started Jan 07 12:27:13 PM PST 24
Finished Jan 07 12:28:25 PM PST 24
Peak memory 198988 kb
Host smart-fe7ae97b-184d-436b-82de-a3c5e19fe002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878999638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3878999638
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2440095339
Short name T490
Test name
Test status
Simulation time 85558740 ps
CPU time 0.84 seconds
Started Jan 07 12:29:37 PM PST 24
Finished Jan 07 12:31:09 PM PST 24
Peak memory 199348 kb
Host smart-e1fc33a7-2cc3-46f1-8487-dfad5a666020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440095339 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2440095339
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2668911769
Short name T68
Test name
Test status
Simulation time 13862606 ps
CPU time 0.68 seconds
Started Jan 07 12:29:08 PM PST 24
Finished Jan 07 12:30:41 PM PST 24
Peak memory 194892 kb
Host smart-406d301b-554e-49e1-8e1b-52e58418a7f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668911769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2668911769
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.542332859
Short name T469
Test name
Test status
Simulation time 15373178 ps
CPU time 0.54 seconds
Started Jan 07 12:33:13 PM PST 24
Finished Jan 07 12:36:33 PM PST 24
Peak memory 194120 kb
Host smart-edcc3a4e-e77d-4cf2-b810-3da03013696d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542332859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.542332859
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2260121238
Short name T464
Test name
Test status
Simulation time 29401005 ps
CPU time 0.7 seconds
Started Jan 07 12:29:34 PM PST 24
Finished Jan 07 12:31:04 PM PST 24
Peak memory 196696 kb
Host smart-24017c82-b363-4242-9ac6-5caf919a8b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260121238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2260121238
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3078432709
Short name T93
Test name
Test status
Simulation time 19946032 ps
CPU time 0.67 seconds
Started Jan 07 12:26:20 PM PST 24
Finished Jan 07 12:27:24 PM PST 24
Peak memory 197040 kb
Host smart-23865898-06e5-4534-8530-056a0f770586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078432709 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3078432709
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3848493306
Short name T42
Test name
Test status
Simulation time 66954750 ps
CPU time 0.57 seconds
Started Jan 07 12:26:28 PM PST 24
Finished Jan 07 12:27:36 PM PST 24
Peak memory 195136 kb
Host smart-c5cb06f6-394d-45a1-8296-b6b3fb65de4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848493306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3848493306
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3401196793
Short name T52
Test name
Test status
Simulation time 257665332 ps
CPU time 0.71 seconds
Started Jan 07 12:24:07 PM PST 24
Finished Jan 07 12:24:24 PM PST 24
Peak memory 196704 kb
Host smart-8176c3ab-047b-44c8-a0c0-0d66f5a6214d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401196793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3401196793
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.975267345
Short name T446
Test name
Test status
Simulation time 108278094 ps
CPU time 1.45 seconds
Started Jan 07 12:29:09 PM PST 24
Finished Jan 07 12:30:27 PM PST 24
Peak memory 199556 kb
Host smart-e394eefe-fee1-4893-ae8e-317100aadac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975267345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.975267345
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.167187769
Short name T342
Test name
Test status
Simulation time 72626576 ps
CPU time 0.92 seconds
Started Jan 07 12:29:51 PM PST 24
Finished Jan 07 12:31:35 PM PST 24
Peak memory 198296 kb
Host smart-ea21962b-d3c4-4996-8dc9-5d90bdb33660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167187769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.167187769
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.869437111
Short name T455
Test name
Test status
Simulation time 57048569 ps
CPU time 0.65 seconds
Started Jan 07 12:24:05 PM PST 24
Finished Jan 07 12:24:22 PM PST 24
Peak memory 194872 kb
Host smart-5bf45e69-43eb-49f9-9b91-b0e6efe62c8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869437111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.869437111
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4281308873
Short name T413
Test name
Test status
Simulation time 35504974 ps
CPU time 1.36 seconds
Started Jan 07 12:31:08 PM PST 24
Finished Jan 07 12:32:42 PM PST 24
Peak memory 196944 kb
Host smart-8ea11c9d-0240-4dbe-8230-f7b4533625a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281308873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4281308873
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.358140279
Short name T448
Test name
Test status
Simulation time 16249213 ps
CPU time 0.55 seconds
Started Jan 07 12:34:40 PM PST 24
Finished Jan 07 12:36:33 PM PST 24
Peak memory 195144 kb
Host smart-d6b43ba8-5728-4256-91f4-e3416287d771
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358140279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.358140279
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4206800123
Short name T435
Test name
Test status
Simulation time 46900891 ps
CPU time 0.56 seconds
Started Jan 07 12:24:42 PM PST 24
Finished Jan 07 12:25:38 PM PST 24
Peak memory 195388 kb
Host smart-bf64a15f-f99e-42a6-9d58-c542db3ca92b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206800123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4206800123
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2595626045
Short name T427
Test name
Test status
Simulation time 25656174 ps
CPU time 0.54 seconds
Started Jan 07 12:30:32 PM PST 24
Finished Jan 07 12:32:00 PM PST 24
Peak memory 193996 kb
Host smart-10a0e836-33b1-4107-a8bc-855d47ad6f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595626045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2595626045
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.543609024
Short name T425
Test name
Test status
Simulation time 12011429 ps
CPU time 0.55 seconds
Started Jan 07 12:25:21 PM PST 24
Finished Jan 07 12:26:24 PM PST 24
Peak memory 185168 kb
Host smart-46d551e7-8945-4336-9e29-80d9fda8e857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543609024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.543609024
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3486492377
Short name T432
Test name
Test status
Simulation time 50504475 ps
CPU time 0.54 seconds
Started Jan 07 12:26:19 PM PST 24
Finished Jan 07 12:27:23 PM PST 24
Peak memory 184840 kb
Host smart-ace6e721-e849-4fa0-ab76-8d25f631dbaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486492377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3486492377
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4248053386
Short name T437
Test name
Test status
Simulation time 20602307 ps
CPU time 0.61 seconds
Started Jan 07 12:26:13 PM PST 24
Finished Jan 07 12:27:15 PM PST 24
Peak memory 193184 kb
Host smart-29ce70f2-7f58-446d-a0b2-67c7cf79662b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248053386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4248053386
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2060790412
Short name T487
Test name
Test status
Simulation time 139564370 ps
CPU time 0.7 seconds
Started Jan 07 12:23:53 PM PST 24
Finished Jan 07 12:24:08 PM PST 24
Peak memory 192712 kb
Host smart-7b324052-c091-420a-81b6-8600d1ebcce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060790412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2060790412
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.447292902
Short name T64
Test name
Test status
Simulation time 22471595 ps
CPU time 0.6 seconds
Started Jan 07 12:26:19 PM PST 24
Finished Jan 07 12:27:22 PM PST 24
Peak memory 184852 kb
Host smart-618f0481-9d9e-431d-ac89-87b2b0b06bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447292902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.447292902
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3618855585
Short name T346
Test name
Test status
Simulation time 12253476 ps
CPU time 0.54 seconds
Started Jan 07 12:26:22 PM PST 24
Finished Jan 07 12:27:26 PM PST 24
Peak memory 184836 kb
Host smart-a534d253-56da-4fa8-a38c-441dfd292d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618855585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3618855585
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2735097020
Short name T458
Test name
Test status
Simulation time 14817917 ps
CPU time 0.59 seconds
Started Jan 07 12:26:19 PM PST 24
Finished Jan 07 12:27:22 PM PST 24
Peak memory 184852 kb
Host smart-bc4250a3-d2d1-4959-8e25-c5d22077533e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735097020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2735097020
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3341701303
Short name T485
Test name
Test status
Simulation time 82072620 ps
CPU time 0.58 seconds
Started Jan 07 12:26:29 PM PST 24
Finished Jan 07 12:27:39 PM PST 24
Peak memory 194052 kb
Host smart-954ff625-0f67-4baf-a1bd-fc960b2a125d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341701303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3341701303
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1710666858
Short name T497
Test name
Test status
Simulation time 63150112 ps
CPU time 0.8 seconds
Started Jan 07 12:23:50 PM PST 24
Finished Jan 07 12:24:00 PM PST 24
Peak memory 196300 kb
Host smart-f8e7406d-73b7-425c-bf21-c91c772256ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710666858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1710666858
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1422023589
Short name T461
Test name
Test status
Simulation time 111512523 ps
CPU time 2.23 seconds
Started Jan 07 12:24:05 PM PST 24
Finished Jan 07 12:24:24 PM PST 24
Peak memory 197916 kb
Host smart-9951f75d-9e02-45ca-975f-9d22bf9ea8e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422023589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1422023589
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.108700061
Short name T92
Test name
Test status
Simulation time 24050756 ps
CPU time 0.63 seconds
Started Jan 07 12:28:10 PM PST 24
Finished Jan 07 12:29:14 PM PST 24
Peak memory 194836 kb
Host smart-d415dca9-2715-4445-a8ad-4de83bbcf150
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108700061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.108700061
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.900795199
Short name T428
Test name
Test status
Simulation time 203999842 ps
CPU time 0.68 seconds
Started Jan 07 12:41:17 PM PST 24
Finished Jan 07 12:42:45 PM PST 24
Peak memory 197288 kb
Host smart-08fbabce-6982-45fd-be61-2a0b69e7b026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900795199 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.900795199
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1615239279
Short name T484
Test name
Test status
Simulation time 13591574 ps
CPU time 0.54 seconds
Started Jan 07 12:28:32 PM PST 24
Finished Jan 07 12:29:36 PM PST 24
Peak memory 195428 kb
Host smart-28b91165-1eb8-417d-86ca-0f99d279d4c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615239279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1615239279
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.326035935
Short name T49
Test name
Test status
Simulation time 13890946 ps
CPU time 0.53 seconds
Started Jan 07 12:28:31 PM PST 24
Finished Jan 07 12:29:32 PM PST 24
Peak memory 184788 kb
Host smart-d37e454e-795f-4eb8-8889-b75cd98d375d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326035935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.326035935
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1225528227
Short name T463
Test name
Test status
Simulation time 57914916 ps
CPU time 2.08 seconds
Started Jan 07 12:31:08 PM PST 24
Finished Jan 07 12:32:43 PM PST 24
Peak memory 199800 kb
Host smart-5f392ccb-b45d-487a-9088-c99ade69259d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225528227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1225528227
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1105998679
Short name T74
Test name
Test status
Simulation time 53094384 ps
CPU time 0.85 seconds
Started Jan 07 12:31:07 PM PST 24
Finished Jan 07 12:32:55 PM PST 24
Peak memory 198308 kb
Host smart-baecb94b-41ad-4423-a990-9ccb64209db8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105998679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1105998679
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.123884192
Short name T431
Test name
Test status
Simulation time 19343946 ps
CPU time 0.53 seconds
Started Jan 07 12:31:16 PM PST 24
Finished Jan 07 12:32:54 PM PST 24
Peak memory 184312 kb
Host smart-b0df2717-d496-4741-850f-d7a9c8dbf265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123884192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.123884192
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.780745224
Short name T472
Test name
Test status
Simulation time 13917797 ps
CPU time 0.56 seconds
Started Jan 07 12:25:24 PM PST 24
Finished Jan 07 12:26:28 PM PST 24
Peak memory 185168 kb
Host smart-80fc9286-c021-4d18-8f3a-f84b52fc9492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780745224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.780745224
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2639641495
Short name T488
Test name
Test status
Simulation time 17516639 ps
CPU time 0.55 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:39 PM PST 24
Peak memory 194080 kb
Host smart-416cb757-c797-4ab7-9a8e-21d46007896c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639641495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2639641495
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3065668275
Short name T473
Test name
Test status
Simulation time 52913584 ps
CPU time 0.61 seconds
Started Jan 07 12:26:12 PM PST 24
Finished Jan 07 12:27:14 PM PST 24
Peak memory 184252 kb
Host smart-81db4cf2-eedb-429c-8bc4-759c0605dbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065668275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3065668275
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1019775342
Short name T442
Test name
Test status
Simulation time 95297613 ps
CPU time 0.55 seconds
Started Jan 07 12:26:29 PM PST 24
Finished Jan 07 12:27:38 PM PST 24
Peak memory 184840 kb
Host smart-2de8dff0-5974-450b-a866-d7b2a60d540f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019775342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1019775342
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4197358247
Short name T418
Test name
Test status
Simulation time 19037770 ps
CPU time 0.54 seconds
Started Jan 07 12:26:27 PM PST 24
Finished Jan 07 12:27:39 PM PST 24
Peak memory 185196 kb
Host smart-20676e06-7654-4218-95c8-0aca07795f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197358247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4197358247
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.781210937
Short name T426
Test name
Test status
Simulation time 20741568 ps
CPU time 0.56 seconds
Started Jan 07 12:32:50 PM PST 24
Finished Jan 07 12:34:06 PM PST 24
Peak memory 194016 kb
Host smart-e50a2605-95fd-42f9-8d02-2b5d450a1faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781210937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.781210937
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3362267639
Short name T440
Test name
Test status
Simulation time 26248353 ps
CPU time 0.57 seconds
Started Jan 07 12:26:32 PM PST 24
Finished Jan 07 12:27:44 PM PST 24
Peak memory 193952 kb
Host smart-6af3a37d-e8a2-439a-ae53-7d7365d384e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362267639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3362267639
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.739578317
Short name T40
Test name
Test status
Simulation time 16144214 ps
CPU time 0.78 seconds
Started Jan 07 12:30:54 PM PST 24
Finished Jan 07 12:32:27 PM PST 24
Peak memory 195260 kb
Host smart-5512785d-ed02-4de8-ac59-6b0b0b3ff85b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739578317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.739578317
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3842372433
Short name T467
Test name
Test status
Simulation time 1294151691 ps
CPU time 2.51 seconds
Started Jan 07 12:26:54 PM PST 24
Finished Jan 07 12:28:14 PM PST 24
Peak memory 197984 kb
Host smart-b53a1fac-0fcb-4ed3-82c1-55d4814168f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842372433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3842372433
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3504308821
Short name T415
Test name
Test status
Simulation time 63484063 ps
CPU time 0.57 seconds
Started Jan 07 12:31:13 PM PST 24
Finished Jan 07 12:32:58 PM PST 24
Peak memory 195168 kb
Host smart-6dea44e0-0afe-41b6-ab73-b0bfdc2cb316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504308821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3504308821
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.359030060
Short name T59
Test name
Test status
Simulation time 17013839 ps
CPU time 0.92 seconds
Started Jan 07 12:27:05 PM PST 24
Finished Jan 07 12:28:23 PM PST 24
Peak memory 199848 kb
Host smart-9016f862-3a7e-4a28-917d-97dbaf372638
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359030060 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.359030060
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3841880940
Short name T67
Test name
Test status
Simulation time 37632682 ps
CPU time 0.61 seconds
Started Jan 07 12:30:54 PM PST 24
Finished Jan 07 12:32:27 PM PST 24
Peak memory 194404 kb
Host smart-8ef84b89-b196-47cc-8ce1-60353eb192fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841880940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3841880940
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2100438108
Short name T433
Test name
Test status
Simulation time 39366042 ps
CPU time 0.54 seconds
Started Jan 07 12:41:49 PM PST 24
Finished Jan 07 12:43:02 PM PST 24
Peak memory 185084 kb
Host smart-cbc0df11-cb2e-4ac5-b8e3-a85bc816cd7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100438108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2100438108
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.378068390
Short name T70
Test name
Test status
Simulation time 31788604 ps
CPU time 0.71 seconds
Started Jan 07 12:25:52 PM PST 24
Finished Jan 07 12:26:55 PM PST 24
Peak memory 197068 kb
Host smart-5fdafa5d-db03-43c6-be9a-021357a7b405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378068390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.378068390
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2525861421
Short name T480
Test name
Test status
Simulation time 161369813 ps
CPU time 1.61 seconds
Started Jan 07 12:31:12 PM PST 24
Finished Jan 07 12:32:55 PM PST 24
Peak memory 199724 kb
Host smart-c590e20c-e9e5-48ce-8bf9-21d1045df505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525861421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2525861421
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3508861156
Short name T478
Test name
Test status
Simulation time 185464898 ps
CPU time 0.99 seconds
Started Jan 07 12:28:33 PM PST 24
Finished Jan 07 12:29:44 PM PST 24
Peak memory 198128 kb
Host smart-0e2be7b1-e33a-4527-94b0-7a526462d18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508861156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3508861156
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3407965511
Short name T422
Test name
Test status
Simulation time 14322790 ps
CPU time 0.55 seconds
Started Jan 07 12:31:20 PM PST 24
Finished Jan 07 12:33:05 PM PST 24
Peak memory 194096 kb
Host smart-62c3ad20-1d80-4a47-91a9-77fe67938da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407965511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3407965511
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1295905381
Short name T452
Test name
Test status
Simulation time 153088587 ps
CPU time 0.54 seconds
Started Jan 07 12:25:51 PM PST 24
Finished Jan 07 12:26:52 PM PST 24
Peak memory 184828 kb
Host smart-847ee676-ff80-4a1e-a1b8-9f7e204e095a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295905381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1295905381
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2912440053
Short name T491
Test name
Test status
Simulation time 17591959 ps
CPU time 0.58 seconds
Started Jan 07 12:26:32 PM PST 24
Finished Jan 07 12:27:43 PM PST 24
Peak memory 184316 kb
Host smart-00dc965d-571b-4942-a461-c8d69a9ca6e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912440053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2912440053
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3502173196
Short name T423
Test name
Test status
Simulation time 81762810 ps
CPU time 0.56 seconds
Started Jan 07 12:25:52 PM PST 24
Finished Jan 07 12:26:55 PM PST 24
Peak memory 184828 kb
Host smart-95bf08c0-8596-4fdf-8888-7840d779ab81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502173196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3502173196
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2250823303
Short name T54
Test name
Test status
Simulation time 18722148 ps
CPU time 0.77 seconds
Started Jan 07 12:23:53 PM PST 24
Finished Jan 07 12:24:08 PM PST 24
Peak memory 183552 kb
Host smart-a4791226-4509-46b0-a732-29f4efdd8d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250823303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2250823303
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.4184110303
Short name T465
Test name
Test status
Simulation time 16273770 ps
CPU time 0.6 seconds
Started Jan 07 12:25:37 PM PST 24
Finished Jan 07 12:26:40 PM PST 24
Peak memory 184076 kb
Host smart-f541cdb7-4923-449a-b4a5-7e6e772703ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184110303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.4184110303
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.441494188
Short name T434
Test name
Test status
Simulation time 12760869 ps
CPU time 0.56 seconds
Started Jan 07 12:26:00 PM PST 24
Finished Jan 07 12:27:01 PM PST 24
Peak memory 185092 kb
Host smart-6d19d718-3b04-4c61-822b-d5744980b88f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441494188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.441494188
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1064476186
Short name T443
Test name
Test status
Simulation time 203571013 ps
CPU time 0.57 seconds
Started Jan 07 12:28:52 PM PST 24
Finished Jan 07 12:30:19 PM PST 24
Peak memory 184376 kb
Host smart-e6eb7d33-6a16-47f2-8ae3-0c6b3d76b089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064476186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1064476186
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3198428820
Short name T65
Test name
Test status
Simulation time 26959102 ps
CPU time 0.59 seconds
Started Jan 07 12:30:57 PM PST 24
Finished Jan 07 12:33:15 PM PST 24
Peak memory 195160 kb
Host smart-00d87427-e58f-4f9b-b6f2-155d5f7feae5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198428820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3198428820
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3839367808
Short name T447
Test name
Test status
Simulation time 46366561 ps
CPU time 0.54 seconds
Started Jan 07 12:34:15 PM PST 24
Finished Jan 07 12:35:36 PM PST 24
Peak memory 194092 kb
Host smart-0d5b969c-e1be-440f-909f-d6e993fd290a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839367808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3839367808
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3672100839
Short name T451
Test name
Test status
Simulation time 24941344 ps
CPU time 1.27 seconds
Started Jan 07 12:25:46 PM PST 24
Finished Jan 07 12:26:48 PM PST 24
Peak memory 199956 kb
Host smart-ad7bbbc4-799b-4341-8d90-cb8c1682be06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672100839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3672100839
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.55944633
Short name T48
Test name
Test status
Simulation time 52581366 ps
CPU time 0.72 seconds
Started Jan 07 12:25:37 PM PST 24
Finished Jan 07 12:26:40 PM PST 24
Peak memory 197668 kb
Host smart-866fa899-8678-49f3-94b9-ff64bcdd4a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55944633 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.55944633
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1796265381
Short name T445
Test name
Test status
Simulation time 11328922 ps
CPU time 0.54 seconds
Started Jan 07 12:31:27 PM PST 24
Finished Jan 07 12:33:05 PM PST 24
Peak memory 184092 kb
Host smart-9b92aa20-f160-4b31-a470-3ac9e9606ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796265381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1796265381
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2105544655
Short name T439
Test name
Test status
Simulation time 30648496 ps
CPU time 0.78 seconds
Started Jan 07 12:25:13 PM PST 24
Finished Jan 07 12:26:20 PM PST 24
Peak memory 197004 kb
Host smart-61b2ba41-dfd3-4f70-82a5-6fd6dc286603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105544655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2105544655
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1623894932
Short name T460
Test name
Test status
Simulation time 205332449 ps
CPU time 1.77 seconds
Started Jan 07 12:41:42 PM PST 24
Finished Jan 07 12:43:16 PM PST 24
Peak memory 199956 kb
Host smart-a48751ba-d408-4b49-8792-a430ca1d3b54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623894932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1623894932
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.168457870
Short name T76
Test name
Test status
Simulation time 196391922 ps
CPU time 0.9 seconds
Started Jan 07 12:27:53 PM PST 24
Finished Jan 07 12:29:03 PM PST 24
Peak memory 198896 kb
Host smart-77577e75-1f92-4885-bf31-50f310db28ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168457870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.168457870
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3058924465
Short name T496
Test name
Test status
Simulation time 50806062 ps
CPU time 0.61 seconds
Started Jan 07 12:31:19 PM PST 24
Finished Jan 07 12:32:47 PM PST 24
Peak memory 194996 kb
Host smart-821fe4b3-bbc4-4e81-b428-9b952a677f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058924465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3058924465
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2729463273
Short name T456
Test name
Test status
Simulation time 24253811 ps
CPU time 0.57 seconds
Started Jan 07 12:25:37 PM PST 24
Finished Jan 07 12:26:40 PM PST 24
Peak memory 183436 kb
Host smart-3a4db88a-9fb7-4db3-bf29-e3e17336e389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729463273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2729463273
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3842619247
Short name T462
Test name
Test status
Simulation time 66284000 ps
CPU time 0.62 seconds
Started Jan 07 12:30:54 PM PST 24
Finished Jan 07 12:32:30 PM PST 24
Peak memory 195180 kb
Host smart-7f1cc004-9830-4e78-bac7-72bf9580f223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842619247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3842619247
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1096593443
Short name T421
Test name
Test status
Simulation time 46594821 ps
CPU time 2.02 seconds
Started Jan 07 12:26:32 PM PST 24
Finished Jan 07 12:27:46 PM PST 24
Peak memory 199604 kb
Host smart-67911d8a-9706-45da-a95c-fb7f78ce4d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096593443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1096593443
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1896501535
Short name T482
Test name
Test status
Simulation time 50344312 ps
CPU time 0.81 seconds
Started Jan 07 12:32:50 PM PST 24
Finished Jan 07 12:34:02 PM PST 24
Peak memory 198236 kb
Host smart-f51ffdb4-f876-4872-b40c-89892ad29f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896501535 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1896501535
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.497188498
Short name T44
Test name
Test status
Simulation time 57649043 ps
CPU time 0.6 seconds
Started Jan 07 12:26:39 PM PST 24
Finished Jan 07 12:27:56 PM PST 24
Peak memory 195408 kb
Host smart-42c9c5fe-bba2-4db3-9b9f-71d7d94593d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497188498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.497188498
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4199527371
Short name T474
Test name
Test status
Simulation time 127881972 ps
CPU time 0.72 seconds
Started Jan 07 12:32:14 PM PST 24
Finished Jan 07 12:33:46 PM PST 24
Peak memory 197420 kb
Host smart-d7e99507-11f0-4091-9831-bbfbe40e8945
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199527371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4199527371
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1521589366
Short name T429
Test name
Test status
Simulation time 271501717 ps
CPU time 1.77 seconds
Started Jan 07 12:25:38 PM PST 24
Finished Jan 07 12:26:40 PM PST 24
Peak memory 199256 kb
Host smart-434533b1-e7dd-4ec3-806a-f2ca2cd0ab28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521589366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1521589366
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.314936073
Short name T80
Test name
Test status
Simulation time 68086431 ps
CPU time 1.22 seconds
Started Jan 07 12:25:37 PM PST 24
Finished Jan 07 12:26:41 PM PST 24
Peak memory 197496 kb
Host smart-424f960b-cc66-4ac2-b395-318614e80834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314936073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.314936073
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3811081910
Short name T424
Test name
Test status
Simulation time 15277942 ps
CPU time 0.58 seconds
Started Jan 07 12:32:21 PM PST 24
Finished Jan 07 12:34:04 PM PST 24
Peak memory 195200 kb
Host smart-947b7cf7-b3b8-4eb3-8bba-03d3b0271ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811081910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3811081910
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.691807446
Short name T450
Test name
Test status
Simulation time 50990630 ps
CPU time 0.63 seconds
Started Jan 07 12:29:21 PM PST 24
Finished Jan 07 12:30:45 PM PST 24
Peak memory 194560 kb
Host smart-36de875c-522b-4e0c-869a-0e91eda15afc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691807446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.691807446
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1490969970
Short name T27
Test name
Test status
Simulation time 306041959 ps
CPU time 0.99 seconds
Started Jan 07 12:32:50 PM PST 24
Finished Jan 07 12:34:02 PM PST 24
Peak memory 198052 kb
Host smart-f5766b79-415e-44f1-a2d4-7f59661761e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490969970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1490969970
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2267501347
Short name T704
Test name
Test status
Simulation time 39239654 ps
CPU time 0.54 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 12:55:30 PM PST 24
Peak memory 195508 kb
Host smart-38e52ac2-477e-4415-b7e3-5f28c3e3287c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267501347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2267501347
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.39229463
Short name T351
Test name
Test status
Simulation time 70781957621 ps
CPU time 113.11 seconds
Started Jan 07 12:53:02 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 199976 kb
Host smart-a032724b-8347-4ab9-83f6-b3c2dda1b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39229463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.39229463
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1996043389
Short name T642
Test name
Test status
Simulation time 157658671950 ps
CPU time 752.99 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 01:08:13 PM PST 24
Peak memory 200136 kb
Host smart-71d68f8b-6cee-4cb6-aeea-587ade765845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1996043389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1996043389
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2779476211
Short name T823
Test name
Test status
Simulation time 7667300835 ps
CPU time 6.14 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 12:54:45 PM PST 24
Peak memory 199656 kb
Host smart-8118d22b-79f9-45a1-af1b-c26e78a7b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779476211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2779476211
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.4129952491
Short name T692
Test name
Test status
Simulation time 2285549224 ps
CPU time 4.09 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:39 PM PST 24
Peak memory 198240 kb
Host smart-478f7d17-7687-4b03-aa46-a6b888490934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129952491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.4129952491
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1490444021
Short name T864
Test name
Test status
Simulation time 3704961611 ps
CPU time 4.2 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:32 PM PST 24
Peak memory 196020 kb
Host smart-6727a59c-c591-4c07-a0c8-4037d61af488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490444021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1490444021
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3863032348
Short name T618
Test name
Test status
Simulation time 5690714303 ps
CPU time 23.27 seconds
Started Jan 07 12:53:02 PM PST 24
Finished Jan 07 12:54:38 PM PST 24
Peak memory 199492 kb
Host smart-7a1980d3-171c-4e07-8898-e09cc3b7854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863032348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3863032348
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1602740589
Short name T556
Test name
Test status
Simulation time 1330262656 ps
CPU time 2.13 seconds
Started Jan 07 12:53:08 PM PST 24
Finished Jan 07 12:54:31 PM PST 24
Peak memory 198144 kb
Host smart-948859c3-ab2e-46c3-a408-14364677cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602740589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1602740589
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.985390019
Short name T338
Test name
Test status
Simulation time 127153681080 ps
CPU time 55.11 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 12:55:41 PM PST 24
Peak memory 200064 kb
Host smart-e3ffce7a-4d01-468d-b52b-dc448e66ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985390019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.985390019
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.435829648
Short name T784
Test name
Test status
Simulation time 18240479003 ps
CPU time 40.22 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 12:55:34 PM PST 24
Peak memory 200104 kb
Host smart-b05f9b55-e5df-4737-b512-21e8c9f0283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435829648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.435829648
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2478025739
Short name T767
Test name
Test status
Simulation time 51427411930 ps
CPU time 121.66 seconds
Started Jan 07 12:53:41 PM PST 24
Finished Jan 07 12:57:21 PM PST 24
Peak memory 200220 kb
Host smart-165a15d2-125a-4a38-96d4-a4df3e575613
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478025739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2478025739
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3037647467
Short name T771
Test name
Test status
Simulation time 115408545897 ps
CPU time 44.98 seconds
Started Jan 07 12:54:04 PM PST 24
Finished Jan 07 12:56:25 PM PST 24
Peak memory 208356 kb
Host smart-635932ac-768b-4a19-9d34-82665a66bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037647467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3037647467
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2501296099
Short name T983
Test name
Test status
Simulation time 11876469973 ps
CPU time 622.12 seconds
Started Jan 07 12:53:39 PM PST 24
Finished Jan 07 01:05:19 PM PST 24
Peak memory 200176 kb
Host smart-43065bef-bc4b-4d03-8153-975d3510bf09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501296099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2501296099
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2057249246
Short name T408
Test name
Test status
Simulation time 3577249939 ps
CPU time 9.26 seconds
Started Jan 07 12:53:41 PM PST 24
Finished Jan 07 12:55:02 PM PST 24
Peak memory 198596 kb
Host smart-8bac246a-a72a-4dcf-a193-48a7072f360e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057249246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2057249246
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2833926152
Short name T885
Test name
Test status
Simulation time 46765201177 ps
CPU time 22.22 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:55:16 PM PST 24
Peak memory 195656 kb
Host smart-a6065b63-3d7d-4938-b457-716650fe82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833926152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2833926152
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2198931832
Short name T72
Test name
Test status
Simulation time 85159688 ps
CPU time 0.88 seconds
Started Jan 07 12:54:11 PM PST 24
Finished Jan 07 12:56:37 PM PST 24
Peak memory 218696 kb
Host smart-e9abf196-82e6-4680-af32-daba8bf5f491
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198931832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2198931832
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.432978351
Short name T601
Test name
Test status
Simulation time 5957643544 ps
CPU time 9.83 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:55:08 PM PST 24
Peak memory 199600 kb
Host smart-35c61675-91e0-48b5-80da-3529c2f1ceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432978351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.432978351
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3769049789
Short name T747
Test name
Test status
Simulation time 648646115 ps
CPU time 1.13 seconds
Started Jan 07 12:53:46 PM PST 24
Finished Jan 07 12:55:08 PM PST 24
Peak memory 199000 kb
Host smart-46dfd6fa-bae6-4bdc-b64c-9c9cf348044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769049789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3769049789
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.298268097
Short name T872
Test name
Test status
Simulation time 66281970379 ps
CPU time 29.78 seconds
Started Jan 07 12:53:14 PM PST 24
Finished Jan 07 12:55:16 PM PST 24
Peak memory 200204 kb
Host smart-0e2bdf96-06fb-4312-89ca-dd006eacc115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298268097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.298268097
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3141068070
Short name T787
Test name
Test status
Simulation time 20806098 ps
CPU time 0.54 seconds
Started Jan 07 12:53:04 PM PST 24
Finished Jan 07 12:54:16 PM PST 24
Peak memory 195576 kb
Host smart-eb0aa1ca-33d1-4df2-bd93-36f6fb033341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141068070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3141068070
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3247547089
Short name T753
Test name
Test status
Simulation time 407133797246 ps
CPU time 50.16 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:57:17 PM PST 24
Peak memory 200164 kb
Host smart-2bcca144-42a4-4ddd-bf00-a7cd2de7f46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247547089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3247547089
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.44223265
Short name T294
Test name
Test status
Simulation time 21037308355 ps
CPU time 32.76 seconds
Started Jan 07 12:54:36 PM PST 24
Finished Jan 07 12:56:26 PM PST 24
Peak memory 200192 kb
Host smart-c744c644-5361-4040-aa2a-87d030b68e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44223265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.44223265
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3033806515
Short name T605
Test name
Test status
Simulation time 276588256304 ps
CPU time 436.44 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 01:02:50 PM PST 24
Peak memory 197064 kb
Host smart-d9e2c58b-a34c-42db-96e8-f81efc3387ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033806515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3033806515
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3375519212
Short name T992
Test name
Test status
Simulation time 139903986474 ps
CPU time 795.5 seconds
Started Jan 07 12:53:07 PM PST 24
Finished Jan 07 01:07:42 PM PST 24
Peak memory 200124 kb
Host smart-0045a9ba-5ea8-493d-8c8e-d7bcbbb75cdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375519212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3375519212
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3447687376
Short name T1035
Test name
Test status
Simulation time 12593470356 ps
CPU time 27.6 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 12:55:35 PM PST 24
Peak memory 199576 kb
Host smart-7143f81c-b847-407a-9b1f-c30964c341b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447687376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3447687376
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1738907489
Short name T574
Test name
Test status
Simulation time 105879490310 ps
CPU time 38.22 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:55:40 PM PST 24
Peak memory 198932 kb
Host smart-83a71814-9f42-44d3-a699-f9658da0e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738907489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1738907489
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1190547786
Short name T573
Test name
Test status
Simulation time 18843100402 ps
CPU time 962.25 seconds
Started Jan 07 12:54:00 PM PST 24
Finished Jan 07 01:11:41 PM PST 24
Peak memory 200136 kb
Host smart-609154e8-849b-44cd-8481-d41fdd2b77be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190547786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1190547786
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2983166785
Short name T631
Test name
Test status
Simulation time 1844692634 ps
CPU time 2.09 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:55:31 PM PST 24
Peak memory 195580 kb
Host smart-49cbb4b6-2ece-4829-b2bd-6d093a52c65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983166785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2983166785
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3142470226
Short name T1036
Test name
Test status
Simulation time 500367191 ps
CPU time 1.96 seconds
Started Jan 07 12:53:44 PM PST 24
Finished Jan 07 12:55:06 PM PST 24
Peak memory 197916 kb
Host smart-02d4e340-fc23-4117-b86d-591412cacb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142470226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3142470226
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3578771691
Short name T997
Test name
Test status
Simulation time 20143587085 ps
CPU time 225.03 seconds
Started Jan 07 12:53:02 PM PST 24
Finished Jan 07 12:57:57 PM PST 24
Peak memory 216492 kb
Host smart-6d07f13c-dd94-4274-ae05-4309163bc0e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578771691 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3578771691
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4044643354
Short name T30
Test name
Test status
Simulation time 286028993781 ps
CPU time 410.65 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 01:04:03 PM PST 24
Peak memory 200132 kb
Host smart-bc9d0b7e-026b-47bb-801b-0deb6874683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044643354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4044643354
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3635104795
Short name T603
Test name
Test status
Simulation time 39719486 ps
CPU time 0.56 seconds
Started Jan 07 12:53:10 PM PST 24
Finished Jan 07 12:54:27 PM PST 24
Peak memory 195156 kb
Host smart-3b8757a6-1044-463f-88d7-3abc74cc95dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635104795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3635104795
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3958914957
Short name T627
Test name
Test status
Simulation time 67442715640 ps
CPU time 26.95 seconds
Started Jan 07 12:52:52 PM PST 24
Finished Jan 07 12:54:36 PM PST 24
Peak memory 199608 kb
Host smart-2d3e93d0-115c-4393-8f1d-e8bf633e2ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958914957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3958914957
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2950940898
Short name T330
Test name
Test status
Simulation time 12303595583 ps
CPU time 6.47 seconds
Started Jan 07 12:53:23 PM PST 24
Finished Jan 07 12:55:00 PM PST 24
Peak memory 199528 kb
Host smart-1a755771-a481-4e25-bb6f-ce93f7a7f589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950940898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2950940898
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2945796201
Short name T653
Test name
Test status
Simulation time 71926644319 ps
CPU time 33.08 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:55:25 PM PST 24
Peak memory 198704 kb
Host smart-c126bc41-1bf1-4c8c-8120-cf20e10c2540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945796201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2945796201
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.495119784
Short name T755
Test name
Test status
Simulation time 125915181546 ps
CPU time 1172.03 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 01:14:16 PM PST 24
Peak memory 200212 kb
Host smart-293c136c-09ab-4b4a-a4fe-3b2563af39ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495119784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.495119784
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3964652390
Short name T941
Test name
Test status
Simulation time 55950234332 ps
CPU time 45.54 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 12:55:35 PM PST 24
Peak memory 199812 kb
Host smart-3132ba45-b496-4686-b8f7-bcf20db2df02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964652390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3964652390
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2025485987
Short name T715
Test name
Test status
Simulation time 4357433825 ps
CPU time 12.73 seconds
Started Jan 07 12:53:18 PM PST 24
Finished Jan 07 12:54:40 PM PST 24
Peak memory 198960 kb
Host smart-84d8c0f9-6c41-4051-b8fb-cbcb3a8d45b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025485987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2025485987
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2969401452
Short name T254
Test name
Test status
Simulation time 94783101051 ps
CPU time 164.98 seconds
Started Jan 07 12:53:38 PM PST 24
Finished Jan 07 12:57:35 PM PST 24
Peak memory 200200 kb
Host smart-f7299469-c845-4f69-94f0-ee799b24bd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969401452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2969401452
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.721432847
Short name T1020
Test name
Test status
Simulation time 42712705064 ps
CPU time 30.09 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 12:55:09 PM PST 24
Peak memory 196080 kb
Host smart-a2ac8d12-2e23-4de8-86da-ab2cbb8519a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721432847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.721432847
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1712687992
Short name T372
Test name
Test status
Simulation time 743354760 ps
CPU time 1.31 seconds
Started Jan 07 12:53:08 PM PST 24
Finished Jan 07 12:54:27 PM PST 24
Peak memory 198956 kb
Host smart-c7c6f3d9-5f8f-422d-92eb-d0cbccb259fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712687992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1712687992
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1781205927
Short name T301
Test name
Test status
Simulation time 2931309240742 ps
CPU time 1121.75 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 01:13:20 PM PST 24
Peak memory 216412 kb
Host smart-6c7c33d0-bb0c-41c1-9daf-94c0e903f125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781205927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1781205927
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2063902842
Short name T510
Test name
Test status
Simulation time 7127744439 ps
CPU time 19.46 seconds
Started Jan 07 12:53:12 PM PST 24
Finished Jan 07 12:54:42 PM PST 24
Peak memory 199404 kb
Host smart-95f061ac-a788-4266-8072-8d309eb88cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063902842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2063902842
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3272421872
Short name T765
Test name
Test status
Simulation time 11641847845 ps
CPU time 16.73 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:43 PM PST 24
Peak memory 197040 kb
Host smart-9e43d3d3-6136-4c82-a383-48ed57a350d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272421872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3272421872
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3355822860
Short name T89
Test name
Test status
Simulation time 92168224222 ps
CPU time 80.88 seconds
Started Jan 07 12:55:19 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 200156 kb
Host smart-acdf9412-9a67-4a29-a274-eb968a3e565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355822860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3355822860
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1855442337
Short name T154
Test name
Test status
Simulation time 83648350583 ps
CPU time 137.3 seconds
Started Jan 07 12:55:16 PM PST 24
Finished Jan 07 12:59:42 PM PST 24
Peak memory 200208 kb
Host smart-9513e92e-4bb7-4535-821b-157622d63a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855442337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1855442337
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1968058178
Short name T967
Test name
Test status
Simulation time 38431998213 ps
CPU time 17.71 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:57:17 PM PST 24
Peak memory 199468 kb
Host smart-3360b6de-145e-4bf6-bf8a-3fdc92147e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968058178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1968058178
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1403171424
Short name T277
Test name
Test status
Simulation time 46394026098 ps
CPU time 20.11 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:56:53 PM PST 24
Peak memory 199456 kb
Host smart-527d7a16-b8db-473a-b959-b0abe1fe5d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403171424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1403171424
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.658718666
Short name T86
Test name
Test status
Simulation time 19673087769 ps
CPU time 31.05 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 199192 kb
Host smart-ef5f20b6-9b25-44e6-a61f-726bbf7c23fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658718666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.658718666
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.561242866
Short name T124
Test name
Test status
Simulation time 72629979856 ps
CPU time 121.4 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:59:03 PM PST 24
Peak memory 200116 kb
Host smart-9ae972a0-1360-47fe-87f8-1e23f2ea1e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561242866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.561242866
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1576348255
Short name T919
Test name
Test status
Simulation time 210473623732 ps
CPU time 77.12 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 200188 kb
Host smart-7f506d7f-967b-440b-b3d6-37f6ddd3bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576348255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1576348255
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3394196955
Short name T7
Test name
Test status
Simulation time 35413101871 ps
CPU time 16.98 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:56:56 PM PST 24
Peak memory 198620 kb
Host smart-890e7b65-e9e9-4367-9452-911acae9527f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394196955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3394196955
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.739072291
Short name T811
Test name
Test status
Simulation time 65432568026 ps
CPU time 116.09 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:58:55 PM PST 24
Peak memory 200152 kb
Host smart-ec2126ca-440e-4018-a456-5af54add0de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739072291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.739072291
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2440153107
Short name T523
Test name
Test status
Simulation time 13313414 ps
CPU time 0.55 seconds
Started Jan 07 12:53:35 PM PST 24
Finished Jan 07 12:55:27 PM PST 24
Peak memory 195516 kb
Host smart-260a9670-4bf1-4015-8bae-9d66053e40f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440153107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2440153107
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2404005479
Short name T170
Test name
Test status
Simulation time 52549192334 ps
CPU time 20.89 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 12:54:59 PM PST 24
Peak memory 200116 kb
Host smart-0efc4bf9-d6fc-4272-ac5b-91117a27abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404005479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2404005479
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2035703581
Short name T250
Test name
Test status
Simulation time 69090654256 ps
CPU time 100.06 seconds
Started Jan 07 12:53:15 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 199972 kb
Host smart-d05b61a7-e1cf-430f-958e-7703e826f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035703581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2035703581
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3565584438
Short name T147
Test name
Test status
Simulation time 26493103016 ps
CPU time 29.73 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:09 PM PST 24
Peak memory 200100 kb
Host smart-5f03a827-8812-4e2b-822c-3ef3c1de60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565584438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3565584438
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.579537951
Short name T127
Test name
Test status
Simulation time 55516396153 ps
CPU time 75.29 seconds
Started Jan 07 12:53:26 PM PST 24
Finished Jan 07 12:56:03 PM PST 24
Peak memory 200116 kb
Host smart-24953500-3dc6-4c48-9596-6a0e3c21dc15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579537951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.579537951
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2281779334
Short name T385
Test name
Test status
Simulation time 35329475339 ps
CPU time 206.72 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:58:09 PM PST 24
Peak memory 200188 kb
Host smart-d1846d86-d1c1-4e5f-bbfc-7ea0a50293c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281779334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2281779334
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1984827329
Short name T661
Test name
Test status
Simulation time 51409706011 ps
CPU time 76.4 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:56:21 PM PST 24
Peak memory 200492 kb
Host smart-5fc31295-4ffe-47c7-a14f-8ae38fc309a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984827329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1984827329
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2037030945
Short name T547
Test name
Test status
Simulation time 2530019979 ps
CPU time 21.28 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 12:55:21 PM PST 24
Peak memory 198560 kb
Host smart-6c388551-c93c-467e-bb53-9615799fa34a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037030945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2037030945
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_smoke.1636111261
Short name T793
Test name
Test status
Simulation time 722441624 ps
CPU time 1.94 seconds
Started Jan 07 12:53:32 PM PST 24
Finished Jan 07 12:54:53 PM PST 24
Peak memory 198580 kb
Host smart-e46fc57a-6d83-4a02-9ad5-3ae2b1f9e5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636111261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1636111261
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1810171498
Short name T256
Test name
Test status
Simulation time 277309641524 ps
CPU time 695.17 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 01:06:14 PM PST 24
Peak memory 200192 kb
Host smart-d0c4151a-d73b-4620-bc7c-4892cc75c1f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810171498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1810171498
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1670238878
Short name T231
Test name
Test status
Simulation time 120420038603 ps
CPU time 683.73 seconds
Started Jan 07 12:53:22 PM PST 24
Finished Jan 07 01:06:18 PM PST 24
Peak memory 225088 kb
Host smart-0d51cfe4-221f-41f8-a560-8b920873a22f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670238878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1670238878
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.453027075
Short name T862
Test name
Test status
Simulation time 7001698292 ps
CPU time 10.51 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 12:54:50 PM PST 24
Peak memory 199516 kb
Host smart-34accd32-9022-45a2-9a6b-bb1b051e14a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453027075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.453027075
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1336277852
Short name T972
Test name
Test status
Simulation time 133113015509 ps
CPU time 49.6 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:55:59 PM PST 24
Peak memory 200188 kb
Host smart-b8aeedad-337a-4583-818d-b824a0f0cb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336277852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1336277852
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3978958388
Short name T732
Test name
Test status
Simulation time 23767717929 ps
CPU time 41.14 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 200168 kb
Host smart-2c3263ae-b4c1-4953-934b-6a379782da71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978958388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3978958388
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1827506481
Short name T102
Test name
Test status
Simulation time 19534668028 ps
CPU time 12.61 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:56:59 PM PST 24
Peak memory 199820 kb
Host smart-f6d690a1-eaee-4581-afc4-97d796e0d4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827506481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1827506481
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1775832031
Short name T113
Test name
Test status
Simulation time 101413215702 ps
CPU time 12.41 seconds
Started Jan 07 12:55:09 PM PST 24
Finished Jan 07 12:57:03 PM PST 24
Peak memory 198604 kb
Host smart-293b5b2d-3a52-4459-bb25-e8106b78adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775832031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1775832031
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2133870685
Short name T896
Test name
Test status
Simulation time 33861976006 ps
CPU time 54.99 seconds
Started Jan 07 12:54:53 PM PST 24
Finished Jan 07 12:57:12 PM PST 24
Peak memory 200152 kb
Host smart-87e29cc1-7d35-4df6-83e6-857e2dd990ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133870685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2133870685
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2689690295
Short name T762
Test name
Test status
Simulation time 12987651 ps
CPU time 0.58 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 12:54:31 PM PST 24
Peak memory 194536 kb
Host smart-65c92931-185b-4b89-9199-11878b9a039e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689690295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2689690295
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3549236487
Short name T792
Test name
Test status
Simulation time 67990342753 ps
CPU time 28.67 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:55:18 PM PST 24
Peak memory 200108 kb
Host smart-481acb3c-a5e8-4612-a3d3-4beb16cc33bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549236487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3549236487
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2787916333
Short name T706
Test name
Test status
Simulation time 5193653057 ps
CPU time 9.65 seconds
Started Jan 07 12:53:45 PM PST 24
Finished Jan 07 12:55:42 PM PST 24
Peak memory 199620 kb
Host smart-5d0ce0f0-d488-4090-8e26-c5391e94070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787916333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2787916333
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.4055322891
Short name T617
Test name
Test status
Simulation time 285383281340 ps
CPU time 289.52 seconds
Started Jan 07 12:54:28 PM PST 24
Finished Jan 07 01:01:06 PM PST 24
Peak memory 200124 kb
Host smart-01e25ad8-b7a3-4cb3-8451-9e945817ca0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055322891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.4055322891
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_loopback.1993202487
Short name T404
Test name
Test status
Simulation time 4265591714 ps
CPU time 4.04 seconds
Started Jan 07 12:53:16 PM PST 24
Finished Jan 07 12:54:54 PM PST 24
Peak memory 197128 kb
Host smart-4a1e5492-9830-41f2-b60f-d0f3d5d1d530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993202487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1993202487
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3812496363
Short name T625
Test name
Test status
Simulation time 35080027909 ps
CPU time 57.23 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 12:56:17 PM PST 24
Peak memory 199772 kb
Host smart-26a0ea09-26dc-468c-b3f6-c2ef17e2a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812496363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3812496363
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.453923832
Short name T1010
Test name
Test status
Simulation time 20258335153 ps
CPU time 513.59 seconds
Started Jan 07 12:53:45 PM PST 24
Finished Jan 07 01:03:43 PM PST 24
Peak memory 200152 kb
Host smart-81959e96-8c60-4813-accc-cf2f7b3e3293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453923832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.453923832
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.82691893
Short name T623
Test name
Test status
Simulation time 1633885810 ps
CPU time 4.6 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:55:27 PM PST 24
Peak memory 198432 kb
Host smart-fe7c5932-1b07-4b28-8722-5706351125f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82691893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.82691893
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1522022484
Short name T980
Test name
Test status
Simulation time 49054544224 ps
CPU time 358.83 seconds
Started Jan 07 12:53:16 PM PST 24
Finished Jan 07 01:00:28 PM PST 24
Peak memory 216152 kb
Host smart-4db6ac07-f961-4434-b184-a99056c14790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522022484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1522022484
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1620249331
Short name T914
Test name
Test status
Simulation time 688421771 ps
CPU time 2.33 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:31 PM PST 24
Peak memory 198440 kb
Host smart-c4700a83-353a-4cea-b5e5-4f001318a71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620249331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1620249331
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4278746845
Short name T650
Test name
Test status
Simulation time 250362434833 ps
CPU time 60.15 seconds
Started Jan 07 12:53:48 PM PST 24
Finished Jan 07 12:56:06 PM PST 24
Peak memory 200124 kb
Host smart-d27bb1cc-80d1-4b54-af9e-107ba6f08e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278746845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4278746845
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1371708838
Short name T243
Test name
Test status
Simulation time 102829058838 ps
CPU time 159.83 seconds
Started Jan 07 12:55:26 PM PST 24
Finished Jan 07 01:00:02 PM PST 24
Peak memory 200188 kb
Host smart-38851fdb-5fe3-4e4b-971d-9cf05c2ddd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371708838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1371708838
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3800665637
Short name T157
Test name
Test status
Simulation time 64453849209 ps
CPU time 62.37 seconds
Started Jan 07 12:55:30 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 199948 kb
Host smart-69222b49-c5b5-497a-9aed-e5b852809aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800665637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3800665637
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.76261056
Short name T150
Test name
Test status
Simulation time 39495878284 ps
CPU time 37.05 seconds
Started Jan 07 12:55:34 PM PST 24
Finished Jan 07 12:57:27 PM PST 24
Peak memory 200168 kb
Host smart-831ed08f-ae9e-4d41-8982-8856e8d753d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76261056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.76261056
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2231005812
Short name T674
Test name
Test status
Simulation time 123836599536 ps
CPU time 94.27 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:58:07 PM PST 24
Peak memory 199892 kb
Host smart-58f6e1bd-912b-45e9-bf17-60fd9244cfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231005812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2231005812
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3609445233
Short name T152
Test name
Test status
Simulation time 12806220963 ps
CPU time 20.77 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 12:56:47 PM PST 24
Peak memory 200076 kb
Host smart-b7086b41-354e-472d-afaa-a8b37d7827c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609445233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3609445233
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.975801067
Short name T214
Test name
Test status
Simulation time 53114604901 ps
CPU time 18.51 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 12:56:54 PM PST 24
Peak memory 199976 kb
Host smart-d4940eb6-2b93-4ff0-8996-2db7bb30f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975801067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.975801067
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.116097064
Short name T549
Test name
Test status
Simulation time 33374404 ps
CPU time 0.55 seconds
Started Jan 07 12:53:12 PM PST 24
Finished Jan 07 12:54:23 PM PST 24
Peak memory 195576 kb
Host smart-b1d77575-dc6e-4ab1-b15b-b204e3435146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116097064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.116097064
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3520290566
Short name T1025
Test name
Test status
Simulation time 132165604889 ps
CPU time 68.61 seconds
Started Jan 07 12:53:46 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 200164 kb
Host smart-1a31629d-0dda-4bbd-b94c-ed8e4601aa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520290566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3520290566
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3593517485
Short name T142
Test name
Test status
Simulation time 50835121069 ps
CPU time 84.35 seconds
Started Jan 07 12:53:12 PM PST 24
Finished Jan 07 12:55:46 PM PST 24
Peak memory 199864 kb
Host smart-6851877c-70c3-48b5-928a-03f94c9c9bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593517485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3593517485
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1221499791
Short name T973
Test name
Test status
Simulation time 161045382194 ps
CPU time 40.7 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:55:12 PM PST 24
Peak memory 200052 kb
Host smart-db835d42-bcb3-44f7-b3fe-535e90cad6ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221499791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1221499791
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_loopback.4087006240
Short name T527
Test name
Test status
Simulation time 3523638647 ps
CPU time 6.77 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 12:54:39 PM PST 24
Peak memory 197404 kb
Host smart-ebd7ae99-4219-45cf-a5d8-5e4b9f0f0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087006240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.4087006240
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1471300195
Short name T193
Test name
Test status
Simulation time 25656387416 ps
CPU time 41.39 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 12:55:12 PM PST 24
Peak memory 199076 kb
Host smart-ac274e76-0b58-4ff6-8831-70395b9fa908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471300195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1471300195
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.13603324
Short name T357
Test name
Test status
Simulation time 16477428879 ps
CPU time 822.37 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 01:08:02 PM PST 24
Peak memory 200128 kb
Host smart-82aecb6f-2b3b-48d4-86cf-23b36448fa24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13603324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.13603324
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2562721810
Short name T1006
Test name
Test status
Simulation time 3610205330 ps
CPU time 6.91 seconds
Started Jan 07 12:53:07 PM PST 24
Finished Jan 07 12:54:33 PM PST 24
Peak memory 198608 kb
Host smart-c04dd963-7a59-4316-81c5-e5a917e70d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562721810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2562721810
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3495392536
Short name T1041
Test name
Test status
Simulation time 65384868141 ps
CPU time 15.99 seconds
Started Jan 07 12:53:37 PM PST 24
Finished Jan 07 12:55:18 PM PST 24
Peak memory 199556 kb
Host smart-365bf78f-d49c-4198-be01-1940dff8df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495392536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3495392536
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_smoke.645558456
Short name T621
Test name
Test status
Simulation time 692470590 ps
CPU time 2.2 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:31 PM PST 24
Peak memory 198592 kb
Host smart-d8d39c16-966b-4f75-8aac-0129a979fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645558456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.645558456
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.751805519
Short name T677
Test name
Test status
Simulation time 816987274 ps
CPU time 3.6 seconds
Started Jan 07 12:53:10 PM PST 24
Finished Jan 07 12:54:23 PM PST 24
Peak memory 198884 kb
Host smart-52118e17-41b4-4017-9b42-db3b0ca97b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751805519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.751805519
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3776457607
Short name T664
Test name
Test status
Simulation time 36721130007 ps
CPU time 11.64 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 12:54:44 PM PST 24
Peak memory 200032 kb
Host smart-d0fff138-9e25-461f-942f-1072d27917ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776457607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3776457607
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3172104418
Short name T937
Test name
Test status
Simulation time 12258528588 ps
CPU time 10.52 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 200176 kb
Host smart-4d721868-eb82-48ef-be4f-fbc2bb28a64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172104418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3172104418
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.4262479884
Short name T645
Test name
Test status
Simulation time 89629012634 ps
CPU time 66.1 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 12:57:36 PM PST 24
Peak memory 200112 kb
Host smart-668f0704-705c-4671-ab3a-fe06bc481348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262479884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4262479884
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.696482406
Short name T635
Test name
Test status
Simulation time 100597038691 ps
CPU time 24.05 seconds
Started Jan 07 12:55:36 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 200124 kb
Host smart-c5ba2e39-5efb-4c13-b76f-ca63f967e4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696482406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.696482406
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2628762278
Short name T279
Test name
Test status
Simulation time 27006855918 ps
CPU time 22.93 seconds
Started Jan 07 12:55:31 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 199964 kb
Host smart-18232491-54ec-4d1f-89d6-0e87a2bd8b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628762278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2628762278
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1707342655
Short name T780
Test name
Test status
Simulation time 21208092153 ps
CPU time 13.18 seconds
Started Jan 07 12:55:30 PM PST 24
Finished Jan 07 12:57:01 PM PST 24
Peak memory 198948 kb
Host smart-6ec0aac7-e178-441d-a456-13f34010068b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707342655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1707342655
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.363748865
Short name T1023
Test name
Test status
Simulation time 11627883 ps
CPU time 0.54 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 12:55:30 PM PST 24
Peak memory 195584 kb
Host smart-d5392c09-38c7-4a7a-b185-3026aef176a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363748865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.363748865
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.175473603
Short name T291
Test name
Test status
Simulation time 84918002951 ps
CPU time 57.48 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:55:21 PM PST 24
Peak memory 200172 kb
Host smart-d9f24177-71bb-4e93-b285-1f0106087805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175473603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.175473603
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1566146573
Short name T710
Test name
Test status
Simulation time 147655695588 ps
CPU time 100.47 seconds
Started Jan 07 12:53:08 PM PST 24
Finished Jan 07 12:56:05 PM PST 24
Peak memory 199320 kb
Host smart-24964e1e-07a6-4ba9-95d2-bb095d0a000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566146573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1566146573
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2057558576
Short name T115
Test name
Test status
Simulation time 122270191308 ps
CPU time 78.99 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:56:00 PM PST 24
Peak memory 200120 kb
Host smart-aaa2feb0-fe46-4450-8ec4-3907fa7c8f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057558576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2057558576
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.396451684
Short name T1034
Test name
Test status
Simulation time 498499994900 ps
CPU time 950.17 seconds
Started Jan 07 12:53:20 PM PST 24
Finished Jan 07 01:10:34 PM PST 24
Peak memory 200120 kb
Host smart-22bf65c6-8080-4a6f-9685-f31c7e0e43f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396451684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.396451684
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3627380617
Short name T1007
Test name
Test status
Simulation time 99163266392 ps
CPU time 826 seconds
Started Jan 07 12:53:37 PM PST 24
Finished Jan 07 01:08:39 PM PST 24
Peak memory 200208 kb
Host smart-ad1fa56d-064d-419a-aade-03f368cb1e74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627380617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3627380617
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2024797190
Short name T566
Test name
Test status
Simulation time 6689288302 ps
CPU time 22.55 seconds
Started Jan 07 12:53:20 PM PST 24
Finished Jan 07 12:54:57 PM PST 24
Peak memory 198212 kb
Host smart-a3b03ce8-fe40-4bd5-a7ee-4d1482e6c97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024797190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2024797190
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.886189406
Short name T388
Test name
Test status
Simulation time 78327647180 ps
CPU time 221.01 seconds
Started Jan 07 12:53:14 PM PST 24
Finished Jan 07 12:58:30 PM PST 24
Peak memory 200168 kb
Host smart-bad34cef-d834-4e5d-ad4a-5d425e94d403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886189406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.886189406
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2372537037
Short name T679
Test name
Test status
Simulation time 4852143947 ps
CPU time 61.59 seconds
Started Jan 07 12:53:14 PM PST 24
Finished Jan 07 12:56:08 PM PST 24
Peak memory 200088 kb
Host smart-2611af41-e7cd-47d0-afac-324ecbbc79b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372537037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2372537037
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.4273680523
Short name T816
Test name
Test status
Simulation time 19743036331 ps
CPU time 15.57 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:54:55 PM PST 24
Peak memory 198260 kb
Host smart-30f541d4-edcf-4c3d-978f-89ce73c11756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273680523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4273680523
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2442041706
Short name T503
Test name
Test status
Simulation time 1730492189 ps
CPU time 3.57 seconds
Started Jan 07 12:53:15 PM PST 24
Finished Jan 07 12:54:36 PM PST 24
Peak memory 195640 kb
Host smart-9251ad0b-4bb5-4a53-be09-b73a2208062a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442041706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2442041706
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3973311972
Short name T384
Test name
Test status
Simulation time 5534166504 ps
CPU time 21.49 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:55:53 PM PST 24
Peak memory 199736 kb
Host smart-77392964-1c5a-4615-b973-a3c6f9cb5893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973311972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3973311972
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1927130004
Short name T883
Test name
Test status
Simulation time 155159383489 ps
CPU time 106.63 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:57:11 PM PST 24
Peak memory 200152 kb
Host smart-c170d6cd-5633-4bed-81e6-70afaf45af84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927130004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1927130004
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1073516246
Short name T788
Test name
Test status
Simulation time 6823032296 ps
CPU time 44.39 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 12:55:21 PM PST 24
Peak memory 199760 kb
Host smart-3ea38084-86e5-4119-8e0c-1542f8c233bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073516246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1073516246
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.752326493
Short name T347
Test name
Test status
Simulation time 100552180310 ps
CPU time 138.58 seconds
Started Jan 07 12:53:35 PM PST 24
Finished Jan 07 12:57:30 PM PST 24
Peak memory 200128 kb
Host smart-21ebd798-e1e9-4ea3-a7a1-b1d9011bd5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752326493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.752326493
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3817629905
Short name T296
Test name
Test status
Simulation time 55102128274 ps
CPU time 16.07 seconds
Started Jan 07 12:55:09 PM PST 24
Finished Jan 07 12:57:06 PM PST 24
Peak memory 199040 kb
Host smart-aaeba247-cfaa-4ffd-9a54-87aefb2ee5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817629905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3817629905
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2967503814
Short name T311
Test name
Test status
Simulation time 17003920626 ps
CPU time 68.59 seconds
Started Jan 07 12:55:27 PM PST 24
Finished Jan 07 12:57:59 PM PST 24
Peak memory 200116 kb
Host smart-9df2b603-a661-4615-9265-f7fcbcca9f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967503814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2967503814
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3250676645
Short name T643
Test name
Test status
Simulation time 129750490859 ps
CPU time 46.71 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:57:37 PM PST 24
Peak memory 198804 kb
Host smart-1bcdb508-fa4f-4e71-bb6a-4487c5ed5ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250676645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3250676645
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2269949075
Short name T164
Test name
Test status
Simulation time 120142693742 ps
CPU time 69.13 seconds
Started Jan 07 12:55:38 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 200100 kb
Host smart-667cf9a5-aa8d-40e0-81fc-7f62730af2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269949075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2269949075
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1977350219
Short name T286
Test name
Test status
Simulation time 119069487123 ps
CPU time 187.88 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:59:35 PM PST 24
Peak memory 200104 kb
Host smart-e658416c-5c58-41b0-886e-d9c9473b9620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977350219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1977350219
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2191449537
Short name T1013
Test name
Test status
Simulation time 59370792891 ps
CPU time 32.05 seconds
Started Jan 07 12:55:35 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 200192 kb
Host smart-d4f30eeb-f1df-4f0b-96ca-cae2f4c6dddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191449537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2191449537
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3992188056
Short name T612
Test name
Test status
Simulation time 16590957 ps
CPU time 0.53 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 12:55:34 PM PST 24
Peak memory 194476 kb
Host smart-c0a15bc4-865f-409f-9bbb-3576c8fc5e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992188056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3992188056
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.763032253
Short name T801
Test name
Test status
Simulation time 155985422971 ps
CPU time 132.87 seconds
Started Jan 07 12:53:21 PM PST 24
Finished Jan 07 12:56:58 PM PST 24
Peak memory 200104 kb
Host smart-bf631221-18a2-467c-9bf2-7047bdf2970d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763032253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.763032253
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1214630714
Short name T719
Test name
Test status
Simulation time 134958039902 ps
CPU time 197.34 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:58:04 PM PST 24
Peak memory 200152 kb
Host smart-ef6dd05c-edcc-47d7-9b97-22cac7dcb1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214630714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1214630714
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3855421677
Short name T84
Test name
Test status
Simulation time 47401380081 ps
CPU time 46.26 seconds
Started Jan 07 12:53:20 PM PST 24
Finished Jan 07 12:55:21 PM PST 24
Peak memory 200208 kb
Host smart-da89244b-2572-4981-baf9-4d8114b9cc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855421677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3855421677
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1789554498
Short name T628
Test name
Test status
Simulation time 38809011115 ps
CPU time 24.53 seconds
Started Jan 07 12:53:20 PM PST 24
Finished Jan 07 12:54:55 PM PST 24
Peak memory 200092 kb
Host smart-79e419eb-c7fc-431f-99d3-79e0fc17f3cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789554498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1789554498
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3194227214
Short name T588
Test name
Test status
Simulation time 104555496126 ps
CPU time 117.03 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 200156 kb
Host smart-72c2a093-4f4f-4a09-a119-9a2f59f1dbc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194227214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3194227214
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2899547984
Short name T567
Test name
Test status
Simulation time 7353791320 ps
CPU time 4.6 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:54:49 PM PST 24
Peak memory 198448 kb
Host smart-97c05aad-a6ba-4250-a343-43c77db30c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899547984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2899547984
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2525439530
Short name T779
Test name
Test status
Simulation time 269050369805 ps
CPU time 69.23 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:56:37 PM PST 24
Peak memory 198404 kb
Host smart-ffe6b5b9-348e-4883-a9f6-7d320e5268c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525439530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2525439530
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2332618686
Short name T952
Test name
Test status
Simulation time 9825245437 ps
CPU time 477.63 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 01:02:59 PM PST 24
Peak memory 200076 kb
Host smart-a58cc45a-1934-4a1f-bb67-113b74485d3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332618686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2332618686
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.786467784
Short name T9
Test name
Test status
Simulation time 1668341866 ps
CPU time 0.84 seconds
Started Jan 07 12:54:03 PM PST 24
Finished Jan 07 12:55:41 PM PST 24
Peak memory 196800 kb
Host smart-19cbce5e-4906-418f-9aaa-a74a936cf9af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786467784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.786467784
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2295323185
Short name T331
Test name
Test status
Simulation time 20932263173 ps
CPU time 33.84 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 12:55:59 PM PST 24
Peak memory 200188 kb
Host smart-56d4d79b-b92b-4a8f-81ee-52dd7fff9315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295323185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2295323185
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_smoke.2567446845
Short name T720
Test name
Test status
Simulation time 11108020896 ps
CPU time 48.97 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:55:50 PM PST 24
Peak memory 199768 kb
Host smart-5a0b8b2e-77db-4ad4-bec5-3f810f941d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567446845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2567446845
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2336571542
Short name T175
Test name
Test status
Simulation time 226471765383 ps
CPU time 379.06 seconds
Started Jan 07 12:54:11 PM PST 24
Finished Jan 07 01:01:57 PM PST 24
Peak memory 200064 kb
Host smart-beef1dcb-a74d-41a2-9df8-8df6f137c684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336571542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2336571542
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2680359905
Short name T935
Test name
Test status
Simulation time 40021753432 ps
CPU time 836.01 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 01:09:02 PM PST 24
Peak memory 216728 kb
Host smart-f96456d6-7d6d-463e-81c4-786e4d849ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680359905 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2680359905
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2087059657
Short name T386
Test name
Test status
Simulation time 2729711964 ps
CPU time 2.46 seconds
Started Jan 07 12:53:49 PM PST 24
Finished Jan 07 12:55:15 PM PST 24
Peak memory 199820 kb
Host smart-1c42d053-3c54-4657-b3f8-6bb71339925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087059657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2087059657
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1465410292
Short name T501
Test name
Test status
Simulation time 5618896202 ps
CPU time 9.68 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 12:55:24 PM PST 24
Peak memory 200084 kb
Host smart-b78d3b7e-d2cb-4300-b99b-f41e138a05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465410292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1465410292
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.520187102
Short name T198
Test name
Test status
Simulation time 40746613654 ps
CPU time 40.25 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 200180 kb
Host smart-d7700977-1222-43da-aa6f-2846f825e110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520187102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.520187102
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.856678225
Short name T1030
Test name
Test status
Simulation time 41703318178 ps
CPU time 34.62 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 12:57:01 PM PST 24
Peak memory 200152 kb
Host smart-6fc2cfa8-7730-4267-bfa8-1bec5f2a59b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856678225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.856678225
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3235371269
Short name T986
Test name
Test status
Simulation time 71611357830 ps
CPU time 40.55 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 200160 kb
Host smart-0f608969-2c48-4478-8c7d-14a1d735918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235371269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3235371269
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1298315766
Short name T700
Test name
Test status
Simulation time 198692507206 ps
CPU time 72.18 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 12:58:11 PM PST 24
Peak memory 199684 kb
Host smart-c3b0939a-1179-456c-9acf-9e1d7ae7d055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298315766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1298315766
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1334187877
Short name T270
Test name
Test status
Simulation time 117538857419 ps
CPU time 51.35 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 199924 kb
Host smart-f2029356-0d1f-47ac-af63-926608fd1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334187877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1334187877
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3826110987
Short name T610
Test name
Test status
Simulation time 36651867088 ps
CPU time 4.39 seconds
Started Jan 07 12:55:10 PM PST 24
Finished Jan 07 12:56:33 PM PST 24
Peak memory 199384 kb
Host smart-a0a2174d-da22-4295-9f9d-15badad31081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826110987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3826110987
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4142129397
Short name T217
Test name
Test status
Simulation time 15236770817 ps
CPU time 27.73 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 200244 kb
Host smart-3c36889d-18bb-4ea0-8725-a0ee5769f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142129397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4142129397
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.126733775
Short name T505
Test name
Test status
Simulation time 41995241 ps
CPU time 0.53 seconds
Started Jan 07 12:53:10 PM PST 24
Finished Jan 07 12:54:29 PM PST 24
Peak memory 195540 kb
Host smart-9e4e67fa-d45a-4024-9185-f5a6aa128ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126733775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.126733775
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_intr.4066612385
Short name T561
Test name
Test status
Simulation time 51287509663 ps
CPU time 49.24 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:56:02 PM PST 24
Peak memory 199620 kb
Host smart-06ec6099-b123-411e-bf00-a3c1271bf5dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066612385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.4066612385
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_loopback.3799312737
Short name T751
Test name
Test status
Simulation time 6730127716 ps
CPU time 3.5 seconds
Started Jan 07 12:53:38 PM PST 24
Finished Jan 07 12:54:51 PM PST 24
Peak memory 197204 kb
Host smart-a685c491-70a2-43c0-a6bf-4848e1797e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799312737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3799312737
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2901868346
Short name T685
Test name
Test status
Simulation time 115751545074 ps
CPU time 42.52 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 12:56:46 PM PST 24
Peak memory 197556 kb
Host smart-34da7020-f773-4354-9fb5-5add4e6cdc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901868346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2901868346
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3720707420
Short name T915
Test name
Test status
Simulation time 2048865511 ps
CPU time 23.74 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 12:55:11 PM PST 24
Peak memory 198404 kb
Host smart-52fa99f0-ca65-437e-beb6-acf2554de80b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3720707420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3720707420
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_smoke.1046300212
Short name T995
Test name
Test status
Simulation time 5976588117 ps
CPU time 10.39 seconds
Started Jan 07 12:54:01 PM PST 24
Finished Jan 07 12:55:47 PM PST 24
Peak memory 199664 kb
Host smart-307f4c4c-7c95-4f8f-9d07-b36bdc36180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046300212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1046300212
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2782682511
Short name T1015
Test name
Test status
Simulation time 945773870061 ps
CPU time 937.36 seconds
Started Jan 07 12:53:12 PM PST 24
Finished Jan 07 01:10:07 PM PST 24
Peak memory 208688 kb
Host smart-16f460b9-a28f-431c-b0f1-0f72d1c7d0c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782682511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2782682511
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3707606990
Short name T389
Test name
Test status
Simulation time 2715632193 ps
CPU time 2.16 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:54:36 PM PST 24
Peak memory 199108 kb
Host smart-3f13c1d4-fc42-43b5-a6a0-0e754a118224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707606990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3707606990
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3811575106
Short name T360
Test name
Test status
Simulation time 42521859685 ps
CPU time 43.1 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 200252 kb
Host smart-dff1dba3-425b-437d-be4f-fceeb4fd1861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811575106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3811575106
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3126003953
Short name T119
Test name
Test status
Simulation time 8102135428 ps
CPU time 13.57 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:56:51 PM PST 24
Peak memory 199484 kb
Host smart-784ef103-c44c-4322-b75a-c8cf7cd754c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126003953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3126003953
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.844793341
Short name T652
Test name
Test status
Simulation time 103178234950 ps
CPU time 17.7 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 200160 kb
Host smart-c4ce09ff-a21f-42a1-adba-6ce3307f4bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844793341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.844793341
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2464126372
Short name T161
Test name
Test status
Simulation time 48264828338 ps
CPU time 19.68 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:56:50 PM PST 24
Peak memory 200080 kb
Host smart-0ea3af7e-d010-4571-b886-1952a30439da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464126372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2464126372
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3144454704
Short name T188
Test name
Test status
Simulation time 53476315196 ps
CPU time 16.02 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:57:14 PM PST 24
Peak memory 199576 kb
Host smart-08880265-e803-462f-9455-e4ec37d52e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144454704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3144454704
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3166673617
Short name T902
Test name
Test status
Simulation time 21729563 ps
CPU time 0.56 seconds
Started Jan 07 12:53:21 PM PST 24
Finished Jan 07 12:54:46 PM PST 24
Peak memory 195636 kb
Host smart-db4ea7fe-1c82-4592-918c-49bf03ef39c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166673617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3166673617
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3019856901
Short name T716
Test name
Test status
Simulation time 170008585819 ps
CPU time 193.21 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:57:37 PM PST 24
Peak memory 200144 kb
Host smart-311e7c28-8d87-4547-ac01-79f9168ee49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019856901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3019856901
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1597042407
Short name T197
Test name
Test status
Simulation time 11273494824 ps
CPU time 31.28 seconds
Started Jan 07 12:53:22 PM PST 24
Finished Jan 07 12:55:04 PM PST 24
Peak memory 199976 kb
Host smart-ca43b1c3-f788-408a-8802-cb96470b4d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597042407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1597042407
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1785164814
Short name T590
Test name
Test status
Simulation time 139424982090 ps
CPU time 262.78 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:59:13 PM PST 24
Peak memory 200228 kb
Host smart-a7ae79e8-fb1f-46a2-82dd-b37198201952
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785164814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1785164814
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3719690387
Short name T563
Test name
Test status
Simulation time 45031239704 ps
CPU time 223.58 seconds
Started Jan 07 12:53:39 PM PST 24
Finished Jan 07 12:58:53 PM PST 24
Peak memory 200160 kb
Host smart-ed4a0469-c74b-4b94-a9f8-2e252c5f7b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719690387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3719690387
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.560622020
Short name T895
Test name
Test status
Simulation time 4687305620 ps
CPU time 2.96 seconds
Started Jan 07 12:53:39 PM PST 24
Finished Jan 07 12:54:58 PM PST 24
Peak memory 196424 kb
Host smart-d6c7286c-6593-40d8-acb2-317ec1f72e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560622020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.560622020
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1512513810
Short name T876
Test name
Test status
Simulation time 86596245434 ps
CPU time 80.02 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 12:55:59 PM PST 24
Peak memory 200096 kb
Host smart-76fb365c-77c6-4cb2-b8cb-a5d85e8155ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512513810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1512513810
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3990752861
Short name T1032
Test name
Test status
Simulation time 24673728057 ps
CPU time 180.08 seconds
Started Jan 07 12:53:23 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 200224 kb
Host smart-b53935f8-e86a-4c2b-a2a0-30a91c4a0dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990752861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3990752861
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1905426079
Short name T773
Test name
Test status
Simulation time 22651480428 ps
CPU time 37.37 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:56:05 PM PST 24
Peak memory 200024 kb
Host smart-b33a1d8d-b1e9-483d-a0a4-08e90d41e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905426079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1905426079
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2864289525
Short name T548
Test name
Test status
Simulation time 2539180898 ps
CPU time 4.5 seconds
Started Jan 07 12:53:20 PM PST 24
Finished Jan 07 12:54:39 PM PST 24
Peak memory 195740 kb
Host smart-f7f37215-827a-429a-aca7-d96d5e1b5522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864289525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2864289525
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3798527608
Short name T534
Test name
Test status
Simulation time 491904281 ps
CPU time 1.58 seconds
Started Jan 07 12:53:48 PM PST 24
Finished Jan 07 12:55:01 PM PST 24
Peak memory 198316 kb
Host smart-2ea6dcef-093c-42a0-98dd-5193593055b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798527608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3798527608
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2697066535
Short name T724
Test name
Test status
Simulation time 85349841027 ps
CPU time 599.62 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 01:04:59 PM PST 24
Peak memory 215692 kb
Host smart-8f157a9f-a0b1-4f10-98fa-39c93eefc36c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697066535 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2697066535
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1341822831
Short name T943
Test name
Test status
Simulation time 861562942 ps
CPU time 1.79 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:54:50 PM PST 24
Peak memory 198240 kb
Host smart-a608d327-1a13-4700-be02-7b2d2fb5b113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341822831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1341822831
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2695209363
Short name T167
Test name
Test status
Simulation time 116175170486 ps
CPU time 238.5 seconds
Started Jan 07 12:53:37 PM PST 24
Finished Jan 07 12:59:26 PM PST 24
Peak memory 200144 kb
Host smart-6a8088b8-25c2-49f2-8731-751615d13103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695209363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2695209363
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.240567041
Short name T785
Test name
Test status
Simulation time 40487078821 ps
CPU time 19 seconds
Started Jan 07 12:55:02 PM PST 24
Finished Jan 07 12:56:41 PM PST 24
Peak memory 200228 kb
Host smart-c59740b4-f157-47ed-b134-ea4ebf9d8435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240567041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.240567041
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1554824672
Short name T221
Test name
Test status
Simulation time 12749249080 ps
CPU time 19.1 seconds
Started Jan 07 12:55:03 PM PST 24
Finished Jan 07 12:56:41 PM PST 24
Peak memory 200192 kb
Host smart-7e2e4b86-5339-430e-b3ef-a1bdda73f028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554824672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1554824672
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2321060981
Short name T125
Test name
Test status
Simulation time 18244055063 ps
CPU time 27.16 seconds
Started Jan 07 12:55:34 PM PST 24
Finished Jan 07 12:57:23 PM PST 24
Peak memory 199908 kb
Host smart-d5656099-1d52-4f77-b200-ec403bc1e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321060981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2321060981
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2334591253
Short name T204
Test name
Test status
Simulation time 30312659009 ps
CPU time 14.26 seconds
Started Jan 07 12:55:38 PM PST 24
Finished Jan 07 12:57:21 PM PST 24
Peak memory 200132 kb
Host smart-ec58f065-c754-41c0-8665-c76d0dd8211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334591253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2334591253
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2538746412
Short name T678
Test name
Test status
Simulation time 13842627 ps
CPU time 0.54 seconds
Started Jan 07 12:53:37 PM PST 24
Finished Jan 07 12:55:19 PM PST 24
Peak memory 194596 kb
Host smart-26fe7365-084a-4de0-867e-56ac454595fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538746412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2538746412
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.386353879
Short name T613
Test name
Test status
Simulation time 43599497852 ps
CPU time 75.34 seconds
Started Jan 07 12:54:06 PM PST 24
Finished Jan 07 12:56:42 PM PST 24
Peak memory 200188 kb
Host smart-ea07ccc3-89f5-4cb6-81b7-9221a7119615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386353879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.386353879
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.4197726549
Short name T88
Test name
Test status
Simulation time 297387985825 ps
CPU time 63.36 seconds
Started Jan 07 12:53:49 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 200152 kb
Host smart-857f3460-85ce-41b0-98a2-fbbc28414331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197726549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4197726549
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.1408325204
Short name T633
Test name
Test status
Simulation time 212630364576 ps
CPU time 62.26 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:56:30 PM PST 24
Peak memory 200168 kb
Host smart-79cc85f5-b5d3-4445-b1b8-f70896aabab1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408325204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1408325204
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3545222100
Short name T682
Test name
Test status
Simulation time 70525543793 ps
CPU time 133.33 seconds
Started Jan 07 12:53:40 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 200172 kb
Host smart-af50caf6-5b52-46c2-ab19-646e78bea5fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545222100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3545222100
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3116028626
Short name T989
Test name
Test status
Simulation time 3232734725 ps
CPU time 3.63 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 12:55:30 PM PST 24
Peak memory 198908 kb
Host smart-6594b5a5-1aac-440a-99ef-402db6df5403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116028626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3116028626
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1727691534
Short name T847
Test name
Test status
Simulation time 103148608833 ps
CPU time 51.88 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:56:39 PM PST 24
Peak memory 208892 kb
Host smart-87c10b57-e467-4d18-9eea-49b1d5bb044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727691534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1727691534
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2281476720
Short name T135
Test name
Test status
Simulation time 13685618098 ps
CPU time 613.79 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 01:05:21 PM PST 24
Peak memory 200176 kb
Host smart-339b660d-d156-43d7-87ff-3008837c9734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281476720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2281476720
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3822373082
Short name T947
Test name
Test status
Simulation time 5113827381 ps
CPU time 38.76 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 12:56:05 PM PST 24
Peak memory 198944 kb
Host smart-495f4f72-9ab7-4532-b1d4-3d62c1d58a1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822373082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3822373082
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.530984966
Short name T369
Test name
Test status
Simulation time 69477710839 ps
CPU time 57.25 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:55:42 PM PST 24
Peak memory 199860 kb
Host smart-c05f2ea7-b09a-4a8c-bdf5-d71490e49c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530984966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.530984966
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2831809330
Short name T944
Test name
Test status
Simulation time 1724442843 ps
CPU time 3.2 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:55:09 PM PST 24
Peak memory 195644 kb
Host smart-794c1ba2-2944-4e34-89f5-d3702f65b5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831809330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2831809330
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3570082157
Short name T939
Test name
Test status
Simulation time 519105783 ps
CPU time 1.14 seconds
Started Jan 07 12:53:49 PM PST 24
Finished Jan 07 12:55:24 PM PST 24
Peak memory 197972 kb
Host smart-94da878a-565f-4ead-a55d-8167af3e6124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570082157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3570082157
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4175057182
Short name T173
Test name
Test status
Simulation time 548788740548 ps
CPU time 154.65 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:57:09 PM PST 24
Peak memory 208556 kb
Host smart-d4d728bd-73eb-4920-bc55-e659c1b02cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175057182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4175057182
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.677616005
Short name T738
Test name
Test status
Simulation time 8570873809 ps
CPU time 104.84 seconds
Started Jan 07 12:53:37 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 208544 kb
Host smart-8fdb4e96-45d5-44d1-9a70-dad8d3dc9d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677616005 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.677616005
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2433767262
Short name T10
Test name
Test status
Simulation time 2089371810 ps
CPU time 2.68 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 12:55:23 PM PST 24
Peak memory 198704 kb
Host smart-47db72ab-7057-436e-bcc1-c82254345178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433767262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2433767262
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.782075103
Short name T390
Test name
Test status
Simulation time 64649256669 ps
CPU time 26.22 seconds
Started Jan 07 12:53:46 PM PST 24
Finished Jan 07 12:55:26 PM PST 24
Peak memory 200172 kb
Host smart-c5f1fb48-5ce4-4d56-bbc1-7c4a8848439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782075103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.782075103
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3167498160
Short name T171
Test name
Test status
Simulation time 74091717841 ps
CPU time 15.68 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:11 PM PST 24
Peak memory 200140 kb
Host smart-5299d0b8-340b-4732-9464-ae0d2fd40dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167498160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3167498160
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.644203029
Short name T814
Test name
Test status
Simulation time 70778484159 ps
CPU time 27.28 seconds
Started Jan 07 12:55:15 PM PST 24
Finished Jan 07 12:57:43 PM PST 24
Peak memory 200048 kb
Host smart-f219c420-c51a-46b7-8aac-b989f7774fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644203029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.644203029
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2712380446
Short name T926
Test name
Test status
Simulation time 21626629700 ps
CPU time 35.35 seconds
Started Jan 07 12:55:19 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 199628 kb
Host smart-e7b700fb-0676-4de6-99e6-c1d53251030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712380446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2712380446
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3035788520
Short name T829
Test name
Test status
Simulation time 18929100684 ps
CPU time 26.73 seconds
Started Jan 07 12:55:40 PM PST 24
Finished Jan 07 12:57:41 PM PST 24
Peak memory 199572 kb
Host smart-6d919dbd-0c0a-4d4c-a7fd-87963286211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035788520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3035788520
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2495048469
Short name T339
Test name
Test status
Simulation time 101593616754 ps
CPU time 41.06 seconds
Started Jan 07 12:55:21 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 200164 kb
Host smart-8a91f52f-525c-4cda-adc9-a2409cacfae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495048469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2495048469
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1805348041
Short name T695
Test name
Test status
Simulation time 47579938 ps
CPU time 0.56 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:29 PM PST 24
Peak memory 195548 kb
Host smart-3333583a-a007-4b82-b272-7b556d434c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805348041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1805348041
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.52684005
Short name T202
Test name
Test status
Simulation time 21019062515 ps
CPU time 16.43 seconds
Started Jan 07 12:53:05 PM PST 24
Finished Jan 07 12:54:42 PM PST 24
Peak memory 200128 kb
Host smart-c406157d-d1af-4f45-8ca3-a822683e0b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52684005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.52684005
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2988870996
Short name T186
Test name
Test status
Simulation time 39027345394 ps
CPU time 67.68 seconds
Started Jan 07 12:53:00 PM PST 24
Finished Jan 07 12:55:28 PM PST 24
Peak memory 200188 kb
Host smart-943a0379-f4d2-47a9-abb1-fca603959dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988870996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2988870996
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2381921210
Short name T17
Test name
Test status
Simulation time 264809411434 ps
CPU time 115.94 seconds
Started Jan 07 12:53:15 PM PST 24
Finished Jan 07 12:56:30 PM PST 24
Peak memory 200096 kb
Host smart-a68c16dd-f824-499d-9ad4-ef86c8382ad5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381921210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2381921210
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2806921743
Short name T886
Test name
Test status
Simulation time 153321527069 ps
CPU time 761.91 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 01:07:10 PM PST 24
Peak memory 200148 kb
Host smart-ec18b7ab-8d38-41c0-963b-5a90d7a19039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806921743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2806921743
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_noise_filter.378897711
Short name T354
Test name
Test status
Simulation time 297563758558 ps
CPU time 27.38 seconds
Started Jan 07 12:53:02 PM PST 24
Finished Jan 07 12:54:44 PM PST 24
Peak memory 200496 kb
Host smart-ff9e9ce6-7a1f-4ea9-9012-b0ab9338c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378897711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.378897711
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.110129531
Short name T391
Test name
Test status
Simulation time 14798004784 ps
CPU time 169.48 seconds
Started Jan 07 12:53:02 PM PST 24
Finished Jan 07 12:57:09 PM PST 24
Peak memory 200144 kb
Host smart-cd7a909e-8413-466a-b877-f47adf5daf3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110129531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.110129531
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.429409499
Short name T800
Test name
Test status
Simulation time 1736525880 ps
CPU time 19.71 seconds
Started Jan 07 12:52:59 PM PST 24
Finished Jan 07 12:54:37 PM PST 24
Peak memory 198004 kb
Host smart-6971eefa-cf71-4eea-90f4-8e5242aa6c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429409499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.429409499
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4075394193
Short name T14
Test name
Test status
Simulation time 86385308277 ps
CPU time 135.9 seconds
Started Jan 07 12:53:03 PM PST 24
Finished Jan 07 12:56:44 PM PST 24
Peak memory 200088 kb
Host smart-e5261ccf-11ee-4750-9480-27155679f400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075394193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4075394193
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2150440574
Short name T599
Test name
Test status
Simulation time 3239821111 ps
CPU time 5.41 seconds
Started Jan 07 12:53:43 PM PST 24
Finished Jan 07 12:55:14 PM PST 24
Peak memory 195904 kb
Host smart-e08608e4-bd9e-4391-8366-c3e954ad86b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150440574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2150440574
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3386764346
Short name T73
Test name
Test status
Simulation time 149939282 ps
CPU time 0.76 seconds
Started Jan 07 12:53:02 PM PST 24
Finished Jan 07 12:54:28 PM PST 24
Peak memory 217712 kb
Host smart-156190c3-77d3-4f83-94a4-c93dd1acbcf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386764346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3386764346
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1980117800
Short name T833
Test name
Test status
Simulation time 496893140 ps
CPU time 2.5 seconds
Started Jan 07 12:54:11 PM PST 24
Finished Jan 07 12:55:43 PM PST 24
Peak memory 198220 kb
Host smart-c13e5ff4-75d0-4fff-b97e-041836ba49b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980117800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1980117800
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2640781367
Short name T821
Test name
Test status
Simulation time 400640626692 ps
CPU time 159.42 seconds
Started Jan 07 12:53:13 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 208976 kb
Host smart-36003d92-a2e5-4806-8042-030d23f2afb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640781367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2640781367
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1678149377
Short name T636
Test name
Test status
Simulation time 244334781208 ps
CPU time 1014.66 seconds
Started Jan 07 12:53:46 PM PST 24
Finished Jan 07 01:12:00 PM PST 24
Peak memory 228548 kb
Host smart-eb83db74-f133-4381-9e8c-ca18a412fb89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678149377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1678149377
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3446023852
Short name T880
Test name
Test status
Simulation time 10755407887 ps
CPU time 10.94 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 200052 kb
Host smart-f712efb8-9544-43dd-8d16-3dcd4d26a233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446023852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3446023852
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.553374760
Short name T717
Test name
Test status
Simulation time 20219738 ps
CPU time 0.54 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:34 PM PST 24
Peak memory 195580 kb
Host smart-dbb75cbe-bf2a-4857-bbc4-2c697e37ecd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553374760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.553374760
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_intr.3201247285
Short name T690
Test name
Test status
Simulation time 771484223577 ps
CPU time 113.4 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:57:00 PM PST 24
Peak memory 200100 kb
Host smart-d673105d-8b3f-4f21-b471-b46e00306a37
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201247285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3201247285
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1985634549
Short name T1016
Test name
Test status
Simulation time 98060585274 ps
CPU time 316.34 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 01:00:09 PM PST 24
Peak memory 200180 kb
Host smart-4ff5f72a-09e8-4c7d-b2d7-ee3c47b898b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985634549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1985634549
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_noise_filter.4085349574
Short name T130
Test name
Test status
Simulation time 3235729236 ps
CPU time 5.65 seconds
Started Jan 07 12:53:44 PM PST 24
Finished Jan 07 12:55:12 PM PST 24
Peak memory 193876 kb
Host smart-580f498f-32b3-4fda-b61c-002b890a1b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085349574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.4085349574
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.2477822689
Short name T731
Test name
Test status
Simulation time 12578689409 ps
CPU time 164.58 seconds
Started Jan 07 12:54:08 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 200228 kb
Host smart-ddbc6e48-e02f-48e3-93a4-d289eb8b9327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477822689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2477822689
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2367950400
Short name T958
Test name
Test status
Simulation time 3227228765 ps
CPU time 5.64 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:55:08 PM PST 24
Peak memory 198244 kb
Host smart-42a1be79-2f17-4ce4-b6b7-e319d767b827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367950400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2367950400
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.4215201366
Short name T1012
Test name
Test status
Simulation time 154073618159 ps
CPU time 246.13 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 12:59:22 PM PST 24
Peak memory 200068 kb
Host smart-8ed07f86-6cc0-463f-95a8-c905a1d22cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215201366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4215201366
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2709427411
Short name T978
Test name
Test status
Simulation time 3746092292 ps
CPU time 6.1 seconds
Started Jan 07 12:53:51 PM PST 24
Finished Jan 07 12:56:31 PM PST 24
Peak memory 196000 kb
Host smart-a4c0dfa7-757f-42e4-9631-5a7175eec186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709427411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2709427411
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.517254470
Short name T909
Test name
Test status
Simulation time 250453831099 ps
CPU time 914.94 seconds
Started Jan 07 12:53:44 PM PST 24
Finished Jan 07 01:10:08 PM PST 24
Peak memory 225096 kb
Host smart-bfbd2696-4642-4eee-bcf5-4bea839d8716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517254470 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.517254470
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3944157647
Short name T91
Test name
Test status
Simulation time 7366762713 ps
CPU time 6.3 seconds
Started Jan 07 12:53:26 PM PST 24
Finished Jan 07 12:54:49 PM PST 24
Peak memory 199500 kb
Host smart-d6c6444f-6018-46be-b1cb-f83c914c15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944157647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3944157647
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.639364695
Short name T932
Test name
Test status
Simulation time 108473115478 ps
CPU time 231.02 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:58:41 PM PST 24
Peak memory 200212 kb
Host smart-f1e91996-da9e-4e68-8793-053771329db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639364695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.639364695
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3706553854
Short name T843
Test name
Test status
Simulation time 205801662062 ps
CPU time 71.67 seconds
Started Jan 07 12:55:21 PM PST 24
Finished Jan 07 12:58:10 PM PST 24
Peak memory 200248 kb
Host smart-7ff87fe2-0561-4539-b40b-f3dadcbc2153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706553854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3706553854
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1734771356
Short name T387
Test name
Test status
Simulation time 210349695899 ps
CPU time 73.45 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 200144 kb
Host smart-a8be3636-ea73-4920-a9dc-60cf4323b759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734771356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1734771356
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2053038237
Short name T206
Test name
Test status
Simulation time 51636098850 ps
CPU time 191.93 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:59:39 PM PST 24
Peak memory 200168 kb
Host smart-4c94d09c-7d75-4223-973f-1872ab73588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053038237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2053038237
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1207378111
Short name T293
Test name
Test status
Simulation time 279109038384 ps
CPU time 146.94 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:59:09 PM PST 24
Peak memory 200216 kb
Host smart-cde23f2d-a54d-4703-b5db-23abd400704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207378111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1207378111
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3285323866
Short name T761
Test name
Test status
Simulation time 20037893 ps
CPU time 0.55 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:14 PM PST 24
Peak memory 195536 kb
Host smart-dedf5d37-6bcf-4440-ad72-56ab338cb274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285323866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3285323866
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.673764023
Short name T558
Test name
Test status
Simulation time 99531263897 ps
CPU time 52.17 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 12:56:10 PM PST 24
Peak memory 200204 kb
Host smart-38c63b24-8da7-42e2-beed-0df617a47d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673764023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.673764023
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.627383190
Short name T713
Test name
Test status
Simulation time 130674428718 ps
CPU time 46.81 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:33 PM PST 24
Peak memory 199364 kb
Host smart-2e580f11-4132-42e6-bf47-5d39718470b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627383190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.627383190
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3688169502
Short name T139
Test name
Test status
Simulation time 106561069062 ps
CPU time 154.28 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 200064 kb
Host smart-73146a56-cbd0-4407-9352-adba5cf1678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688169502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3688169502
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2028258611
Short name T371
Test name
Test status
Simulation time 1532435160455 ps
CPU time 2364.27 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 01:34:48 PM PST 24
Peak memory 200144 kb
Host smart-e633fec9-6ba7-4c32-aef7-3ed3fd615bda
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028258611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2028258611
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3498977711
Short name T748
Test name
Test status
Simulation time 67884798122 ps
CPU time 206.87 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 12:59:00 PM PST 24
Peak memory 200164 kb
Host smart-d71fa63c-44c3-473d-a278-cb169f85f93b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498977711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3498977711
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3497729538
Short name T789
Test name
Test status
Simulation time 72962656180 ps
CPU time 32.86 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 12:55:56 PM PST 24
Peak memory 199860 kb
Host smart-a3b5bfb6-e9b5-4a4a-91d3-6b506553a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497729538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3497729538
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.651851482
Short name T36
Test name
Test status
Simulation time 12198761745 ps
CPU time 394.98 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 01:01:20 PM PST 24
Peak memory 200136 kb
Host smart-e59e8ed7-1d62-44c6-92e2-fdad57398381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651851482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.651851482
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3237419634
Short name T684
Test name
Test status
Simulation time 1652986561 ps
CPU time 15.38 seconds
Started Jan 07 12:54:08 PM PST 24
Finished Jan 07 12:56:03 PM PST 24
Peak memory 197896 kb
Host smart-3d559883-d529-447f-b112-dda8d9e54a58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237419634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3237419634
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2501365173
Short name T514
Test name
Test status
Simulation time 3969824776 ps
CPU time 2.08 seconds
Started Jan 07 12:53:54 PM PST 24
Finished Jan 07 12:55:20 PM PST 24
Peak memory 196024 kb
Host smart-f91cdcd1-6850-4e09-bb76-4ad50f733dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501365173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2501365173
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.572631608
Short name T832
Test name
Test status
Simulation time 5909539192 ps
CPU time 35.6 seconds
Started Jan 07 12:53:39 PM PST 24
Finished Jan 07 12:55:45 PM PST 24
Peak memory 200184 kb
Host smart-62e29d33-31ca-4334-bce3-a52efc48ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572631608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.572631608
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3735512067
Short name T15
Test name
Test status
Simulation time 1905926113150 ps
CPU time 818.31 seconds
Started Jan 07 12:53:48 PM PST 24
Finished Jan 07 01:08:56 PM PST 24
Peak memory 200400 kb
Host smart-168a02c3-0f83-4b7a-903c-0da3ba5e52bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735512067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3735512067
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2697486672
Short name T1017
Test name
Test status
Simulation time 115769241746 ps
CPU time 338.37 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 01:01:12 PM PST 24
Peak memory 216716 kb
Host smart-501a9918-4251-4e52-a41c-5d9e0e4ebd2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697486672 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2697486672
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.258745946
Short name T818
Test name
Test status
Simulation time 1107217710 ps
CPU time 3.49 seconds
Started Jan 07 12:53:33 PM PST 24
Finished Jan 07 12:54:54 PM PST 24
Peak memory 198296 kb
Host smart-a951cdd4-29cd-4914-bc16-d4999b7eb94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258745946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.258745946
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3123846222
Short name T392
Test name
Test status
Simulation time 34166471113 ps
CPU time 16.43 seconds
Started Jan 07 12:54:00 PM PST 24
Finished Jan 07 12:55:48 PM PST 24
Peak memory 200024 kb
Host smart-60c5538b-cc59-49ff-be14-51c0389c8a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123846222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3123846222
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.609743012
Short name T878
Test name
Test status
Simulation time 25400476436 ps
CPU time 39.38 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:57:06 PM PST 24
Peak memory 200196 kb
Host smart-8cdbabd4-b564-4ca8-9ef6-8f1de5b62fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609743012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.609743012
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.488080619
Short name T176
Test name
Test status
Simulation time 14184572477 ps
CPU time 21.55 seconds
Started Jan 07 12:55:36 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 198792 kb
Host smart-7f36e57c-019c-4a27-95ef-b61194e14cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488080619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.488080619
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3821188301
Short name T812
Test name
Test status
Simulation time 61539352886 ps
CPU time 26.64 seconds
Started Jan 07 12:55:37 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 199292 kb
Host smart-198dbc5b-8c1e-48b2-9d15-c2e3b1647495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821188301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3821188301
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.575126673
Short name T884
Test name
Test status
Simulation time 265178261328 ps
CPU time 458.21 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 01:04:31 PM PST 24
Peak memory 200156 kb
Host smart-3e286dbf-f1dd-42e8-8566-d0c36ff474c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575126673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.575126673
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3789057155
Short name T234
Test name
Test status
Simulation time 28894436784 ps
CPU time 45.98 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:41 PM PST 24
Peak memory 200160 kb
Host smart-c5ab2885-b560-46e3-a9b5-67156b7f1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789057155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3789057155
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4244689468
Short name T246
Test name
Test status
Simulation time 200424618543 ps
CPU time 17.56 seconds
Started Jan 07 12:55:35 PM PST 24
Finished Jan 07 12:57:26 PM PST 24
Peak memory 199644 kb
Host smart-6b0ea2b6-27d8-4c01-905d-9e2c5145a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244689468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4244689468
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2498689253
Short name T662
Test name
Test status
Simulation time 15085616 ps
CPU time 0.55 seconds
Started Jan 07 12:53:25 PM PST 24
Finished Jan 07 12:54:50 PM PST 24
Peak memory 195584 kb
Host smart-a7f45641-7cf6-42dc-b44d-6759b1d5c8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498689253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2498689253
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2928948091
Short name T578
Test name
Test status
Simulation time 129977189249 ps
CPU time 206.42 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 12:58:26 PM PST 24
Peak memory 200056 kb
Host smart-d8c5544a-3bc4-4485-94cc-54bc608e26ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928948091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2928948091
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4247514150
Short name T177
Test name
Test status
Simulation time 36893666121 ps
CPU time 16.07 seconds
Started Jan 07 12:53:25 PM PST 24
Finished Jan 07 12:55:10 PM PST 24
Peak memory 198568 kb
Host smart-e5f3bdb4-e4b6-465e-8d9a-c78415437cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247514150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4247514150
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1684183844
Short name T736
Test name
Test status
Simulation time 6076693208 ps
CPU time 11.22 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:41 PM PST 24
Peak memory 199112 kb
Host smart-1581c414-39da-4184-83f3-7fd93b3ef488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684183844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1684183844
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3944394232
Short name T600
Test name
Test status
Simulation time 997511663346 ps
CPU time 258.65 seconds
Started Jan 07 12:53:54 PM PST 24
Finished Jan 07 12:59:37 PM PST 24
Peak memory 200300 kb
Host smart-dd2bafc9-dc2f-42d0-b8aa-a231ca5edd6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944394232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3944394232
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.437216873
Short name T819
Test name
Test status
Simulation time 119721143384 ps
CPU time 854.81 seconds
Started Jan 07 12:53:59 PM PST 24
Finished Jan 07 01:09:54 PM PST 24
Peak memory 200064 kb
Host smart-9cf337f7-f7d4-4cd0-8631-0afc98c100e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437216873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.437216873
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2999678253
Short name T1000
Test name
Test status
Simulation time 5100024498 ps
CPU time 3.5 seconds
Started Jan 07 12:53:48 PM PST 24
Finished Jan 07 12:55:03 PM PST 24
Peak memory 199088 kb
Host smart-f53f774b-c6ec-4ac1-9c75-492a67779705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999678253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2999678253
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.76606110
Short name T145
Test name
Test status
Simulation time 108721571743 ps
CPU time 201.63 seconds
Started Jan 07 12:53:43 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 200508 kb
Host smart-d3030691-0f47-492c-869d-96446838348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76606110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.76606110
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1901902216
Short name T798
Test name
Test status
Simulation time 129538006126 ps
CPU time 166.93 seconds
Started Jan 07 12:53:57 PM PST 24
Finished Jan 07 12:58:24 PM PST 24
Peak memory 200192 kb
Host smart-a1483c85-5f9a-4c87-bf8b-660b0463b244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901902216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1901902216
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3425859805
Short name T596
Test name
Test status
Simulation time 30773456642 ps
CPU time 43.94 seconds
Started Jan 07 12:53:54 PM PST 24
Finished Jan 07 12:56:02 PM PST 24
Peak memory 196152 kb
Host smart-99c0f86a-ea16-402c-a8fd-aba8b2281536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425859805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3425859805
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1445979094
Short name T159
Test name
Test status
Simulation time 65085833716 ps
CPU time 310.7 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 01:00:01 PM PST 24
Peak memory 208428 kb
Host smart-028ce40d-a744-461e-b948-4220073a23df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445979094 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1445979094
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2066338292
Short name T606
Test name
Test status
Simulation time 6158121537 ps
CPU time 22.25 seconds
Started Jan 07 12:53:26 PM PST 24
Finished Jan 07 12:55:05 PM PST 24
Peak memory 199624 kb
Host smart-d47f4bd4-6b83-42c8-a689-0af091285ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066338292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2066338292
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3969986073
Short name T938
Test name
Test status
Simulation time 41852691275 ps
CPU time 22.21 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 12:55:28 PM PST 24
Peak memory 200200 kb
Host smart-32cb5ee5-a69f-4aec-8ea7-50cb912b6d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969986073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3969986073
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.942821985
Short name T238
Test name
Test status
Simulation time 35521273580 ps
CPU time 50.63 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 200220 kb
Host smart-5c9a08f4-4889-456b-80fd-cab36e0e3662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942821985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.942821985
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1639473687
Short name T920
Test name
Test status
Simulation time 94742365458 ps
CPU time 65.89 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:57:40 PM PST 24
Peak memory 200060 kb
Host smart-404a223a-c5b3-4d6a-ad95-3260f1a1c444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639473687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1639473687
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.220305664
Short name T308
Test name
Test status
Simulation time 25481222597 ps
CPU time 12.09 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 199576 kb
Host smart-4d7911ee-e7a9-449f-b6d1-1b687c6c4c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220305664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.220305664
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2561517892
Short name T215
Test name
Test status
Simulation time 27846420824 ps
CPU time 42.14 seconds
Started Jan 07 12:55:33 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 200244 kb
Host smart-dbfeba55-8ac6-4787-931b-e8fa3ae783b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561517892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2561517892
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3874033649
Short name T185
Test name
Test status
Simulation time 172605774603 ps
CPU time 16.12 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:03 PM PST 24
Peak memory 200032 kb
Host smart-d665b64c-0300-44f6-a815-6f2e7a05f606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874033649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3874033649
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1711953538
Short name T179
Test name
Test status
Simulation time 250743333253 ps
CPU time 109.14 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:59:08 PM PST 24
Peak memory 200188 kb
Host smart-de46b373-6326-4693-bcc3-1bd4acf56816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711953538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1711953538
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3561164281
Short name T38
Test name
Test status
Simulation time 27260181953 ps
CPU time 54.08 seconds
Started Jan 07 12:55:13 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 200212 kb
Host smart-2e441771-8ea4-4a6f-8cba-67e2ad69bbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561164281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3561164281
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3012734104
Short name T576
Test name
Test status
Simulation time 120259568988 ps
CPU time 48.38 seconds
Started Jan 07 12:55:40 PM PST 24
Finished Jan 07 12:58:03 PM PST 24
Peak memory 199384 kb
Host smart-af4554f8-8088-49ee-9a5e-eec85453f125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012734104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3012734104
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3698772904
Short name T891
Test name
Test status
Simulation time 31855119 ps
CPU time 0.55 seconds
Started Jan 07 12:54:25 PM PST 24
Finished Jan 07 12:56:14 PM PST 24
Peak memory 195632 kb
Host smart-3eb814f8-9810-43f9-892a-f545fb2c10ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698772904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3698772904
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1542175962
Short name T803
Test name
Test status
Simulation time 57217708139 ps
CPU time 93.48 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:56:25 PM PST 24
Peak memory 200216 kb
Host smart-48cd9e6c-16d0-4e32-9c40-12fa85076c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542175962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1542175962
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1773105319
Short name T317
Test name
Test status
Simulation time 151718264372 ps
CPU time 67.2 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 199660 kb
Host smart-2d5ee737-65eb-4e3b-8868-535c9a6c3e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773105319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1773105319
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2629399339
Short name T959
Test name
Test status
Simulation time 101458240647 ps
CPU time 106.06 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 12:56:46 PM PST 24
Peak memory 200188 kb
Host smart-94bc5611-7845-499b-9d27-97f85767d10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629399339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2629399339
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3869191433
Short name T871
Test name
Test status
Simulation time 702542681248 ps
CPU time 1079.72 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 01:12:40 PM PST 24
Peak memory 199716 kb
Host smart-0ed8953c-26ce-48d2-be44-829ae7084513
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869191433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3869191433
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2121237765
Short name T828
Test name
Test status
Simulation time 150929553474 ps
CPU time 1038.16 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 01:12:06 PM PST 24
Peak memory 200224 kb
Host smart-d348d2b1-462c-4ca1-9503-e6691343a2b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121237765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2121237765
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3090045835
Short name T569
Test name
Test status
Simulation time 427890209 ps
CPU time 1.07 seconds
Started Jan 07 12:54:01 PM PST 24
Finished Jan 07 12:55:15 PM PST 24
Peak memory 198548 kb
Host smart-d8ffaca9-69e6-4802-b8df-57db055ab267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090045835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3090045835
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3260414221
Short name T790
Test name
Test status
Simulation time 143162198790 ps
CPU time 53.37 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 208264 kb
Host smart-a0ed5990-c98b-4179-88e0-9c8e5486e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260414221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3260414221
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1382217478
Short name T752
Test name
Test status
Simulation time 230812602661 ps
CPU time 176.59 seconds
Started Jan 07 12:53:41 PM PST 24
Finished Jan 07 12:57:55 PM PST 24
Peak memory 200052 kb
Host smart-600f3b78-5e18-4e1f-81ec-264f077646aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382217478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1382217478
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_stress_all.1020245602
Short name T805
Test name
Test status
Simulation time 70021159243 ps
CPU time 51.43 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:56:41 PM PST 24
Peak memory 199600 kb
Host smart-b0a176a6-4e18-4d04-bba8-ad952d4d5d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020245602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1020245602
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1904341312
Short name T648
Test name
Test status
Simulation time 6261723594 ps
CPU time 25.2 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:55:30 PM PST 24
Peak memory 199592 kb
Host smart-17192618-f819-445c-a443-9f1696fbbbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904341312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1904341312
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3863021
Short name T365
Test name
Test status
Simulation time 47538910815 ps
CPU time 7.2 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:41 PM PST 24
Peak memory 197668 kb
Host smart-0074ccfe-aa09-4a29-878a-911cdc1dcebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3863021
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.597000505
Short name T285
Test name
Test status
Simulation time 71327970496 ps
CPU time 130.8 seconds
Started Jan 07 12:55:23 PM PST 24
Finished Jan 07 12:59:06 PM PST 24
Peak memory 200140 kb
Host smart-f48efa77-3781-4938-8701-150b41832272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597000505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.597000505
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.4265970000
Short name T181
Test name
Test status
Simulation time 31758354543 ps
CPU time 46.52 seconds
Started Jan 07 12:55:12 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 200224 kb
Host smart-5a8efc1c-094b-42e5-bb6e-bd9507f12e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265970000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4265970000
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3861922114
Short name T1018
Test name
Test status
Simulation time 6395159296 ps
CPU time 10.25 seconds
Started Jan 07 12:55:52 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 198752 kb
Host smart-e2853d7b-5444-4be7-bc52-dda6ee185a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861922114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3861922114
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3445862568
Short name T248
Test name
Test status
Simulation time 36094869857 ps
CPU time 23.18 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 199904 kb
Host smart-b311a88b-b8fc-468a-b521-d8429dc9a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445862568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3445862568
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3105259157
Short name T132
Test name
Test status
Simulation time 63235077823 ps
CPU time 101.87 seconds
Started Jan 07 12:55:32 PM PST 24
Finished Jan 07 12:59:01 PM PST 24
Peak memory 200148 kb
Host smart-77896c00-0452-4301-973d-3dfa87eb2701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105259157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3105259157
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_full.259784545
Short name T615
Test name
Test status
Simulation time 190307627916 ps
CPU time 75.85 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 12:56:41 PM PST 24
Peak memory 200064 kb
Host smart-c1e1bfd6-36d1-4599-b595-7420f25448bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259784545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.259784545
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_intr.1300007730
Short name T402
Test name
Test status
Simulation time 71452585352 ps
CPU time 40.3 seconds
Started Jan 07 12:54:03 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 200216 kb
Host smart-bdf33c8d-d806-46fb-ac5f-41e2a4ebb863
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300007730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1300007730
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1269209763
Short name T813
Test name
Test status
Simulation time 153451398137 ps
CPU time 427.56 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 01:02:41 PM PST 24
Peak memory 200144 kb
Host smart-2425e899-4e8e-4517-a5fb-77ab71fac16e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269209763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1269209763
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3827527802
Short name T916
Test name
Test status
Simulation time 7331456112 ps
CPU time 5.29 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:55:24 PM PST 24
Peak memory 198172 kb
Host smart-9e0c4007-ee34-4451-936c-5b6e4b139cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827527802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3827527802
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4291625382
Short name T533
Test name
Test status
Simulation time 52490790430 ps
CPU time 51.29 seconds
Started Jan 07 12:54:05 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 199384 kb
Host smart-66755506-7957-4c71-b3cc-a9b2859cef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291625382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4291625382
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2098043748
Short name T984
Test name
Test status
Simulation time 23339145721 ps
CPU time 1263.39 seconds
Started Jan 07 12:54:04 PM PST 24
Finished Jan 07 01:16:27 PM PST 24
Peak memory 200152 kb
Host smart-8196b3ad-aa09-4f63-b09f-0e9d57a7ebf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098043748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2098043748
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.4208247573
Short name T553
Test name
Test status
Simulation time 4260418515 ps
CPU time 39.65 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:56:22 PM PST 24
Peak memory 198652 kb
Host smart-bec839e7-91c7-4655-b538-7f5de9df090f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208247573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.4208247573
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.63675697
Short name T733
Test name
Test status
Simulation time 20840532043 ps
CPU time 33.85 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 12:55:55 PM PST 24
Peak memory 199296 kb
Host smart-0170549f-d87f-47c0-b246-24d14e866b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63675697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.63675697
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.12174846
Short name T949
Test name
Test status
Simulation time 5185364582 ps
CPU time 1.28 seconds
Started Jan 07 12:53:59 PM PST 24
Finished Jan 07 12:55:30 PM PST 24
Peak memory 195996 kb
Host smart-f63a06bb-623e-438b-a036-a2b18e0a08f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12174846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.12174846
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2630351636
Short name T957
Test name
Test status
Simulation time 5906783631 ps
CPU time 15.36 seconds
Started Jan 07 12:54:20 PM PST 24
Finished Jan 07 12:56:01 PM PST 24
Peak memory 199980 kb
Host smart-a28aca02-8463-4948-832b-1bd41b596211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630351636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2630351636
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3003424807
Short name T136
Test name
Test status
Simulation time 159845049286 ps
CPU time 454.98 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 01:02:57 PM PST 24
Peak memory 200168 kb
Host smart-8f369fb1-1692-4fa2-820e-0b485f5d6606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003424807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3003424807
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1792374392
Short name T877
Test name
Test status
Simulation time 48913660373 ps
CPU time 711.09 seconds
Started Jan 07 12:54:04 PM PST 24
Finished Jan 07 01:07:20 PM PST 24
Peak memory 216616 kb
Host smart-d6ebe892-c5f7-4958-900f-f791b53fb86e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792374392 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1792374392
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2251431714
Short name T580
Test name
Test status
Simulation time 166388825455 ps
CPU time 63.14 seconds
Started Jan 07 12:53:47 PM PST 24
Finished Jan 07 12:56:30 PM PST 24
Peak memory 200200 kb
Host smart-3bbf82f7-693c-4830-ba72-327a79b1b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251431714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2251431714
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.776859554
Short name T942
Test name
Test status
Simulation time 30736095149 ps
CPU time 14.64 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 200140 kb
Host smart-84f94bef-23ce-46f0-b9cc-82044af09494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776859554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.776859554
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.529047234
Short name T929
Test name
Test status
Simulation time 22660181215 ps
CPU time 23.18 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 199404 kb
Host smart-ed5b4df6-e620-4bc9-b603-276ccf2622aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529047234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.529047234
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2866226103
Short name T865
Test name
Test status
Simulation time 60770949750 ps
CPU time 50.58 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 199972 kb
Host smart-959e8a64-85c8-4641-b125-b4f4fa88ff21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866226103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2866226103
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1522039334
Short name T141
Test name
Test status
Simulation time 51070540094 ps
CPU time 49.17 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:57:37 PM PST 24
Peak memory 199960 kb
Host smart-27f93b07-c734-43ff-b0d0-c048eb3e59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522039334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1522039334
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2977128435
Short name T582
Test name
Test status
Simulation time 44632029 ps
CPU time 0.54 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:55:19 PM PST 24
Peak memory 195564 kb
Host smart-99b86881-12a7-45f9-9884-dd95e15ac598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977128435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2977128435
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2891154653
Short name T921
Test name
Test status
Simulation time 48401486795 ps
CPU time 22.26 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 200088 kb
Host smart-0706bd57-abc0-4d69-8a41-011d065d9e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891154653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2891154653
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2169914309
Short name T898
Test name
Test status
Simulation time 24541048275 ps
CPU time 30.56 seconds
Started Jan 07 12:54:06 PM PST 24
Finished Jan 07 12:55:52 PM PST 24
Peak memory 199208 kb
Host smart-ec79b3d5-aa83-43bc-91ca-616b53b4613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169914309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2169914309
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_loopback.1498926019
Short name T975
Test name
Test status
Simulation time 6084393368 ps
CPU time 6.61 seconds
Started Jan 07 12:54:10 PM PST 24
Finished Jan 07 12:55:45 PM PST 24
Peak memory 199492 kb
Host smart-d1a93fc7-c207-40e7-893a-8a5fa4d2528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498926019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1498926019
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1548080661
Short name T782
Test name
Test status
Simulation time 50781493383 ps
CPU time 22.09 seconds
Started Jan 07 12:54:03 PM PST 24
Finished Jan 07 12:56:18 PM PST 24
Peak memory 197696 kb
Host smart-fbffb0ca-0f39-4082-a015-198d5bf957e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548080661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1548080661
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4228126048
Short name T335
Test name
Test status
Simulation time 53665606167 ps
CPU time 25.9 seconds
Started Jan 07 12:54:30 PM PST 24
Finished Jan 07 12:56:19 PM PST 24
Peak memory 200012 kb
Host smart-856e7c12-977f-4968-b44e-1a826d64d63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228126048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4228126048
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_smoke.2778592078
Short name T537
Test name
Test status
Simulation time 5770375368 ps
CPU time 17.91 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 12:55:22 PM PST 24
Peak memory 199500 kb
Host smart-da192b2c-f25a-40f7-bea2-16149aaf9699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778592078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2778592078
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2101548275
Short name T850
Test name
Test status
Simulation time 123168857146 ps
CPU time 194.24 seconds
Started Jan 07 12:53:57 PM PST 24
Finished Jan 07 12:58:46 PM PST 24
Peak memory 200096 kb
Host smart-a265faa8-b4f4-4b20-820c-c171626a4b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101548275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2101548275
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2852227924
Short name T297
Test name
Test status
Simulation time 43014765209 ps
CPU time 119.44 seconds
Started Jan 07 12:54:26 PM PST 24
Finished Jan 07 12:57:42 PM PST 24
Peak memory 216968 kb
Host smart-0406546e-c28a-4c2b-9a2f-13ce2eea19c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852227924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2852227924
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.148819220
Short name T21
Test name
Test status
Simulation time 1492184999 ps
CPU time 1.28 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 12:55:17 PM PST 24
Peak memory 196472 kb
Host smart-a2a747df-46d4-4edc-824c-f8d52aa65533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148819220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.148819220
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.726627913
Short name T255
Test name
Test status
Simulation time 140879830876 ps
CPU time 60.49 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 200016 kb
Host smart-dc242b6e-9f86-45b1-856a-5e36622c94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726627913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.726627913
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1181577747
Short name T244
Test name
Test status
Simulation time 21278095329 ps
CPU time 34.38 seconds
Started Jan 07 12:55:46 PM PST 24
Finished Jan 07 12:57:49 PM PST 24
Peak memory 200080 kb
Host smart-89c4a8c2-8273-4163-a44b-1caf0f885a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181577747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1181577747
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2214365488
Short name T555
Test name
Test status
Simulation time 56262207228 ps
CPU time 22.85 seconds
Started Jan 07 12:55:32 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 198132 kb
Host smart-85de7140-4636-452d-8645-ed2846369209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214365488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2214365488
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1808793074
Short name T313
Test name
Test status
Simulation time 60843375554 ps
CPU time 23.5 seconds
Started Jan 07 12:55:15 PM PST 24
Finished Jan 07 12:57:08 PM PST 24
Peak memory 200152 kb
Host smart-f208cd40-d820-4635-808e-52d786112196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808793074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1808793074
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3930801965
Short name T184
Test name
Test status
Simulation time 105381685946 ps
CPU time 79.38 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:58:34 PM PST 24
Peak memory 200204 kb
Host smart-e9896817-790e-4949-8657-7e3b88e3783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930801965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3930801965
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.4022515830
Short name T158
Test name
Test status
Simulation time 66290615115 ps
CPU time 94.97 seconds
Started Jan 07 12:55:13 PM PST 24
Finished Jan 07 12:58:06 PM PST 24
Peak memory 200184 kb
Host smart-adb8f58d-f093-4257-84fb-446b0e74e10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022515830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.4022515830
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1266103734
Short name T282
Test name
Test status
Simulation time 163861087094 ps
CPU time 143.81 seconds
Started Jan 07 12:55:39 PM PST 24
Finished Jan 07 12:59:50 PM PST 24
Peak memory 200160 kb
Host smart-9a16d574-0828-4264-ab4f-4ffc63790d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266103734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1266103734
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4107991850
Short name T162
Test name
Test status
Simulation time 18404429751 ps
CPU time 26.32 seconds
Started Jan 07 12:55:43 PM PST 24
Finished Jan 07 12:57:49 PM PST 24
Peak memory 200012 kb
Host smart-bacff7fe-846f-42e4-add7-6feb5f6e2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107991850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4107991850
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1075196837
Short name T25
Test name
Test status
Simulation time 52190028 ps
CPU time 0.54 seconds
Started Jan 07 12:54:17 PM PST 24
Finished Jan 07 12:55:37 PM PST 24
Peak memory 195612 kb
Host smart-e8c15b94-adc0-47e2-ba1d-ed5b78cc1001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075196837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1075196837
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1807752113
Short name T820
Test name
Test status
Simulation time 32027546742 ps
CPU time 14.25 seconds
Started Jan 07 12:54:35 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 200228 kb
Host smart-b873c27e-227b-4d40-8a78-11651ca41b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807752113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1807752113
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4252393740
Short name T1026
Test name
Test status
Simulation time 11566480291 ps
CPU time 21.57 seconds
Started Jan 07 12:53:57 PM PST 24
Finished Jan 07 12:55:59 PM PST 24
Peak memory 199508 kb
Host smart-c40483db-45dd-464f-8fbb-32f658974524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252393740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4252393740
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1515737690
Short name T824
Test name
Test status
Simulation time 43661267140 ps
CPU time 23.86 seconds
Started Jan 07 12:53:57 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 200128 kb
Host smart-d224b793-ff01-4c42-b24d-c8e69419868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515737690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1515737690
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.857567317
Short name T1027
Test name
Test status
Simulation time 35432991231 ps
CPU time 61.88 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 12:56:12 PM PST 24
Peak memory 197780 kb
Host smart-eba93684-2ff2-42dd-b7c3-eb7ffe347887
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857567317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.857567317
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.169611062
Short name T887
Test name
Test status
Simulation time 202683965727 ps
CPU time 331.73 seconds
Started Jan 07 12:54:03 PM PST 24
Finished Jan 07 01:01:01 PM PST 24
Peak memory 200176 kb
Host smart-65c719b3-5c3b-4880-a838-a766c5ff2426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169611062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.169611062
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3478051443
Short name T511
Test name
Test status
Simulation time 1791043228 ps
CPU time 3.02 seconds
Started Jan 07 12:54:30 PM PST 24
Finished Jan 07 12:55:56 PM PST 24
Peak memory 198208 kb
Host smart-9fa407dc-f614-4877-bca2-475f36afab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478051443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3478051443
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1656546792
Short name T121
Test name
Test status
Simulation time 127923384575 ps
CPU time 57.87 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 198244 kb
Host smart-408fb876-261d-4736-82f9-0b48c921ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656546792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1656546792
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3936709864
Short name T809
Test name
Test status
Simulation time 18946769351 ps
CPU time 455.36 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 01:02:54 PM PST 24
Peak memory 200116 kb
Host smart-e0218243-950d-49ab-890c-ef0fbf1b3d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936709864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3936709864
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2849166356
Short name T1045
Test name
Test status
Simulation time 9436652676 ps
CPU time 16.6 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:55:44 PM PST 24
Peak memory 198776 kb
Host smart-f006f6e4-8669-4986-ad1f-eb097c20b309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849166356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2849166356
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_smoke.999622630
Short name T667
Test name
Test status
Simulation time 6245088738 ps
CPU time 9.78 seconds
Started Jan 07 12:54:08 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 199628 kb
Host smart-df78a0d5-ccc6-4299-bc76-7ceb0a674879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999622630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.999622630
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2187102515
Short name T348
Test name
Test status
Simulation time 25891424774 ps
CPU time 40.95 seconds
Started Jan 07 12:54:11 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 198600 kb
Host smart-e439fc4b-24ce-4a0a-b913-271d4cdd85d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187102515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2187102515
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3335165742
Short name T889
Test name
Test status
Simulation time 124166356426 ps
CPU time 750.4 seconds
Started Jan 07 12:54:26 PM PST 24
Finished Jan 07 01:08:32 PM PST 24
Peak memory 216584 kb
Host smart-18d51efa-269e-4434-b285-af23e0fa93a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335165742 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3335165742
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_rx.889926379
Short name T688
Test name
Test status
Simulation time 112593141310 ps
CPU time 28.34 seconds
Started Jan 07 12:54:00 PM PST 24
Finished Jan 07 12:56:02 PM PST 24
Peak memory 199948 kb
Host smart-eaef6fcb-7a5d-435f-8c67-3dd11403401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889926379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.889926379
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3514517147
Short name T860
Test name
Test status
Simulation time 9767471830 ps
CPU time 11.8 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 12:57:20 PM PST 24
Peak memory 200128 kb
Host smart-facbbee7-1aee-42d7-a519-0e8b6764b2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514517147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3514517147
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1915551513
Short name T999
Test name
Test status
Simulation time 13855955253 ps
CPU time 24.92 seconds
Started Jan 07 12:55:38 PM PST 24
Finished Jan 07 12:57:22 PM PST 24
Peak memory 200192 kb
Host smart-b320efe7-546e-4470-bcfc-978e9b08c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915551513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1915551513
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1434789549
Short name T236
Test name
Test status
Simulation time 95583636963 ps
CPU time 33.46 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:57:11 PM PST 24
Peak memory 200252 kb
Host smart-97ecca39-0649-47d8-a785-43b7d151ecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434789549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1434789549
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3890743703
Short name T1029
Test name
Test status
Simulation time 20467465165 ps
CPU time 44.1 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 200144 kb
Host smart-fd0142e3-a858-486c-9547-dfe6c6326bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890743703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3890743703
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3212945507
Short name T196
Test name
Test status
Simulation time 68855144008 ps
CPU time 138.49 seconds
Started Jan 07 12:55:53 PM PST 24
Finished Jan 07 12:59:45 PM PST 24
Peak memory 199884 kb
Host smart-e49585c1-c82b-4d2e-bfb7-ee1ca54d6c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212945507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3212945507
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2902668415
Short name T128
Test name
Test status
Simulation time 25705125958 ps
CPU time 38.16 seconds
Started Jan 07 12:55:15 PM PST 24
Finished Jan 07 12:57:41 PM PST 24
Peak memory 199972 kb
Host smart-f01dd4ee-90d5-4902-bc48-218f517a0fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902668415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2902668415
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3729399089
Short name T796
Test name
Test status
Simulation time 24309258 ps
CPU time 0.54 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 12:55:45 PM PST 24
Peak memory 195504 kb
Host smart-f304fbb9-f72e-4cb9-bfd2-f36d332832d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729399089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3729399089
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.870330467
Short name T519
Test name
Test status
Simulation time 37254381669 ps
CPU time 62.96 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 200200 kb
Host smart-3816d850-3b91-41a6-a86a-61e5957e23c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870330467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.870330467
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3413334431
Short name T163
Test name
Test status
Simulation time 27524950278 ps
CPU time 47.17 seconds
Started Jan 07 12:54:15 PM PST 24
Finished Jan 07 12:56:18 PM PST 24
Peak memory 200052 kb
Host smart-3895b2d9-18cc-4ee4-89d2-51bb3dfc7e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413334431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3413334431
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.885665863
Short name T189
Test name
Test status
Simulation time 21580805349 ps
CPU time 19.07 seconds
Started Jan 07 12:54:24 PM PST 24
Finished Jan 07 12:56:22 PM PST 24
Peak memory 200160 kb
Host smart-2a9ede6b-9b56-4743-bf29-35d84df13103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885665863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.885665863
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1597781259
Short name T698
Test name
Test status
Simulation time 98189851541 ps
CPU time 39.33 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:56:06 PM PST 24
Peak memory 199372 kb
Host smart-078c0d4b-ab7c-4636-a8df-35a1b73c776c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597781259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1597781259
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1222016448
Short name T353
Test name
Test status
Simulation time 66025001770 ps
CPU time 454.61 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 01:03:02 PM PST 24
Peak memory 200180 kb
Host smart-9402cb4c-0909-4e64-befa-d3bbd1b439d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222016448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1222016448
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.717458710
Short name T694
Test name
Test status
Simulation time 742996416 ps
CPU time 0.71 seconds
Started Jan 07 12:54:27 PM PST 24
Finished Jan 07 12:56:11 PM PST 24
Peak memory 195736 kb
Host smart-a4a7255c-18ae-4d0b-90eb-440a5068f64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717458710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.717458710
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3102448979
Short name T964
Test name
Test status
Simulation time 13622993076 ps
CPU time 24.41 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:55:37 PM PST 24
Peak memory 197376 kb
Host smart-42ee96f2-07f1-4700-bea7-778353ac1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102448979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3102448979
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1049155555
Short name T37
Test name
Test status
Simulation time 12649292139 ps
CPU time 347.61 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 01:01:40 PM PST 24
Peak memory 200120 kb
Host smart-58f57e0b-48ae-4821-b5f6-1cb58d1ecfbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049155555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1049155555
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1907125917
Short name T1003
Test name
Test status
Simulation time 245241578349 ps
CPU time 190.07 seconds
Started Jan 07 12:53:45 PM PST 24
Finished Jan 07 12:58:34 PM PST 24
Peak memory 200116 kb
Host smart-aa34512f-a858-4a87-8c43-ad4134db9e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907125917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1907125917
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.4112574575
Short name T644
Test name
Test status
Simulation time 2917998170 ps
CPU time 4.87 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:55:45 PM PST 24
Peak memory 195664 kb
Host smart-5989889c-8495-46d7-ad58-7353a5b04dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112574575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.4112574575
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3206865888
Short name T776
Test name
Test status
Simulation time 264240011 ps
CPU time 1.39 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 12:55:30 PM PST 24
Peak memory 198064 kb
Host smart-af5a6486-31f7-4fce-94c7-033ec85dfae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206865888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3206865888
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3836274102
Short name T649
Test name
Test status
Simulation time 182536992210 ps
CPU time 802.77 seconds
Started Jan 07 12:54:24 PM PST 24
Finished Jan 07 01:09:08 PM PST 24
Peak memory 213932 kb
Host smart-048c73a8-6874-42c8-991e-a6c5e18ff73d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836274102 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3836274102
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1188311675
Short name T665
Test name
Test status
Simulation time 9562766108 ps
CPU time 6.16 seconds
Started Jan 07 12:53:59 PM PST 24
Finished Jan 07 12:55:45 PM PST 24
Peak memory 200044 kb
Host smart-2690f1cc-13a3-4e5f-b335-f2e3b3d94945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188311675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1188311675
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3059654451
Short name T570
Test name
Test status
Simulation time 8636609219 ps
CPU time 14.28 seconds
Started Jan 07 12:53:56 PM PST 24
Finished Jan 07 12:55:46 PM PST 24
Peak memory 200128 kb
Host smart-1a621b3b-cd6e-4dbb-93fe-8922e591cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059654451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3059654451
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1578479218
Short name T146
Test name
Test status
Simulation time 23028550800 ps
CPU time 20.92 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 199656 kb
Host smart-7c45d206-0e19-45d1-84d4-8e0951eaa84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578479218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1578479218
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3837847623
Short name T208
Test name
Test status
Simulation time 33346770222 ps
CPU time 60.95 seconds
Started Jan 07 12:55:43 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 199932 kb
Host smart-365e42ed-4b43-49b9-8384-137ec2fbace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837847623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3837847623
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.656857114
Short name T283
Test name
Test status
Simulation time 35430252566 ps
CPU time 26.12 seconds
Started Jan 07 12:55:15 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 200096 kb
Host smart-c97b8ea8-ad0f-4c03-83cb-0452d5059bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656857114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.656857114
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2072751505
Short name T240
Test name
Test status
Simulation time 125269989185 ps
CPU time 203.99 seconds
Started Jan 07 12:55:40 PM PST 24
Finished Jan 07 01:00:36 PM PST 24
Peak memory 200080 kb
Host smart-1b786a62-8453-4c45-945c-89a117cdf093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072751505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2072751505
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1520291737
Short name T1011
Test name
Test status
Simulation time 69388145378 ps
CPU time 31.63 seconds
Started Jan 07 12:55:54 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 200252 kb
Host smart-389136c0-e24a-46d6-890b-71c50cfcfae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520291737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1520291737
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.205133720
Short name T143
Test name
Test status
Simulation time 314515759649 ps
CPU time 281.36 seconds
Started Jan 07 12:55:10 PM PST 24
Finished Jan 07 01:01:29 PM PST 24
Peak memory 200096 kb
Host smart-f21a4b12-7230-48a0-a843-fcccc281bcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205133720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.205133720
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1466955824
Short name T881
Test name
Test status
Simulation time 21770548 ps
CPU time 0.55 seconds
Started Jan 07 12:54:26 PM PST 24
Finished Jan 07 12:55:52 PM PST 24
Peak memory 194764 kb
Host smart-78e04e5a-8689-470e-ae76-3cddfc013753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466955824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1466955824
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.749775369
Short name T922
Test name
Test status
Simulation time 143596176086 ps
CPU time 120.54 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:57:47 PM PST 24
Peak memory 200108 kb
Host smart-89903ead-49a0-4452-bb3d-19b68709cc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749775369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.749775369
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2493479036
Short name T760
Test name
Test status
Simulation time 78978236057 ps
CPU time 116.33 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 12:57:24 PM PST 24
Peak memory 199516 kb
Host smart-666f3766-81fd-4b94-8d8f-8116078b3993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493479036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2493479036
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3366733870
Short name T1037
Test name
Test status
Simulation time 50408956230 ps
CPU time 84.5 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 12:57:22 PM PST 24
Peak memory 199352 kb
Host smart-1c4dae90-5a21-4b10-ab7b-b4e86232931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366733870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3366733870
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2476418613
Short name T377
Test name
Test status
Simulation time 268765919160 ps
CPU time 721.31 seconds
Started Jan 07 12:53:54 PM PST 24
Finished Jan 07 01:07:15 PM PST 24
Peak memory 200136 kb
Host smart-32500b8d-6af1-43c0-9a14-d2924c3c58b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476418613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2476418613
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2082438320
Short name T663
Test name
Test status
Simulation time 180864188084 ps
CPU time 163.24 seconds
Started Jan 07 12:54:36 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 200204 kb
Host smart-283eb315-ca74-4dea-bc30-a97a6567ca3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2082438320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2082438320
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.963697548
Short name T672
Test name
Test status
Simulation time 6460685291 ps
CPU time 7.8 seconds
Started Jan 07 12:54:05 PM PST 24
Finished Jan 07 12:55:25 PM PST 24
Peak memory 200084 kb
Host smart-de06b779-0b9c-42aa-a6be-5ee017fe8241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963697548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.963697548
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1984695550
Short name T913
Test name
Test status
Simulation time 69857734249 ps
CPU time 21.1 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 12:55:54 PM PST 24
Peak memory 200512 kb
Host smart-5f9c42ad-dc51-44c1-af96-3ee027dec0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984695550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1984695550
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.311565687
Short name T592
Test name
Test status
Simulation time 14045839053 ps
CPU time 70.7 seconds
Started Jan 07 12:54:05 PM PST 24
Finished Jan 07 12:57:29 PM PST 24
Peak memory 200096 kb
Host smart-c241c9fc-1c51-40ce-890a-9f6f213c8f22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311565687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.311565687
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.417613966
Short name T98
Test name
Test status
Simulation time 141760936047 ps
CPU time 35.65 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 12:56:06 PM PST 24
Peak memory 200204 kb
Host smart-be5a528b-9f35-4d7e-9fc2-98bc514318ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417613966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.417613966
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.54466428
Short name T946
Test name
Test status
Simulation time 33831015349 ps
CPU time 48.3 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:55:57 PM PST 24
Peak memory 195980 kb
Host smart-64bf2c6f-f8a6-41ae-b0b1-fe558c72c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54466428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.54466428
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_stress_all.3587297119
Short name T315
Test name
Test status
Simulation time 154670514153 ps
CPU time 170.26 seconds
Started Jan 07 12:54:00 PM PST 24
Finished Jan 07 12:58:22 PM PST 24
Peak memory 200172 kb
Host smart-5812d387-9146-4009-8c0a-dd12e398a7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587297119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3587297119
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4266230598
Short name T1009
Test name
Test status
Simulation time 698263057 ps
CPU time 2.28 seconds
Started Jan 07 12:54:35 PM PST 24
Finished Jan 07 12:56:18 PM PST 24
Peak memory 198268 kb
Host smart-e47b27ef-3b93-4a9e-8f2c-a8887d68bbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266230598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4266230598
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1160478697
Short name T239
Test name
Test status
Simulation time 16311774257 ps
CPU time 51.08 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:58:11 PM PST 24
Peak memory 199880 kb
Host smart-a7f19d28-c004-4317-8b86-d6d7d56d906d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160478697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1160478697
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3177017725
Short name T526
Test name
Test status
Simulation time 97280049255 ps
CPU time 25.11 seconds
Started Jan 07 12:55:15 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 199644 kb
Host smart-291b2543-330f-43be-bdea-05cde1412e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177017725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3177017725
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1441127546
Short name T272
Test name
Test status
Simulation time 56823508115 ps
CPU time 25.29 seconds
Started Jan 07 12:55:42 PM PST 24
Finished Jan 07 12:57:34 PM PST 24
Peak memory 200152 kb
Host smart-8333b041-5fd3-4117-80ad-88699fb35e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441127546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1441127546
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2154566014
Short name T187
Test name
Test status
Simulation time 25016918030 ps
CPU time 45.47 seconds
Started Jan 07 12:55:50 PM PST 24
Finished Jan 07 12:58:05 PM PST 24
Peak memory 200168 kb
Host smart-d994a89b-5c46-41bf-a807-9b45a26771ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154566014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2154566014
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.4055572628
Short name T155
Test name
Test status
Simulation time 18762348755 ps
CPU time 10.21 seconds
Started Jan 07 12:55:51 PM PST 24
Finished Jan 07 12:57:46 PM PST 24
Peak memory 200032 kb
Host smart-a7fd821a-b374-4584-b7b6-92abc204f150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055572628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.4055572628
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.676581865
Short name T859
Test name
Test status
Simulation time 26892176764 ps
CPU time 22.98 seconds
Started Jan 07 12:55:10 PM PST 24
Finished Jan 07 12:56:51 PM PST 24
Peak memory 200240 kb
Host smart-66b6ae54-34ea-44de-81f1-2d41038b33f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676581865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.676581865
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2715422543
Short name T1043
Test name
Test status
Simulation time 35289493 ps
CPU time 0.56 seconds
Started Jan 07 12:54:19 PM PST 24
Finished Jan 07 12:55:49 PM PST 24
Peak memory 195600 kb
Host smart-0911c7a1-e49b-4a20-9210-b88799fa4302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715422543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2715422543
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2089632716
Short name T936
Test name
Test status
Simulation time 90745756575 ps
CPU time 32.54 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 12:56:11 PM PST 24
Peak memory 200044 kb
Host smart-65f5178a-1431-4fb6-a940-46b39098ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089632716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2089632716
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1066301024
Short name T252
Test name
Test status
Simulation time 31880057412 ps
CPU time 13.11 seconds
Started Jan 07 12:54:06 PM PST 24
Finished Jan 07 12:55:40 PM PST 24
Peak memory 200256 kb
Host smart-b867a6ae-f43f-44d7-b7ae-2c760181f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066301024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1066301024
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1056045444
Short name T316
Test name
Test status
Simulation time 82820657701 ps
CPU time 14.54 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:55:57 PM PST 24
Peak memory 200208 kb
Host smart-c5ba798c-e798-4bca-b012-20fba1da8243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056045444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1056045444
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_loopback.3455170716
Short name T726
Test name
Test status
Simulation time 4564505446 ps
CPU time 2.01 seconds
Started Jan 07 12:54:11 PM PST 24
Finished Jan 07 12:55:50 PM PST 24
Peak memory 198440 kb
Host smart-d23b837e-69ad-48d6-b0f7-541f655edc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455170716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3455170716
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1138071472
Short name T654
Test name
Test status
Simulation time 113766331860 ps
CPU time 74.51 seconds
Started Jan 07 12:54:07 PM PST 24
Finished Jan 07 12:56:54 PM PST 24
Peak memory 208412 kb
Host smart-bf9cb3bb-e2bc-4c1a-a979-cb11ce1343b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138071472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1138071472
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.1661163216
Short name T268
Test name
Test status
Simulation time 11124949393 ps
CPU time 574.56 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 01:06:12 PM PST 24
Peak memory 200152 kb
Host smart-8cb1804e-8d7f-4ed0-8a9b-e0245ee4e4fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661163216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1661163216
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3815754379
Short name T1039
Test name
Test status
Simulation time 3738580606 ps
CPU time 8.64 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:55:48 PM PST 24
Peak memory 198220 kb
Host smart-9613951a-624b-4efc-ae7a-2e737414476f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815754379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3815754379
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2155245090
Short name T899
Test name
Test status
Simulation time 1566481816 ps
CPU time 1.94 seconds
Started Jan 07 12:54:05 PM PST 24
Finished Jan 07 12:55:31 PM PST 24
Peak memory 195580 kb
Host smart-472e1b51-70cf-4ea5-a8dd-e5ad0ae40b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155245090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2155245090
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1199041791
Short name T370
Test name
Test status
Simulation time 926608601 ps
CPU time 3.34 seconds
Started Jan 07 12:54:24 PM PST 24
Finished Jan 07 12:56:06 PM PST 24
Peak memory 198204 kb
Host smart-6e0efdd9-46c9-456d-8966-175278ea43a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199041791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1199041791
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3487799769
Short name T1001
Test name
Test status
Simulation time 69791736633 ps
CPU time 580.47 seconds
Started Jan 07 12:54:39 PM PST 24
Finished Jan 07 01:05:37 PM PST 24
Peak memory 216604 kb
Host smart-e1a0f811-6fbf-4c71-a71b-57fe24ed9bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487799769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3487799769
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_rx.288628581
Short name T583
Test name
Test status
Simulation time 2004282219 ps
CPU time 1.12 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 12:56:10 PM PST 24
Peak memory 195976 kb
Host smart-0c04c883-ba87-4a76-8ba2-9ab623fad686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288628581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.288628581
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.4251570322
Short name T105
Test name
Test status
Simulation time 45430794140 ps
CPU time 36.5 seconds
Started Jan 07 12:55:43 PM PST 24
Finished Jan 07 12:58:03 PM PST 24
Peak memory 200148 kb
Host smart-0457a1be-0d11-4305-ad04-5cd4fb621bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251570322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.4251570322
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2091334882
Short name T223
Test name
Test status
Simulation time 14165217729 ps
CPU time 21.39 seconds
Started Jan 07 12:55:26 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 200140 kb
Host smart-3f02175a-67ef-43b8-9243-33a2738d0fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091334882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2091334882
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4074873714
Short name T216
Test name
Test status
Simulation time 16860354009 ps
CPU time 23.22 seconds
Started Jan 07 12:55:46 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 199196 kb
Host smart-6e65aaee-0b09-44d2-a0d4-073fa906e74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074873714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4074873714
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.598054877
Short name T227
Test name
Test status
Simulation time 158381648977 ps
CPU time 130.23 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:59:08 PM PST 24
Peak memory 200172 kb
Host smart-5804076d-283d-4ae4-9b9c-a55509f2b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598054877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.598054877
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3518622508
Short name T565
Test name
Test status
Simulation time 31497461165 ps
CPU time 28.13 seconds
Started Jan 07 12:55:46 PM PST 24
Finished Jan 07 12:57:52 PM PST 24
Peak memory 200112 kb
Host smart-b10ff931-989c-412c-8aed-18aa2b7011c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518622508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3518622508
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.663939684
Short name T849
Test name
Test status
Simulation time 218352076443 ps
CPU time 39.16 seconds
Started Jan 07 12:56:01 PM PST 24
Finished Jan 07 12:58:29 PM PST 24
Peak memory 200076 kb
Host smart-11d3f9f9-ef6d-4b0b-b0f8-c5e8cffe8456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663939684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.663939684
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1882543140
Short name T140
Test name
Test status
Simulation time 46273837256 ps
CPU time 20.47 seconds
Started Jan 07 12:55:20 PM PST 24
Finished Jan 07 12:57:33 PM PST 24
Peak memory 200236 kb
Host smart-f189915d-ab0d-4ea5-ae21-30701d70b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882543140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1882543140
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1344602828
Short name T595
Test name
Test status
Simulation time 33291816 ps
CPU time 0.53 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:54:41 PM PST 24
Peak memory 195528 kb
Host smart-06a67a4e-e792-4d9e-8ab8-6dde0035fe86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344602828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1344602828
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.131454695
Short name T734
Test name
Test status
Simulation time 241933043077 ps
CPU time 338.4 seconds
Started Jan 07 12:53:15 PM PST 24
Finished Jan 07 01:00:11 PM PST 24
Peak memory 200296 kb
Host smart-9454e489-ce99-4056-bbdd-5603901017b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131454695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.131454695
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.529007467
Short name T224
Test name
Test status
Simulation time 184518178247 ps
CPU time 29.65 seconds
Started Jan 07 12:53:59 PM PST 24
Finished Jan 07 12:56:08 PM PST 24
Peak memory 199672 kb
Host smart-062526c9-573f-4062-acfd-005bf029f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529007467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.529007467
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1451227071
Short name T323
Test name
Test status
Simulation time 61425152419 ps
CPU time 28.06 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:55:10 PM PST 24
Peak memory 199976 kb
Host smart-ed48a001-ddc5-4b0c-a66e-cb441e82486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451227071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1451227071
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3581645948
Short name T504
Test name
Test status
Simulation time 60359502237 ps
CPU time 83.16 seconds
Started Jan 07 12:53:12 PM PST 24
Finished Jan 07 12:55:48 PM PST 24
Peak memory 198340 kb
Host smart-34b72935-ca55-4ef5-9986-091701b5cde3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581645948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3581645948
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2691143534
Short name T1033
Test name
Test status
Simulation time 132758824474 ps
CPU time 916.05 seconds
Started Jan 07 12:53:21 PM PST 24
Finished Jan 07 01:09:52 PM PST 24
Peak memory 200180 kb
Host smart-50660c22-3bff-4ffd-b9c3-8561a264111f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691143534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2691143534
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.950739217
Short name T1019
Test name
Test status
Simulation time 10274397552 ps
CPU time 5.34 seconds
Started Jan 07 12:53:25 PM PST 24
Finished Jan 07 12:54:42 PM PST 24
Peak memory 198964 kb
Host smart-fca48420-ab88-481e-87d8-97ddd6fa923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950739217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.950739217
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2234117375
Short name T126
Test name
Test status
Simulation time 94386705095 ps
CPU time 236.2 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 12:58:55 PM PST 24
Peak memory 199040 kb
Host smart-3793b35e-fbe7-458c-bd1a-84ee9fbde511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234117375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2234117375
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.4041332216
Short name T562
Test name
Test status
Simulation time 21133927706 ps
CPU time 155.63 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 12:57:15 PM PST 24
Peak memory 200092 kb
Host smart-d5f14e9d-1324-4c3d-beaa-7db4ba95044d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041332216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4041332216
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.431800825
Short name T839
Test name
Test status
Simulation time 4129596426 ps
CPU time 9.55 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 12:54:58 PM PST 24
Peak memory 198708 kb
Host smart-85a37346-858a-4000-aa44-ca73c74268d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431800825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.431800825
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1895522103
Short name T769
Test name
Test status
Simulation time 25884963862 ps
CPU time 12.34 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:54:53 PM PST 24
Peak memory 199392 kb
Host smart-9f58b9d5-31c2-4a92-becc-00911e8b938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895522103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1895522103
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2198837713
Short name T71
Test name
Test status
Simulation time 43958131 ps
CPU time 0.75 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:54:31 PM PST 24
Peak memory 217640 kb
Host smart-b2024681-8970-4bbd-9a20-01393cb5f339
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198837713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2198837713
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2402438137
Short name T912
Test name
Test status
Simulation time 5874316686 ps
CPU time 8.1 seconds
Started Jan 07 12:53:23 PM PST 24
Finished Jan 07 12:54:53 PM PST 24
Peak memory 198896 kb
Host smart-c13ef912-07cd-419f-bb3c-590fac437f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402438137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2402438137
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1562769330
Short name T994
Test name
Test status
Simulation time 669979429655 ps
CPU time 1145.94 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 01:13:41 PM PST 24
Peak memory 200188 kb
Host smart-e3b4ed5d-4dca-4db3-8c66-2c580673a715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562769330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1562769330
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1768261286
Short name T355
Test name
Test status
Simulation time 1517988005 ps
CPU time 2.9 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 12:54:53 PM PST 24
Peak memory 199064 kb
Host smart-fa7b3b81-c922-446e-b6c5-99146d14ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768261286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1768261286
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2488100822
Short name T611
Test name
Test status
Simulation time 63928388415 ps
CPU time 49.3 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:55:13 PM PST 24
Peak memory 200240 kb
Host smart-1ed65729-47b7-4d24-9a17-d73a0b41145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488100822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2488100822
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1572054703
Short name T836
Test name
Test status
Simulation time 26885189 ps
CPU time 0.53 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 12:55:41 PM PST 24
Peak memory 194572 kb
Host smart-beb10ddb-c021-4d07-8207-d58708bb094f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572054703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1572054703
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1423774027
Short name T931
Test name
Test status
Simulation time 225972783568 ps
CPU time 400.67 seconds
Started Jan 07 12:54:12 PM PST 24
Finished Jan 07 01:02:09 PM PST 24
Peak memory 199700 kb
Host smart-938a0c62-c4a0-4d4d-bfad-e604c5cc897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423774027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1423774027
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2113739516
Short name T965
Test name
Test status
Simulation time 239304099398 ps
CPU time 252.87 seconds
Started Jan 07 12:54:10 PM PST 24
Finished Jan 07 12:59:50 PM PST 24
Peak memory 200104 kb
Host smart-bc878b5f-8b72-4b5a-9422-31dea726a9d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2113739516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2113739516
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3569476177
Short name T5
Test name
Test status
Simulation time 3020409643 ps
CPU time 7.98 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 199064 kb
Host smart-662a9fa3-4293-433f-b57b-f62208542844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569476177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3569476177
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2457856504
Short name T622
Test name
Test status
Simulation time 111879627144 ps
CPU time 65.55 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 12:57:26 PM PST 24
Peak memory 200280 kb
Host smart-fbb2d3f8-d9da-4c3b-8351-bcf099b900b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457856504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2457856504
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1432890523
Short name T897
Test name
Test status
Simulation time 16880340312 ps
CPU time 120.87 seconds
Started Jan 07 12:54:26 PM PST 24
Finished Jan 07 12:58:17 PM PST 24
Peak memory 200092 kb
Host smart-53eeab77-0297-4645-948f-09ee7776ccad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432890523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1432890523
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3008444328
Short name T969
Test name
Test status
Simulation time 2855321271 ps
CPU time 16.38 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:56:05 PM PST 24
Peak memory 198220 kb
Host smart-42a32f1d-7940-4ffb-b66b-c71cced82a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008444328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3008444328
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1314033647
Short name T673
Test name
Test status
Simulation time 58294632948 ps
CPU time 25.74 seconds
Started Jan 07 12:54:53 PM PST 24
Finished Jan 07 12:57:02 PM PST 24
Peak memory 200200 kb
Host smart-bbfb6f35-6152-48a7-94d8-50ba85c35ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314033647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1314033647
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3516540341
Short name T506
Test name
Test status
Simulation time 2718430208 ps
CPU time 0.95 seconds
Started Jan 07 12:54:23 PM PST 24
Finished Jan 07 12:56:00 PM PST 24
Peak memory 195596 kb
Host smart-0ad4e56c-a55c-4a06-973c-893fdf8bb882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516540341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3516540341
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1041083059
Short name T971
Test name
Test status
Simulation time 6316448599 ps
CPU time 21.41 seconds
Started Jan 07 12:54:52 PM PST 24
Finished Jan 07 12:56:38 PM PST 24
Peak memory 199100 kb
Host smart-d05e968b-0fa0-450a-9764-9ffe4ef00c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041083059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1041083059
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.620909349
Short name T394
Test name
Test status
Simulation time 34591674048 ps
CPU time 31.73 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:56:55 PM PST 24
Peak memory 200256 kb
Host smart-dc584c18-6cb9-469e-844e-9955f2835599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620909349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.620909349
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2441483969
Short name T930
Test name
Test status
Simulation time 34752345 ps
CPU time 0.57 seconds
Started Jan 07 12:54:06 PM PST 24
Finished Jan 07 12:55:27 PM PST 24
Peak memory 195568 kb
Host smart-def99132-b062-4da2-ac72-8f001f1266d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441483969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2441483969
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1648128073
Short name T307
Test name
Test status
Simulation time 462422097455 ps
CPU time 45.11 seconds
Started Jan 07 12:54:23 PM PST 24
Finished Jan 07 12:56:47 PM PST 24
Peak memory 200052 kb
Host smart-7a8a18ce-d79c-49b9-93a5-46b84edb62fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648128073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1648128073
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1060820156
Short name T575
Test name
Test status
Simulation time 20255539097 ps
CPU time 6.51 seconds
Started Jan 07 12:54:28 PM PST 24
Finished Jan 07 12:56:27 PM PST 24
Peak memory 197556 kb
Host smart-b6ede792-b4ac-4e90-a8b3-6a5df7cc7479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060820156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1060820156
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3532841082
Short name T744
Test name
Test status
Simulation time 28192125589 ps
CPU time 39.99 seconds
Started Jan 07 12:55:02 PM PST 24
Finished Jan 07 12:57:32 PM PST 24
Peak memory 199732 kb
Host smart-2a21ef4b-a8f0-45a7-89f2-25d74048989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532841082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3532841082
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2151443586
Short name T863
Test name
Test status
Simulation time 830437355991 ps
CPU time 1248.09 seconds
Started Jan 07 12:54:49 PM PST 24
Finished Jan 07 01:17:14 PM PST 24
Peak memory 200088 kb
Host smart-c34fe094-c67d-4a62-b7a2-08f0817f838a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151443586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2151443586
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.175460700
Short name T777
Test name
Test status
Simulation time 90343305690 ps
CPU time 437.64 seconds
Started Jan 07 12:54:15 PM PST 24
Finished Jan 07 01:03:02 PM PST 24
Peak memory 200124 kb
Host smart-b55410c9-2e1a-405d-855d-e13b47631981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=175460700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.175460700
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.404349853
Short name T398
Test name
Test status
Simulation time 1191644893 ps
CPU time 4.28 seconds
Started Jan 07 12:54:27 PM PST 24
Finished Jan 07 12:56:16 PM PST 24
Peak memory 197840 kb
Host smart-f405c995-c264-4ddc-b4d7-721127dd7ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404349853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.404349853
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3603183942
Short name T851
Test name
Test status
Simulation time 37225071913 ps
CPU time 37.28 seconds
Started Jan 07 12:56:12 PM PST 24
Finished Jan 07 12:58:16 PM PST 24
Peak memory 198848 kb
Host smart-3c78542d-dc29-424a-a351-a14128fe0b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603183942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3603183942
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3803335251
Short name T893
Test name
Test status
Simulation time 20042681625 ps
CPU time 483.17 seconds
Started Jan 07 12:54:10 PM PST 24
Finished Jan 07 01:03:33 PM PST 24
Peak memory 200104 kb
Host smart-a80759f0-c4d4-41b1-b2c1-8398cdbdf0c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803335251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3803335251
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3460615357
Short name T867
Test name
Test status
Simulation time 4280004341 ps
CPU time 33.43 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 12:56:50 PM PST 24
Peak memory 198760 kb
Host smart-0109bc9e-72fa-4920-8c0e-319bdef8c259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460615357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3460615357
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.969951898
Short name T172
Test name
Test status
Simulation time 182410652447 ps
CPU time 185.76 seconds
Started Jan 07 12:54:42 PM PST 24
Finished Jan 07 12:59:19 PM PST 24
Peak memory 200120 kb
Host smart-626eba9d-49e2-4a72-a2ba-ca2f21f7eadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969951898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.969951898
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2224507053
Short name T538
Test name
Test status
Simulation time 3632717225 ps
CPU time 5.87 seconds
Started Jan 07 12:54:19 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 195948 kb
Host smart-8fc9292d-027c-4ff8-a35c-46ee41dcc4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224507053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2224507053
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_stress_all.1147533478
Short name T321
Test name
Test status
Simulation time 58482386685 ps
CPU time 24.75 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:55:56 PM PST 24
Peak memory 200172 kb
Host smart-3aeea12d-6067-4d9b-a0f2-59f3d032b148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147533478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1147533478
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1158769341
Short name T535
Test name
Test status
Simulation time 1317653423 ps
CPU time 1.54 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 12:56:16 PM PST 24
Peak memory 197744 kb
Host smart-a68c1319-d48f-4ece-bc89-92e11e0b52bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158769341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1158769341
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2664422952
Short name T1042
Test name
Test status
Simulation time 55113143620 ps
CPU time 39.57 seconds
Started Jan 07 12:54:37 PM PST 24
Finished Jan 07 12:56:33 PM PST 24
Peak memory 200252 kb
Host smart-cba9b268-c0e5-4d17-a47d-2d1bf076b6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664422952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2664422952
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2358329091
Short name T405
Test name
Test status
Simulation time 14632370 ps
CPU time 0.55 seconds
Started Jan 07 12:54:41 PM PST 24
Finished Jan 07 12:56:00 PM PST 24
Peak memory 195588 kb
Host smart-89a883c5-a991-438c-a297-a4e0009cd287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358329091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2358329091
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2629089147
Short name T1021
Test name
Test status
Simulation time 224926828983 ps
CPU time 91.58 seconds
Started Jan 07 12:54:32 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 200256 kb
Host smart-f97a0c7c-7249-490a-b906-f6e3fb1c74f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629089147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2629089147
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2684868986
Short name T329
Test name
Test status
Simulation time 38236129652 ps
CPU time 13.11 seconds
Started Jan 07 12:54:42 PM PST 24
Finished Jan 07 12:56:25 PM PST 24
Peak memory 199444 kb
Host smart-a3bc628d-7a21-4cb6-85e8-67150dd0f0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684868986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2684868986
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.171634413
Short name T981
Test name
Test status
Simulation time 10495662400 ps
CPU time 13.19 seconds
Started Jan 07 12:54:28 PM PST 24
Finished Jan 07 12:56:26 PM PST 24
Peak memory 199912 kb
Host smart-01bab376-866b-4b61-a1d8-316ade6135fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171634413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.171634413
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3455805606
Short name T826
Test name
Test status
Simulation time 169046176192 ps
CPU time 257.33 seconds
Started Jan 07 12:54:37 PM PST 24
Finished Jan 07 01:00:19 PM PST 24
Peak memory 198444 kb
Host smart-90b078e6-9674-4367-b8d9-78196a122788
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455805606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3455805606
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1447201366
Short name T522
Test name
Test status
Simulation time 64177759093 ps
CPU time 301.92 seconds
Started Jan 07 12:54:04 PM PST 24
Finished Jan 07 01:00:19 PM PST 24
Peak memory 200140 kb
Host smart-a0139277-ea2f-41fc-8f55-11531328f6b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447201366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1447201366
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2480743641
Short name T728
Test name
Test status
Simulation time 41047010148 ps
CPU time 78.18 seconds
Started Jan 07 12:54:11 PM PST 24
Finished Jan 07 12:57:54 PM PST 24
Peak memory 208576 kb
Host smart-23cae40f-3287-4c74-a337-1468817ef530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480743641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2480743641
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1316494235
Short name T620
Test name
Test status
Simulation time 15928105614 ps
CPU time 465.52 seconds
Started Jan 07 12:54:50 PM PST 24
Finished Jan 07 01:04:10 PM PST 24
Peak memory 200188 kb
Host smart-e5996bee-5700-49e9-9416-a3fcf0674ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1316494235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1316494235
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3031841108
Short name T638
Test name
Test status
Simulation time 3645786495 ps
CPU time 9.12 seconds
Started Jan 07 12:54:02 PM PST 24
Finished Jan 07 12:55:23 PM PST 24
Peak memory 199088 kb
Host smart-cbff6a9c-e469-4157-800c-4103db494f29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031841108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3031841108
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1989486689
Short name T350
Test name
Test status
Simulation time 100693059944 ps
CPU time 175.61 seconds
Started Jan 07 12:54:47 PM PST 24
Finished Jan 07 12:59:11 PM PST 24
Peak memory 200184 kb
Host smart-047186a1-91f9-4b88-ab19-9aceb8385212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989486689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1989486689
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1421064698
Short name T718
Test name
Test status
Simulation time 4000455583 ps
CPU time 7.37 seconds
Started Jan 07 12:54:01 PM PST 24
Finished Jan 07 12:56:47 PM PST 24
Peak memory 195816 kb
Host smart-394ee5bb-9589-4dde-9a12-9ef9269f35e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421064698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1421064698
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1871348125
Short name T707
Test name
Test status
Simulation time 6053611769 ps
CPU time 12.27 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 12:56:45 PM PST 24
Peak memory 198960 kb
Host smart-773969ff-5507-4628-9d6f-c7217253ce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871348125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1871348125
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.389831766
Short name T903
Test name
Test status
Simulation time 227429967239 ps
CPU time 237.68 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 01:00:53 PM PST 24
Peak memory 208748 kb
Host smart-a35adf9b-cf2e-4818-b254-667a55467fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389831766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.389831766
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3096458378
Short name T906
Test name
Test status
Simulation time 131301436849 ps
CPU time 42.16 seconds
Started Jan 07 12:54:11 PM PST 24
Finished Jan 07 12:56:16 PM PST 24
Peak memory 200032 kb
Host smart-9791b230-9dc1-44cd-8671-58f66aebb822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096458378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3096458378
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2963796878
Short name T579
Test name
Test status
Simulation time 28286048207 ps
CPU time 43.78 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 12:56:58 PM PST 24
Peak memory 200224 kb
Host smart-3690c7e7-df5d-46b8-99f5-96452b3411f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963796878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2963796878
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3581633079
Short name T963
Test name
Test status
Simulation time 161802116977 ps
CPU time 279.82 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 01:00:22 PM PST 24
Peak memory 200136 kb
Host smart-0aa6f745-0257-4a4d-9e6c-38cb3435bacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581633079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3581633079
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1922512802
Short name T904
Test name
Test status
Simulation time 58261869717 ps
CPU time 14 seconds
Started Jan 07 12:54:08 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 200136 kb
Host smart-f9e39a4d-fc7b-43ee-bea3-71327ee55b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922512802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1922512802
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.4203329342
Short name T651
Test name
Test status
Simulation time 67345782092 ps
CPU time 272.86 seconds
Started Jan 07 12:54:17 PM PST 24
Finished Jan 07 01:00:06 PM PST 24
Peak memory 200120 kb
Host smart-af4d9b5e-6b4b-4035-b8ca-ce42064986fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203329342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4203329342
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.217432491
Short name T608
Test name
Test status
Simulation time 14238758965 ps
CPU time 5.94 seconds
Started Jan 07 12:54:20 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 199288 kb
Host smart-0b80f035-5fc1-414c-99f6-027d41fb267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217432491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.217432491
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2263234777
Short name T521
Test name
Test status
Simulation time 83332301280 ps
CPU time 159.16 seconds
Started Jan 07 12:54:31 PM PST 24
Finished Jan 07 12:58:52 PM PST 24
Peak memory 199188 kb
Host smart-2de048d6-3fdb-4f05-bdbd-932188983fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263234777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2263234777
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1243411399
Short name T879
Test name
Test status
Simulation time 8904985165 ps
CPU time 37.81 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:57:06 PM PST 24
Peak memory 200188 kb
Host smart-4df864d9-ba87-4e03-bee8-9d52b23e3c2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243411399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1243411399
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2859646299
Short name T723
Test name
Test status
Simulation time 2376674265 ps
CPU time 8.54 seconds
Started Jan 07 12:54:23 PM PST 24
Finished Jan 07 12:56:05 PM PST 24
Peak memory 198628 kb
Host smart-75ac3257-4ad1-411e-8f6b-dab39cb2dbaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859646299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2859646299
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4271236481
Short name T571
Test name
Test status
Simulation time 148805211042 ps
CPU time 217.17 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:59:18 PM PST 24
Peak memory 200192 kb
Host smart-f96d9a00-828c-4bce-af99-007a92a89ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271236481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4271236481
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1425384826
Short name T666
Test name
Test status
Simulation time 2042966159 ps
CPU time 3.81 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:55:37 PM PST 24
Peak memory 195640 kb
Host smart-32f65f95-a7fe-4155-a59c-435f27e95b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425384826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1425384826
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2256688477
Short name T383
Test name
Test status
Simulation time 714767686 ps
CPU time 2.2 seconds
Started Jan 07 12:54:10 PM PST 24
Finished Jan 07 12:55:39 PM PST 24
Peak memory 197996 kb
Host smart-618d6809-0bd4-46f0-b41f-2055698e422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256688477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2256688477
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3599864695
Short name T401
Test name
Test status
Simulation time 34516780745 ps
CPU time 245.91 seconds
Started Jan 07 12:54:52 PM PST 24
Finished Jan 07 01:00:23 PM PST 24
Peak memory 216900 kb
Host smart-f78d4c90-f52a-4ef9-a065-0056013e8a37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599864695 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3599864695
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.11529545
Short name T722
Test name
Test status
Simulation time 841266458 ps
CPU time 2.57 seconds
Started Jan 07 12:54:40 PM PST 24
Finished Jan 07 12:56:03 PM PST 24
Peak memory 198484 kb
Host smart-e414390e-469f-469b-9edb-6263c3d9cf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11529545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.11529545
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_alert_test.2736654267
Short name T24
Test name
Test status
Simulation time 14185561 ps
CPU time 0.53 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 12:55:49 PM PST 24
Peak memory 195572 kb
Host smart-cc9aa3dd-3854-4010-8d36-b55a1614c2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736654267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2736654267
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.4168360957
Short name T928
Test name
Test status
Simulation time 24553780135 ps
CPU time 41.43 seconds
Started Jan 07 12:54:56 PM PST 24
Finished Jan 07 12:57:01 PM PST 24
Peak memory 200140 kb
Host smart-799a5120-cde2-4599-a9ae-03575d7acec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168360957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4168360957
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_intr.4004986959
Short name T500
Test name
Test status
Simulation time 10143850738 ps
CPU time 5.24 seconds
Started Jan 07 12:54:24 PM PST 24
Finished Jan 07 12:55:45 PM PST 24
Peak memory 197164 kb
Host smart-b61f1744-cea6-4546-8df7-fb9f3971a1f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004986959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4004986959
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3655877234
Short name T539
Test name
Test status
Simulation time 38886203346 ps
CPU time 211.06 seconds
Started Jan 07 12:54:37 PM PST 24
Finished Jan 07 12:59:40 PM PST 24
Peak memory 200048 kb
Host smart-21e6c9c0-428e-4e11-8957-c37564f06fae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655877234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3655877234
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2647555323
Short name T594
Test name
Test status
Simulation time 143555896 ps
CPU time 0.82 seconds
Started Jan 07 12:54:05 PM PST 24
Finished Jan 07 12:55:18 PM PST 24
Peak memory 197020 kb
Host smart-3bbf66e4-8f76-4239-aae8-4028177bcd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647555323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2647555323
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.107647129
Short name T683
Test name
Test status
Simulation time 68084248613 ps
CPU time 36.04 seconds
Started Jan 07 12:54:23 PM PST 24
Finished Jan 07 12:56:32 PM PST 24
Peak memory 208508 kb
Host smart-8a891d2d-5336-477d-a262-b0a8fcc51136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107647129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.107647129
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1691468043
Short name T934
Test name
Test status
Simulation time 423524629 ps
CPU time 5.16 seconds
Started Jan 07 12:54:23 PM PST 24
Finished Jan 07 12:56:32 PM PST 24
Peak memory 197768 kb
Host smart-dbfada88-2c3d-4f47-9610-526ed0e54d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1691468043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1691468043
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.164034821
Short name T1004
Test name
Test status
Simulation time 131391266775 ps
CPU time 53.35 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:57:07 PM PST 24
Peak memory 200140 kb
Host smart-6bb3f32d-b45a-4200-a723-8c2d3c4a95ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164034821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.164034821
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2761364742
Short name T680
Test name
Test status
Simulation time 31014795111 ps
CPU time 50.19 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:56:21 PM PST 24
Peak memory 196040 kb
Host smart-456df92d-09a8-473e-8708-051008ca8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761364742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2761364742
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1492528428
Short name T840
Test name
Test status
Simulation time 11617644882 ps
CPU time 31.66 seconds
Started Jan 07 12:54:25 PM PST 24
Finished Jan 07 12:56:36 PM PST 24
Peak memory 199744 kb
Host smart-da642176-a885-4fa4-8fe4-b555f343ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492528428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1492528428
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2593123499
Short name T396
Test name
Test status
Simulation time 293356805863 ps
CPU time 183.66 seconds
Started Jan 07 12:54:10 PM PST 24
Finished Jan 07 12:58:46 PM PST 24
Peak memory 216032 kb
Host smart-a5d858b2-0bbc-4999-b0c7-71f16d210021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593123499 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2593123499
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3031448380
Short name T749
Test name
Test status
Simulation time 6850622355 ps
CPU time 14.86 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:56:04 PM PST 24
Peak memory 199608 kb
Host smart-a673cad4-0b00-47db-8d55-fa35be764684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031448380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3031448380
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2754315588
Short name T968
Test name
Test status
Simulation time 101805029126 ps
CPU time 59.93 seconds
Started Jan 07 12:54:28 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 200064 kb
Host smart-18900f6f-72fb-4b75-8a21-3d0a0394de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754315588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2754315588
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1894287467
Short name T858
Test name
Test status
Simulation time 11811596 ps
CPU time 0.53 seconds
Started Jan 07 12:54:18 PM PST 24
Finished Jan 07 12:55:41 PM PST 24
Peak memory 194484 kb
Host smart-e01d3804-d328-43ca-8e6a-d330562d19d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894287467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1894287467
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3701903736
Short name T245
Test name
Test status
Simulation time 37290663785 ps
CPU time 13.26 seconds
Started Jan 07 12:54:39 PM PST 24
Finished Jan 07 12:56:29 PM PST 24
Peak memory 200136 kb
Host smart-c8fedffd-99dc-41b0-ba23-2575254c62c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701903736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3701903736
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_intr.2775086762
Short name T581
Test name
Test status
Simulation time 94604924743 ps
CPU time 78.51 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:56:57 PM PST 24
Peak memory 200024 kb
Host smart-e594f77a-297a-4f09-843c-67caa31290b1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775086762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2775086762
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3790827380
Short name T910
Test name
Test status
Simulation time 72011971100 ps
CPU time 286.37 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 01:00:40 PM PST 24
Peak memory 200152 kb
Host smart-082c9b79-9d3c-4c75-9fac-75e1f16e477a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790827380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3790827380
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1614905919
Short name T961
Test name
Test status
Simulation time 818028466 ps
CPU time 2.1 seconds
Started Jan 07 12:54:08 PM PST 24
Finished Jan 07 12:55:42 PM PST 24
Peak memory 195860 kb
Host smart-d6e38e1a-7211-4353-a2a9-6085aed93ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614905919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1614905919
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2626712724
Short name T382
Test name
Test status
Simulation time 54455117621 ps
CPU time 23.29 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:56:02 PM PST 24
Peak memory 200104 kb
Host smart-f7175ed6-f0f2-46c0-ad4a-e3fd05c2e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626712724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2626712724
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.797653516
Short name T660
Test name
Test status
Simulation time 10874476159 ps
CPU time 154.51 seconds
Started Jan 07 12:54:50 PM PST 24
Finished Jan 07 12:58:49 PM PST 24
Peak memory 200256 kb
Host smart-66964e01-8d8c-4758-82ac-5bdfabf44351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797653516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.797653516
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2925159732
Short name T591
Test name
Test status
Simulation time 124503436 ps
CPU time 0.64 seconds
Started Jan 07 12:54:01 PM PST 24
Finished Jan 07 12:55:15 PM PST 24
Peak memory 195616 kb
Host smart-e535a31d-ec9c-4f6f-a81a-248807854688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925159732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2925159732
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.63508003
Short name T834
Test name
Test status
Simulation time 192428026072 ps
CPU time 38.33 seconds
Started Jan 07 12:54:08 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 200136 kb
Host smart-b7823f90-c017-4d02-aa3c-521ae5d186a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63508003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.63508003
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3958309859
Short name T810
Test name
Test status
Simulation time 1338647723 ps
CPU time 2.34 seconds
Started Jan 07 12:54:45 PM PST 24
Finished Jan 07 12:56:18 PM PST 24
Peak memory 198120 kb
Host smart-163d9591-74dc-44aa-ba50-043102334354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958309859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3958309859
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2617781864
Short name T656
Test name
Test status
Simulation time 55447739835 ps
CPU time 94 seconds
Started Jan 07 12:54:04 PM PST 24
Finished Jan 07 12:56:57 PM PST 24
Peak memory 200132 kb
Host smart-8708c675-8603-49f4-9a49-27a63fc9f70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617781864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2617781864
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.754124352
Short name T854
Test name
Test status
Simulation time 11505808 ps
CPU time 0.53 seconds
Started Jan 07 12:54:22 PM PST 24
Finished Jan 07 12:55:38 PM PST 24
Peak memory 195648 kb
Host smart-4772376a-e344-43ca-9546-781961ffc9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754124352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.754124352
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2011565781
Short name T831
Test name
Test status
Simulation time 55509395979 ps
CPU time 17.49 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:55:55 PM PST 24
Peak memory 200160 kb
Host smart-20a0b3d5-ef1b-42bd-80de-459a07913e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011565781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2011565781
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3949379506
Short name T112
Test name
Test status
Simulation time 12674371901 ps
CPU time 23 seconds
Started Jan 07 12:54:45 PM PST 24
Finished Jan 07 12:56:31 PM PST 24
Peak memory 200192 kb
Host smart-3e3de74d-b170-4fc2-8ec7-33bef2c5c485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949379506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3949379506
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3419049370
Short name T882
Test name
Test status
Simulation time 16937259425 ps
CPU time 10.24 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 200144 kb
Host smart-6139c298-6c99-425b-8277-d684ba9f3bc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419049370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3419049370
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.778453487
Short name T950
Test name
Test status
Simulation time 57601458811 ps
CPU time 433.1 seconds
Started Jan 07 12:54:32 PM PST 24
Finished Jan 07 01:03:10 PM PST 24
Peak memory 200128 kb
Host smart-723e3383-38d6-43df-bf2e-b9d321fdfa53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778453487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.778453487
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3171713374
Short name T517
Test name
Test status
Simulation time 9547579831 ps
CPU time 16.71 seconds
Started Jan 07 12:54:43 PM PST 24
Finished Jan 07 12:56:40 PM PST 24
Peak memory 199552 kb
Host smart-ad2a4e12-450e-4b84-9251-c80326629e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171713374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3171713374
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.3745590743
Short name T976
Test name
Test status
Simulation time 9005507323 ps
CPU time 250.91 seconds
Started Jan 07 12:54:43 PM PST 24
Finished Jan 07 01:00:40 PM PST 24
Peak memory 200164 kb
Host smart-ee711ce6-4748-4480-8a30-53e88a2d43fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745590743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3745590743
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2723495926
Short name T815
Test name
Test status
Simulation time 2394124257 ps
CPU time 16.49 seconds
Started Jan 07 12:54:35 PM PST 24
Finished Jan 07 12:56:35 PM PST 24
Peak memory 198028 kb
Host smart-09277f9c-db8e-4e08-818a-3ca6cca361f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723495926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2723495926
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2010223635
Short name T1014
Test name
Test status
Simulation time 39051860125 ps
CPU time 61.07 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:56:38 PM PST 24
Peak memory 199356 kb
Host smart-d6441bca-af19-492d-b943-a1ac1cf60d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010223635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2010223635
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.591579652
Short name T763
Test name
Test status
Simulation time 42149437352 ps
CPU time 30.06 seconds
Started Jan 07 12:54:50 PM PST 24
Finished Jan 07 12:56:58 PM PST 24
Peak memory 195924 kb
Host smart-4e25e1ad-6364-45cd-8166-436894889093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591579652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.591579652
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2565424462
Short name T376
Test name
Test status
Simulation time 855223744 ps
CPU time 2.2 seconds
Started Jan 07 12:54:15 PM PST 24
Finished Jan 07 12:56:28 PM PST 24
Peak memory 198512 kb
Host smart-63562cc5-9934-4eae-a502-f052f3bdbf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565424462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2565424462
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3148010506
Short name T778
Test name
Test status
Simulation time 1741412576 ps
CPU time 2.01 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 198440 kb
Host smart-4c93707f-b399-4aec-a8a4-f3903bc1fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148010506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3148010506
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.3073315405
Short name T557
Test name
Test status
Simulation time 160843980437 ps
CPU time 47.36 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:56:22 PM PST 24
Peak memory 200120 kb
Host smart-9c4f66cb-5ec5-4cd3-a793-42be248b1c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073315405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3073315405
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2960938373
Short name T502
Test name
Test status
Simulation time 14290264 ps
CPU time 0.55 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 12:56:19 PM PST 24
Peak memory 194728 kb
Host smart-4158fae2-ef4a-4539-8bcc-8e4eaa7f52bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960938373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2960938373
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1529241589
Short name T669
Test name
Test status
Simulation time 125684750628 ps
CPU time 175.64 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 12:59:10 PM PST 24
Peak memory 200080 kb
Host smart-b3b3ea80-6663-415c-94cc-6cb0d7a2ffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529241589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1529241589
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1294586479
Short name T237
Test name
Test status
Simulation time 22471356186 ps
CPU time 37.27 seconds
Started Jan 07 12:54:48 PM PST 24
Finished Jan 07 12:57:16 PM PST 24
Peak memory 200200 kb
Host smart-e4a94642-13e1-4aeb-9321-2ef7b463bec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294586479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1294586479
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_loopback.4014453389
Short name T764
Test name
Test status
Simulation time 784759583 ps
CPU time 1.25 seconds
Started Jan 07 12:54:56 PM PST 24
Finished Jan 07 12:56:36 PM PST 24
Peak memory 195560 kb
Host smart-13d86e72-be54-4de7-a73e-6a88b87103bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014453389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.4014453389
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.4294547994
Short name T1005
Test name
Test status
Simulation time 65430691502 ps
CPU time 30.99 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 12:56:32 PM PST 24
Peak memory 199476 kb
Host smart-db750cce-5dd8-48c1-8c8c-2c2ac20efe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294547994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4294547994
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3365001752
Short name T996
Test name
Test status
Simulation time 3772914965 ps
CPU time 16.62 seconds
Started Jan 07 12:54:10 PM PST 24
Finished Jan 07 12:55:47 PM PST 24
Peak memory 198504 kb
Host smart-a0077a77-475c-4c44-a750-b5c0ba1aee2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365001752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3365001752
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2282817791
Short name T123
Test name
Test status
Simulation time 132945020088 ps
CPU time 115.34 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 12:57:42 PM PST 24
Peak memory 200160 kb
Host smart-d7d69ff9-f584-406b-b6e8-470f3a97349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282817791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2282817791
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_smoke.2164609279
Short name T953
Test name
Test status
Simulation time 5392283220 ps
CPU time 29.54 seconds
Started Jan 07 12:54:55 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 199400 kb
Host smart-826943f7-a703-4885-841b-00398cda105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164609279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2164609279
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.450713493
Short name T775
Test name
Test status
Simulation time 187188204883 ps
CPU time 637.1 seconds
Started Jan 07 12:54:44 PM PST 24
Finished Jan 07 01:06:48 PM PST 24
Peak memory 216480 kb
Host smart-7133f7d0-d91b-4c59-b597-cab07e130a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450713493 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.450713493
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.137696373
Short name T781
Test name
Test status
Simulation time 1238386286 ps
CPU time 5.07 seconds
Started Jan 07 12:54:31 PM PST 24
Finished Jan 07 12:56:18 PM PST 24
Peak memory 198104 kb
Host smart-9b91a3b4-9136-4948-9dd3-28e335e0f00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137696373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.137696373
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1069476375
Short name T866
Test name
Test status
Simulation time 172370968647 ps
CPU time 18.03 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 12:56:38 PM PST 24
Peak memory 200056 kb
Host smart-78843af1-3771-4df0-8558-15b7ad235f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069476375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1069476375
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1544865394
Short name T702
Test name
Test status
Simulation time 20128110 ps
CPU time 0.55 seconds
Started Jan 07 12:54:31 PM PST 24
Finished Jan 07 12:56:34 PM PST 24
Peak memory 195620 kb
Host smart-72deb3ea-6ede-4716-af1e-190dd67c8533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544865394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1544865394
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3098821870
Short name T708
Test name
Test status
Simulation time 102502253192 ps
CPU time 160.17 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 12:59:38 PM PST 24
Peak memory 200124 kb
Host smart-2b1f2ec4-49e1-42d1-92c5-7f772c4b0c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098821870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3098821870
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3229005792
Short name T701
Test name
Test status
Simulation time 34344896377 ps
CPU time 58.52 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:56:43 PM PST 24
Peak memory 199752 kb
Host smart-2ddcc9d2-bf99-42db-9281-360e2da2079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229005792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3229005792
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_loopback.3717411211
Short name T697
Test name
Test status
Simulation time 9409392080 ps
CPU time 5.89 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:56:29 PM PST 24
Peak memory 199436 kb
Host smart-3ac0e908-d6ea-4fff-909a-34ab2a8fcdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717411211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3717411211
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.4265129296
Short name T85
Test name
Test status
Simulation time 15617263926 ps
CPU time 11.91 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 12:55:54 PM PST 24
Peak memory 196048 kb
Host smart-9f3922a2-5ae7-40ea-901a-d2bda73152ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265129296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.4265129296
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4161139619
Short name T587
Test name
Test status
Simulation time 451762953 ps
CPU time 1.77 seconds
Started Jan 07 12:54:27 PM PST 24
Finished Jan 07 12:56:12 PM PST 24
Peak memory 198672 kb
Host smart-74fdfc75-d56c-4c2d-85f1-daa9c4853382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161139619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4161139619
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.633995722
Short name T597
Test name
Test status
Simulation time 39299795844 ps
CPU time 676.45 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 01:07:19 PM PST 24
Peak memory 225152 kb
Host smart-7e4e33d5-2e2d-4694-9f12-6f6ac331eaa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633995722 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.633995722
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3037717284
Short name T542
Test name
Test status
Simulation time 14729042871 ps
CPU time 14.95 seconds
Started Jan 07 12:54:47 PM PST 24
Finished Jan 07 12:56:32 PM PST 24
Peak memory 200032 kb
Host smart-6d0ab6e4-2a1b-4378-996a-b7577960879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037717284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3037717284
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3739382921
Short name T118
Test name
Test status
Simulation time 38689185926 ps
CPU time 19.63 seconds
Started Jan 07 12:54:28 PM PST 24
Finished Jan 07 12:56:10 PM PST 24
Peak memory 200136 kb
Host smart-36e8b0b0-9dba-4d59-9fd1-e307bad308af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739382921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3739382921
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.858351399
Short name T23
Test name
Test status
Simulation time 109334787 ps
CPU time 0.57 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 12:56:14 PM PST 24
Peak memory 195544 kb
Host smart-f11aa885-4d8b-4dbc-8008-5477e3766917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858351399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.858351399
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2614434705
Short name T229
Test name
Test status
Simulation time 17479579189 ps
CPU time 13.1 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:55:52 PM PST 24
Peak memory 198772 kb
Host smart-e4d0b410-af77-4dde-a5d8-8350455d50d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614434705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2614434705
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3914479463
Short name T242
Test name
Test status
Simulation time 8529679595 ps
CPU time 15.33 seconds
Started Jan 07 12:56:12 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 199664 kb
Host smart-8e6082a9-67ba-43b3-b2e2-36bf5933a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914479463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3914479463
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3872055284
Short name T525
Test name
Test status
Simulation time 104552253413 ps
CPU time 618.26 seconds
Started Jan 07 12:55:17 PM PST 24
Finished Jan 07 01:07:14 PM PST 24
Peak memory 200136 kb
Host smart-effbdf7b-984e-4a7d-b7b1-ffbdc37826d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872055284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3872055284
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.231227792
Short name T18
Test name
Test status
Simulation time 335246494 ps
CPU time 0.99 seconds
Started Jan 07 12:54:22 PM PST 24
Finished Jan 07 12:55:49 PM PST 24
Peak memory 195520 kb
Host smart-27cbab59-f11a-4042-8c8d-74b3205adec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231227792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.231227792
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.762604032
Short name T393
Test name
Test status
Simulation time 7974553566 ps
CPU time 406.45 seconds
Started Jan 07 12:54:19 PM PST 24
Finished Jan 07 01:02:25 PM PST 24
Peak memory 200128 kb
Host smart-e0c67ea7-49cb-44ea-89ac-6eec2b4c3628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762604032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.762604032
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2195484123
Short name T689
Test name
Test status
Simulation time 87520317744 ps
CPU time 37.25 seconds
Started Jan 07 12:54:17 PM PST 24
Finished Jan 07 12:56:13 PM PST 24
Peak memory 198704 kb
Host smart-a4582da3-829c-4042-bc10-0361af323ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195484123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2195484123
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_stress_all.4088311704
Short name T668
Test name
Test status
Simulation time 940373042317 ps
CPU time 224.74 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 12:59:53 PM PST 24
Peak memory 200204 kb
Host smart-d8a664ae-3b5a-48c8-8eb4-104e56a9f3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088311704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.4088311704
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1282481285
Short name T604
Test name
Test status
Simulation time 2779597125 ps
CPU time 1.64 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 198472 kb
Host smart-e1686837-bbef-4433-a495-57653bee6e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282481285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1282481285
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_alert_test.3581362254
Short name T409
Test name
Test status
Simulation time 13174488 ps
CPU time 0.55 seconds
Started Jan 07 12:52:57 PM PST 24
Finished Jan 07 12:54:19 PM PST 24
Peak memory 195560 kb
Host smart-7213d86c-6c1c-4ff8-95a0-fddaa431e1fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581362254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3581362254
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1586150324
Short name T96
Test name
Test status
Simulation time 74617619236 ps
CPU time 29.12 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 12:55:24 PM PST 24
Peak memory 200108 kb
Host smart-27f9eacc-4c00-49ed-b702-a909888522ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586150324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1586150324
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1094656980
Short name T359
Test name
Test status
Simulation time 137665931588 ps
CPU time 292.14 seconds
Started Jan 07 12:53:40 PM PST 24
Finished Jan 07 12:59:54 PM PST 24
Peak memory 200240 kb
Host smart-7d12d4c2-d96d-4609-828d-51f637772788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094656980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1094656980
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2703758152
Short name T332
Test name
Test status
Simulation time 76957140202 ps
CPU time 20.08 seconds
Started Jan 07 12:54:00 PM PST 24
Finished Jan 07 12:55:54 PM PST 24
Peak memory 200208 kb
Host smart-48aa9f8a-c2c7-49da-9b52-2efe81d154f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703758152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2703758152
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2353427962
Short name T632
Test name
Test status
Simulation time 400198709307 ps
CPU time 206.04 seconds
Started Jan 07 12:53:48 PM PST 24
Finished Jan 07 12:58:57 PM PST 24
Peak memory 200220 kb
Host smart-5810e534-cf69-4220-b7b0-e4274263fd35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353427962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2353427962
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3127155483
Short name T869
Test name
Test status
Simulation time 97520947874 ps
CPU time 364.69 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 01:01:32 PM PST 24
Peak memory 200092 kb
Host smart-46bd4113-18c4-45b6-95bd-c06ca1d0605f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3127155483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3127155483
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1175258417
Short name T924
Test name
Test status
Simulation time 6702933575 ps
CPU time 14.02 seconds
Started Jan 07 12:53:53 PM PST 24
Finished Jan 07 12:56:03 PM PST 24
Peak memory 198392 kb
Host smart-5a1e3298-68e7-4b8d-b6ad-8b4328d6fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175258417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1175258417
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2880348087
Short name T593
Test name
Test status
Simulation time 34886651856 ps
CPU time 63.17 seconds
Started Jan 07 12:53:46 PM PST 24
Finished Jan 07 12:56:08 PM PST 24
Peak memory 199600 kb
Host smart-89bb1a39-99b1-4ad1-b1cb-1926c95c8da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880348087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2880348087
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1220764926
Short name T641
Test name
Test status
Simulation time 23223490496 ps
CPU time 1150.16 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 01:14:19 PM PST 24
Peak memory 200104 kb
Host smart-aa632420-839c-40a3-a7d4-e031e17a5205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220764926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1220764926
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2251355308
Short name T727
Test name
Test status
Simulation time 30743910783 ps
CPU time 24.61 seconds
Started Jan 07 12:53:52 PM PST 24
Finished Jan 07 12:55:54 PM PST 24
Peak memory 199784 kb
Host smart-df4a7960-cc1d-4f7c-97f7-17e518ecbe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251355308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2251355308
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2083753238
Short name T87
Test name
Test status
Simulation time 1629689937 ps
CPU time 1.79 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:55:08 PM PST 24
Peak memory 195652 kb
Host smart-5a88518f-0a1b-4d34-a3d1-fd78fb7bbbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083753238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2083753238
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3727385654
Short name T82
Test name
Test status
Simulation time 217448967 ps
CPU time 0.8 seconds
Started Jan 07 12:52:54 PM PST 24
Finished Jan 07 12:54:16 PM PST 24
Peak memory 217808 kb
Host smart-4fb88aa6-db16-49f0-ac44-3a236d97f5c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727385654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3727385654
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2482416038
Short name T770
Test name
Test status
Simulation time 5860061686 ps
CPU time 18.3 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:55:11 PM PST 24
Peak memory 200128 kb
Host smart-66040325-e048-4f97-a030-d4fff0f96d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482416038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2482416038
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2120042760
Short name T309
Test name
Test status
Simulation time 452620128505 ps
CPU time 451.64 seconds
Started Jan 07 12:53:58 PM PST 24
Finished Jan 07 01:02:56 PM PST 24
Peak memory 200232 kb
Host smart-de983dbf-89b7-4217-b17b-bc03d6950b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120042760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2120042760
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2629611330
Short name T160
Test name
Test status
Simulation time 70237501490 ps
CPU time 2751.44 seconds
Started Jan 07 12:53:59 PM PST 24
Finished Jan 07 01:41:07 PM PST 24
Peak memory 215564 kb
Host smart-4984d6e4-f77a-463f-9254-341d9b4a1f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629611330 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2629611330
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_rx.4189205908
Short name T797
Test name
Test status
Simulation time 27526841216 ps
CPU time 52 seconds
Started Jan 07 12:53:39 PM PST 24
Finished Jan 07 12:56:04 PM PST 24
Peak memory 200068 kb
Host smart-9c226be5-d6d6-4ec6-a2ad-c4d5ef66ca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189205908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.4189205908
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2436167233
Short name T857
Test name
Test status
Simulation time 32012244 ps
CPU time 0.52 seconds
Started Jan 07 12:54:45 PM PST 24
Finished Jan 07 12:56:03 PM PST 24
Peak memory 194608 kb
Host smart-89dd8aeb-e37f-4a8a-bab3-0e2ed8d01b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436167233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2436167233
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1027825355
Short name T712
Test name
Test status
Simulation time 28471102039 ps
CPU time 39.48 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 12:57:48 PM PST 24
Peak memory 200104 kb
Host smart-7aae462d-88c1-4501-86ea-ea419b509fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027825355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1027825355
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1187288848
Short name T2
Test name
Test status
Simulation time 13579247600 ps
CPU time 10.48 seconds
Started Jan 07 12:54:54 PM PST 24
Finished Jan 07 12:56:41 PM PST 24
Peak memory 198712 kb
Host smart-78fd9d6d-fade-4024-8224-839f938cc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187288848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1187288848
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.856113090
Short name T646
Test name
Test status
Simulation time 66206188162 ps
CPU time 28.7 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 12:57:27 PM PST 24
Peak memory 200136 kb
Host smart-0bc0ee36-d0e0-40b1-8249-59f86d827f08
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856113090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.856113090
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1096584942
Short name T705
Test name
Test status
Simulation time 48678056480 ps
CPU time 274.88 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 01:01:11 PM PST 24
Peak memory 200144 kb
Host smart-bcebee2e-7f37-4cbf-bf97-d8b18bb17119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096584942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1096584942
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2624557676
Short name T111
Test name
Test status
Simulation time 141103415 ps
CPU time 0.8 seconds
Started Jan 07 12:54:22 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 193748 kb
Host smart-c1e7d047-53c5-4c12-bdde-567d4f0a0f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624557676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2624557676
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1536812137
Short name T1044
Test name
Test status
Simulation time 15955384690 ps
CPU time 375.53 seconds
Started Jan 07 12:54:10 PM PST 24
Finished Jan 07 01:01:59 PM PST 24
Peak memory 200164 kb
Host smart-0bf77a3a-5761-4717-852f-4f6b721c5463
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536812137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1536812137
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3318173877
Short name T894
Test name
Test status
Simulation time 32646237042 ps
CPU time 51 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:57:18 PM PST 24
Peak memory 199408 kb
Host smart-5454e466-fbbe-473f-9832-1c3fdf7ee2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318173877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3318173877
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_smoke.3715256659
Short name T406
Test name
Test status
Simulation time 101699149 ps
CPU time 0.77 seconds
Started Jan 07 12:54:48 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 196788 kb
Host smart-a87e713f-8bb6-4fe8-9116-17b9a74b43ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715256659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3715256659
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3295391070
Short name T395
Test name
Test status
Simulation time 9508556530 ps
CPU time 105.64 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 12:58:44 PM PST 24
Peak memory 216308 kb
Host smart-ddfd8494-9146-463e-a853-08be2828d791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295391070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3295391070
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.509693761
Short name T407
Test name
Test status
Simulation time 493218850 ps
CPU time 2.01 seconds
Started Jan 07 12:54:13 PM PST 24
Finished Jan 07 12:55:51 PM PST 24
Peak memory 198700 kb
Host smart-528e0dfe-0444-4e27-b75c-d0f6cf6ca347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509693761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.509693761
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1004755099
Short name T22
Test name
Test status
Simulation time 52215250030 ps
CPU time 28.09 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 12:56:31 PM PST 24
Peak memory 200120 kb
Host smart-8588adf0-95bb-441d-98fc-3814a140a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004755099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1004755099
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.536521268
Short name T602
Test name
Test status
Simulation time 11540305 ps
CPU time 0.58 seconds
Started Jan 07 12:55:57 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 194440 kb
Host smart-ccad2d9e-3df9-4135-9ea4-4aacc92455f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536521268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.536521268
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1560441497
Short name T911
Test name
Test status
Simulation time 110181546948 ps
CPU time 167.76 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:59:14 PM PST 24
Peak memory 200212 kb
Host smart-940fdfbf-f5a5-4d03-98f7-ac951e46bab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560441497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1560441497
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3009694838
Short name T585
Test name
Test status
Simulation time 43434914780 ps
CPU time 39.95 seconds
Started Jan 07 12:54:49 PM PST 24
Finished Jan 07 12:57:00 PM PST 24
Peak memory 200124 kb
Host smart-632b3997-12f4-4eb2-bb7c-50c2a0ebc0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009694838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3009694838
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.893314409
Short name T841
Test name
Test status
Simulation time 68441488170 ps
CPU time 26.24 seconds
Started Jan 07 12:54:31 PM PST 24
Finished Jan 07 12:56:39 PM PST 24
Peak memory 200212 kb
Host smart-f881a19a-3fdb-49c5-8f98-323704dbc5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893314409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.893314409
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.825702814
Short name T940
Test name
Test status
Simulation time 180038223535 ps
CPU time 936.13 seconds
Started Jan 07 12:55:57 PM PST 24
Finished Jan 07 01:13:15 PM PST 24
Peak memory 199020 kb
Host smart-77a5fea1-a7a4-4fbd-87fa-5af2f4325c48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825702814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.825702814
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3599779533
Short name T529
Test name
Test status
Simulation time 5207637518 ps
CPU time 14.26 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:56:56 PM PST 24
Peak memory 199168 kb
Host smart-24338684-d4a7-43ee-99c3-c0a0f64142b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599779533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3599779533
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.283722727
Short name T671
Test name
Test status
Simulation time 10749022696 ps
CPU time 16.93 seconds
Started Jan 07 12:56:18 PM PST 24
Finished Jan 07 12:58:20 PM PST 24
Peak memory 198872 kb
Host smart-2be844ef-cfba-4aca-98e5-1b5072662a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283722727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.283722727
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1607793267
Short name T987
Test name
Test status
Simulation time 674072558 ps
CPU time 1.74 seconds
Started Jan 07 12:54:58 PM PST 24
Finished Jan 07 12:56:51 PM PST 24
Peak memory 195624 kb
Host smart-f140b811-5e9c-473e-85fe-967943126ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607793267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1607793267
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2715622856
Short name T349
Test name
Test status
Simulation time 5548545663 ps
CPU time 11.88 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 12:56:28 PM PST 24
Peak memory 199044 kb
Host smart-9c4c78bc-683b-4e73-8194-3d7cdc6508bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715622856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2715622856
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.247965853
Short name T991
Test name
Test status
Simulation time 616041701722 ps
CPU time 354.16 seconds
Started Jan 07 12:54:28 PM PST 24
Finished Jan 07 01:01:52 PM PST 24
Peak memory 200308 kb
Host smart-bef9d1b7-a5a4-4a92-8197-19733a6dfeaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247965853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.247965853
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2962849479
Short name T57
Test name
Test status
Simulation time 298363956764 ps
CPU time 1253.69 seconds
Started Jan 07 12:56:12 PM PST 24
Finished Jan 07 01:18:34 PM PST 24
Peak memory 224672 kb
Host smart-73190ab1-a1c1-421f-a7e9-10180e11f3fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962849479 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2962849479
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1926676851
Short name T659
Test name
Test status
Simulation time 1106329645 ps
CPU time 4.26 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 12:56:24 PM PST 24
Peak memory 198684 kb
Host smart-5a05fe03-9091-42ca-a8a2-18a868b2e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926676851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1926676851
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2614535674
Short name T1022
Test name
Test status
Simulation time 55160436195 ps
CPU time 68.31 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:56:50 PM PST 24
Peak memory 200132 kb
Host smart-1eba00f9-4864-4eb3-92c0-2be6435fb687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614535674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2614535674
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2921303127
Short name T742
Test name
Test status
Simulation time 113041475659 ps
CPU time 52.26 seconds
Started Jan 07 12:56:18 PM PST 24
Finished Jan 07 12:58:41 PM PST 24
Peak memory 199804 kb
Host smart-bc36e400-58e7-4571-b7d1-52598cdd36f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921303127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2921303127
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3802343302
Short name T629
Test name
Test status
Simulation time 251998969381 ps
CPU time 38.19 seconds
Started Jan 07 12:54:25 PM PST 24
Finished Jan 07 12:56:26 PM PST 24
Peak memory 199624 kb
Host smart-26e8018a-f361-4021-a0a1-f596be36e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802343302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3802343302
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3926961731
Short name T381
Test name
Test status
Simulation time 97150664068 ps
CPU time 105.06 seconds
Started Jan 07 12:54:56 PM PST 24
Finished Jan 07 12:58:05 PM PST 24
Peak memory 200016 kb
Host smart-597f7152-8aed-4afe-b4ba-16577ac3b10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926961731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3926961731
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2877074730
Short name T577
Test name
Test status
Simulation time 210343778444 ps
CPU time 394.69 seconds
Started Jan 07 12:54:47 PM PST 24
Finished Jan 07 01:02:58 PM PST 24
Peak memory 200172 kb
Host smart-7f3b450a-aa17-49e2-b285-06bce8ee83ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877074730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2877074730
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3590656309
Short name T746
Test name
Test status
Simulation time 211798350808 ps
CPU time 954.91 seconds
Started Jan 07 12:54:24 PM PST 24
Finished Jan 07 01:12:29 PM PST 24
Peak memory 200088 kb
Host smart-d2826fe0-c74d-495b-bbfb-e8d133a7b621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590656309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3590656309
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2865068508
Short name T874
Test name
Test status
Simulation time 5664766160 ps
CPU time 3 seconds
Started Jan 07 12:54:19 PM PST 24
Finished Jan 07 12:56:04 PM PST 24
Peak memory 197572 kb
Host smart-5a9eb2d6-a57f-46b8-9b79-21685c4ab3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865068508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2865068508
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2343839079
Short name T985
Test name
Test status
Simulation time 1709794924 ps
CPU time 4.42 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:55:42 PM PST 24
Peak memory 197800 kb
Host smart-f76139fe-0399-4443-86b9-a5145e92ec00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343839079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2343839079
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3962402699
Short name T320
Test name
Test status
Simulation time 200970766910 ps
CPU time 24.97 seconds
Started Jan 07 12:54:36 PM PST 24
Finished Jan 07 12:56:22 PM PST 24
Peak memory 199536 kb
Host smart-c2a7d068-06b4-4e23-9c3f-07f9b4c82133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962402699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3962402699
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3478593560
Short name T584
Test name
Test status
Simulation time 26350348353 ps
CPU time 4.45 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 196008 kb
Host smart-83c1d5b2-b1ce-44d5-add6-f7a6447e129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478593560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3478593560
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.291311297
Short name T741
Test name
Test status
Simulation time 663743516 ps
CPU time 2.69 seconds
Started Jan 07 12:56:12 PM PST 24
Finished Jan 07 12:57:53 PM PST 24
Peak memory 198140 kb
Host smart-156fe4e9-c451-4866-bdce-870254cac6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291311297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.291311297
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1663571804
Short name T853
Test name
Test status
Simulation time 1268009036 ps
CPU time 2.98 seconds
Started Jan 07 12:54:32 PM PST 24
Finished Jan 07 12:55:50 PM PST 24
Peak memory 198444 kb
Host smart-1c3526cf-147d-41ae-954a-d263c3533c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663571804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1663571804
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1666406102
Short name T830
Test name
Test status
Simulation time 98220980899 ps
CPU time 41.9 seconds
Started Jan 07 12:56:12 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 199312 kb
Host smart-db342fd4-a214-49ab-9747-7c2a8b4fa4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666406102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1666406102
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.956200728
Short name T551
Test name
Test status
Simulation time 17169580 ps
CPU time 0.54 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 12:56:15 PM PST 24
Peak memory 195504 kb
Host smart-f05b5535-f10e-4645-b373-476868e17497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956200728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.956200728
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3275951175
Short name T267
Test name
Test status
Simulation time 270887009075 ps
CPU time 37.64 seconds
Started Jan 07 12:54:55 PM PST 24
Finished Jan 07 12:56:53 PM PST 24
Peak memory 200180 kb
Host smart-1cffb3ac-5d33-4182-94e8-ba248b309f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275951175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3275951175
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2371744227
Short name T203
Test name
Test status
Simulation time 32165460049 ps
CPU time 13.25 seconds
Started Jan 07 12:54:27 PM PST 24
Finished Jan 07 12:55:58 PM PST 24
Peak memory 200232 kb
Host smart-3bdf21c9-b74c-4e35-b69e-37b6df9d06d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371744227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2371744227
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3718055912
Short name T979
Test name
Test status
Simulation time 1850389058747 ps
CPU time 2879.59 seconds
Started Jan 07 12:54:50 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 199976 kb
Host smart-72ab71f6-3b45-4c8c-821c-48a91ce8e113
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718055912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3718055912
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2247662103
Short name T545
Test name
Test status
Simulation time 104398147233 ps
CPU time 135.76 seconds
Started Jan 07 12:54:26 PM PST 24
Finished Jan 07 12:58:31 PM PST 24
Peak memory 200156 kb
Host smart-16c9abbf-2670-457c-a092-7cb28331d05e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247662103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2247662103
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2105453735
Short name T901
Test name
Test status
Simulation time 8263540057 ps
CPU time 3.73 seconds
Started Jan 07 12:55:12 PM PST 24
Finished Jan 07 12:57:02 PM PST 24
Peak memory 200052 kb
Host smart-c6e10728-89b1-45c6-ae1b-84ad8366e764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105453735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2105453735
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1670607321
Short name T806
Test name
Test status
Simulation time 5194320451 ps
CPU time 233.32 seconds
Started Jan 07 12:54:55 PM PST 24
Finished Jan 07 01:00:45 PM PST 24
Peak memory 200188 kb
Host smart-7f9123d3-fe78-4444-82d5-98a4798c7b08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670607321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1670607321
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2199946167
Short name T541
Test name
Test status
Simulation time 3350535653 ps
CPU time 26.44 seconds
Started Jan 07 12:54:27 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 198196 kb
Host smart-8d6941c0-0ebd-47a5-96bd-f75b150d651d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199946167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2199946167
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3380798855
Short name T686
Test name
Test status
Simulation time 45561286853 ps
CPU time 38.29 seconds
Started Jan 07 12:54:44 PM PST 24
Finished Jan 07 12:56:57 PM PST 24
Peak memory 199960 kb
Host smart-4150c220-5ff9-4329-a2e3-cd534e55bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380798855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3380798855
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1368935926
Short name T735
Test name
Test status
Simulation time 35784606083 ps
CPU time 13.42 seconds
Started Jan 07 12:54:16 PM PST 24
Finished Jan 07 12:56:40 PM PST 24
Peak memory 195720 kb
Host smart-39170459-1808-472e-b838-79053de5346e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368935926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1368935926
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.31362673
Short name T550
Test name
Test status
Simulation time 5965817587 ps
CPU time 16.64 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 12:57:24 PM PST 24
Peak memory 199600 kb
Host smart-2e43f6ca-c251-49ed-9c11-22d2aec74b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31362673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.31362673
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3302865526
Short name T892
Test name
Test status
Simulation time 142351455555 ps
CPU time 738.38 seconds
Started Jan 07 12:55:06 PM PST 24
Finished Jan 07 01:09:01 PM PST 24
Peak memory 216928 kb
Host smart-2573d26b-fb72-40b4-bf77-ec05395a8791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302865526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3302865526
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1558008614
Short name T586
Test name
Test status
Simulation time 1186307009 ps
CPU time 2.52 seconds
Started Jan 07 12:54:41 PM PST 24
Finished Jan 07 12:57:01 PM PST 24
Peak memory 198196 kb
Host smart-1915f0b7-9ac4-43ba-bb41-2e85bcacac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558008614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1558008614
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_alert_test.4183760752
Short name T954
Test name
Test status
Simulation time 14213657 ps
CPU time 0.55 seconds
Started Jan 07 12:54:45 PM PST 24
Finished Jan 07 12:56:08 PM PST 24
Peak memory 195612 kb
Host smart-66ae9fed-22b8-4780-8c7b-35b90b829100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183760752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.4183760752
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1375035952
Short name T670
Test name
Test status
Simulation time 110329255622 ps
CPU time 94.51 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 199164 kb
Host smart-5e510012-0b93-4788-acb2-c807bee8c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375035952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1375035952
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1394923578
Short name T536
Test name
Test status
Simulation time 123863615548 ps
CPU time 846.25 seconds
Started Jan 07 12:54:37 PM PST 24
Finished Jan 07 01:10:17 PM PST 24
Peak memory 200172 kb
Host smart-06c6705c-3245-4db8-87e9-dbfeccb5f11a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394923578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1394923578
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.56112850
Short name T530
Test name
Test status
Simulation time 4124454376 ps
CPU time 5.14 seconds
Started Jan 07 12:54:25 PM PST 24
Finished Jan 07 12:55:57 PM PST 24
Peak memory 198668 kb
Host smart-1544e0e9-1e4b-4004-88ce-6b8f35ba525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56112850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.56112850
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.3283852940
Short name T729
Test name
Test status
Simulation time 9064381423 ps
CPU time 125.8 seconds
Started Jan 07 12:54:26 PM PST 24
Finished Jan 07 12:58:00 PM PST 24
Peak memory 200200 kb
Host smart-c304a102-aefb-4d74-9f03-e4e35adfe99f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283852940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3283852940
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.833268390
Short name T559
Test name
Test status
Simulation time 148342836 ps
CPU time 0.69 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 12:56:08 PM PST 24
Peak memory 195768 kb
Host smart-096300fd-6cda-48b7-aec6-e2667872fb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833268390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.833268390
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2072225976
Short name T568
Test name
Test status
Simulation time 50266806787 ps
CPU time 76.79 seconds
Started Jan 07 12:54:36 PM PST 24
Finished Jan 07 12:57:21 PM PST 24
Peak memory 199528 kb
Host smart-0df7f369-ccf6-4005-b923-e889745198f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072225976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2072225976
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_stress_all.1908191541
Short name T852
Test name
Test status
Simulation time 501688900053 ps
CPU time 464.23 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 01:03:29 PM PST 24
Peak memory 200420 kb
Host smart-82041071-5df5-4003-ab91-0df1d5da79da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908191541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1908191541
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2653313826
Short name T699
Test name
Test status
Simulation time 9459986164 ps
CPU time 129.01 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:59:14 PM PST 24
Peak memory 215716 kb
Host smart-7c433037-2fa2-48bb-9155-142a53b80864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653313826 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2653313826
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1870145586
Short name T1008
Test name
Test status
Simulation time 1124054978 ps
CPU time 2.82 seconds
Started Jan 07 12:55:04 PM PST 24
Finished Jan 07 12:56:29 PM PST 24
Peak memory 198932 kb
Host smart-621ec357-94ef-40de-a754-c715c8277a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870145586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1870145586
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1983759895
Short name T848
Test name
Test status
Simulation time 15945344072 ps
CPU time 26.41 seconds
Started Jan 07 12:54:25 PM PST 24
Finished Jan 07 12:56:19 PM PST 24
Peak memory 199208 kb
Host smart-63261e30-da4c-4f52-90a4-403a020adfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983759895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1983759895
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1252189758
Short name T589
Test name
Test status
Simulation time 14051609 ps
CPU time 0.57 seconds
Started Jan 07 12:54:21 PM PST 24
Finished Jan 07 12:55:48 PM PST 24
Peak memory 195676 kb
Host smart-1fb9026c-bfa2-4cff-8eba-0e8d6eb540c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252189758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1252189758
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1404447407
Short name T207
Test name
Test status
Simulation time 23026520245 ps
CPU time 39.4 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 12:56:58 PM PST 24
Peak memory 200088 kb
Host smart-124fe573-cf25-4e28-b737-0d3c3120d9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404447407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1404447407
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1340463422
Short name T917
Test name
Test status
Simulation time 125678201679 ps
CPU time 93.1 seconds
Started Jan 07 12:54:40 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 199916 kb
Host smart-54538613-bf96-4044-b271-fe1f967b6060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340463422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1340463422
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1774452731
Short name T1024
Test name
Test status
Simulation time 110725039332 ps
CPU time 162.79 seconds
Started Jan 07 12:55:07 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 198864 kb
Host smart-6fa84247-5bb2-4ca9-bdbc-58e23f49eb8e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774452731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1774452731
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2316162131
Short name T528
Test name
Test status
Simulation time 118967301851 ps
CPU time 375.75 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 01:03:11 PM PST 24
Peak memory 200188 kb
Host smart-732f6eb5-1521-4cf9-af2c-8ee6e4513ce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316162131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2316162131
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.3201690788
Short name T842
Test name
Test status
Simulation time 2846606806 ps
CPU time 4.37 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:56:40 PM PST 24
Peak memory 196872 kb
Host smart-a25ab49c-a164-479c-b405-d46fbc2dad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201690788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3201690788
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1809755427
Short name T772
Test name
Test status
Simulation time 283188614352 ps
CPU time 68.94 seconds
Started Jan 07 12:54:57 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 208688 kb
Host smart-11b13636-02cc-4c5d-926e-636f3803b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809755427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1809755427
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3544438045
Short name T411
Test name
Test status
Simulation time 11800274362 ps
CPU time 161.77 seconds
Started Jan 07 12:54:40 PM PST 24
Finished Jan 07 12:58:53 PM PST 24
Peak memory 200096 kb
Host smart-b38793e4-346c-49ba-8b82-ce22acc9928e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3544438045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3544438045
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.878773033
Short name T756
Test name
Test status
Simulation time 173362908436 ps
CPU time 689.88 seconds
Started Jan 07 12:54:39 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 200132 kb
Host smart-29446e8a-d20f-4a0c-a64e-e61a10c2c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878773033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.878773033
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2921307713
Short name T647
Test name
Test status
Simulation time 5262737684 ps
CPU time 1.54 seconds
Started Jan 07 12:54:37 PM PST 24
Finished Jan 07 12:56:00 PM PST 24
Peak memory 196008 kb
Host smart-c6e36286-fd80-42db-a240-dae55aaea298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921307713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2921307713
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3399110300
Short name T835
Test name
Test status
Simulation time 433781061 ps
CPU time 1.71 seconds
Started Jan 07 12:54:36 PM PST 24
Finished Jan 07 12:56:28 PM PST 24
Peak memory 199980 kb
Host smart-d8049e46-0b36-4492-8ae8-c2dcc1a79ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399110300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3399110300
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.385210377
Short name T998
Test name
Test status
Simulation time 128221719899 ps
CPU time 434.67 seconds
Started Jan 07 12:54:41 PM PST 24
Finished Jan 07 01:04:04 PM PST 24
Peak memory 212620 kb
Host smart-328a2172-d212-4836-9410-0be4a4135aff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385210377 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.385210377
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3446121371
Short name T560
Test name
Test status
Simulation time 4327542762 ps
CPU time 1.75 seconds
Started Jan 07 12:54:31 PM PST 24
Finished Jan 07 12:56:48 PM PST 24
Peak memory 198664 kb
Host smart-b14b48a7-aeb1-452a-8bef-63eeed392213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446121371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3446121371
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_alert_test.1949383414
Short name T410
Test name
Test status
Simulation time 22184353 ps
CPU time 0.55 seconds
Started Jan 07 12:54:34 PM PST 24
Finished Jan 07 12:56:03 PM PST 24
Peak memory 195528 kb
Host smart-1dcb619c-f47f-4412-af4e-dc5cef567ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949383414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1949383414
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3398028992
Short name T655
Test name
Test status
Simulation time 25055509915 ps
CPU time 43.19 seconds
Started Jan 07 12:54:18 PM PST 24
Finished Jan 07 12:57:19 PM PST 24
Peak memory 200180 kb
Host smart-298ae0a9-9383-482a-891d-b3f66902deea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398028992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3398028992
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_intr.2907839364
Short name T861
Test name
Test status
Simulation time 99322779799 ps
CPU time 44.05 seconds
Started Jan 07 12:54:31 PM PST 24
Finished Jan 07 12:57:36 PM PST 24
Peak memory 199780 kb
Host smart-c2bcadaa-7066-449c-a6d5-9444fd1e2cc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907839364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2907839364
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3179090403
Short name T356
Test name
Test status
Simulation time 73651358945 ps
CPU time 521.37 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 01:04:29 PM PST 24
Peak memory 200208 kb
Host smart-851c5fe2-4e70-44e5-bd95-79fd8835d09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179090403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3179090403
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3658703963
Short name T624
Test name
Test status
Simulation time 153342778511 ps
CPU time 121.48 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 12:58:23 PM PST 24
Peak memory 200304 kb
Host smart-510bf171-b70d-4df4-b51a-2ee941112f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658703963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3658703963
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3075586515
Short name T211
Test name
Test status
Simulation time 18099715403 ps
CPU time 449.61 seconds
Started Jan 07 12:54:30 PM PST 24
Finished Jan 07 01:03:23 PM PST 24
Peak memory 200100 kb
Host smart-94334b4f-daad-4ac2-a9aa-5f8b962b16fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075586515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3075586515
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1261026440
Short name T508
Test name
Test status
Simulation time 47195719850 ps
CPU time 23.48 seconds
Started Jan 07 12:54:26 PM PST 24
Finished Jan 07 12:56:09 PM PST 24
Peak memory 200072 kb
Host smart-a857ecd4-c36f-40cc-9c42-23aee20a2623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261026440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1261026440
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_smoke.3057711373
Short name T990
Test name
Test status
Simulation time 773081668 ps
CPU time 1.42 seconds
Started Jan 07 12:54:39 PM PST 24
Finished Jan 07 12:55:58 PM PST 24
Peak memory 198552 kb
Host smart-6d46ac58-8f12-4ef0-88aa-44a8311614a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057711373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3057711373
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1634816484
Short name T304
Test name
Test status
Simulation time 416208689240 ps
CPU time 328.39 seconds
Started Jan 07 12:54:33 PM PST 24
Finished Jan 07 01:01:53 PM PST 24
Peak memory 208928 kb
Host smart-774f8808-271d-4f75-b5ee-f43b2ee2e0d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634816484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1634816484
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1398827001
Short name T794
Test name
Test status
Simulation time 619938874 ps
CPU time 2.04 seconds
Started Jan 07 12:54:44 PM PST 24
Finished Jan 07 12:56:28 PM PST 24
Peak memory 199020 kb
Host smart-b49ef829-09a1-4965-a8a8-a445f1061b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398827001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1398827001
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_alert_test.597792591
Short name T807
Test name
Test status
Simulation time 68440694 ps
CPU time 0.52 seconds
Started Jan 07 12:54:53 PM PST 24
Finished Jan 07 12:56:13 PM PST 24
Peak memory 195572 kb
Host smart-9692bbe0-d75d-4f26-aa9b-23b423713b84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597792591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.597792591
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2850130477
Short name T927
Test name
Test status
Simulation time 95082399884 ps
CPU time 44.08 seconds
Started Jan 07 12:55:10 PM PST 24
Finished Jan 07 12:57:12 PM PST 24
Peak memory 200152 kb
Host smart-15b210fc-b090-4dac-a856-e98c1e8a674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850130477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2850130477
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.498022668
Short name T634
Test name
Test status
Simulation time 1717217447184 ps
CPU time 779.23 seconds
Started Jan 07 12:55:11 PM PST 24
Finished Jan 07 01:09:35 PM PST 24
Peak memory 200228 kb
Host smart-9985418e-081f-4fcb-8465-fb4d5d958d56
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498022668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.498022668
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3485908231
Short name T361
Test name
Test status
Simulation time 73852634675 ps
CPU time 450.31 seconds
Started Jan 07 12:55:12 PM PST 24
Finished Jan 07 01:04:34 PM PST 24
Peak memory 200160 kb
Host smart-c22cacd7-1872-438f-89e7-87a8d8ebc810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485908231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3485908231
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.259790501
Short name T799
Test name
Test status
Simulation time 8494545599 ps
CPU time 14.97 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:57:01 PM PST 24
Peak memory 198792 kb
Host smart-b86a2a83-ed7b-444f-bc26-c33f611789c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259790501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.259790501
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3023709500
Short name T362
Test name
Test status
Simulation time 89174602989 ps
CPU time 35.79 seconds
Started Jan 07 12:54:40 PM PST 24
Finished Jan 07 12:56:47 PM PST 24
Peak memory 197804 kb
Host smart-df5833f4-d878-48e7-8bea-54ef5127aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023709500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3023709500
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.638088822
Short name T607
Test name
Test status
Simulation time 8824336183 ps
CPU time 83.17 seconds
Started Jan 07 12:54:48 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 200180 kb
Host smart-6a193805-5c2d-4bbb-847c-f158ec0a5b81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638088822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.638088822
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4203878630
Short name T856
Test name
Test status
Simulation time 2686897098 ps
CPU time 5.54 seconds
Started Jan 07 12:54:55 PM PST 24
Finished Jan 07 12:56:20 PM PST 24
Peak memory 198620 kb
Host smart-7f88aa89-a9c3-4544-a3a1-b26bc0996c60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203878630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4203878630
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3960318929
Short name T499
Test name
Test status
Simulation time 4737475553 ps
CPU time 8.53 seconds
Started Jan 07 12:55:16 PM PST 24
Finished Jan 07 12:57:02 PM PST 24
Peak memory 196032 kb
Host smart-0b484d84-31cb-4a02-8587-a02a20b99bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960318929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3960318929
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3232332584
Short name T703
Test name
Test status
Simulation time 269139390 ps
CPU time 1.63 seconds
Started Jan 07 12:55:23 PM PST 24
Finished Jan 07 12:57:08 PM PST 24
Peak memory 197868 kb
Host smart-63954324-b263-403d-bff7-73effd7aa8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232332584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3232332584
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3560831018
Short name T532
Test name
Test status
Simulation time 147179452174 ps
CPU time 406 seconds
Started Jan 07 12:54:57 PM PST 24
Finished Jan 07 01:03:18 PM PST 24
Peak memory 200120 kb
Host smart-90fc2940-5b48-4448-b70c-d27f92733edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560831018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3560831018
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.933258429
Short name T518
Test name
Test status
Simulation time 710903163 ps
CPU time 3.13 seconds
Started Jan 07 12:54:48 PM PST 24
Finished Jan 07 12:56:22 PM PST 24
Peak memory 198188 kb
Host smart-0386d9fc-2905-433a-b676-edca9942dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933258429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.933258429
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1832502420
Short name T870
Test name
Test status
Simulation time 8306503733 ps
CPU time 11.47 seconds
Started Jan 07 12:54:36 PM PST 24
Finished Jan 07 12:56:27 PM PST 24
Peak memory 197192 kb
Host smart-c7c74312-2315-4665-8f4b-769f0484ac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832502420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1832502420
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1627029552
Short name T681
Test name
Test status
Simulation time 211653209008 ps
CPU time 194.83 seconds
Started Jan 07 12:55:12 PM PST 24
Finished Jan 07 01:00:07 PM PST 24
Peak memory 200164 kb
Host smart-8ba9feee-deb4-45b0-b654-f6051c92560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627029552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1627029552
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1434522080
Short name T263
Test name
Test status
Simulation time 30787933902 ps
CPU time 46.56 seconds
Started Jan 07 12:55:22 PM PST 24
Finished Jan 07 12:57:29 PM PST 24
Peak memory 200148 kb
Host smart-59153ac5-56b4-4582-bcd9-302f3ba2e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434522080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1434522080
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.1850633670
Short name T379
Test name
Test status
Simulation time 53950401850 ps
CPU time 156.5 seconds
Started Jan 07 12:54:49 PM PST 24
Finished Jan 07 12:59:00 PM PST 24
Peak memory 200072 kb
Host smart-0f64ac82-9ce0-44e8-9f83-8434f54a53f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850633670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1850633670
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2752857232
Short name T512
Test name
Test status
Simulation time 104255541208 ps
CPU time 263 seconds
Started Jan 07 12:54:45 PM PST 24
Finished Jan 07 01:00:26 PM PST 24
Peak memory 200228 kb
Host smart-85a006c3-10b0-474f-993c-dd0fc181f705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752857232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2752857232
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.7432882
Short name T639
Test name
Test status
Simulation time 6820864315 ps
CPU time 5.16 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:56:34 PM PST 24
Peak memory 198612 kb
Host smart-6a2d1efd-272d-411d-b445-d4e883439ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7432882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.7432882
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.310491151
Short name T253
Test name
Test status
Simulation time 14727990146 ps
CPU time 687.78 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 01:08:20 PM PST 24
Peak memory 200196 kb
Host smart-15035971-7f26-4756-8624-0361485ce856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=310491151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.310491151
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1199958137
Short name T845
Test name
Test status
Simulation time 1269587779 ps
CPU time 12.13 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:56:46 PM PST 24
Peak memory 197880 kb
Host smart-5b238c26-b4d0-4ca0-97ad-2be70087f7aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199958137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1199958137
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.600827800
Short name T20
Test name
Test status
Simulation time 17398078012 ps
CPU time 178.67 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 12:59:35 PM PST 24
Peak memory 210248 kb
Host smart-e1ebc1bf-fee0-45c0-8084-aeaabd3051eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600827800 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.600827800
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1314421638
Short name T955
Test name
Test status
Simulation time 500721065 ps
CPU time 1.64 seconds
Started Jan 07 12:55:26 PM PST 24
Finished Jan 07 12:57:30 PM PST 24
Peak memory 198060 kb
Host smart-e10afe04-a545-4833-8e17-abd2100c663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314421638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1314421638
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1704997158
Short name T721
Test name
Test status
Simulation time 122783455068 ps
CPU time 31.01 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 12:57:14 PM PST 24
Peak memory 200224 kb
Host smart-5d9f26b9-0ae6-4381-a767-2ec93c22e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704997158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1704997158
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1746901023
Short name T768
Test name
Test status
Simulation time 35842777 ps
CPU time 0.54 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 12:56:31 PM PST 24
Peak memory 195544 kb
Host smart-f4efc555-73ce-4b74-8224-b5b9c956d61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746901023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1746901023
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3246081373
Short name T3
Test name
Test status
Simulation time 66936073881 ps
CPU time 102.29 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:58:19 PM PST 24
Peak memory 200316 kb
Host smart-5b123c15-20fb-4606-9b8e-89cd02863110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246081373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3246081373
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.455528076
Short name T367
Test name
Test status
Simulation time 26608830759 ps
CPU time 43.83 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 12:57:42 PM PST 24
Peak memory 200256 kb
Host smart-be8d699b-3f75-46e8-bb46-2ebbbf885040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455528076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.455528076
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.2493580030
Short name T725
Test name
Test status
Simulation time 578126586600 ps
CPU time 3511.51 seconds
Started Jan 07 12:54:58 PM PST 24
Finished Jan 07 01:54:51 PM PST 24
Peak memory 200144 kb
Host smart-4e87992e-9f85-43f1-a2dd-15fa84ac20e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493580030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2493580030
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_noise_filter.912378070
Short name T400
Test name
Test status
Simulation time 10068124241 ps
CPU time 11.71 seconds
Started Jan 07 12:54:53 PM PST 24
Finished Jan 07 12:56:48 PM PST 24
Peak memory 198216 kb
Host smart-ad375dee-4273-44c7-9725-df6a8b9b1f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912378070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.912378070
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.414622329
Short name T804
Test name
Test status
Simulation time 23059029880 ps
CPU time 530.64 seconds
Started Jan 07 12:55:17 PM PST 24
Finished Jan 07 01:05:49 PM PST 24
Peak memory 200320 kb
Host smart-ab41deee-e372-4fbd-807b-cdafe077807e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=414622329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.414622329
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3508614579
Short name T740
Test name
Test status
Simulation time 21759001616 ps
CPU time 18.13 seconds
Started Jan 07 12:54:54 PM PST 24
Finished Jan 07 12:56:48 PM PST 24
Peak memory 198640 kb
Host smart-f424b43b-be40-42bf-9aa0-26859e7a9e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508614579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3508614579
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3613487156
Short name T795
Test name
Test status
Simulation time 42856878479 ps
CPU time 8.62 seconds
Started Jan 07 12:54:58 PM PST 24
Finished Jan 07 12:56:47 PM PST 24
Peak memory 195904 kb
Host smart-b78e8db9-8dc9-43ce-86ee-170a7b91e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613487156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3613487156
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_stress_all.111135761
Short name T543
Test name
Test status
Simulation time 70652190174 ps
CPU time 376.35 seconds
Started Jan 07 12:54:52 PM PST 24
Finished Jan 07 01:02:59 PM PST 24
Peak memory 200116 kb
Host smart-4d1c29f5-123c-4872-b2fe-f70f4b05360c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111135761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.111135761
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2543909792
Short name T375
Test name
Test status
Simulation time 7568863743 ps
CPU time 10.27 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 12:56:42 PM PST 24
Peak memory 199936 kb
Host smart-6b3b224e-5ea0-48e1-b7f6-1f06df45bc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543909792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2543909792
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.466974153
Short name T364
Test name
Test status
Simulation time 22285545624 ps
CPU time 42.4 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:57:27 PM PST 24
Peak memory 200064 kb
Host smart-5ce1b9ed-8a19-4b59-b2cc-61e744dc3b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466974153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.466974153
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3594608100
Short name T754
Test name
Test status
Simulation time 13282707 ps
CPU time 0.56 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 12:54:40 PM PST 24
Peak memory 195556 kb
Host smart-506fe511-e157-45dc-bc2c-1658e589f048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594608100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3594608100
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3195227861
Short name T948
Test name
Test status
Simulation time 193112456816 ps
CPU time 344 seconds
Started Jan 07 12:53:03 PM PST 24
Finished Jan 07 01:00:31 PM PST 24
Peak memory 200152 kb
Host smart-ed7a590b-ccca-42da-af74-ac01f1ec2093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195227861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3195227861
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2773518440
Short name T614
Test name
Test status
Simulation time 331997257269 ps
CPU time 671.74 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 01:05:50 PM PST 24
Peak memory 200196 kb
Host smart-d1e9ecfc-412b-47b0-80dd-a22da88c68be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773518440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2773518440
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3875403557
Short name T352
Test name
Test status
Simulation time 186835539642 ps
CPU time 489.81 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 01:02:42 PM PST 24
Peak memory 200132 kb
Host smart-c8fe038a-7e43-4a24-86db-f587c650a1e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875403557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3875403557
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1512703622
Short name T531
Test name
Test status
Simulation time 12514821958 ps
CPU time 32.18 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:55:54 PM PST 24
Peak memory 199792 kb
Host smart-a4e1341e-3c2f-499b-87f4-cc89a79d9c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512703622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1512703622
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1218471101
Short name T822
Test name
Test status
Simulation time 50891816471 ps
CPU time 22.58 seconds
Started Jan 07 12:53:08 PM PST 24
Finished Jan 07 12:54:51 PM PST 24
Peak memory 197736 kb
Host smart-f0ea485f-a6f9-4d0a-a67c-4169dd0cc17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218471101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1218471101
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2996283654
Short name T520
Test name
Test status
Simulation time 19254179339 ps
CPU time 447.59 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 01:02:07 PM PST 24
Peak memory 200144 kb
Host smart-7bd03ef6-15d0-4778-bd6e-8b93f4449cc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996283654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2996283654
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1861452587
Short name T399
Test name
Test status
Simulation time 1734071874 ps
CPU time 8.16 seconds
Started Jan 07 12:52:57 PM PST 24
Finished Jan 07 12:54:23 PM PST 24
Peak memory 198320 kb
Host smart-f5faf0b3-dc3c-449b-a00e-328a2e0470a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861452587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1861452587
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2321103544
Short name T319
Test name
Test status
Simulation time 25779409195 ps
CPU time 11.5 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:54:59 PM PST 24
Peak memory 199764 kb
Host smart-6f6c274f-deff-4380-b15e-1f06e56387d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321103544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2321103544
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3911560193
Short name T373
Test name
Test status
Simulation time 4472117184 ps
CPU time 7.69 seconds
Started Jan 07 12:53:23 PM PST 24
Finished Jan 07 12:55:01 PM PST 24
Peak memory 196036 kb
Host smart-4ceb7614-904d-40a0-a19d-56a55fc4641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911560193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3911560193
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2699144323
Short name T366
Test name
Test status
Simulation time 306070743 ps
CPU time 1.55 seconds
Started Jan 07 12:53:03 PM PST 24
Finished Jan 07 12:54:48 PM PST 24
Peak memory 198136 kb
Host smart-1803cb65-13be-4c8f-a99e-22750512aa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699144323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2699144323
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1623824574
Short name T572
Test name
Test status
Simulation time 55997196818 ps
CPU time 494.57 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 01:02:45 PM PST 24
Peak memory 216632 kb
Host smart-ea7e0d60-8725-4c54-a7f4-4e2f9135f501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623824574 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1623824574
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1446825617
Short name T900
Test name
Test status
Simulation time 12305106781 ps
CPU time 32.55 seconds
Started Jan 07 12:53:10 PM PST 24
Finished Jan 07 12:54:55 PM PST 24
Peak memory 199832 kb
Host smart-838b8a00-2e4d-4e18-976d-55bb39110793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446825617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1446825617
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1294925902
Short name T640
Test name
Test status
Simulation time 34625768940 ps
CPU time 27.54 seconds
Started Jan 07 12:52:55 PM PST 24
Finished Jan 07 12:54:37 PM PST 24
Peak memory 200080 kb
Host smart-151daab2-ea56-4d69-8996-114ccea3107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294925902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1294925902
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1382113971
Short name T988
Test name
Test status
Simulation time 115703147445 ps
CPU time 164.15 seconds
Started Jan 07 12:54:49 PM PST 24
Finished Jan 07 12:59:11 PM PST 24
Peak memory 198856 kb
Host smart-5c0cca6a-3c1b-4f34-90dd-9168f9f5f760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382113971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1382113971
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3853311745
Short name T802
Test name
Test status
Simulation time 121672742100 ps
CPU time 1690.1 seconds
Started Jan 07 12:54:50 PM PST 24
Finished Jan 07 01:24:39 PM PST 24
Peak memory 233292 kb
Host smart-43739ca0-bab8-4483-b117-b1e35526113d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853311745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3853311745
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1913423632
Short name T982
Test name
Test status
Simulation time 20462332070 ps
CPU time 17.59 seconds
Started Jan 07 12:54:57 PM PST 24
Finished Jan 07 12:56:47 PM PST 24
Peak memory 200224 kb
Host smart-b8958223-7556-4862-a81f-716f4b0ccf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913423632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1913423632
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2596685935
Short name T918
Test name
Test status
Simulation time 22847466238 ps
CPU time 239.6 seconds
Started Jan 07 12:54:56 PM PST 24
Finished Jan 07 01:00:14 PM PST 24
Peak memory 208320 kb
Host smart-868607d7-8a21-47c5-b628-d4a8385b80ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596685935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2596685935
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.287544041
Short name T962
Test name
Test status
Simulation time 198470667233 ps
CPU time 376.99 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 01:02:35 PM PST 24
Peak memory 216852 kb
Host smart-3520bc99-9f91-4fce-b205-134b645c4b3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287544041 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.287544041
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3663184008
Short name T757
Test name
Test status
Simulation time 139580997369 ps
CPU time 214.05 seconds
Started Jan 07 12:55:15 PM PST 24
Finished Jan 07 01:00:29 PM PST 24
Peak memory 200120 kb
Host smart-4f96b471-2446-4e7c-b60a-0d0bb07a82f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663184008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3663184008
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3214625787
Short name T122
Test name
Test status
Simulation time 52026132137 ps
CPU time 93.71 seconds
Started Jan 07 12:54:50 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 200176 kb
Host smart-070ec48d-d14b-4d01-be6f-98417257622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214625787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3214625787
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3797255222
Short name T13
Test name
Test status
Simulation time 34022939811 ps
CPU time 360.63 seconds
Started Jan 07 12:54:38 PM PST 24
Finished Jan 07 01:02:59 PM PST 24
Peak memory 215076 kb
Host smart-070e489d-af1b-481b-8a76-6f8412d4d6c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797255222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3797255222
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2434105014
Short name T99
Test name
Test status
Simulation time 68564047955 ps
CPU time 44.61 seconds
Started Jan 07 12:54:29 PM PST 24
Finished Jan 07 12:56:48 PM PST 24
Peak memory 200104 kb
Host smart-313c0262-70b0-4cb4-83af-1497fc3c03ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434105014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2434105014
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1849504365
Short name T1040
Test name
Test status
Simulation time 62129124098 ps
CPU time 353.82 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 01:02:17 PM PST 24
Peak memory 214952 kb
Host smart-480886fb-2303-4814-8678-5da84c1d6e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849504365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1849504365
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2389921436
Short name T791
Test name
Test status
Simulation time 40103201265 ps
CPU time 112.4 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:58:23 PM PST 24
Peak memory 216804 kb
Host smart-7b6785c9-fbe2-443c-8746-9b0034b492e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389921436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2389921436
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2412828577
Short name T516
Test name
Test status
Simulation time 14207495 ps
CPU time 0.56 seconds
Started Jan 07 12:53:54 PM PST 24
Finished Jan 07 12:55:23 PM PST 24
Peak memory 195528 kb
Host smart-60e37125-8e88-453e-a944-e33417008131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412828577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2412828577
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.410884197
Short name T844
Test name
Test status
Simulation time 103077671171 ps
CPU time 43.81 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:55:12 PM PST 24
Peak memory 200168 kb
Host smart-b669e92f-bcb5-4f9c-a48f-7e8d4879c031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410884197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.410884197
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1175756118
Short name T966
Test name
Test status
Simulation time 610105164467 ps
CPU time 1022.93 seconds
Started Jan 07 12:53:11 PM PST 24
Finished Jan 07 01:11:41 PM PST 24
Peak memory 200252 kb
Host smart-6e28404c-23bc-41ae-9229-7f7dae477220
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175756118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1175756118
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2284683871
Short name T737
Test name
Test status
Simulation time 151051943930 ps
CPU time 1258.19 seconds
Started Jan 07 12:53:21 PM PST 24
Finished Jan 07 01:15:41 PM PST 24
Peak memory 200248 kb
Host smart-9fc55f5f-b395-460a-8f01-5035897a21e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284683871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2284683871
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1177148808
Short name T609
Test name
Test status
Simulation time 3885161824 ps
CPU time 7.77 seconds
Started Jan 07 12:53:21 PM PST 24
Finished Jan 07 12:54:53 PM PST 24
Peak memory 197860 kb
Host smart-04bc7699-723a-4577-891e-c1b3aee2c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177148808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1177148808
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1832595286
Short name T908
Test name
Test status
Simulation time 81025920732 ps
CPU time 15.81 seconds
Started Jan 07 12:53:17 PM PST 24
Finished Jan 07 12:54:48 PM PST 24
Peak memory 198468 kb
Host smart-a5a1e5bb-bb54-4ad2-9aa2-effd310523ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832595286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1832595286
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1669332522
Short name T552
Test name
Test status
Simulation time 13236152826 ps
CPU time 706.65 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 01:06:50 PM PST 24
Peak memory 200164 kb
Host smart-edd9d4ea-f83a-4859-990c-c51db9dcd281
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1669332522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1669332522
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1075037453
Short name T619
Test name
Test status
Simulation time 1628964738 ps
CPU time 2.04 seconds
Started Jan 07 12:53:15 PM PST 24
Finished Jan 07 12:54:31 PM PST 24
Peak memory 198156 kb
Host smart-4e33fd03-0471-4cc7-a069-6a4e3c35945c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075037453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1075037453
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2667761133
Short name T873
Test name
Test status
Simulation time 49075083788 ps
CPU time 45.26 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:55:49 PM PST 24
Peak memory 199928 kb
Host smart-5b6bf997-06b6-4c97-893d-e63d26eb2290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667761133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2667761133
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1815309748
Short name T827
Test name
Test status
Simulation time 657120097 ps
CPU time 0.88 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:55:21 PM PST 24
Peak memory 195648 kb
Host smart-e011c437-7f06-48f0-a646-ead50aba2f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815309748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1815309748
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2642675621
Short name T786
Test name
Test status
Simulation time 651299727 ps
CPU time 2.52 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 12:55:25 PM PST 24
Peak memory 198664 kb
Host smart-3faeff50-cedd-40aa-8a1b-320cdecf73c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642675621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2642675621
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3377664705
Short name T274
Test name
Test status
Simulation time 45255395964 ps
CPU time 485.06 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 01:03:32 PM PST 24
Peak memory 216572 kb
Host smart-48f2ee3f-6ec0-48aa-bb6d-2b97e963623a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377664705 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3377664705
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3790470877
Short name T554
Test name
Test status
Simulation time 4834260893 ps
CPU time 2.08 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:54:32 PM PST 24
Peak memory 198892 kb
Host smart-f7f8da5d-8df1-497d-bd1d-bf35b6c47191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790470877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3790470877
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.261421015
Short name T759
Test name
Test status
Simulation time 99449234038 ps
CPU time 255.36 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:58:35 PM PST 24
Peak memory 200188 kb
Host smart-6bfd8fe4-9ee3-4d84-8782-6519cb2a06bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261421015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.261421015
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1075397310
Short name T29
Test name
Test status
Simulation time 16153919659 ps
CPU time 64.5 seconds
Started Jan 07 12:54:39 PM PST 24
Finished Jan 07 12:57:05 PM PST 24
Peak memory 200144 kb
Host smart-30fa327c-4dbe-4e7d-bb6b-b58b3c9fd26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075397310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1075397310
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.928530387
Short name T925
Test name
Test status
Simulation time 65485509865 ps
CPU time 152.02 seconds
Started Jan 07 12:55:10 PM PST 24
Finished Jan 07 12:59:13 PM PST 24
Peak memory 211120 kb
Host smart-89e9ad33-1129-46f0-bdff-c99c81bb34cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928530387 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.928530387
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2370042584
Short name T225
Test name
Test status
Simulation time 27786253240 ps
CPU time 42.4 seconds
Started Jan 07 12:54:49 PM PST 24
Finished Jan 07 12:57:18 PM PST 24
Peak memory 199956 kb
Host smart-65273eb7-61b9-42bb-887b-9ccac00e388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370042584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2370042584
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2781546729
Short name T290
Test name
Test status
Simulation time 116094181177 ps
CPU time 342.84 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 01:02:20 PM PST 24
Peak memory 216888 kb
Host smart-f76d420e-2513-406f-a280-8ffc76b741cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781546729 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2781546729
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.347816663
Short name T178
Test name
Test status
Simulation time 51932847715 ps
CPU time 43.72 seconds
Started Jan 07 12:54:31 PM PST 24
Finished Jan 07 12:57:29 PM PST 24
Peak memory 200092 kb
Host smart-f89fb522-4c2c-4cb2-a22d-c73851b4217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347816663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.347816663
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1051721809
Short name T626
Test name
Test status
Simulation time 212641520043 ps
CPU time 715.84 seconds
Started Jan 07 12:54:36 PM PST 24
Finished Jan 07 01:07:57 PM PST 24
Peak memory 225376 kb
Host smart-48980ad7-b02f-4193-a5b7-e242e745497a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051721809 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1051721809
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1250797526
Short name T616
Test name
Test status
Simulation time 8000484384 ps
CPU time 14.5 seconds
Started Jan 07 12:54:57 PM PST 24
Finished Jan 07 12:57:03 PM PST 24
Peak memory 200104 kb
Host smart-25520f75-a0ce-4ad3-b1e4-6a8418dd66e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250797526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1250797526
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2040367264
Short name T295
Test name
Test status
Simulation time 551635048733 ps
CPU time 2122.3 seconds
Started Jan 07 12:54:47 PM PST 24
Finished Jan 07 01:31:29 PM PST 24
Peak memory 226676 kb
Host smart-1b891dc5-c8b2-489e-ada6-53a92df3a034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040367264 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2040367264
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.112690786
Short name T148
Test name
Test status
Simulation time 107814034542 ps
CPU time 39.55 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 12:57:10 PM PST 24
Peak memory 200068 kb
Host smart-8e67a544-7e19-44d5-9545-274691755f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112690786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.112690786
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2582497094
Short name T276
Test name
Test status
Simulation time 100669427297 ps
CPU time 75.2 seconds
Started Jan 07 12:55:09 PM PST 24
Finished Jan 07 12:57:44 PM PST 24
Peak memory 200128 kb
Host smart-fdc3b683-e9bb-4d35-b500-339dad6b23d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582497094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2582497094
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2985750188
Short name T269
Test name
Test status
Simulation time 98099344585 ps
CPU time 32.38 seconds
Started Jan 07 12:54:59 PM PST 24
Finished Jan 07 12:57:09 PM PST 24
Peak memory 200244 kb
Host smart-167d451c-58e6-4bd3-ad53-81d76e01c682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985750188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2985750188
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3685021131
Short name T923
Test name
Test status
Simulation time 26028135523 ps
CPU time 232.76 seconds
Started Jan 07 12:55:03 PM PST 24
Finished Jan 07 01:00:14 PM PST 24
Peak memory 215972 kb
Host smart-b341acaf-eb87-4def-8ae4-f3407fff34a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685021131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3685021131
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3507297530
Short name T837
Test name
Test status
Simulation time 11744064676 ps
CPU time 9.98 seconds
Started Jan 07 12:54:57 PM PST 24
Finished Jan 07 12:56:37 PM PST 24
Peak memory 199964 kb
Host smart-19eb5c15-ed24-40f8-9286-d29726b5536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507297530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3507297530
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.681292750
Short name T129
Test name
Test status
Simulation time 24918040940 ps
CPU time 41.56 seconds
Started Jan 07 12:54:56 PM PST 24
Finished Jan 07 12:57:13 PM PST 24
Peak memory 200208 kb
Host smart-85d0ac65-6061-449d-93fb-dfc1be20ca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681292750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.681292750
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.588836674
Short name T907
Test name
Test status
Simulation time 28670116090 ps
CPU time 287.72 seconds
Started Jan 07 12:55:01 PM PST 24
Finished Jan 07 01:01:21 PM PST 24
Peak memory 210896 kb
Host smart-a7dff545-46d6-4fd0-8392-07104fe744d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588836674 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.588836674
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2570393799
Short name T750
Test name
Test status
Simulation time 163877666901 ps
CPU time 109.83 seconds
Started Jan 07 12:55:16 PM PST 24
Finished Jan 07 12:58:43 PM PST 24
Peak memory 199576 kb
Host smart-fb7fd67d-df94-4d05-8779-df441035bcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570393799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2570393799
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3453293971
Short name T19
Test name
Test status
Simulation time 234069693927 ps
CPU time 590.01 seconds
Started Jan 07 12:54:46 PM PST 24
Finished Jan 07 01:06:14 PM PST 24
Peak memory 216600 kb
Host smart-3dc9f7ec-6352-4434-b114-63bdefb5cd82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453293971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3453293971
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2636560622
Short name T507
Test name
Test status
Simulation time 11822321 ps
CPU time 0.52 seconds
Started Jan 07 12:53:30 PM PST 24
Finished Jan 07 12:54:41 PM PST 24
Peak memory 195508 kb
Host smart-ef53340b-b9ce-4641-bbb4-d20bacce87e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636560622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2636560622
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1865339818
Short name T846
Test name
Test status
Simulation time 148180792450 ps
CPU time 190.43 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:57:51 PM PST 24
Peak memory 200220 kb
Host smart-b7b243e0-a994-4af5-a376-b562ac3f9532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865339818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1865339818
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1701746675
Short name T743
Test name
Test status
Simulation time 63855470701 ps
CPU time 53 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:56:23 PM PST 24
Peak memory 200148 kb
Host smart-ad3c49b0-a62f-4611-ae90-67ebac3b8be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701746675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1701746675
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3125202668
Short name T970
Test name
Test status
Simulation time 7445707150 ps
CPU time 12 seconds
Started Jan 07 12:53:28 PM PST 24
Finished Jan 07 12:55:17 PM PST 24
Peak memory 199412 kb
Host smart-04b18604-a008-4ff0-a6c4-97fed602ebba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125202668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3125202668
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2933509040
Short name T709
Test name
Test status
Simulation time 47479003820 ps
CPU time 210.27 seconds
Started Jan 07 12:53:44 PM PST 24
Finished Jan 07 12:58:35 PM PST 24
Peak memory 200156 kb
Host smart-2218a8a4-f2c5-4cad-ba1e-a1c476ce7741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2933509040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2933509040
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1657415574
Short name T658
Test name
Test status
Simulation time 6109276411 ps
CPU time 3.45 seconds
Started Jan 07 12:54:00 PM PST 24
Finished Jan 07 12:55:34 PM PST 24
Peak memory 196048 kb
Host smart-55c54d44-7865-43b0-8cae-d79df4e333db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657415574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1657415574
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3286624383
Short name T711
Test name
Test status
Simulation time 94247194471 ps
CPU time 83.18 seconds
Started Jan 07 12:53:43 PM PST 24
Finished Jan 07 12:56:28 PM PST 24
Peak memory 200536 kb
Host smart-78aefa63-c86c-4eb8-9f03-9c39583408a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286624383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3286624383
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3003701741
Short name T774
Test name
Test status
Simulation time 28556672778 ps
CPU time 1400.4 seconds
Started Jan 07 12:53:44 PM PST 24
Finished Jan 07 01:18:23 PM PST 24
Peak memory 200228 kb
Host smart-fc9da001-f64e-48af-b450-8892cc451867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003701741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3003701741
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3489224088
Short name T714
Test name
Test status
Simulation time 3783429481 ps
CPU time 11.92 seconds
Started Jan 07 12:54:00 PM PST 24
Finished Jan 07 12:55:34 PM PST 24
Peak memory 198552 kb
Host smart-af55f1b5-3956-454e-926f-c1c94d8a9e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489224088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3489224088
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.631919420
Short name T657
Test name
Test status
Simulation time 20897842758 ps
CPU time 30.67 seconds
Started Jan 07 12:53:55 PM PST 24
Finished Jan 07 12:55:54 PM PST 24
Peak memory 199348 kb
Host smart-a88a2945-681e-43f4-9158-b1955c502e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631919420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.631919420
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1161105776
Short name T637
Test name
Test status
Simulation time 2839720000 ps
CPU time 1.68 seconds
Started Jan 07 12:53:50 PM PST 24
Finished Jan 07 12:55:58 PM PST 24
Peak memory 195700 kb
Host smart-1459d14a-54bc-49fa-9199-a5e9f7642802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161105776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1161105776
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1369653371
Short name T676
Test name
Test status
Simulation time 155080791 ps
CPU time 0.8 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 12:54:36 PM PST 24
Peak memory 196696 kb
Host smart-9d5d7279-0cb9-49c5-876a-4077c6460e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369653371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1369653371
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.4458227
Short name T278
Test name
Test status
Simulation time 98436143417 ps
CPU time 157.86 seconds
Started Jan 07 12:53:25 PM PST 24
Finished Jan 07 12:57:17 PM PST 24
Peak memory 200092 kb
Host smart-a5a66736-da69-4042-8358-ae8f962dde11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4458227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.4458227
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1651473249
Short name T327
Test name
Test status
Simulation time 82684786507 ps
CPU time 134.79 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:56:46 PM PST 24
Peak memory 215900 kb
Host smart-83c93c65-70ba-47e9-a6e6-bd30949db389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651473249 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1651473249
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2758137059
Short name T868
Test name
Test status
Simulation time 6918400417 ps
CPU time 20.44 seconds
Started Jan 07 12:54:14 PM PST 24
Finished Jan 07 12:56:01 PM PST 24
Peak memory 199608 kb
Host smart-d5cc526f-ad2e-4ab1-b21b-07c08744b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758137059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2758137059
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.870948868
Short name T513
Test name
Test status
Simulation time 123885435263 ps
CPU time 79.05 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:56:17 PM PST 24
Peak memory 200132 kb
Host smart-19bb63ef-97a9-4cc4-adbc-37b507b0bd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870948868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.870948868
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2792696099
Short name T691
Test name
Test status
Simulation time 255409068637 ps
CPU time 74.44 seconds
Started Jan 07 12:54:49 PM PST 24
Finished Jan 07 12:57:50 PM PST 24
Peak memory 200152 kb
Host smart-eb0d0d5a-d975-4a2e-9fc3-d09cea7b3fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792696099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2792696099
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2381799605
Short name T693
Test name
Test status
Simulation time 40340838983 ps
CPU time 425.5 seconds
Started Jan 07 12:55:12 PM PST 24
Finished Jan 07 01:04:12 PM PST 24
Peak memory 215088 kb
Host smart-65f62967-09b8-4404-acec-a5d2af05ecfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381799605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2381799605
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3810707857
Short name T783
Test name
Test status
Simulation time 29261769509 ps
CPU time 290.07 seconds
Started Jan 07 12:54:53 PM PST 24
Finished Jan 07 01:01:18 PM PST 24
Peak memory 213168 kb
Host smart-e98ae579-adb0-48e3-889b-5ea4a31978d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810707857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3810707857
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1758122393
Short name T808
Test name
Test status
Simulation time 47592537521 ps
CPU time 7.78 seconds
Started Jan 07 12:55:20 PM PST 24
Finished Jan 07 12:56:55 PM PST 24
Peak memory 200128 kb
Host smart-d8a02597-4e8e-4f86-8a65-395fa09aa5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758122393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1758122393
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.531264568
Short name T1038
Test name
Test status
Simulation time 200058866860 ps
CPU time 552.81 seconds
Started Jan 07 12:54:57 PM PST 24
Finished Jan 07 01:05:38 PM PST 24
Peak memory 216664 kb
Host smart-3cf05f0c-7343-448b-87bb-22c032f7e0fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531264568 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.531264568
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3133024315
Short name T192
Test name
Test status
Simulation time 93341773057 ps
CPU time 41.02 seconds
Started Jan 07 12:54:48 PM PST 24
Finished Jan 07 12:57:39 PM PST 24
Peak memory 200148 kb
Host smart-f55841a8-abab-4b99-b8b6-8e7766fc7659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133024315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3133024315
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.952577913
Short name T273
Test name
Test status
Simulation time 10361896746 ps
CPU time 155.71 seconds
Started Jan 07 12:55:37 PM PST 24
Finished Jan 07 12:59:45 PM PST 24
Peak memory 215880 kb
Host smart-730d025f-9e71-4948-9cf2-5a0ce2f1d315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952577913 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.952577913
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2395901664
Short name T232
Test name
Test status
Simulation time 50263014422 ps
CPU time 85.5 seconds
Started Jan 07 12:54:53 PM PST 24
Finished Jan 07 12:57:38 PM PST 24
Peak memory 200200 kb
Host smart-b20d83b7-7397-477d-9612-785a599817ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395901664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2395901664
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2666427341
Short name T153
Test name
Test status
Simulation time 111107554814 ps
CPU time 920.6 seconds
Started Jan 07 12:55:26 PM PST 24
Finished Jan 07 01:12:35 PM PST 24
Peak memory 225028 kb
Host smart-b5517f06-61de-47cc-9d08-426f5c0b96c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666427341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2666427341
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.142415674
Short name T110
Test name
Test status
Simulation time 102559207221 ps
CPU time 164.13 seconds
Started Jan 07 12:54:54 PM PST 24
Finished Jan 07 12:59:21 PM PST 24
Peak memory 199588 kb
Host smart-7e2b1cfd-2aa4-495c-93a0-9169654565a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142415674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.142415674
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1367507816
Short name T249
Test name
Test status
Simulation time 30145932202 ps
CPU time 35.6 seconds
Started Jan 07 12:55:25 PM PST 24
Finished Jan 07 12:57:22 PM PST 24
Peak memory 200060 kb
Host smart-3d44e1b9-6073-4e1c-9f63-4e62a5dafe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367507816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1367507816
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2580216767
Short name T397
Test name
Test status
Simulation time 110883432621 ps
CPU time 458.93 seconds
Started Jan 07 12:55:03 PM PST 24
Finished Jan 07 01:04:01 PM PST 24
Peak memory 216816 kb
Host smart-38092b4e-4720-400d-afaf-838916628fe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580216767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2580216767
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3210695906
Short name T977
Test name
Test status
Simulation time 10382887 ps
CPU time 0.53 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:54:41 PM PST 24
Peak memory 194444 kb
Host smart-d0b77d88-db76-4245-9a39-637674789058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210695906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3210695906
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.4027208546
Short name T838
Test name
Test status
Simulation time 34329819122 ps
CPU time 56.14 seconds
Started Jan 07 12:52:53 PM PST 24
Finished Jan 07 12:55:05 PM PST 24
Peak memory 200184 kb
Host smart-bdfdec02-f1d0-4bce-b67f-b2999cd875f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027208546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4027208546
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3423913584
Short name T730
Test name
Test status
Simulation time 101967350547 ps
CPU time 73.99 seconds
Started Jan 07 12:53:37 PM PST 24
Finished Jan 07 12:56:07 PM PST 24
Peak memory 199348 kb
Host smart-e7c8958a-71b2-4db3-8e66-30b9ccc227c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423913584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3423913584
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2264190039
Short name T960
Test name
Test status
Simulation time 160735206431 ps
CPU time 264.15 seconds
Started Jan 07 12:53:38 PM PST 24
Finished Jan 07 12:59:39 PM PST 24
Peak memory 199992 kb
Host smart-1ac005b8-8853-4a46-9c1a-73656d12c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264190039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2264190039
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.107817670
Short name T630
Test name
Test status
Simulation time 31312120702 ps
CPU time 45.75 seconds
Started Jan 07 12:53:10 PM PST 24
Finished Jan 07 12:55:13 PM PST 24
Peak memory 199800 kb
Host smart-4181da7e-0a73-40ac-9580-87c2209cd231
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107817670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.107817670
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3453710926
Short name T675
Test name
Test status
Simulation time 89026810171 ps
CPU time 375.32 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 01:00:50 PM PST 24
Peak memory 200120 kb
Host smart-f8b8af76-5e3e-4219-8fca-c8c19d936ff2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453710926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3453710926
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2248783761
Short name T825
Test name
Test status
Simulation time 742739097 ps
CPU time 0.9 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:21 PM PST 24
Peak memory 195504 kb
Host smart-f9856db2-39ec-4b27-b6b6-ea70eb6a6e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248783761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2248783761
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.290742043
Short name T380
Test name
Test status
Simulation time 39930219562 ps
CPU time 19.26 seconds
Started Jan 07 12:53:03 PM PST 24
Finished Jan 07 12:54:40 PM PST 24
Peak memory 198924 kb
Host smart-93ff5d03-927b-409e-b4e5-6315d9fe9c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290742043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.290742043
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2726807603
Short name T875
Test name
Test status
Simulation time 32982796984 ps
CPU time 448.16 seconds
Started Jan 07 12:53:03 PM PST 24
Finished Jan 07 01:01:49 PM PST 24
Peak memory 200192 kb
Host smart-84543da8-9baa-41d2-ad95-a634ec6d436e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726807603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2726807603
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.958719170
Short name T905
Test name
Test status
Simulation time 1163661231 ps
CPU time 6.24 seconds
Started Jan 07 12:53:09 PM PST 24
Finished Jan 07 12:54:35 PM PST 24
Peak memory 198208 kb
Host smart-eb6607e5-4463-45b9-b1f6-27d2d936f581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=958719170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.958719170
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2887074984
Short name T325
Test name
Test status
Simulation time 14498439316 ps
CPU time 14.37 seconds
Started Jan 07 12:52:57 PM PST 24
Finished Jan 07 12:54:34 PM PST 24
Peak memory 199732 kb
Host smart-1c281ebf-cadd-4d7a-bc24-7b42fb3c9dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887074984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2887074984
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3058249777
Short name T368
Test name
Test status
Simulation time 2043626462 ps
CPU time 2.1 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:54:42 PM PST 24
Peak memory 195628 kb
Host smart-fced96b5-f491-4705-91eb-716610054520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058249777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3058249777
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_stress_all.1153669136
Short name T598
Test name
Test status
Simulation time 68946055281 ps
CPU time 134.4 seconds
Started Jan 07 12:53:25 PM PST 24
Finished Jan 07 12:57:00 PM PST 24
Peak memory 200104 kb
Host smart-4f6ce13b-aefa-438f-aec3-0a3fe3dce07b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153669136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1153669136
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3906664591
Short name T956
Test name
Test status
Simulation time 164461881698 ps
CPU time 42.26 seconds
Started Jan 07 12:53:19 PM PST 24
Finished Jan 07 12:55:26 PM PST 24
Peak memory 200132 kb
Host smart-f3fd9bef-e79e-4897-a4a5-14cf4bcbd2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906664591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3906664591
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2661582191
Short name T334
Test name
Test status
Simulation time 46427242861 ps
CPU time 443.37 seconds
Started Jan 07 12:55:00 PM PST 24
Finished Jan 07 01:03:45 PM PST 24
Peak memory 216808 kb
Host smart-b22ee203-68f6-4cec-8c6c-dfb880637c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661582191 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2661582191
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4014593884
Short name T106
Test name
Test status
Simulation time 292886913987 ps
CPU time 127.29 seconds
Started Jan 07 12:55:08 PM PST 24
Finished Jan 07 12:58:54 PM PST 24
Peak memory 200056 kb
Host smart-dd594623-6143-4a40-8cf1-cc1e27ac0cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014593884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4014593884
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2045993928
Short name T183
Test name
Test status
Simulation time 68913612945 ps
CPU time 647.58 seconds
Started Jan 07 12:55:26 PM PST 24
Finished Jan 07 01:07:42 PM PST 24
Peak memory 216992 kb
Host smart-dc2f2d17-a0ab-4f4b-83aa-cbfa2f7ae059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045993928 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2045993928
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2817237187
Short name T974
Test name
Test status
Simulation time 11715699671 ps
CPU time 10.47 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 12:57:00 PM PST 24
Peak memory 200080 kb
Host smart-d65f067e-b726-4e1c-8ab5-476daea81462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817237187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2817237187
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3047907685
Short name T378
Test name
Test status
Simulation time 12217920152 ps
CPU time 150.56 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:59:26 PM PST 24
Peak memory 215828 kb
Host smart-35d84f31-7cce-4753-afb4-db1edaa53195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047907685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3047907685
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1622356979
Short name T1031
Test name
Test status
Simulation time 20310715285 ps
CPU time 617.16 seconds
Started Jan 07 12:54:51 PM PST 24
Finished Jan 07 01:07:10 PM PST 24
Peak memory 210736 kb
Host smart-26b2be6d-df3e-48de-a13f-baebc03437a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622356979 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1622356979
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2948950409
Short name T540
Test name
Test status
Simulation time 24239649540 ps
CPU time 11.1 seconds
Started Jan 07 12:55:20 PM PST 24
Finished Jan 07 12:56:59 PM PST 24
Peak memory 200196 kb
Host smart-d8b9d912-272e-4849-ba51-73410e0ec8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948950409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2948950409
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.862489049
Short name T945
Test name
Test status
Simulation time 43829803059 ps
CPU time 589.53 seconds
Started Jan 07 12:55:02 PM PST 24
Finished Jan 07 01:06:45 PM PST 24
Peak memory 215816 kb
Host smart-92c3993d-9aca-4761-aa15-0e9b8bd2e9e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862489049 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.862489049
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1416266484
Short name T890
Test name
Test status
Simulation time 29283253899 ps
CPU time 158.1 seconds
Started Jan 07 12:54:58 PM PST 24
Finished Jan 07 12:58:56 PM PST 24
Peak memory 216940 kb
Host smart-b7291a4e-9d0f-4311-918d-f1598309b0d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416266484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1416266484
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.116710130
Short name T745
Test name
Test status
Simulation time 113735481091 ps
CPU time 47.38 seconds
Started Jan 07 12:55:14 PM PST 24
Finished Jan 07 12:57:25 PM PST 24
Peak memory 199788 kb
Host smart-875581db-91e3-4955-ad5d-816aa8554493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116710130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.116710130
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1489495568
Short name T302
Test name
Test status
Simulation time 305820474815 ps
CPU time 841.64 seconds
Started Jan 07 12:55:27 PM PST 24
Finished Jan 07 01:10:52 PM PST 24
Peak memory 216516 kb
Host smart-6c1ac435-e560-41f5-855d-22f06090db13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489495568 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1489495568
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.155045255
Short name T1002
Test name
Test status
Simulation time 51613517 ps
CPU time 0.53 seconds
Started Jan 07 12:54:02 PM PST 24
Finished Jan 07 12:55:37 PM PST 24
Peak memory 194468 kb
Host smart-6c8b0244-646f-4483-9122-d3d298220084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155045255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.155045255
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2669835992
Short name T374
Test name
Test status
Simulation time 224023933285 ps
CPU time 88.42 seconds
Started Jan 07 12:53:27 PM PST 24
Finished Jan 07 12:56:08 PM PST 24
Peak memory 200064 kb
Host smart-c4505293-9efc-45f2-b29e-e31a6b6f98a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669835992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2669835992
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.528617241
Short name T951
Test name
Test status
Simulation time 29648671322 ps
CPU time 50.95 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 12:55:56 PM PST 24
Peak memory 199756 kb
Host smart-6056b88a-f419-4936-acbb-0251575c27a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528617241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.528617241
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2553808971
Short name T993
Test name
Test status
Simulation time 52123371197 ps
CPU time 87.92 seconds
Started Jan 07 12:53:31 PM PST 24
Finished Jan 07 12:56:56 PM PST 24
Peak memory 200164 kb
Host smart-7d242493-d82f-441b-a630-6ce49d748b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553808971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2553808971
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1066926384
Short name T16
Test name
Test status
Simulation time 80137869787 ps
CPU time 15.62 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 12:55:00 PM PST 24
Peak memory 198732 kb
Host smart-7f65a3d8-7aaa-4939-8f8f-ec9d01cf58ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066926384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1066926384
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2842405282
Short name T766
Test name
Test status
Simulation time 216770042393 ps
CPU time 68.33 seconds
Started Jan 07 12:53:24 PM PST 24
Finished Jan 07 12:55:58 PM PST 24
Peak memory 200144 kb
Host smart-19bb7424-8aec-4ffa-9ae5-52ff8705da98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842405282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2842405282
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_perf.1843798534
Short name T509
Test name
Test status
Simulation time 6526393559 ps
CPU time 379.37 seconds
Started Jan 07 12:53:36 PM PST 24
Finished Jan 07 01:01:13 PM PST 24
Peak memory 200144 kb
Host smart-c52f0122-6b10-4cd3-b1e8-0e96ce4da101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843798534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1843798534
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1539842278
Short name T696
Test name
Test status
Simulation time 3040498321 ps
CPU time 25.28 seconds
Started Jan 07 12:53:22 PM PST 24
Finished Jan 07 12:54:58 PM PST 24
Peak memory 198560 kb
Host smart-cfa1b709-dcd2-4852-931f-076f6699b19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539842278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1539842278
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2968750989
Short name T544
Test name
Test status
Simulation time 6466569759 ps
CPU time 5.49 seconds
Started Jan 07 12:53:34 PM PST 24
Finished Jan 07 12:54:59 PM PST 24
Peak memory 195928 kb
Host smart-fd66d634-3bbd-455e-b521-a6ac4cce5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968750989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2968750989
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1074877460
Short name T855
Test name
Test status
Simulation time 929965788 ps
CPU time 3.71 seconds
Started Jan 07 12:53:15 PM PST 24
Finished Jan 07 12:54:36 PM PST 24
Peak memory 199288 kb
Host smart-42fd91fe-268c-434f-945d-ef0223e1226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074877460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1074877460
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.69449049
Short name T546
Test name
Test status
Simulation time 44581662671 ps
CPU time 499.83 seconds
Started Jan 07 12:53:42 PM PST 24
Finished Jan 07 01:03:25 PM PST 24
Peak memory 216868 kb
Host smart-6d960014-ad7d-4609-b742-708559193bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69449049 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.69449049
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.562670862
Short name T363
Test name
Test status
Simulation time 7483521448 ps
CPU time 8.92 seconds
Started Jan 07 12:53:29 PM PST 24
Finished Jan 07 12:54:56 PM PST 24
Peak memory 200156 kb
Host smart-10ad7b92-94a4-4b5a-9fed-683c55743cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562670862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.562670862
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.111586546
Short name T888
Test name
Test status
Simulation time 70178570197 ps
CPU time 53.13 seconds
Started Jan 07 12:53:13 PM PST 24
Finished Jan 07 12:55:32 PM PST 24
Peak memory 200204 kb
Host smart-fc18340b-c601-4183-8972-02c1a2d2d7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111586546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.111586546
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.972202543
Short name T280
Test name
Test status
Simulation time 23282296504 ps
CPU time 198.01 seconds
Started Jan 07 12:55:29 PM PST 24
Finished Jan 07 01:00:44 PM PST 24
Peak memory 216560 kb
Host smart-e0b8d433-751e-4cc8-bb64-679632c32e39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972202543 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.972202543
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.139253545
Short name T515
Test name
Test status
Simulation time 114423247120 ps
CPU time 94.66 seconds
Started Jan 07 12:54:53 PM PST 24
Finished Jan 07 12:58:11 PM PST 24
Peak memory 199708 kb
Host smart-cc3b3384-52b2-4d29-9f84-5943c7dc56d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139253545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.139253545
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.121140628
Short name T138
Test name
Test status
Simulation time 77140844121 ps
CPU time 30.06 seconds
Started Jan 07 12:54:54 PM PST 24
Finished Jan 07 12:57:03 PM PST 24
Peak memory 200092 kb
Host smart-4060a9a6-3e64-4d73-b3fe-a61383efdd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121140628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.121140628
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1680629559
Short name T144
Test name
Test status
Simulation time 15896255925 ps
CPU time 27.63 seconds
Started Jan 07 12:54:48 PM PST 24
Finished Jan 07 12:56:46 PM PST 24
Peak memory 200160 kb
Host smart-940bd83b-2aac-4a5b-8da5-b4570dd002c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680629559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1680629559
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1525407563
Short name T306
Test name
Test status
Simulation time 54655894513 ps
CPU time 214.4 seconds
Started Jan 07 12:55:25 PM PST 24
Finished Jan 07 01:00:19 PM PST 24
Peak memory 216372 kb
Host smart-fe5548d0-af4f-4910-a9c3-4d2336480cd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525407563 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1525407563
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3523249226
Short name T739
Test name
Test status
Simulation time 23529924679 ps
CPU time 8.54 seconds
Started Jan 07 12:55:02 PM PST 24
Finished Jan 07 12:56:46 PM PST 24
Peak memory 200208 kb
Host smart-917131f9-ea95-4024-97cd-5a8a0adb2161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523249226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3523249226
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.4043728882
Short name T687
Test name
Test status
Simulation time 222057299203 ps
CPU time 1441.2 seconds
Started Jan 07 12:55:05 PM PST 24
Finished Jan 07 01:20:46 PM PST 24
Peak memory 224808 kb
Host smart-96c4c31b-6cf0-4480-8b38-38ae5b83ff11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043728882 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.4043728882
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3861008773
Short name T933
Test name
Test status
Simulation time 91289985825 ps
CPU time 27.08 seconds
Started Jan 07 12:55:35 PM PST 24
Finished Jan 07 12:57:21 PM PST 24
Peak memory 200144 kb
Host smart-0f7c9779-9b2c-4323-9c22-d987d1271dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861008773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3861008773
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.878678014
Short name T758
Test name
Test status
Simulation time 45788114720 ps
CPU time 100.7 seconds
Started Jan 07 12:55:18 PM PST 24
Finished Jan 07 12:58:27 PM PST 24
Peak memory 208492 kb
Host smart-3cd68e08-d76e-45a1-abd2-5b4b70ded85a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878678014 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.878678014
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4129458995
Short name T817
Test name
Test status
Simulation time 53488641713 ps
CPU time 71.19 seconds
Started Jan 07 12:55:35 PM PST 24
Finished Jan 07 12:58:25 PM PST 24
Peak memory 200224 kb
Host smart-6f3384e6-570e-473f-95dc-32f9eeaba0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129458995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4129458995
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1614294051
Short name T358
Test name
Test status
Simulation time 87544891154 ps
CPU time 1574.58 seconds
Started Jan 07 12:55:36 PM PST 24
Finished Jan 07 01:23:39 PM PST 24
Peak memory 225084 kb
Host smart-20f3c747-30ef-4857-8357-5ca20e34c0d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614294051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1614294051
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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