Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	142229	1			T9	1		T10	8		T32	5
all_values[1]	142229	1			T9	1		T10	8		T32	5
all_values[2]	142229	1			T9	1		T10	8		T32	5
all_values[3]	142229	1			T9	1		T10	8		T32	5
all_values[4]	142229	1			T9	1		T10	8		T32	5
all_values[5]	142229	1			T9	1		T10	8		T32	5
all_values[6]	142229	1			T9	1		T10	8		T32	5
all_values[7]	142229	1			T9	1		T10	8		T32	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

567851

1

T9

8

T10

29

T32

19

auto[1]

569981

1

T10

35

T32

21

T33

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119901

1

T9

8

T10

37

T32

19

auto[1]

17931

1

T10

27

T32

21

T33

28

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	74839	1			T9	1		T32	4		T33	4
all_values[0]	auto[0]	auto[1]	2682	1			T10	2		T85	2		T91	1
all_values[0]	auto[1]	auto[0]	62422	1			T10	5		T33	1		T85	2
all_values[0]	auto[1]	auto[1]	2286	1			T10	1		T32	1		T33	3
all_values[1]	auto[0]	auto[0]	65581	1			T9	1		T10	2		T32	2
all_values[1]	auto[0]	auto[1]	2433	1			T32	2		T33	1		T50	1
all_values[1]	auto[1]	auto[0]	71323	1			T10	6		T32	1		T33	3
all_values[1]	auto[1]	auto[1]	2892	1			T33	1		T63	1		T401	2
all_values[2]	auto[0]	auto[0]	65390	1			T9	1		T10	1		T32	1
all_values[2]	auto[0]	auto[1]	2559	1			T10	3		T32	3		T33	1
all_values[2]	auto[1]	auto[0]	71946	1			T10	3		T33	3		T50	1
all_values[2]	auto[1]	auto[1]	2334	1			T10	1		T32	1		T33	4
all_values[3]	auto[0]	auto[0]	71144	1			T9	1		T10	4		T32	1
all_values[3]	auto[0]	auto[1]	261	1			T10	2		T33	3		T85	2
all_values[3]	auto[1]	auto[0]	70590	1			T32	2		T50	4		T85	1
all_values[3]	auto[1]	auto[1]	234	1			T10	2		T32	2		T33	2
all_values[4]	auto[0]	auto[0]	73915	1			T9	1		T10	1		T33	5
all_values[4]	auto[0]	auto[1]	449	1			T10	3		T85	2		T401	2
all_values[4]	auto[1]	auto[0]	67451	1			T10	3		T32	2		T33	1
all_values[4]	auto[1]	auto[1]	414	1			T10	1		T32	3		T33	2
all_values[5]	auto[0]	auto[0]	70916	1			T9	1		T10	1		T33	3
all_values[5]	auto[0]	auto[1]	165	1			T33	2		T92	2		T63	1
all_values[5]	auto[1]	auto[0]	70937	1			T10	2		T32	2		T33	2
all_values[5]	auto[1]	auto[1]	211	1			T10	5		T32	3		T33	1
all_values[6]	auto[0]	auto[0]	67553	1			T9	1		T10	3		T32	3
all_values[6]	auto[0]	auto[1]	173	1			T10	3		T32	2		T33	1
all_values[6]	auto[1]	auto[0]	74309	1			T10	1		T33	1		T50	1
all_values[6]	auto[1]	auto[1]	194	1			T10	1		T33	4		T91	3
all_values[7]	auto[0]	auto[0]	69480	1			T9	1		T10	3		T33	4
all_values[7]	auto[0]	auto[1]	311	1			T10	1		T32	1		T33	2
all_values[7]	auto[1]	auto[0]	72105	1			T10	2		T32	1		T33	1
all_values[7]	auto[1]	auto[1]	333	1			T10	2		T32	3		T33	1