Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2523

1

T1

11

T2

1

T3

1

auto[UartRx]

2523

1

T1

11

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4469	1			T1	22		T2	2		T3	2
values[1]	44	1			T29	1		T27	2		T422	1
values[2]	44	1			T28	1		T21	1		T412	1
values[3]	44	1			T28	1		T29	1		T27	1
values[4]	47	1			T26	1		T28	1		T21	1
values[5]	64	1			T26	1		T21	2		T29	1
values[6]	50	1			T26	2		T28	1		T21	3
values[7]	57	1			T25	1		T29	1		T322	1
values[8]	53	1			T25	1		T28	1		T27	1
values[9]	54	1			T322	2		T422	1		T96	1
values[10]	72	1			T26	1		T21	1		T29	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2327	1			T1	11		T2	1		T3	1
auto[UartTx]	values[1]	14	1			T29	1		T422	1		T459	1
auto[UartTx]	values[2]	13	1			T21	1		T422	1		T429	1
auto[UartTx]	values[3]	13	1			T28	1		T422	1		T425	1
auto[UartTx]	values[4]	27	1			T26	1		T412	1		T23	1
auto[UartTx]	values[5]	20	1			T29	1		T322	2		T433	1
auto[UartTx]	values[6]	16	1			T344	1		T459	1		T202	1
auto[UartTx]	values[7]	19	1			T29	1		T412	1		T422	2
auto[UartTx]	values[8]	15	1			T426	1		T202	1		T450	1
auto[UartTx]	values[9]	21	1			T322	1		T96	1		T459	1
auto[UartTx]	values[10]	24	1			T412	1		T422	1		T433	1
auto[UartRx]	values[0]	2142	1			T1	11		T2	1		T3	1
auto[UartRx]	values[1]	30	1			T27	2		T96	1		T344	1
auto[UartRx]	values[2]	31	1			T28	1		T412	1		T429	1
auto[UartRx]	values[3]	31	1			T29	1		T27	1		T433	1
auto[UartRx]	values[4]	20	1			T28	1		T21	1		T412	1
auto[UartRx]	values[5]	44	1			T26	1		T21	2		T322	2
auto[UartRx]	values[6]	34	1			T26	2		T28	1		T21	3
auto[UartRx]	values[7]	38	1			T25	1		T322	1		T425	1
auto[UartRx]	values[8]	38	1			T25	1		T28	1		T27	1
auto[UartRx]	values[9]	33	1			T322	1		T422	1		T448	4
auto[UartRx]	values[10]	48	1			T26	1		T21	1		T29	1