Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1992	1			T12	2		T13	2		T14	4
auto[BaudRate115200]	2189	1			T11	1		T14	1		T18	1
auto[BaudRate230400]	2121	1			T13	3		T16	3		T17	1
auto[BaudRate128Kbps]	1975	1			T12	3		T13	1		T14	1
auto[BaudRate256Kbps]	2131	1			T12	2		T13	2		T15	3
auto[BaudRate1Mbps]	1735	1			T11	1		T13	1		T14	1
auto[BaudRate1p5Mbps]	1261	1			T12	2		T15	1		T16	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1305	1			T11	2		T15	5		T20	16
freqs[25]	883	1			T17	2		T19	6		T28	44
freqs[48]	564	1			T24	7		T313	9		T410	20
freqs[50]	605	1			T413	12		T257	5		T346	10
freqs[100]	1520	1			T12	9		T13	9		T114	7

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	189	1			T20	1		T25	4		T21	5
auto[BaudRate9600]	freqs[25]	109	1			T28	7		T216	1		T129	3
auto[BaudRate9600]	freqs[48]	95	1			T24	1		T410	5		T126	1
auto[BaudRate9600]	freqs[50]	72	1			T413	3		T346	2		T443	1
auto[BaudRate9600]	freqs[100]	228	1			T12	2		T13	2		T114	2
auto[BaudRate115200]	freqs[24]	221	1			T11	1		T20	1		T25	10
auto[BaudRate115200]	freqs[25]	135	1			T28	11		T216	1		T131	1
auto[BaudRate115200]	freqs[48]	96	1			T24	2		T313	2		T410	2
auto[BaudRate115200]	freqs[50]	97	1			T413	2		T346	1		T227	1
auto[BaudRate115200]	freqs[100]	217	1			T123	2		T188	2		T412	14
auto[BaudRate230400]	freqs[24]	151	1			T20	1		T25	3		T21	7
auto[BaudRate230400]	freqs[25]	148	1			T17	1		T19	1		T28	5
auto[BaudRate230400]	freqs[48]	68	1			T313	1		T410	2		T357	1
auto[BaudRate230400]	freqs[50]	109	1			T413	1		T346	2		T227	1
auto[BaudRate230400]	freqs[100]	236	1			T13	3		T458	1		T123	1
auto[BaudRate128Kbps]	freqs[24]	202	1			T20	3		T25	8		T21	3
auto[BaudRate128Kbps]	freqs[25]	109	1			T19	4		T28	5		T216	2
auto[BaudRate128Kbps]	freqs[48]	62	1			T313	2		T410	2		T357	1
auto[BaudRate128Kbps]	freqs[50]	81	1			T413	1		T257	1		T346	1
auto[BaudRate128Kbps]	freqs[100]	235	1			T12	3		T13	1		T114	2
auto[BaudRate256Kbps]	freqs[24]	221	1			T15	3		T20	4		T25	5
auto[BaudRate256Kbps]	freqs[25]	157	1			T17	1		T19	1		T28	6
auto[BaudRate256Kbps]	freqs[48]	86	1			T24	3		T313	1		T410	5
auto[BaudRate256Kbps]	freqs[50]	79	1			T413	1		T346	1		T120	2
auto[BaudRate256Kbps]	freqs[100]	201	1			T12	2		T13	2		T188	2
auto[BaudRate1Mbps]	freqs[24]	211	1			T11	1		T15	1		T20	5
auto[BaudRate1Mbps]	freqs[25]	148	1			T28	7		T417	3		T409	2
auto[BaudRate1Mbps]	freqs[48]	69	1			T313	1		T410	3		T357	1
auto[BaudRate1Mbps]	freqs[50]	96	1			T413	2		T257	3		T346	1
auto[BaudRate1Mbps]	freqs[100]	217	1			T13	1		T114	2		T123	1
auto[BaudRate1p5Mbps]	freqs[25]	77	1			T28	3		T417	5		T409	3
auto[BaudRate1p5Mbps]	freqs[48]	88	1			T24	1		T313	2		T410	1
auto[BaudRate1p5Mbps]	freqs[50]	71	1			T413	2		T257	1		T346	2
auto[BaudRate1p5Mbps]	freqs[100]	186	1			T12	2		T114	1		T123	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded