Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2364 1 T32 2 T33 2 T50 1
all_levels[1] 516 1 T13 6 T114 1 T26 1
all_levels[2] 375 1 T19 1 T24 4 T223 1
all_levels[3] 309 1 T14 1 T16 1 T20 1
all_levels[4] 545 1 T13 2 T18 1 T25 2
all_levels[5] 782 1 T417 2 T318 1 T357 2
all_levels[6] 219 1 T114 2 T26 3 T140 1
all_levels[7] 213 1 T154 2 T166 1 T121 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%