Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[1] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[2] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[3] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[4] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[5] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[6] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[7] |
142229 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
1128140 |
1 |
|
|
T9 |
8 |
|
T10 |
51 |
|
T32 |
27 |
values[0x1] |
9692 |
1 |
|
|
T10 |
13 |
|
T32 |
13 |
|
T33 |
18 |
transitions[0x0=>0x1] |
8778 |
1 |
|
|
T10 |
10 |
|
T32 |
8 |
|
T33 |
10 |
transitions[0x1=>0x0] |
8788 |
1 |
|
|
T10 |
10 |
|
T32 |
8 |
|
T33 |
10 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
32 |
0 |
32 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
139893 |
1 |
|
|
T9 |
1 |
|
T10 |
7 |
|
T32 |
4 |
all_pins[0] |
values[0x1] |
2336 |
1 |
|
|
T10 |
1 |
|
T32 |
1 |
|
T33 |
3 |
all_pins[0] |
transitions[0x0=>0x1] |
2037 |
1 |
|
|
T10 |
1 |
|
T32 |
1 |
|
T33 |
2 |
all_pins[0] |
transitions[0x1=>0x0] |
2595 |
1 |
|
|
T63 |
1 |
|
T401 |
1 |
|
T402 |
1 |
all_pins[1] |
values[0x0] |
139335 |
1 |
|
|
T9 |
1 |
|
T10 |
8 |
|
T32 |
5 |
all_pins[1] |
values[0x1] |
2894 |
1 |
|
|
T33 |
1 |
|
T63 |
1 |
|
T401 |
2 |
all_pins[1] |
transitions[0x0=>0x1] |
2615 |
1 |
|
|
T63 |
1 |
|
T401 |
2 |
|
T402 |
1 |
all_pins[1] |
transitions[0x1=>0x0] |
2133 |
1 |
|
|
T10 |
1 |
|
T32 |
1 |
|
T33 |
3 |
all_pins[2] |
values[0x0] |
139817 |
1 |
|
|
T9 |
1 |
|
T10 |
7 |
|
T32 |
4 |
all_pins[2] |
values[0x1] |
2412 |
1 |
|
|
T10 |
1 |
|
T32 |
1 |
|
T33 |
4 |
all_pins[2] |
transitions[0x0=>0x1] |
2372 |
1 |
|
|
T10 |
1 |
|
T32 |
1 |
|
T33 |
2 |
all_pins[2] |
transitions[0x1=>0x0] |
194 |
1 |
|
|
T10 |
2 |
|
T32 |
2 |
|
T50 |
1 |
all_pins[3] |
values[0x0] |
141995 |
1 |
|
|
T9 |
1 |
|
T10 |
6 |
|
T32 |
3 |
all_pins[3] |
values[0x1] |
234 |
1 |
|
|
T10 |
2 |
|
T32 |
2 |
|
T33 |
2 |
all_pins[3] |
transitions[0x0=>0x1] |
189 |
1 |
|
|
T10 |
1 |
|
T85 |
2 |
|
T92 |
3 |
all_pins[3] |
transitions[0x1=>0x0] |
369 |
1 |
|
|
T32 |
1 |
|
T85 |
2 |
|
T91 |
1 |
all_pins[4] |
values[0x0] |
141815 |
1 |
|
|
T9 |
1 |
|
T10 |
7 |
|
T32 |
2 |
all_pins[4] |
values[0x1] |
414 |
1 |
|
|
T10 |
1 |
|
T32 |
3 |
|
T33 |
2 |
all_pins[4] |
transitions[0x0=>0x1] |
335 |
1 |
|
|
T32 |
1 |
|
T33 |
2 |
|
T85 |
2 |
all_pins[4] |
transitions[0x1=>0x0] |
183 |
1 |
|
|
T10 |
4 |
|
T32 |
1 |
|
T33 |
1 |
all_pins[5] |
values[0x0] |
141967 |
1 |
|
|
T9 |
1 |
|
T10 |
3 |
|
T32 |
2 |
all_pins[5] |
values[0x1] |
262 |
1 |
|
|
T10 |
5 |
|
T32 |
3 |
|
T33 |
1 |
all_pins[5] |
transitions[0x0=>0x1] |
209 |
1 |
|
|
T10 |
4 |
|
T32 |
3 |
|
T50 |
1 |
all_pins[5] |
transitions[0x1=>0x0] |
754 |
1 |
|
|
T33 |
3 |
|
T63 |
2 |
|
T401 |
4 |
all_pins[6] |
values[0x0] |
141422 |
1 |
|
|
T9 |
1 |
|
T10 |
7 |
|
T32 |
5 |
all_pins[6] |
values[0x1] |
807 |
1 |
|
|
T10 |
1 |
|
T33 |
4 |
|
T91 |
3 |
all_pins[6] |
transitions[0x0=>0x1] |
756 |
1 |
|
|
T10 |
1 |
|
T33 |
3 |
|
T91 |
2 |
all_pins[6] |
transitions[0x1=>0x0] |
282 |
1 |
|
|
T10 |
2 |
|
T32 |
3 |
|
T91 |
1 |
all_pins[7] |
values[0x0] |
141896 |
1 |
|
|
T9 |
1 |
|
T10 |
6 |
|
T32 |
2 |
all_pins[7] |
values[0x1] |
333 |
1 |
|
|
T10 |
2 |
|
T32 |
3 |
|
T33 |
1 |
all_pins[7] |
transitions[0x0=>0x1] |
265 |
1 |
|
|
T10 |
2 |
|
T32 |
2 |
|
T33 |
1 |
all_pins[7] |
transitions[0x1=>0x0] |
2278 |
1 |
|
|
T10 |
1 |
|
T33 |
3 |
|
T85 |
2 |