Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	794	1			T10	7		T32	4		T33	7
all_values[1]	794	1			T10	7		T32	4		T33	7
all_values[2]	794	1			T10	7		T32	4		T33	7
all_values[3]	794	1			T10	7		T32	4		T33	7
all_values[4]	794	1			T10	7		T32	4		T33	7
all_values[5]	794	1			T10	7		T32	4		T33	7
all_values[6]	794	1			T10	7		T32	4		T33	7
all_values[7]	794	1			T10	7		T32	4		T33	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3453

1

T10

32

T32

19

T33

32

auto[1]

2899

1

T10

24

T32

13

T33

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2507

1

T10

18

T32

8

T33

18

auto[1]

3845

1

T10

38

T32

24

T33

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3740

1

T10

34

T32

17

T33

28

auto[1]

2612

1

T10

22

T32

15

T33

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	187	1			T32	2		T33	2		T50	4
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T10	1		T85	1		T92	1
all_values[0]	auto[0]	auto[1]	auto[0]	144	1			T10	2		T85	1		T91	1
all_values[0]	auto[0]	auto[1]	auto[1]	64	1			T10	1		T32	1		T85	1
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T10	2		T32	1		T33	3
all_values[0]	auto[1]	auto[1]	auto[1]	138	1			T10	1		T33	2		T85	2
all_values[1]	auto[0]	auto[0]	auto[0]	155	1			T10	4		T32	1		T33	3
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T32	1		T50	1		T401	1
all_values[1]	auto[0]	auto[1]	auto[0]	145	1			T10	2		T33	1		T50	1
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T33	2		T403	1		T404	2
all_values[1]	auto[1]	auto[0]	auto[1]	196	1			T10	1		T32	1		T33	1
all_values[1]	auto[1]	auto[1]	auto[1]	143	1			T32	1		T92	1		T63	1
all_values[2]	auto[0]	auto[0]	auto[0]	159	1			T50	1		T85	2		T91	1
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T10	2		T32	1		T85	2
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T10	1		T33	1		T92	1
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T10	1		T33	2		T50	1
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T10	3		T32	2		T33	1
all_values[2]	auto[1]	auto[1]	auto[1]	142	1			T32	1		T33	3		T50	1
all_values[3]	auto[0]	auto[0]	auto[0]	182	1			T10	3		T32	2		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T10	2		T33	1		T85	1
all_values[3]	auto[0]	auto[1]	auto[0]	126	1			T50	2		T91	2		T63	3
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T10	1		T32	1		T92	2
all_values[3]	auto[1]	auto[0]	auto[1]	185	1			T33	4		T85	2		T92	1
all_values[3]	auto[1]	auto[1]	auto[1]	135	1			T10	1		T32	1		T33	1
all_values[4]	auto[0]	auto[0]	auto[0]	183	1			T10	1		T32	1		T33	3
all_values[4]	auto[0]	auto[0]	auto[1]	70	1			T10	1		T85	1		T401	1
all_values[4]	auto[0]	auto[1]	auto[0]	155	1			T10	1		T85	1		T91	1
all_values[4]	auto[0]	auto[1]	auto[1]	62	1			T10	1		T32	1		T85	1
all_values[4]	auto[1]	auto[0]	auto[1]	185	1			T10	1		T33	3		T85	2
all_values[4]	auto[1]	auto[1]	auto[1]	139	1			T10	2		T32	2		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	167	1			T10	1		T33	2		T50	1
all_values[5]	auto[0]	auto[0]	auto[1]	75	1			T405	2		T74	1		T406	1
all_values[5]	auto[0]	auto[1]	auto[0]	131	1			T33	1		T50	1		T92	1
all_values[5]	auto[0]	auto[1]	auto[1]	85	1			T10	3		T32	1		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	167	1			T32	1		T33	2		T85	1
all_values[5]	auto[1]	auto[1]	auto[1]	169	1			T10	3		T32	2		T33	1
all_values[6]	auto[0]	auto[0]	auto[0]	185	1			T10	1		T32	2		T33	2
all_values[6]	auto[0]	auto[0]	auto[1]	67	1			T10	1		T32	1		T401	1
all_values[6]	auto[0]	auto[1]	auto[0]	131	1			T10	1		T50	1		T85	1
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T33	2		T91	2		T63	1
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T10	3		T32	1		T50	1
all_values[6]	auto[1]	auto[1]	auto[1]	147	1			T10	1		T33	3		T91	1
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T10	1		T33	2		T50	2
all_values[7]	auto[0]	auto[0]	auto[1]	81	1			T10	1		T32	1		T33	1
all_values[7]	auto[0]	auto[1]	auto[0]	151	1			T50	1		T85	1		T91	1
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T10	1		T32	1		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	167	1			T10	3		T32	1		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	140	1			T10	1		T32	1		T33	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal