Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.79 98.45 100.00 99.76 100.00 97.67


Total test records in report: 1302
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T1255 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4070325451 Jan 17 12:43:43 PM PST 24 Jan 17 12:43:46 PM PST 24 26111536 ps
T1256 /workspace/coverage/cover_reg_top/2.uart_intr_test.969487143 Jan 17 12:43:45 PM PST 24 Jan 17 12:43:49 PM PST 24 12614701 ps
T1257 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1785281181 Jan 17 12:43:52 PM PST 24 Jan 17 12:43:54 PM PST 24 30697532 ps
T1258 /workspace/coverage/cover_reg_top/49.uart_intr_test.692760183 Jan 17 12:44:22 PM PST 24 Jan 17 12:44:24 PM PST 24 43213416 ps
T1259 /workspace/coverage/cover_reg_top/37.uart_intr_test.4277450198 Jan 17 12:44:13 PM PST 24 Jan 17 12:44:14 PM PST 24 38994504 ps
T1260 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.79919891 Jan 17 12:43:48 PM PST 24 Jan 17 12:43:51 PM PST 24 199744718 ps
T1261 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1277132045 Jan 17 12:44:04 PM PST 24 Jan 17 12:44:11 PM PST 24 25329451 ps
T1262 /workspace/coverage/cover_reg_top/41.uart_intr_test.578753535 Jan 17 12:44:18 PM PST 24 Jan 17 12:44:19 PM PST 24 11879464 ps
T1263 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2925753550 Jan 17 12:44:17 PM PST 24 Jan 17 12:44:19 PM PST 24 15593206 ps
T1264 /workspace/coverage/cover_reg_top/16.uart_intr_test.3805292411 Jan 17 12:44:16 PM PST 24 Jan 17 12:44:18 PM PST 24 45573099 ps
T1265 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.839390096 Jan 17 12:44:17 PM PST 24 Jan 17 12:44:18 PM PST 24 120088668 ps
T1266 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1530374910 Jan 17 12:44:01 PM PST 24 Jan 17 12:44:04 PM PST 24 56183472 ps
T1267 /workspace/coverage/cover_reg_top/7.uart_intr_test.3308358513 Jan 17 12:44:17 PM PST 24 Jan 17 12:44:18 PM PST 24 12466558 ps
T1268 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3395632168 Jan 17 12:44:15 PM PST 24 Jan 17 12:44:18 PM PST 24 63082523 ps
T1269 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3989310842 Jan 17 12:44:16 PM PST 24 Jan 17 12:44:17 PM PST 24 11453521 ps
T75 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3268354929 Jan 17 12:44:01 PM PST 24 Jan 17 12:44:04 PM PST 24 40455078 ps
T1270 /workspace/coverage/cover_reg_top/16.uart_csr_rw.192814562 Jan 17 12:44:15 PM PST 24 Jan 17 12:44:17 PM PST 24 51876984 ps
T1271 /workspace/coverage/cover_reg_top/47.uart_intr_test.3651407247 Jan 17 12:44:13 PM PST 24 Jan 17 12:44:14 PM PST 24 42442884 ps
T1272 /workspace/coverage/cover_reg_top/39.uart_intr_test.3603984934 Jan 17 12:44:10 PM PST 24 Jan 17 12:44:12 PM PST 24 49242804 ps
T1273 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1778060682 Jan 17 12:44:18 PM PST 24 Jan 17 12:44:20 PM PST 24 129617625 ps
T1274 /workspace/coverage/cover_reg_top/18.uart_csr_rw.1759191079 Jan 17 12:44:12 PM PST 24 Jan 17 12:44:13 PM PST 24 60426434 ps
T1275 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1032580083 Jan 17 12:44:25 PM PST 24 Jan 17 12:44:27 PM PST 24 156321470 ps
T1276 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1463244547 Jan 17 12:44:17 PM PST 24 Jan 17 12:44:20 PM PST 24 74122415 ps
T1277 /workspace/coverage/cover_reg_top/10.uart_csr_rw.328298205 Jan 17 12:44:08 PM PST 24 Jan 17 12:44:11 PM PST 24 39426675 ps
T1278 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2878580231 Jan 17 12:44:00 PM PST 24 Jan 17 12:44:03 PM PST 24 21770718 ps
T1279 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3500694886 Jan 17 12:43:49 PM PST 24 Jan 17 12:43:52 PM PST 24 104264051 ps
T1280 /workspace/coverage/cover_reg_top/4.uart_tl_errors.453927433 Jan 17 12:43:56 PM PST 24 Jan 17 12:44:01 PM PST 24 488475929 ps
T1281 /workspace/coverage/cover_reg_top/11.uart_intr_test.1394836940 Jan 17 12:44:20 PM PST 24 Jan 17 12:44:21 PM PST 24 40342459 ps
T97 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2065580144 Jan 17 12:44:12 PM PST 24 Jan 17 12:44:14 PM PST 24 87870792 ps
T1282 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4026762623 Jan 17 12:44:11 PM PST 24 Jan 17 12:44:13 PM PST 24 132334254 ps
T1283 /workspace/coverage/cover_reg_top/22.uart_intr_test.2243343919 Jan 17 12:44:11 PM PST 24 Jan 17 12:44:12 PM PST 24 12688357 ps
T1284 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.659388506 Jan 17 12:43:56 PM PST 24 Jan 17 12:43:59 PM PST 24 45266324 ps
T1285 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1985526872 Jan 17 12:44:12 PM PST 24 Jan 17 12:44:15 PM PST 24 259959606 ps
T76 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.189782190 Jan 17 12:44:02 PM PST 24 Jan 17 12:44:10 PM PST 24 28375862 ps
T1286 /workspace/coverage/cover_reg_top/4.uart_intr_test.1715214477 Jan 17 12:43:58 PM PST 24 Jan 17 12:44:02 PM PST 24 28210599 ps
T1287 /workspace/coverage/cover_reg_top/30.uart_intr_test.1237470990 Jan 17 12:44:10 PM PST 24 Jan 17 12:44:12 PM PST 24 13689354 ps
T1288 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1884876840 Jan 17 12:43:52 PM PST 24 Jan 17 12:43:56 PM PST 24 272618890 ps
T1289 /workspace/coverage/cover_reg_top/20.uart_intr_test.1971308917 Jan 17 12:44:16 PM PST 24 Jan 17 12:44:17 PM PST 24 16405531 ps
T1290 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2620438528 Jan 17 12:44:12 PM PST 24 Jan 17 12:44:14 PM PST 24 45542725 ps
T1291 /workspace/coverage/cover_reg_top/29.uart_intr_test.1101532400 Jan 17 12:44:14 PM PST 24 Jan 17 12:44:16 PM PST 24 11952254 ps
T1292 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.628615558 Jan 17 12:44:04 PM PST 24 Jan 17 12:44:11 PM PST 24 78571319 ps
T1293 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.128444366 Jan 17 12:44:10 PM PST 24 Jan 17 12:44:12 PM PST 24 93054765 ps
T1294 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1818511324 Jan 17 12:44:08 PM PST 24 Jan 17 12:44:11 PM PST 24 169859944 ps
T1295 /workspace/coverage/cover_reg_top/2.uart_tl_errors.783805050 Jan 17 12:43:58 PM PST 24 Jan 17 12:44:02 PM PST 24 23255586 ps
T1296 /workspace/coverage/cover_reg_top/9.uart_intr_test.1551895524 Jan 17 12:44:11 PM PST 24 Jan 17 12:44:13 PM PST 24 14438657 ps
T1297 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.317111824 Jan 17 12:44:03 PM PST 24 Jan 17 12:44:11 PM PST 24 56216060 ps
T1298 /workspace/coverage/cover_reg_top/33.uart_intr_test.776272722 Jan 17 12:44:12 PM PST 24 Jan 17 12:44:14 PM PST 24 148117260 ps
T1299 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1056138824 Jan 17 12:44:12 PM PST 24 Jan 17 12:44:15 PM PST 24 218188330 ps
T1300 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.122463375 Jan 17 12:44:02 PM PST 24 Jan 17 12:44:10 PM PST 24 24251856 ps
T77 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1762505085 Jan 17 12:44:04 PM PST 24 Jan 17 12:44:11 PM PST 24 133280670 ps
T1301 /workspace/coverage/cover_reg_top/3.uart_intr_test.3082174583 Jan 17 12:43:52 PM PST 24 Jan 17 12:43:54 PM PST 24 120794262 ps
T1302 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1387150719 Jan 17 12:43:56 PM PST 24 Jan 17 12:43:59 PM PST 24 51889003 ps

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2990018698
Short name T6
Test name
Test status
Simulation time 615231775 ps
CPU time 1.32 seconds
Started Jan 17 12:45:30 PM PST 24
Finished Jan 17 12:45:34 PM PST 24
Peak memory 199204 kb
Host smart-2a8473fc-b6b2-4782-9713-cc4b04e4f776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990018698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2990018698
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3876600709
Short name T15
Test name
Test status
Simulation time 118205424903 ps
CPU time 174.38 seconds
Started Jan 17 01:54:53 PM PST 24
Finished Jan 17 01:57:48 PM PST 24
Peak memory 200392 kb
Host smart-8c3330e3-4feb-4c0e-9cc3-1fb6d80c2d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876600709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3876600709
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2078490503
Short name T28
Test name
Test status
Simulation time 402701692660 ps
CPU time 500.56 seconds
Started Jan 17 02:02:35 PM PST 24
Finished Jan 17 02:11:02 PM PST 24
Peak memory 216668 kb
Host smart-5404430a-d6cc-45c6-9f01-6c3edfbfcf8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078490503 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2078490503
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1395032449
Short name T33
Test name
Test status
Simulation time 42844001 ps
CPU time 0.6 seconds
Started Jan 17 12:44:20 PM PST 24
Finished Jan 17 12:44:21 PM PST 24
Peak memory 185192 kb
Host smart-4be95496-cc1f-4877-87df-1bfca852c647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395032449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1395032449
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2861586874
Short name T21
Test name
Test status
Simulation time 242505141392 ps
CPU time 764.11 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:13:44 PM PST 24
Peak memory 225156 kb
Host smart-43ad9aba-4eee-4140-9f3b-8975c3063b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861586874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2861586874
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all.3678077899
Short name T140
Test name
Test status
Simulation time 294940309531 ps
CPU time 861.77 seconds
Started Jan 17 02:01:20 PM PST 24
Finished Jan 17 02:15:53 PM PST 24
Peak memory 208684 kb
Host smart-9c56c557-4acd-40a0-bda4-2a80b2c4dc75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678077899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3678077899
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1202508348
Short name T26
Test name
Test status
Simulation time 166584162741 ps
CPU time 885.03 seconds
Started Jan 17 01:55:21 PM PST 24
Finished Jan 17 02:10:08 PM PST 24
Peak memory 232508 kb
Host smart-565c8315-fa06-402b-8ca6-b675b3cbbd46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202508348 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1202508348
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.46543584
Short name T29
Test name
Test status
Simulation time 596918021022 ps
CPU time 593.51 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:10:54 PM PST 24
Peak memory 216628 kb
Host smart-0a491258-1a0d-40cb-84ca-df25848b1f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46543584 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.46543584
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2438236918
Short name T9
Test name
Test status
Simulation time 41047744 ps
CPU time 1.98 seconds
Started Jan 17 12:43:54 PM PST 24
Finished Jan 17 12:43:57 PM PST 24
Peak memory 200044 kb
Host smart-35591a97-c6bc-40bd-a53c-6bf9e4c6ff47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438236918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2438236918
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/default/10.uart_stress_all.3835936365
Short name T18
Test name
Test status
Simulation time 37605767119 ps
CPU time 20.39 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:56:02 PM PST 24
Peak memory 200144 kb
Host smart-926dec50-f398-4554-ac90-dbd8bfa09ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835936365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3835936365
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1759659406
Short name T23
Test name
Test status
Simulation time 125427624788 ps
CPU time 763.65 seconds
Started Jan 17 02:02:37 PM PST 24
Finished Jan 17 02:15:27 PM PST 24
Peak memory 213028 kb
Host smart-f370ca2f-f119-4a15-8188-6ce7a0bee9c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759659406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1759659406
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3165122639
Short name T56
Test name
Test status
Simulation time 558271669 ps
CPU time 1.49 seconds
Started Jan 17 12:43:55 PM PST 24
Finished Jan 17 12:43:59 PM PST 24
Peak memory 197888 kb
Host smart-0527fe7a-7c43-45b4-a920-ba5f8225bf09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165122639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3165122639
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2380334235
Short name T96
Test name
Test status
Simulation time 219073023661 ps
CPU time 535.95 seconds
Started Jan 17 01:56:22 PM PST 24
Finished Jan 17 02:05:18 PM PST 24
Peak memory 216968 kb
Host smart-437bcffc-fd84-4a53-8952-db3a2d20394c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380334235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2380334235
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2285052720
Short name T414
Test name
Test status
Simulation time 144410673117 ps
CPU time 237.82 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:04:55 PM PST 24
Peak memory 199072 kb
Host smart-cf6d7859-b57e-431b-aaa3-4f353d1a80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285052720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2285052720
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_stress_all.1288017194
Short name T168
Test name
Test status
Simulation time 206847539596 ps
CPU time 105.84 seconds
Started Jan 17 02:01:51 PM PST 24
Finished Jan 17 02:03:42 PM PST 24
Peak memory 208680 kb
Host smart-f4459bdf-bf33-4a37-af77-9ef6760b0faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288017194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1288017194
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1867976449
Short name T351
Test name
Test status
Simulation time 204721019300 ps
CPU time 45.69 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:02:17 PM PST 24
Peak memory 200288 kb
Host smart-c4a647a2-b5ad-44b8-80b0-a83549d21b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867976449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1867976449
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_perf.3353315742
Short name T224
Test name
Test status
Simulation time 27002945533 ps
CPU time 1607.57 seconds
Started Jan 17 01:56:38 PM PST 24
Finished Jan 17 02:23:35 PM PST 24
Peak memory 200272 kb
Host smart-e23f660a-2fe8-4986-b627-4e5220d28715
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353315742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3353315742
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3262433765
Short name T86
Test name
Test status
Simulation time 51746332 ps
CPU time 0.66 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 195468 kb
Host smart-e0a51c5d-deb8-493d-8f07-7bfe4d1ef429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262433765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3262433765
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2630947709
Short name T93
Test name
Test status
Simulation time 41214268 ps
CPU time 0.8 seconds
Started Jan 17 01:54:42 PM PST 24
Finished Jan 17 01:54:44 PM PST 24
Peak memory 217780 kb
Host smart-853d606d-2759-4228-ac2a-95817cb6f4c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630947709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2630947709
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/14.uart_tx_rx.211714682
Short name T410
Test name
Test status
Simulation time 139837102667 ps
CPU time 171.29 seconds
Started Jan 17 01:56:04 PM PST 24
Finished Jan 17 01:58:57 PM PST 24
Peak memory 200276 kb
Host smart-803cd532-35fc-436d-b987-7f31200f3f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211714682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.211714682
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/3.uart_stress_all.369130724
Short name T217
Test name
Test status
Simulation time 475026947208 ps
CPU time 776.73 seconds
Started Jan 17 01:55:11 PM PST 24
Finished Jan 17 02:08:08 PM PST 24
Peak memory 200388 kb
Host smart-3972994e-8fdc-4dd8-ba11-f79d0222ad68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369130724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.369130724
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2005221805
Short name T119
Test name
Test status
Simulation time 29781848923 ps
CPU time 56.68 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:56:38 PM PST 24
Peak memory 200192 kb
Host smart-45114f1a-1aad-4b89-81cb-f2aa9e327fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005221805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2005221805
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4043314197
Short name T417
Test name
Test status
Simulation time 110490432699 ps
CPU time 171.63 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:58:33 PM PST 24
Peak memory 200280 kb
Host smart-49e23a14-c63c-45e4-b1f3-6f77343d62fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043314197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4043314197
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_alert_test.3685577220
Short name T496
Test name
Test status
Simulation time 38198287 ps
CPU time 0.6 seconds
Started Jan 17 01:55:41 PM PST 24
Finished Jan 17 01:55:42 PM PST 24
Peak memory 195704 kb
Host smart-4ea3d0ba-c17a-4d5f-b42f-c3bb5176ba60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685577220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3685577220
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1387349417
Short name T137
Test name
Test status
Simulation time 404121102969 ps
CPU time 262.61 seconds
Started Jan 17 02:02:38 PM PST 24
Finished Jan 17 02:07:06 PM PST 24
Peak memory 217028 kb
Host smart-4574ae92-7a4b-499a-8b32-b8bf3eb97765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387349417 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1387349417
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2672997340
Short name T183
Test name
Test status
Simulation time 47841606776 ps
CPU time 76.25 seconds
Started Jan 17 02:04:22 PM PST 24
Finished Jan 17 02:05:41 PM PST 24
Peak memory 200224 kb
Host smart-270fd0fa-44de-4791-a1be-107fa8251c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672997340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2672997340
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3227601488
Short name T36
Test name
Test status
Simulation time 52649149 ps
CPU time 0.94 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 199148 kb
Host smart-f392a048-265b-429f-83ff-eed80ca7fd37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227601488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3227601488
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2305593597
Short name T85
Test name
Test status
Simulation time 40959948 ps
CPU time 0.58 seconds
Started Jan 17 12:44:10 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 185092 kb
Host smart-66bf79ad-c95f-4d4a-9909-02e532e24205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305593597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2305593597
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2809774428
Short name T12
Test name
Test status
Simulation time 101790840205 ps
CPU time 372.7 seconds
Started Jan 17 02:03:39 PM PST 24
Finished Jan 17 02:09:52 PM PST 24
Peak memory 200172 kb
Host smart-6ec4f14f-846a-4ee9-9444-868b63ca9d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809774428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2809774428
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all.351924722
Short name T438
Test name
Test status
Simulation time 3551710079678 ps
CPU time 1112.8 seconds
Started Jan 17 01:55:07 PM PST 24
Finished Jan 17 02:13:41 PM PST 24
Peak memory 208672 kb
Host smart-ec38d45e-b487-4e98-b786-2a4605695d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351924722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.351924722
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.831697548
Short name T165
Test name
Test status
Simulation time 40083595102 ps
CPU time 22.64 seconds
Started Jan 17 01:55:59 PM PST 24
Finished Jan 17 01:56:26 PM PST 24
Peak memory 200080 kb
Host smart-31fb79e3-a7f4-4985-a53f-663988d273ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831697548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.831697548
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3320571166
Short name T227
Test name
Test status
Simulation time 29817490657 ps
CPU time 27.29 seconds
Started Jan 17 02:02:41 PM PST 24
Finished Jan 17 02:03:12 PM PST 24
Peak memory 200244 kb
Host smart-fa7e674a-c5ba-495e-a8d4-13a9144f2370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320571166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3320571166
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.1812356900
Short name T220
Test name
Test status
Simulation time 231306099129 ps
CPU time 603.84 seconds
Started Jan 17 01:55:52 PM PST 24
Finished Jan 17 02:05:58 PM PST 24
Peak memory 200280 kb
Host smart-2759edd7-d77b-44e4-a532-4cc1ef0ee7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812356900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1812356900
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1960761726
Short name T202
Test name
Test status
Simulation time 126934891874 ps
CPU time 797.33 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:13:40 PM PST 24
Peak memory 225156 kb
Host smart-9c2918e5-7e00-463e-b2c7-9ca06626b76f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960761726 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1960761726
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1996701894
Short name T139
Test name
Test status
Simulation time 138514671040 ps
CPU time 549.84 seconds
Started Jan 17 02:03:00 PM PST 24
Finished Jan 17 02:12:13 PM PST 24
Peak memory 200196 kb
Host smart-0fc7f355-3bf3-4f89-9c8f-cd7f06081d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996701894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1996701894
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2103122845
Short name T370
Test name
Test status
Simulation time 6045686941 ps
CPU time 10.53 seconds
Started Jan 17 02:04:56 PM PST 24
Finished Jan 17 02:05:09 PM PST 24
Peak memory 200032 kb
Host smart-36b411d8-2eea-4cdf-9a3f-444d81586eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103122845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2103122845
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1703601895
Short name T43
Test name
Test status
Simulation time 136403986 ps
CPU time 1.21 seconds
Started Jan 17 12:43:51 PM PST 24
Finished Jan 17 12:43:53 PM PST 24
Peak memory 199320 kb
Host smart-54523b8e-bccc-4a43-aca9-2100996637cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703601895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1703601895
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.664582136
Short name T63
Test name
Test status
Simulation time 13520119 ps
CPU time 0.53 seconds
Started Jan 17 12:43:44 PM PST 24
Finished Jan 17 12:43:47 PM PST 24
Peak memory 185116 kb
Host smart-e4be691e-1a13-4e68-aa80-42124165be90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664582136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.664582136
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.215858260
Short name T300
Test name
Test status
Simulation time 141683236504 ps
CPU time 206.06 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:04:02 PM PST 24
Peak memory 200204 kb
Host smart-1c55288f-e8c2-4570-8de9-f25a662d4d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215858260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.215858260
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_stress_all.1107920069
Short name T378
Test name
Test status
Simulation time 340765385579 ps
CPU time 316.02 seconds
Started Jan 17 02:01:59 PM PST 24
Finished Jan 17 02:07:16 PM PST 24
Peak memory 200200 kb
Host smart-10b91ca9-724e-4051-b58f-e6e0842d8a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107920069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1107920069
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3328785218
Short name T330
Test name
Test status
Simulation time 47033217805 ps
CPU time 20.19 seconds
Started Jan 17 01:56:21 PM PST 24
Finished Jan 17 01:56:43 PM PST 24
Peak memory 200188 kb
Host smart-78958c7c-6d71-48e8-a97c-6a122e7cfff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328785218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3328785218
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4103421381
Short name T16
Test name
Test status
Simulation time 28463531728 ps
CPU time 48.08 seconds
Started Jan 17 02:04:01 PM PST 24
Finished Jan 17 02:04:54 PM PST 24
Peak memory 200224 kb
Host smart-8d634e7e-f37d-4d40-9b8b-c0cae8379880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103421381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4103421381
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2332723365
Short name T206
Test name
Test status
Simulation time 370836535342 ps
CPU time 1069.14 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 02:13:31 PM PST 24
Peak memory 233280 kb
Host smart-42dac769-25a6-4bcd-be8f-3b4da50a700f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332723365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2332723365
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1108987884
Short name T242
Test name
Test status
Simulation time 14519544116 ps
CPU time 24.29 seconds
Started Jan 17 02:03:34 PM PST 24
Finished Jan 17 02:03:59 PM PST 24
Peak memory 200216 kb
Host smart-f481ab48-ba81-436b-b9ce-0a4cee8d033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108987884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1108987884
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3814926699
Short name T208
Test name
Test status
Simulation time 64851281882 ps
CPU time 35.51 seconds
Started Jan 17 02:03:40 PM PST 24
Finished Jan 17 02:04:16 PM PST 24
Peak memory 200176 kb
Host smart-26cfe65f-d9fe-461b-b920-3084ebcce61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814926699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3814926699
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3721072674
Short name T147
Test name
Test status
Simulation time 60793489985 ps
CPU time 91.88 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:58:36 PM PST 24
Peak memory 200188 kb
Host smart-346d6ef6-78ad-43d1-ab2a-b61b1b58d662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721072674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3721072674
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3503825409
Short name T291
Test name
Test status
Simulation time 27805324429 ps
CPU time 12.55 seconds
Started Jan 17 02:04:02 PM PST 24
Finished Jan 17 02:04:18 PM PST 24
Peak memory 200100 kb
Host smart-7620e023-ee5c-4be9-9fb1-9864b575c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503825409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3503825409
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1849702657
Short name T179
Test name
Test status
Simulation time 355827842191 ps
CPU time 83.78 seconds
Started Jan 17 02:04:05 PM PST 24
Finished Jan 17 02:05:34 PM PST 24
Peak memory 200208 kb
Host smart-b7447e8d-eb7a-4186-9f6a-c57097388043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849702657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1849702657
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.158497036
Short name T341
Test name
Test status
Simulation time 130885515570 ps
CPU time 106.36 seconds
Started Jan 17 02:04:10 PM PST 24
Finished Jan 17 02:05:58 PM PST 24
Peak memory 200204 kb
Host smart-a7cca53c-36ca-48d9-82c6-3e732c40aed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158497036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.158497036
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2576532125
Short name T358
Test name
Test status
Simulation time 107946758674 ps
CPU time 147.17 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:03:07 PM PST 24
Peak memory 200280 kb
Host smart-c79cffc2-f3d3-4e51-a483-90abb556c5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576532125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2576532125
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.340369669
Short name T264
Test name
Test status
Simulation time 20924689137 ps
CPU time 10.03 seconds
Started Jan 17 02:04:35 PM PST 24
Finished Jan 17 02:04:47 PM PST 24
Peak memory 200204 kb
Host smart-44dc3657-47a7-4d5c-894e-15e0b46f56c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340369669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.340369669
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3188200084
Short name T212
Test name
Test status
Simulation time 219730497254 ps
CPU time 92.53 seconds
Started Jan 17 02:01:48 PM PST 24
Finished Jan 17 02:03:26 PM PST 24
Peak memory 200256 kb
Host smart-48060467-7d97-44b8-8aa8-6908e7710d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188200084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3188200084
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3739584958
Short name T321
Test name
Test status
Simulation time 86268853768 ps
CPU time 900.79 seconds
Started Jan 17 02:02:32 PM PST 24
Finished Jan 17 02:17:43 PM PST 24
Peak memory 233252 kb
Host smart-45467cf0-1ca7-460d-a5ab-bad1310fc699
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739584958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3739584958
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1065330029
Short name T388
Test name
Test status
Simulation time 87111850223 ps
CPU time 76.2 seconds
Started Jan 17 02:03:22 PM PST 24
Finished Jan 17 02:04:39 PM PST 24
Peak memory 200244 kb
Host smart-4df19996-62df-49f1-80e7-34a1e0f8df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065330029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1065330029
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1986388838
Short name T243
Test name
Test status
Simulation time 22378209305 ps
CPU time 16.43 seconds
Started Jan 17 02:03:50 PM PST 24
Finished Jan 17 02:04:09 PM PST 24
Peak memory 199768 kb
Host smart-4a01f83e-de5d-4330-9a29-387c7d34f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986388838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1986388838
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3302081546
Short name T338
Test name
Test status
Simulation time 367117802560 ps
CPU time 57.7 seconds
Started Jan 17 02:03:58 PM PST 24
Finished Jan 17 02:05:03 PM PST 24
Peak memory 200228 kb
Host smart-d5674360-e7eb-42f0-95d9-fdd1e7eedf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302081546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3302081546
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2997169616
Short name T253
Test name
Test status
Simulation time 21775385896 ps
CPU time 35.51 seconds
Started Jan 17 02:04:12 PM PST 24
Finished Jan 17 02:04:48 PM PST 24
Peak memory 200216 kb
Host smart-18b28bac-b7d8-4bc1-aba9-a7fa09fa3558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997169616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2997169616
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1762853612
Short name T191
Test name
Test status
Simulation time 79002559762 ps
CPU time 28.47 seconds
Started Jan 17 02:04:36 PM PST 24
Finished Jan 17 02:05:07 PM PST 24
Peak memory 200264 kb
Host smart-fa4ec945-a604-4cd1-9d3e-83eaa99bda81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762853612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1762853612
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2983394062
Short name T180
Test name
Test status
Simulation time 17799832116 ps
CPU time 32.21 seconds
Started Jan 17 02:04:48 PM PST 24
Finished Jan 17 02:05:21 PM PST 24
Peak memory 200204 kb
Host smart-147ef82c-bb6e-4300-a40e-2add827e9ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983394062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2983394062
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1753329971
Short name T422
Test name
Test status
Simulation time 37233214527 ps
CPU time 442.08 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:07:58 PM PST 24
Peak memory 210576 kb
Host smart-db1fcb5e-bfd5-4c03-91fd-86c0a9a3a62b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753329971 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1753329971
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1989274041
Short name T146
Test name
Test status
Simulation time 77386218373 ps
CPU time 811.32 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:16:13 PM PST 24
Peak memory 225052 kb
Host smart-e643220f-8740-43af-a3ee-a3cd14de8c6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989274041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1989274041
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1059850221
Short name T120
Test name
Test status
Simulation time 115980188351 ps
CPU time 107.47 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:04:32 PM PST 24
Peak memory 200244 kb
Host smart-708781b6-5375-42b6-ad45-4d67f9af5510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059850221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1059850221
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.33803926
Short name T396
Test name
Test status
Simulation time 463773274606 ps
CPU time 522.52 seconds
Started Jan 17 02:02:53 PM PST 24
Finished Jan 17 02:11:40 PM PST 24
Peak memory 216664 kb
Host smart-ceb6c08b-8acb-4b8e-9ecb-1a07504d4fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33803926 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.33803926
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.155360035
Short name T188
Test name
Test status
Simulation time 86271141384 ps
CPU time 125.28 seconds
Started Jan 17 01:54:46 PM PST 24
Finished Jan 17 01:56:54 PM PST 24
Peak memory 199708 kb
Host smart-ae5259f7-a45c-41c4-aa65-7c780b7744a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155360035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.155360035
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1017704875
Short name T327
Test name
Test status
Simulation time 73110025131 ps
CPU time 30.95 seconds
Started Jan 17 02:03:11 PM PST 24
Finished Jan 17 02:03:43 PM PST 24
Peak memory 199940 kb
Host smart-fded857b-bf37-4d54-b020-1d90fb3822ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017704875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1017704875
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2816602811
Short name T354
Test name
Test status
Simulation time 38964151440 ps
CPU time 8.08 seconds
Started Jan 17 02:03:22 PM PST 24
Finished Jan 17 02:03:31 PM PST 24
Peak memory 200224 kb
Host smart-dcc3ddb6-97a0-4b51-94ab-2102b119d0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816602811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2816602811
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3446687388
Short name T293
Test name
Test status
Simulation time 178747953662 ps
CPU time 68.35 seconds
Started Jan 17 02:03:41 PM PST 24
Finished Jan 17 02:04:50 PM PST 24
Peak memory 200148 kb
Host smart-b76a9403-37e0-489a-af21-0ae0976b5c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446687388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3446687388
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.800842605
Short name T131
Test name
Test status
Simulation time 43426353940 ps
CPU time 30.05 seconds
Started Jan 17 02:03:47 PM PST 24
Finished Jan 17 02:04:18 PM PST 24
Peak memory 200216 kb
Host smart-59279118-6e1b-440d-aa18-d9a820c2556f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800842605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.800842605
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.4226303548
Short name T394
Test name
Test status
Simulation time 45224194766 ps
CPU time 15.41 seconds
Started Jan 17 02:03:54 PM PST 24
Finished Jan 17 02:04:12 PM PST 24
Peak memory 200208 kb
Host smart-24029aa9-ee1a-4a7d-a609-cfc9943f3f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226303548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.4226303548
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2585978371
Short name T157
Test name
Test status
Simulation time 28745207097 ps
CPU time 56.01 seconds
Started Jan 17 02:03:46 PM PST 24
Finished Jan 17 02:04:43 PM PST 24
Peak memory 200272 kb
Host smart-83aab2a2-5f4e-4261-8da5-94b0bd5ae493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585978371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2585978371
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3933823292
Short name T255
Test name
Test status
Simulation time 17337442989 ps
CPU time 44.47 seconds
Started Jan 17 02:03:56 PM PST 24
Finished Jan 17 02:04:48 PM PST 24
Peak memory 200084 kb
Host smart-d0f1e1ed-4814-43a0-ba98-5dbaeb3e45de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933823292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3933823292
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1282740527
Short name T233
Test name
Test status
Simulation time 24832005352 ps
CPU time 44.59 seconds
Started Jan 17 02:03:57 PM PST 24
Finished Jan 17 02:04:50 PM PST 24
Peak memory 200196 kb
Host smart-70964011-974a-4943-85e7-1f0b24fc20b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282740527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1282740527
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3220310993
Short name T230
Test name
Test status
Simulation time 33640162576 ps
CPU time 56.14 seconds
Started Jan 17 02:04:01 PM PST 24
Finished Jan 17 02:05:02 PM PST 24
Peak memory 200240 kb
Host smart-f89ae030-6c47-44d3-9124-251307ecb6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220310993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3220310993
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3173460223
Short name T245
Test name
Test status
Simulation time 47068465064 ps
CPU time 88.76 seconds
Started Jan 17 02:04:44 PM PST 24
Finished Jan 17 02:06:14 PM PST 24
Peak memory 200324 kb
Host smart-18299b73-afcf-44e0-be92-35df9644811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173460223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3173460223
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3126031681
Short name T335
Test name
Test status
Simulation time 104465906208 ps
CPU time 184.03 seconds
Started Jan 17 02:04:44 PM PST 24
Finished Jan 17 02:07:48 PM PST 24
Peak memory 200228 kb
Host smart-51ec7a0c-e106-4dee-b180-a700614a97cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126031681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3126031681
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.413420916
Short name T280
Test name
Test status
Simulation time 159163106646 ps
CPU time 60.33 seconds
Started Jan 17 02:04:55 PM PST 24
Finished Jan 17 02:05:56 PM PST 24
Peak memory 200268 kb
Host smart-3398f36d-dcb1-4519-9517-15b169fa88b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413420916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.413420916
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1142105209
Short name T130
Test name
Test status
Simulation time 64799751713 ps
CPU time 40.31 seconds
Started Jan 17 02:04:55 PM PST 24
Finished Jan 17 02:05:36 PM PST 24
Peak memory 200220 kb
Host smart-f2870374-d253-4edd-bc96-2b1a81acc604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142105209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1142105209
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.1805938311
Short name T266
Test name
Test status
Simulation time 291749525138 ps
CPU time 304.51 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:05:37 PM PST 24
Peak memory 200196 kb
Host smart-7dd59c86-d63f-4510-9c78-3f03035194d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805938311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1805938311
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1157128439
Short name T262
Test name
Test status
Simulation time 58610182280 ps
CPU time 25.39 seconds
Started Jan 17 02:02:43 PM PST 24
Finished Jan 17 02:03:11 PM PST 24
Peak memory 200264 kb
Host smart-dee91d5d-67e9-4a1e-9ae5-bf460e3a35f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157128439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1157128439
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1944605480
Short name T405
Test name
Test status
Simulation time 46406965 ps
CPU time 0.56 seconds
Started Jan 17 12:43:53 PM PST 24
Finished Jan 17 12:43:55 PM PST 24
Peak memory 185120 kb
Host smart-3a41aa0c-2507-4c67-8223-f1e9f497ed17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944605480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1944605480
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/default/1.uart_stress_all.212430643
Short name T198
Test name
Test status
Simulation time 82302633616 ps
CPU time 198.23 seconds
Started Jan 17 01:54:47 PM PST 24
Finished Jan 17 01:58:08 PM PST 24
Peak memory 200188 kb
Host smart-0fcc7e1a-bc6f-455f-8a6f-52d34ffeeb28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212430643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.212430643
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4072173451
Short name T383
Test name
Test status
Simulation time 196419386296 ps
CPU time 295.76 seconds
Started Jan 17 01:55:42 PM PST 24
Finished Jan 17 02:00:39 PM PST 24
Peak memory 200288 kb
Host smart-c06b750a-1404-4174-9111-771bba34c76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072173451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4072173451
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4137872311
Short name T121
Test name
Test status
Simulation time 98588917718 ps
CPU time 54.27 seconds
Started Jan 17 02:03:08 PM PST 24
Finished Jan 17 02:04:03 PM PST 24
Peak memory 200164 kb
Host smart-bb3d2959-6a51-4293-b679-f1b12ae17365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137872311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4137872311
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.500459713
Short name T340
Test name
Test status
Simulation time 36709294356 ps
CPU time 68.3 seconds
Started Jan 17 02:03:12 PM PST 24
Finished Jan 17 02:04:24 PM PST 24
Peak memory 200180 kb
Host smart-ba62ae47-87f4-4070-88d1-65ed60cf782b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500459713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.500459713
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2797933682
Short name T365
Test name
Test status
Simulation time 248467855984 ps
CPU time 131.17 seconds
Started Jan 17 01:55:52 PM PST 24
Finished Jan 17 01:58:04 PM PST 24
Peak memory 200100 kb
Host smart-f6c2804e-d3de-403d-a657-65c7e7497c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797933682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2797933682
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.4091845349
Short name T312
Test name
Test status
Simulation time 129454745296 ps
CPU time 186.76 seconds
Started Jan 17 01:55:59 PM PST 24
Finished Jan 17 01:59:10 PM PST 24
Peak memory 200204 kb
Host smart-7df8a309-4726-411a-ab56-452191601611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091845349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.4091845349
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.578926666
Short name T278
Test name
Test status
Simulation time 35131937297 ps
CPU time 53.54 seconds
Started Jan 17 01:55:54 PM PST 24
Finished Jan 17 01:56:48 PM PST 24
Peak memory 200240 kb
Host smart-2a6e94f0-59e0-4ee6-afe3-2d298dee5089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578926666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.578926666
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1423224475
Short name T249
Test name
Test status
Simulation time 27668144931 ps
CPU time 41.38 seconds
Started Jan 17 02:03:27 PM PST 24
Finished Jan 17 02:04:09 PM PST 24
Peak memory 200264 kb
Host smart-b5dc0e8c-9d0b-4d68-8903-305c588ff376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423224475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1423224475
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3535244011
Short name T152
Test name
Test status
Simulation time 76412972614 ps
CPU time 130.37 seconds
Started Jan 17 02:03:26 PM PST 24
Finished Jan 17 02:05:36 PM PST 24
Peak memory 200252 kb
Host smart-69ed3d4e-027d-410a-9c66-60e019ca5784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535244011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3535244011
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3348497890
Short name T194
Test name
Test status
Simulation time 20923807973 ps
CPU time 32.64 seconds
Started Jan 17 02:03:28 PM PST 24
Finished Jan 17 02:04:04 PM PST 24
Peak memory 200120 kb
Host smart-bc29c7d6-11ac-4ac2-8121-159c0abacf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348497890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3348497890
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3246863381
Short name T400
Test name
Test status
Simulation time 48124937037 ps
CPU time 21.74 seconds
Started Jan 17 02:03:28 PM PST 24
Finished Jan 17 02:03:51 PM PST 24
Peak memory 200168 kb
Host smart-744e2e69-1da3-432b-a6b1-3eae4562b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246863381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3246863381
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.684300852
Short name T282
Test name
Test status
Simulation time 105627866524 ps
CPU time 47.8 seconds
Started Jan 17 02:03:29 PM PST 24
Finished Jan 17 02:04:19 PM PST 24
Peak memory 200200 kb
Host smart-44cfae3a-9590-40ca-bc8f-36d008536c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684300852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.684300852
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3572363234
Short name T375
Test name
Test status
Simulation time 51533612076 ps
CPU time 39.57 seconds
Started Jan 17 02:03:31 PM PST 24
Finished Jan 17 02:04:11 PM PST 24
Peak memory 200308 kb
Host smart-46b485c5-f777-4ba7-a2ff-88f1af164d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572363234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3572363234
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3088566411
Short name T376
Test name
Test status
Simulation time 18081143023 ps
CPU time 28.83 seconds
Started Jan 17 02:03:34 PM PST 24
Finished Jan 17 02:04:04 PM PST 24
Peak memory 200232 kb
Host smart-f876fd78-6976-4a65-9946-103b67d85aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088566411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3088566411
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3581102821
Short name T352
Test name
Test status
Simulation time 36963801358 ps
CPU time 19.57 seconds
Started Jan 17 02:03:56 PM PST 24
Finished Jan 17 02:04:23 PM PST 24
Peak memory 200124 kb
Host smart-3a0cf78a-4ebc-44df-9e48-9385f600804d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581102821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3581102821
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.752975822
Short name T298
Test name
Test status
Simulation time 449752437386 ps
CPU time 942.47 seconds
Started Jan 17 01:56:37 PM PST 24
Finished Jan 17 02:12:30 PM PST 24
Peak memory 224848 kb
Host smart-5048b0a9-3d17-4b7b-a6a6-2c7a2491e1a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752975822 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.752975822
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3285760984
Short name T386
Test name
Test status
Simulation time 40396434112 ps
CPU time 54.76 seconds
Started Jan 17 02:04:02 PM PST 24
Finished Jan 17 02:05:00 PM PST 24
Peak memory 200292 kb
Host smart-2124ec1a-f5c2-4d35-9675-5b917cb61488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285760984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3285760984
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2758565968
Short name T251
Test name
Test status
Simulation time 23019613251 ps
CPU time 35.07 seconds
Started Jan 17 01:54:56 PM PST 24
Finished Jan 17 01:55:34 PM PST 24
Peak memory 200028 kb
Host smart-ea3e03e6-e84f-41ba-bdba-3848c22fc45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758565968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2758565968
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3647121289
Short name T114
Test name
Test status
Simulation time 140332203811 ps
CPU time 205.64 seconds
Started Jan 17 01:57:01 PM PST 24
Finished Jan 17 02:00:31 PM PST 24
Peak memory 199340 kb
Host smart-1f0c1a99-2bf4-47fd-a399-4f85c57f8a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647121289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3647121289
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_stress_all.4268339398
Short name T306
Test name
Test status
Simulation time 156807191008 ps
CPU time 629.64 seconds
Started Jan 17 01:57:16 PM PST 24
Finished Jan 17 02:07:49 PM PST 24
Peak memory 200148 kb
Host smart-8defe69f-b977-4817-885d-b14cb63f8a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268339398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4268339398
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1769079206
Short name T343
Test name
Test status
Simulation time 99733692935 ps
CPU time 70.32 seconds
Started Jan 17 02:04:30 PM PST 24
Finished Jan 17 02:05:43 PM PST 24
Peak memory 200252 kb
Host smart-823eef65-75c5-4452-9ac6-b8baa0ce064c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769079206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1769079206
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2281094587
Short name T459
Test name
Test status
Simulation time 26382888893 ps
CPU time 467.52 seconds
Started Jan 17 02:00:35 PM PST 24
Finished Jan 17 02:08:27 PM PST 24
Peak memory 214272 kb
Host smart-4b2ed517-ff5e-4055-887d-92060ca457a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281094587 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2281094587
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_perf.77338405
Short name T310
Test name
Test status
Simulation time 3877114292 ps
CPU time 55.96 seconds
Started Jan 17 02:00:35 PM PST 24
Finished Jan 17 02:01:35 PM PST 24
Peak memory 200312 kb
Host smart-251ba1fa-8f2b-49a9-bd21-296d38636907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77338405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.77338405
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.4274182529
Short name T307
Test name
Test status
Simulation time 7583151418 ps
CPU time 12.27 seconds
Started Jan 17 01:54:57 PM PST 24
Finished Jan 17 01:55:11 PM PST 24
Peak memory 199504 kb
Host smart-8b162441-cde5-4d59-8109-fbe8240b8809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274182529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4274182529
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_stress_all.2263219780
Short name T289
Test name
Test status
Simulation time 212011029231 ps
CPU time 319.77 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:05:52 PM PST 24
Peak memory 200280 kb
Host smart-b14b94e5-21a0-4a7e-a340-b89443a55fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263219780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2263219780
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all.3099800385
Short name T381
Test name
Test status
Simulation time 342200168363 ps
CPU time 699.99 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:12:38 PM PST 24
Peak memory 200124 kb
Host smart-f3e1daab-4fdc-4be1-9bcf-11aada77fc6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099800385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3099800385
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1484544179
Short name T309
Test name
Test status
Simulation time 113683009172 ps
CPU time 41.68 seconds
Started Jan 17 02:01:28 PM PST 24
Finished Jan 17 02:02:15 PM PST 24
Peak memory 200184 kb
Host smart-70923771-93d1-438b-b461-9f958e34516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484544179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1484544179
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4080018899
Short name T304
Test name
Test status
Simulation time 115789158602 ps
CPU time 25.92 seconds
Started Jan 17 02:01:32 PM PST 24
Finished Jan 17 02:02:01 PM PST 24
Peak memory 200264 kb
Host smart-289a9804-544a-40cb-9841-01ed6892d7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080018899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4080018899
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_perf.2158204738
Short name T238
Test name
Test status
Simulation time 25430489794 ps
CPU time 1559.41 seconds
Started Jan 17 02:01:48 PM PST 24
Finished Jan 17 02:27:53 PM PST 24
Peak memory 200200 kb
Host smart-545f5e87-62ae-4133-8346-fc9c14c4cb00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158204738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2158204738
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1780551895
Short name T1235
Test name
Test status
Simulation time 43034656111 ps
CPU time 693.22 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:13:23 PM PST 24
Peak memory 217044 kb
Host smart-17c7dc05-597a-4ece-ac38-35dfa7e30bf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780551895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1780551895
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_stress_all.2737910736
Short name T303
Test name
Test status
Simulation time 169235518792 ps
CPU time 1313.64 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:24:35 PM PST 24
Peak memory 200196 kb
Host smart-4cad13a1-fa01-42ad-8f50-c4e2fdc885b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737910736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2737910736
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2467479574
Short name T372
Test name
Test status
Simulation time 120641547930 ps
CPU time 32.59 seconds
Started Jan 17 01:55:19 PM PST 24
Finished Jan 17 01:55:52 PM PST 24
Peak memory 200136 kb
Host smart-80933074-b75e-4b13-a26f-2884b3848200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467479574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2467479574
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1136095973
Short name T223
Test name
Test status
Simulation time 329703170886 ps
CPU time 34.18 seconds
Started Jan 17 02:02:34 PM PST 24
Finished Jan 17 02:03:16 PM PST 24
Peak memory 200212 kb
Host smart-95880290-ad57-4260-b909-6cc29c156302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136095973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1136095973
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1127363906
Short name T192
Test name
Test status
Simulation time 299547323787 ps
CPU time 161.77 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:05:27 PM PST 24
Peak memory 199872 kb
Host smart-8a80b107-623b-486d-ad07-13b0f6e4a5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127363906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1127363906
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.431574218
Short name T347
Test name
Test status
Simulation time 53734202225 ps
CPU time 21.79 seconds
Started Jan 17 02:02:54 PM PST 24
Finished Jan 17 02:03:19 PM PST 24
Peak memory 200180 kb
Host smart-d19444a9-e6ee-459a-9303-9b7026558411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431574218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.431574218
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1750632480
Short name T368
Test name
Test status
Simulation time 24886879357 ps
CPU time 12.6 seconds
Started Jan 17 01:55:39 PM PST 24
Finished Jan 17 01:55:53 PM PST 24
Peak memory 200236 kb
Host smart-dabadc79-d600-4cd4-8361-b700fc6ad78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750632480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1750632480
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3021655717
Short name T67
Test name
Test status
Simulation time 44172380 ps
CPU time 0.63 seconds
Started Jan 17 12:43:55 PM PST 24
Finished Jan 17 12:43:57 PM PST 24
Peak memory 195520 kb
Host smart-d0e57121-9484-4c17-8335-d31e27af4b74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021655717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3021655717
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.119288364
Short name T482
Test name
Test status
Simulation time 58463518 ps
CPU time 2.27 seconds
Started Jan 17 12:43:54 PM PST 24
Finished Jan 17 12:43:57 PM PST 24
Peak memory 197416 kb
Host smart-faaa9ca6-c0f7-42b8-ab44-436aadab8e60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119288364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.119288364
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.813735141
Short name T55
Test name
Test status
Simulation time 15715884 ps
CPU time 0.59 seconds
Started Jan 17 12:43:58 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 195524 kb
Host smart-eb133d8c-cdee-4238-b0d8-865a22384b48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813735141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.813735141
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3734245067
Short name T476
Test name
Test status
Simulation time 56239335 ps
CPU time 0.85 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:43:59 PM PST 24
Peak memory 199836 kb
Host smart-2b5a019b-7ca9-42c2-a08a-ab1e49cb30c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734245067 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3734245067
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.322362366
Short name T490
Test name
Test status
Simulation time 13710460 ps
CPU time 0.64 seconds
Started Jan 17 12:44:00 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 195436 kb
Host smart-c78899ad-4a81-4a1f-bd2d-e5ea453cf17b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322362366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.322362366
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1530374910
Short name T1266
Test name
Test status
Simulation time 56183472 ps
CPU time 0.7 seconds
Started Jan 17 12:44:01 PM PST 24
Finished Jan 17 12:44:04 PM PST 24
Peak memory 195944 kb
Host smart-5f4c91ca-12b9-40e4-8b28-4a52ee199475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530374910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1530374910
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3500694886
Short name T1279
Test name
Test status
Simulation time 104264051 ps
CPU time 1.43 seconds
Started Jan 17 12:43:49 PM PST 24
Finished Jan 17 12:43:52 PM PST 24
Peak memory 200024 kb
Host smart-521fa986-8824-4b97-8884-0071ce589fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500694886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3500694886
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.189782190
Short name T76
Test name
Test status
Simulation time 28375862 ps
CPU time 0.81 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 196424 kb
Host smart-0b8104cb-9d1e-41ef-85a3-911fac959352
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189782190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.189782190
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.772354538
Short name T464
Test name
Test status
Simulation time 271875311 ps
CPU time 2.25 seconds
Started Jan 17 12:43:54 PM PST 24
Finished Jan 17 12:43:57 PM PST 24
Peak memory 197804 kb
Host smart-0f9c5938-c71e-4617-bc8b-3575ef9c0150
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772354538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.772354538
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1387150719
Short name T1302
Test name
Test status
Simulation time 51889003 ps
CPU time 0.59 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:43:59 PM PST 24
Peak memory 195520 kb
Host smart-1311fb43-308a-4eab-93c4-62b1d5eeb6ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387150719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1387150719
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1698219893
Short name T1245
Test name
Test status
Simulation time 47989531 ps
CPU time 0.77 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:43:59 PM PST 24
Peak memory 199852 kb
Host smart-fdc0e721-f53b-4270-9ada-3a40b51b4d52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698219893 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1698219893
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3028628646
Short name T3
Test name
Test status
Simulation time 55894520 ps
CPU time 0.59 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 195528 kb
Host smart-cfb97379-9203-41b3-ae08-8b022c6ded08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028628646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3028628646
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.773162425
Short name T478
Test name
Test status
Simulation time 40372238 ps
CPU time 0.56 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:43:59 PM PST 24
Peak memory 185140 kb
Host smart-6746adb6-9720-4fe9-a9cc-e99a436917cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773162425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.773162425
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3221984262
Short name T1247
Test name
Test status
Simulation time 41881680 ps
CPU time 0.7 seconds
Started Jan 17 12:43:45 PM PST 24
Finished Jan 17 12:43:49 PM PST 24
Peak memory 195548 kb
Host smart-f391077d-5550-470f-a80c-f8e9f36296ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221984262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3221984262
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1884876840
Short name T1288
Test name
Test status
Simulation time 272618890 ps
CPU time 1.68 seconds
Started Jan 17 12:43:52 PM PST 24
Finished Jan 17 12:43:56 PM PST 24
Peak memory 200132 kb
Host smart-420892b6-e938-4b78-849d-bf6d96385c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884876840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1884876840
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1994411526
Short name T1254
Test name
Test status
Simulation time 86707629 ps
CPU time 1.36 seconds
Started Jan 17 12:43:51 PM PST 24
Finished Jan 17 12:43:54 PM PST 24
Peak memory 199236 kb
Host smart-c4dea18c-f324-4ef5-9c58-d2c6f314f812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994411526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1994411526
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2925753550
Short name T1263
Test name
Test status
Simulation time 15593206 ps
CPU time 0.67 seconds
Started Jan 17 12:44:17 PM PST 24
Finished Jan 17 12:44:19 PM PST 24
Peak memory 197696 kb
Host smart-1e764154-5a6b-4d5c-a31c-dc62d02f725e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925753550 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2925753550
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.328298205
Short name T1277
Test name
Test status
Simulation time 39426675 ps
CPU time 0.57 seconds
Started Jan 17 12:44:08 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 195496 kb
Host smart-7ec3a8c6-9d6b-4e23-9d6a-c2478bcb6e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328298205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.328298205
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.48650669
Short name T477
Test name
Test status
Simulation time 11696868 ps
CPU time 0.61 seconds
Started Jan 17 12:43:57 PM PST 24
Finished Jan 17 12:44:01 PM PST 24
Peak memory 194416 kb
Host smart-a2f78ea2-8e91-4463-8509-77d1ba0a1a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48650669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.48650669
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.659388506
Short name T1284
Test name
Test status
Simulation time 45266324 ps
CPU time 0.71 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:43:59 PM PST 24
Peak memory 195952 kb
Host smart-1cd10dca-e2d3-4f6f-9e34-76fae04ebba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659388506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.659388506
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3446899001
Short name T39
Test name
Test status
Simulation time 83897083 ps
CPU time 1.61 seconds
Started Jan 17 12:44:20 PM PST 24
Finished Jan 17 12:44:22 PM PST 24
Peak memory 200068 kb
Host smart-7288865d-5594-4ba9-841f-12ae4b8508bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446899001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3446899001
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.234690570
Short name T484
Test name
Test status
Simulation time 84455812 ps
CPU time 0.98 seconds
Started Jan 17 12:44:21 PM PST 24
Finished Jan 17 12:44:24 PM PST 24
Peak memory 198912 kb
Host smart-71479f6a-f70d-4e08-9fd0-4314844621a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234690570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.234690570
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2319805417
Short name T472
Test name
Test status
Simulation time 27786728 ps
CPU time 0.83 seconds
Started Jan 17 12:43:57 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 199832 kb
Host smart-c1338a17-6789-4038-990b-c25ff2920696
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319805417 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2319805417
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.313168646
Short name T69
Test name
Test status
Simulation time 47768374 ps
CPU time 0.61 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 194660 kb
Host smart-fac36516-29f0-4abf-b83e-86f3ce50e64f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313168646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.313168646
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1394836940
Short name T1281
Test name
Test status
Simulation time 40342459 ps
CPU time 0.57 seconds
Started Jan 17 12:44:20 PM PST 24
Finished Jan 17 12:44:21 PM PST 24
Peak memory 185048 kb
Host smart-a83832f2-cb4c-4beb-b84a-8072cb99c61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394836940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1394836940
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.317111824
Short name T1297
Test name
Test status
Simulation time 56216060 ps
CPU time 0.62 seconds
Started Jan 17 12:44:03 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 195580 kb
Host smart-17ad55d4-25ee-4044-a48c-4c7e32dc9e56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317111824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.317111824
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2859882610
Short name T1253
Test name
Test status
Simulation time 340918328 ps
CPU time 1.68 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 199944 kb
Host smart-f7ca1bfb-03db-4d54-8f2b-dfbf222b1c46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859882610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2859882610
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2385505838
Short name T64
Test name
Test status
Simulation time 271624620 ps
CPU time 0.96 seconds
Started Jan 17 12:44:18 PM PST 24
Finished Jan 17 12:44:20 PM PST 24
Peak memory 198388 kb
Host smart-8d8c83b5-2c02-49a7-a3d4-7135d5de318a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385505838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2385505838
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1293399241
Short name T8
Test name
Test status
Simulation time 204580935 ps
CPU time 0.82 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 199028 kb
Host smart-154dac86-997b-40b0-ad47-59fb7d6e5faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293399241 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1293399241
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3270621442
Short name T483
Test name
Test status
Simulation time 179058729 ps
CPU time 0.59 seconds
Started Jan 17 12:44:11 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 195392 kb
Host smart-80c35995-b7a2-4d07-8684-3b4c762f2c3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270621442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3270621442
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4147552880
Short name T79
Test name
Test status
Simulation time 44214893 ps
CPU time 0.6 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 194300 kb
Host smart-aef22a5e-73e6-4e1b-9a82-2f4f33089563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147552880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4147552880
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1785281181
Short name T1257
Test name
Test status
Simulation time 30697532 ps
CPU time 0.7 seconds
Started Jan 17 12:43:52 PM PST 24
Finished Jan 17 12:43:54 PM PST 24
Peak memory 196992 kb
Host smart-59b3a476-908a-46ad-83e5-9c78a0e57eae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785281181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1785281181
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1985526872
Short name T1285
Test name
Test status
Simulation time 259959606 ps
CPU time 1.8 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:15 PM PST 24
Peak memory 199028 kb
Host smart-b3d57340-43fe-4696-91a9-d4e998e1926b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985526872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1985526872
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2681664359
Short name T1
Test name
Test status
Simulation time 51212886 ps
CPU time 0.96 seconds
Started Jan 17 12:43:49 PM PST 24
Finished Jan 17 12:43:52 PM PST 24
Peak memory 198932 kb
Host smart-8706ddce-9790-4b81-b584-df14cd86ec2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681664359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2681664359
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.666494431
Short name T1244
Test name
Test status
Simulation time 56260357 ps
CPU time 0.69 seconds
Started Jan 17 12:44:04 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 196532 kb
Host smart-aa63e099-487f-42b3-b195-de8c3443152b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666494431 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.666494431
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3006041025
Short name T71
Test name
Test status
Simulation time 13086441 ps
CPU time 0.6 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 195404 kb
Host smart-fbfcb396-42d1-4297-be9d-bd7d68a762d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006041025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3006041025
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.609956074
Short name T70
Test name
Test status
Simulation time 63240170 ps
CPU time 0.62 seconds
Started Jan 17 12:44:00 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 195532 kb
Host smart-7cdd0ee3-2c79-49d2-b917-21fec64dadfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609956074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.609956074
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1811113905
Short name T48
Test name
Test status
Simulation time 102926321 ps
CPU time 1.24 seconds
Started Jan 17 12:43:58 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 199936 kb
Host smart-9520668d-5f2f-40a7-bf8c-b11dd3b10a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811113905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1811113905
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3153763360
Short name T49
Test name
Test status
Simulation time 67605261 ps
CPU time 1.22 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 199096 kb
Host smart-ee656834-7b9a-425d-8a07-7631924e79e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153763360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3153763360
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.128444366
Short name T1293
Test name
Test status
Simulation time 93054765 ps
CPU time 0.81 seconds
Started Jan 17 12:44:10 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 198992 kb
Host smart-67df79e7-0e63-4cf9-94f1-1f51099ef940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128444366 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.128444366
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1711762140
Short name T57
Test name
Test status
Simulation time 65863392 ps
CPU time 0.57 seconds
Started Jan 17 12:44:11 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 195452 kb
Host smart-ba721198-4235-46e8-a26c-d9007c734e15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711762140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1711762140
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2205059280
Short name T479
Test name
Test status
Simulation time 34147013 ps
CPU time 0.58 seconds
Started Jan 17 12:44:08 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 185104 kb
Host smart-d416db46-9aae-4c35-a52f-89da85969507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205059280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2205059280
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1818511324
Short name T1294
Test name
Test status
Simulation time 169859944 ps
CPU time 0.78 seconds
Started Jan 17 12:44:08 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 196968 kb
Host smart-f2ab7447-0962-4d0d-b640-a5fc3629a6ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818511324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1818511324
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1032580083
Short name T1275
Test name
Test status
Simulation time 156321470 ps
CPU time 1.52 seconds
Started Jan 17 12:44:25 PM PST 24
Finished Jan 17 12:44:27 PM PST 24
Peak memory 199952 kb
Host smart-44327fe3-9ad5-48f0-99cd-6443f302edd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032580083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1032580083
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2677363836
Short name T489
Test name
Test status
Simulation time 175831781 ps
CPU time 0.94 seconds
Started Jan 17 12:44:05 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 198984 kb
Host smart-647c0e19-27a4-45bc-b588-4732bb043500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677363836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2677363836
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3989310842
Short name T1269
Test name
Test status
Simulation time 11453521 ps
CPU time 0.59 seconds
Started Jan 17 12:44:16 PM PST 24
Finished Jan 17 12:44:17 PM PST 24
Peak memory 196652 kb
Host smart-d260aa69-04c8-4eb3-809d-a59f2f2defd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989310842 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3989310842
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4064700521
Short name T66
Test name
Test status
Simulation time 15977900 ps
CPU time 0.59 seconds
Started Jan 17 12:44:09 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 195528 kb
Host smart-84f2c3cb-afeb-40e7-8468-b03d39c02a6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064700521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4064700521
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2917209052
Short name T486
Test name
Test status
Simulation time 14348403 ps
CPU time 0.58 seconds
Started Jan 17 12:44:07 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 185120 kb
Host smart-27107f7c-1510-451e-9003-7de2410720ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917209052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2917209052
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.851691623
Short name T485
Test name
Test status
Simulation time 21003053 ps
CPU time 0.71 seconds
Started Jan 17 12:44:09 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 196132 kb
Host smart-a465f637-071f-4412-a606-5eef6c5781ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851691623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.851691623
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4038251713
Short name T47
Test name
Test status
Simulation time 33458603 ps
CPU time 0.94 seconds
Started Jan 17 12:43:57 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 199500 kb
Host smart-9a1b959b-2bab-4fe1-94ca-c5441cf39a56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038251713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4038251713
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2620438528
Short name T1290
Test name
Test status
Simulation time 45542725 ps
CPU time 0.79 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 197940 kb
Host smart-7800137a-1c7c-4a6d-b762-38636941321c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620438528 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2620438528
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.192814562
Short name T1270
Test name
Test status
Simulation time 51876984 ps
CPU time 0.59 seconds
Started Jan 17 12:44:15 PM PST 24
Finished Jan 17 12:44:17 PM PST 24
Peak memory 195416 kb
Host smart-7196f4da-b925-4ba5-8ddd-f2364b5f03c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192814562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.192814562
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3805292411
Short name T1264
Test name
Test status
Simulation time 45573099 ps
CPU time 0.58 seconds
Started Jan 17 12:44:16 PM PST 24
Finished Jan 17 12:44:18 PM PST 24
Peak memory 185112 kb
Host smart-b047e1c6-97e9-40e6-9671-19b5c5605b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805292411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3805292411
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.839390096
Short name T1265
Test name
Test status
Simulation time 120088668 ps
CPU time 0.67 seconds
Started Jan 17 12:44:17 PM PST 24
Finished Jan 17 12:44:18 PM PST 24
Peak memory 196884 kb
Host smart-04d33a06-ec1f-4f60-a14b-e27b7dd1a8fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839390096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.839390096
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.381375210
Short name T41
Test name
Test status
Simulation time 254220801 ps
CPU time 0.87 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 199744 kb
Host smart-6216ad3f-2838-429e-86c3-5ec543372582
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381375210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.381375210
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3320224187
Short name T38
Test name
Test status
Simulation time 132351799 ps
CPU time 1.34 seconds
Started Jan 17 12:44:07 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 199244 kb
Host smart-72db55df-3bac-4db2-be24-b9d9e91f3c10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320224187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3320224187
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1488062946
Short name T465
Test name
Test status
Simulation time 16027879 ps
CPU time 0.64 seconds
Started Jan 17 12:44:08 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 196508 kb
Host smart-18f6f8a0-c69e-4832-bf8f-3c4ce02fca7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488062946 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1488062946
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1004134146
Short name T53
Test name
Test status
Simulation time 44623224 ps
CPU time 0.62 seconds
Started Jan 17 12:44:08 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 195532 kb
Host smart-213a3d2d-be10-4213-95cd-9fb2641534e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004134146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1004134146
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4135647924
Short name T470
Test name
Test status
Simulation time 37266719 ps
CPU time 0.64 seconds
Started Jan 17 12:44:06 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 185112 kb
Host smart-7db8d90f-b126-42bd-a9ae-fe8025704e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135647924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4135647924
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.328037106
Short name T61
Test name
Test status
Simulation time 46096294 ps
CPU time 0.75 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 197164 kb
Host smart-4538017e-130e-4743-8d79-a398b44dce15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328037106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.328037106
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3395632168
Short name T1268
Test name
Test status
Simulation time 63082523 ps
CPU time 1.46 seconds
Started Jan 17 12:44:15 PM PST 24
Finished Jan 17 12:44:18 PM PST 24
Peak memory 200044 kb
Host smart-1f46189a-4288-4913-b7f9-07aae06bf9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395632168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3395632168
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2065580144
Short name T97
Test name
Test status
Simulation time 87870792 ps
CPU time 1.21 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 199052 kb
Host smart-c044032e-ad98-4abc-afef-c92b422ad148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065580144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2065580144
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1056138824
Short name T1299
Test name
Test status
Simulation time 218188330 ps
CPU time 0.89 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:15 PM PST 24
Peak memory 199312 kb
Host smart-4835aaf4-9679-490a-a5cd-18ad0814aba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056138824 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1056138824
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1759191079
Short name T1274
Test name
Test status
Simulation time 60426434 ps
CPU time 0.62 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 195448 kb
Host smart-1ce1acfe-0d27-49ce-ad95-a3623a89854d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759191079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1759191079
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.270131903
Short name T406
Test name
Test status
Simulation time 11423187 ps
CPU time 0.56 seconds
Started Jan 17 12:44:14 PM PST 24
Finished Jan 17 12:44:16 PM PST 24
Peak memory 185092 kb
Host smart-1bc3fed2-70b7-4559-96a9-419118920433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270131903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.270131903
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.150559937
Short name T487
Test name
Test status
Simulation time 55974761 ps
CPU time 1.33 seconds
Started Jan 17 12:44:08 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 200004 kb
Host smart-b37abb40-1e2c-4bde-b739-add57de6e637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150559937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.150559937
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3622078511
Short name T5
Test name
Test status
Simulation time 191426666 ps
CPU time 1 seconds
Started Jan 17 12:44:09 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 198776 kb
Host smart-fb2cb362-40cf-4b20-b389-837f67912b05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622078511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3622078511
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.124590259
Short name T42
Test name
Test status
Simulation time 84357330 ps
CPU time 0.8 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:15 PM PST 24
Peak memory 198956 kb
Host smart-4a324262-cead-422b-8393-1aff1a59a44a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124590259 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.124590259
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3630921780
Short name T90
Test name
Test status
Simulation time 27095567 ps
CPU time 0.57 seconds
Started Jan 17 12:44:18 PM PST 24
Finished Jan 17 12:44:19 PM PST 24
Peak memory 195428 kb
Host smart-6268f692-2ed2-44b1-be37-3f4c2bdc3998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630921780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3630921780
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1977185246
Short name T1252
Test name
Test status
Simulation time 18885780 ps
CPU time 0.54 seconds
Started Jan 17 12:44:18 PM PST 24
Finished Jan 17 12:44:19 PM PST 24
Peak memory 185080 kb
Host smart-286791c7-06bc-4703-9bd2-b53d5a62c6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977185246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1977185246
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.432533658
Short name T59
Test name
Test status
Simulation time 23963862 ps
CPU time 0.66 seconds
Started Jan 17 12:44:14 PM PST 24
Finished Jan 17 12:44:16 PM PST 24
Peak memory 195652 kb
Host smart-9538f06f-5b10-424b-ad7f-19afb0877237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432533658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.432533658
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1463244547
Short name T1276
Test name
Test status
Simulation time 74122415 ps
CPU time 1.86 seconds
Started Jan 17 12:44:17 PM PST 24
Finished Jan 17 12:44:20 PM PST 24
Peak memory 200020 kb
Host smart-1d8003ec-90f9-4079-921d-222a7850799d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463244547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1463244547
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2309495279
Short name T471
Test name
Test status
Simulation time 102095559 ps
CPU time 1.01 seconds
Started Jan 17 12:44:15 PM PST 24
Finished Jan 17 12:44:17 PM PST 24
Peak memory 199008 kb
Host smart-597fca07-0d30-40ba-a893-bae4bc3001d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309495279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2309495279
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1092367393
Short name T1249
Test name
Test status
Simulation time 219024266 ps
CPU time 0.77 seconds
Started Jan 17 12:44:06 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 196888 kb
Host smart-be1f539f-b6ea-4a89-9d99-62dcf98b9446
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092367393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1092367393
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1762505085
Short name T77
Test name
Test status
Simulation time 133280670 ps
CPU time 1.53 seconds
Started Jan 17 12:44:04 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 197756 kb
Host smart-52e8b19b-c177-4efd-b39b-1c7074c9ed6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762505085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1762505085
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2617546441
Short name T34
Test name
Test status
Simulation time 25739719 ps
CPU time 0.6 seconds
Started Jan 17 12:43:54 PM PST 24
Finished Jan 17 12:43:55 PM PST 24
Peak memory 195500 kb
Host smart-b538598a-c1d9-455c-a9a2-a1c4ccb41502
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617546441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2617546441
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.122463375
Short name T1300
Test name
Test status
Simulation time 24251856 ps
CPU time 0.76 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 199880 kb
Host smart-cf9f82fc-7a6c-4ffd-a381-4635f0d05577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122463375 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.122463375
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.692264083
Short name T4
Test name
Test status
Simulation time 48905906 ps
CPU time 0.62 seconds
Started Jan 17 12:43:54 PM PST 24
Finished Jan 17 12:43:55 PM PST 24
Peak memory 195524 kb
Host smart-9ff010d2-0711-4667-9804-796161646145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692264083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.692264083
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.969487143
Short name T1256
Test name
Test status
Simulation time 12614701 ps
CPU time 0.6 seconds
Started Jan 17 12:43:45 PM PST 24
Finished Jan 17 12:43:49 PM PST 24
Peak memory 185116 kb
Host smart-3537b2a0-52bb-45a5-b6dd-36637b046952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969487143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.969487143
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2574819027
Short name T488
Test name
Test status
Simulation time 69891281 ps
CPU time 0.64 seconds
Started Jan 17 12:43:58 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 195692 kb
Host smart-cd552cb9-4250-4bc6-bacd-95853a79da0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574819027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2574819027
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.783805050
Short name T1295
Test name
Test status
Simulation time 23255586 ps
CPU time 1.16 seconds
Started Jan 17 12:43:58 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 200028 kb
Host smart-8b502395-2d3a-4bc6-b09a-6d155c745042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783805050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.783805050
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.79919891
Short name T1260
Test name
Test status
Simulation time 199744718 ps
CPU time 1.06 seconds
Started Jan 17 12:43:48 PM PST 24
Finished Jan 17 12:43:51 PM PST 24
Peak memory 199016 kb
Host smart-e473fa43-2831-4186-9eaa-d91a842d6ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79919891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.79919891
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1971308917
Short name T1289
Test name
Test status
Simulation time 16405531 ps
CPU time 0.58 seconds
Started Jan 17 12:44:16 PM PST 24
Finished Jan 17 12:44:17 PM PST 24
Peak memory 185228 kb
Host smart-f3fb5e5f-1987-4c52-974d-932fac66036e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971308917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1971308917
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1067382495
Short name T91
Test name
Test status
Simulation time 40279057 ps
CPU time 0.56 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 185124 kb
Host smart-3c1cffb9-ad85-44d2-95dd-32b533121c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067382495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1067382495
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2243343919
Short name T1283
Test name
Test status
Simulation time 12688357 ps
CPU time 0.55 seconds
Started Jan 17 12:44:11 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 194324 kb
Host smart-ab788997-e96b-4420-b091-bc298031098a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243343919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2243343919
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.413444040
Short name T80
Test name
Test status
Simulation time 31653090 ps
CPU time 0.59 seconds
Started Jan 17 12:44:16 PM PST 24
Finished Jan 17 12:44:17 PM PST 24
Peak memory 194464 kb
Host smart-94613f0f-5df0-479f-a84b-c5cf36232d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413444040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.413444040
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1556153191
Short name T1250
Test name
Test status
Simulation time 50358345 ps
CPU time 0.6 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 185124 kb
Host smart-2e73d1ed-b506-4f11-b162-60abcd97f14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556153191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1556153191
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1828001979
Short name T469
Test name
Test status
Simulation time 164410716 ps
CPU time 0.55 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:15 PM PST 24
Peak memory 185096 kb
Host smart-ed5d4960-a28c-4848-ba5b-623dabd5afd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828001979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1828001979
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1040682172
Short name T50
Test name
Test status
Simulation time 16458768 ps
CPU time 0.54 seconds
Started Jan 17 12:44:07 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 194412 kb
Host smart-e58f6ae1-ccab-448c-8408-d1de56e5c85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040682172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1040682172
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2746700925
Short name T468
Test name
Test status
Simulation time 28299870 ps
CPU time 0.55 seconds
Started Jan 17 12:44:08 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 185060 kb
Host smart-2175d512-6fde-41f3-9a9f-eb99f43cf2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746700925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2746700925
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1101532400
Short name T1291
Test name
Test status
Simulation time 11952254 ps
CPU time 0.55 seconds
Started Jan 17 12:44:14 PM PST 24
Finished Jan 17 12:44:16 PM PST 24
Peak memory 185192 kb
Host smart-a6840d49-6903-4fcc-b7a8-1093491b1e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101532400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1101532400
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3268354929
Short name T75
Test name
Test status
Simulation time 40455078 ps
CPU time 0.68 seconds
Started Jan 17 12:44:01 PM PST 24
Finished Jan 17 12:44:04 PM PST 24
Peak memory 195116 kb
Host smart-47e9ffd5-3f5c-48b4-9481-a601783f06d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268354929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3268354929
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3663193933
Short name T58
Test name
Test status
Simulation time 493537916 ps
CPU time 2.27 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:44:00 PM PST 24
Peak memory 197844 kb
Host smart-a8b90ca9-e1ad-4a90-a9f6-c596869fd41c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663193933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3663193933
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4070325451
Short name T1255
Test name
Test status
Simulation time 26111536 ps
CPU time 0.57 seconds
Started Jan 17 12:43:43 PM PST 24
Finished Jan 17 12:43:46 PM PST 24
Peak memory 195464 kb
Host smart-c35eae1d-4418-4b9a-9301-0c235b1ac573
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070325451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4070325451
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1680172022
Short name T7
Test name
Test status
Simulation time 30753239 ps
CPU time 0.64 seconds
Started Jan 17 12:44:06 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 196396 kb
Host smart-b7a4b7fd-b9d2-4800-8633-ff047ef8f57d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680172022 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1680172022
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.674688864
Short name T475
Test name
Test status
Simulation time 15796077 ps
CPU time 0.62 seconds
Started Jan 17 12:43:49 PM PST 24
Finished Jan 17 12:43:52 PM PST 24
Peak memory 195476 kb
Host smart-3491fecf-09b9-4ff5-a9a6-8ac913a90fe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674688864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.674688864
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3082174583
Short name T1301
Test name
Test status
Simulation time 120794262 ps
CPU time 0.55 seconds
Started Jan 17 12:43:52 PM PST 24
Finished Jan 17 12:43:54 PM PST 24
Peak memory 185080 kb
Host smart-d2522c24-2ffe-473e-b810-56d10a22fe0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082174583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3082174583
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2376391066
Short name T89
Test name
Test status
Simulation time 15198296 ps
CPU time 0.7 seconds
Started Jan 17 12:43:52 PM PST 24
Finished Jan 17 12:43:55 PM PST 24
Peak memory 195772 kb
Host smart-665e97de-064b-4ef2-98ba-8de421c3f90c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376391066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2376391066
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.916373374
Short name T78
Test name
Test status
Simulation time 249901983 ps
CPU time 1.23 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:44:01 PM PST 24
Peak memory 199232 kb
Host smart-74dc30df-9deb-48f8-bb1f-7bf41d3b5d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916373374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.916373374
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1237470990
Short name T1287
Test name
Test status
Simulation time 13689354 ps
CPU time 0.57 seconds
Started Jan 17 12:44:10 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 194324 kb
Host smart-3366d479-2a30-4024-bd67-bafe58e0b9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237470990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1237470990
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1368732562
Short name T401
Test name
Test status
Simulation time 47027005 ps
CPU time 0.63 seconds
Started Jan 17 12:44:22 PM PST 24
Finished Jan 17 12:44:24 PM PST 24
Peak memory 185180 kb
Host smart-b0412823-4d27-48f6-ae64-7147d58d25b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368732562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1368732562
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1607809224
Short name T74
Test name
Test status
Simulation time 23485322 ps
CPU time 0.55 seconds
Started Jan 17 12:44:14 PM PST 24
Finished Jan 17 12:44:15 PM PST 24
Peak memory 185120 kb
Host smart-909e1361-73d4-44b8-80fc-83fde6079d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607809224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1607809224
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.776272722
Short name T1298
Test name
Test status
Simulation time 148117260 ps
CPU time 0.56 seconds
Started Jan 17 12:44:12 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 185180 kb
Host smart-83de3667-ada4-4082-80f1-1d7a399f8879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776272722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.776272722
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2343412008
Short name T92
Test name
Test status
Simulation time 34742180 ps
CPU time 0.55 seconds
Started Jan 17 12:44:16 PM PST 24
Finished Jan 17 12:44:18 PM PST 24
Peak memory 194328 kb
Host smart-59919628-7e5c-42fa-b9c2-d6aa66015391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343412008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2343412008
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3018630852
Short name T481
Test name
Test status
Simulation time 74189635 ps
CPU time 0.55 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:15 PM PST 24
Peak memory 185112 kb
Host smart-0105cf54-1735-47df-b28d-ac95c7eb63d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018630852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3018630852
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1027668732
Short name T402
Test name
Test status
Simulation time 58148178 ps
CPU time 0.53 seconds
Started Jan 17 12:44:15 PM PST 24
Finished Jan 17 12:44:16 PM PST 24
Peak memory 194304 kb
Host smart-8b4d07fc-894a-43c9-a18f-713d9a0dfe40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027668732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1027668732
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4277450198
Short name T1259
Test name
Test status
Simulation time 38994504 ps
CPU time 0.55 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 185100 kb
Host smart-514028c7-b901-4f5f-9add-03b1b8065c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277450198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4277450198
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4080013124
Short name T467
Test name
Test status
Simulation time 12880283 ps
CPU time 0.56 seconds
Started Jan 17 12:44:16 PM PST 24
Finished Jan 17 12:44:18 PM PST 24
Peak memory 185188 kb
Host smart-4f0c7df4-b68c-4a6c-937a-75b020880df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080013124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4080013124
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3603984934
Short name T1272
Test name
Test status
Simulation time 49242804 ps
CPU time 0.56 seconds
Started Jan 17 12:44:10 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 185108 kb
Host smart-7ab08188-b431-4741-be36-bd457cb67998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603984934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3603984934
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1055372801
Short name T2
Test name
Test status
Simulation time 22589951 ps
CPU time 0.65 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 195516 kb
Host smart-9bf38b7c-29cb-4d15-916d-21837bf9e44f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055372801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1055372801
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1495033243
Short name T35
Test name
Test status
Simulation time 13012832 ps
CPU time 0.62 seconds
Started Jan 17 12:43:58 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 195440 kb
Host smart-6ab32547-d6d4-4480-8bc9-032c2dc60f5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495033243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1495033243
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1693758912
Short name T407
Test name
Test status
Simulation time 18179089 ps
CPU time 0.64 seconds
Started Jan 17 12:43:45 PM PST 24
Finished Jan 17 12:43:48 PM PST 24
Peak memory 195756 kb
Host smart-4e8cada7-d3fd-4fd9-92f1-187650c2b9f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693758912 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1693758912
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1191431359
Short name T65
Test name
Test status
Simulation time 33249967 ps
CPU time 0.6 seconds
Started Jan 17 12:43:55 PM PST 24
Finished Jan 17 12:43:58 PM PST 24
Peak memory 195516 kb
Host smart-ae340aba-ce90-496b-ab94-7a806c7f6f0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191431359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1191431359
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1715214477
Short name T1286
Test name
Test status
Simulation time 28210599 ps
CPU time 0.59 seconds
Started Jan 17 12:43:58 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 185176 kb
Host smart-efcfed51-6c14-4447-a244-2e39bd095a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715214477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1715214477
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1406567770
Short name T88
Test name
Test status
Simulation time 25993273 ps
CPU time 0.78 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 197068 kb
Host smart-e3faa48f-7556-4ccb-bee2-79507304d825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406567770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1406567770
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.453927433
Short name T1280
Test name
Test status
Simulation time 488475929 ps
CPU time 2.53 seconds
Started Jan 17 12:43:56 PM PST 24
Finished Jan 17 12:44:01 PM PST 24
Peak memory 200020 kb
Host smart-3b89ebfb-3eba-4934-ab99-360b7b7187bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453927433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.453927433
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3888461060
Short name T463
Test name
Test status
Simulation time 415917129 ps
CPU time 0.9 seconds
Started Jan 17 12:43:55 PM PST 24
Finished Jan 17 12:43:57 PM PST 24
Peak memory 198836 kb
Host smart-df9953df-432f-4fe1-8ce0-d2e31d1400b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888461060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3888461060
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.59242467
Short name T480
Test name
Test status
Simulation time 35699873 ps
CPU time 0.57 seconds
Started Jan 17 12:44:19 PM PST 24
Finished Jan 17 12:44:20 PM PST 24
Peak memory 185080 kb
Host smart-bd772307-4753-4e69-953e-91a342632a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59242467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.59242467
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.578753535
Short name T1262
Test name
Test status
Simulation time 11879464 ps
CPU time 0.56 seconds
Started Jan 17 12:44:18 PM PST 24
Finished Jan 17 12:44:19 PM PST 24
Peak memory 185108 kb
Host smart-ff272a29-2d5c-4965-9198-7e5fb1e33826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578753535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.578753535
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2346852178
Short name T10
Test name
Test status
Simulation time 16462474 ps
CPU time 0.58 seconds
Started Jan 17 12:44:23 PM PST 24
Finished Jan 17 12:44:25 PM PST 24
Peak memory 185184 kb
Host smart-5b108fad-9588-4fd8-b140-6d44bb816d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346852178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2346852178
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1953497161
Short name T72
Test name
Test status
Simulation time 24868556 ps
CPU time 0.61 seconds
Started Jan 17 12:44:18 PM PST 24
Finished Jan 17 12:44:20 PM PST 24
Peak memory 185064 kb
Host smart-45b138d4-074c-495d-958a-ffd23ec13cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953497161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1953497161
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3911661026
Short name T32
Test name
Test status
Simulation time 59213774 ps
CPU time 0.55 seconds
Started Jan 17 12:44:15 PM PST 24
Finished Jan 17 12:44:16 PM PST 24
Peak memory 194332 kb
Host smart-2cd87732-6a4b-4d8e-8436-73c4287f0eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911661026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3911661026
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2238825461
Short name T403
Test name
Test status
Simulation time 13300563 ps
CPU time 0.6 seconds
Started Jan 17 12:44:18 PM PST 24
Finished Jan 17 12:44:20 PM PST 24
Peak memory 185080 kb
Host smart-3e27a7b2-f943-4675-963e-5ece5ed5308f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238825461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2238825461
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3651407247
Short name T1271
Test name
Test status
Simulation time 42442884 ps
CPU time 0.59 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:14 PM PST 24
Peak memory 185116 kb
Host smart-ea898a8f-611e-4c46-a603-db61747b432c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651407247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3651407247
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2672124850
Short name T466
Test name
Test status
Simulation time 12831044 ps
CPU time 0.57 seconds
Started Jan 17 12:44:17 PM PST 24
Finished Jan 17 12:44:19 PM PST 24
Peak memory 194312 kb
Host smart-7a4aabdb-d3d1-49df-be88-6bbe06a9b6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672124850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2672124850
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.692760183
Short name T1258
Test name
Test status
Simulation time 43213416 ps
CPU time 0.58 seconds
Started Jan 17 12:44:22 PM PST 24
Finished Jan 17 12:44:24 PM PST 24
Peak memory 185120 kb
Host smart-0b2974d8-edd3-4434-b05c-a6b1210f41a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692760183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.692760183
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1553545516
Short name T51
Test name
Test status
Simulation time 21175815 ps
CPU time 0.81 seconds
Started Jan 17 12:43:50 PM PST 24
Finished Jan 17 12:43:53 PM PST 24
Peak memory 198404 kb
Host smart-f89feb76-be1a-45f5-9131-4492f8b0059c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553545516 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1553545516
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.96248717
Short name T60
Test name
Test status
Simulation time 33666402 ps
CPU time 0.62 seconds
Started Jan 17 12:44:01 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 195432 kb
Host smart-54bcfe04-beb9-469c-89c9-2c224cb3bb3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96248717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.96248717
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2919157417
Short name T404
Test name
Test status
Simulation time 15684499 ps
CPU time 0.66 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 185172 kb
Host smart-dc681027-c140-413f-8a40-8a114685555a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919157417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2919157417
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1403646962
Short name T474
Test name
Test status
Simulation time 87730018 ps
CPU time 0.75 seconds
Started Jan 17 12:43:45 PM PST 24
Finished Jan 17 12:43:48 PM PST 24
Peak memory 197312 kb
Host smart-b1bccbb1-faf2-494b-a56f-273b58ee69a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403646962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1403646962
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4087396043
Short name T37
Test name
Test status
Simulation time 139893461 ps
CPU time 1.96 seconds
Started Jan 17 12:43:57 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 200136 kb
Host smart-1cff4ce0-9028-4307-9abb-29c77b1e3a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087396043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4087396043
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1328037998
Short name T73
Test name
Test status
Simulation time 185414006 ps
CPU time 0.75 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 198332 kb
Host smart-7a5b9f8f-b1dd-4191-8202-dbfc848aa9f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328037998 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1328037998
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.211123918
Short name T68
Test name
Test status
Simulation time 28534778 ps
CPU time 0.56 seconds
Started Jan 17 12:44:01 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 195432 kb
Host smart-2841339a-086b-4fd5-adb1-24fada848749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211123918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.211123918
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3113768333
Short name T1248
Test name
Test status
Simulation time 15921167 ps
CPU time 0.59 seconds
Started Jan 17 12:43:55 PM PST 24
Finished Jan 17 12:43:56 PM PST 24
Peak memory 194724 kb
Host smart-527c19a7-1554-420a-879f-258201001f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113768333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3113768333
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.4191957202
Short name T54
Test name
Test status
Simulation time 61568115 ps
CPU time 0.62 seconds
Started Jan 17 12:43:58 PM PST 24
Finished Jan 17 12:44:02 PM PST 24
Peak memory 195552 kb
Host smart-dcbcb39e-1fd7-433f-9c1f-40d45f0f7562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191957202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.4191957202
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2878580231
Short name T1278
Test name
Test status
Simulation time 21770718 ps
CPU time 1.12 seconds
Started Jan 17 12:44:00 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 200008 kb
Host smart-ed9e730d-90b1-4995-adf8-1f78cbd48815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878580231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2878580231
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.934195841
Short name T98
Test name
Test status
Simulation time 90480015 ps
CPU time 1.33 seconds
Started Jan 17 12:44:10 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 199104 kb
Host smart-b654e3d2-8daa-468c-94e4-7cd50ce1cf2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934195841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.934195841
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.628615558
Short name T1292
Test name
Test status
Simulation time 78571319 ps
CPU time 0.76 seconds
Started Jan 17 12:44:04 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 198380 kb
Host smart-461e74ef-d43f-4f3a-b680-f1e1eae135d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628615558 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.628615558
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1197113326
Short name T44
Test name
Test status
Simulation time 15030687 ps
CPU time 0.59 seconds
Started Jan 17 12:43:57 PM PST 24
Finished Jan 17 12:44:01 PM PST 24
Peak memory 195456 kb
Host smart-8cfecefe-669c-47ff-809c-d451a75e0562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197113326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1197113326
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3308358513
Short name T1267
Test name
Test status
Simulation time 12466558 ps
CPU time 0.55 seconds
Started Jan 17 12:44:17 PM PST 24
Finished Jan 17 12:44:18 PM PST 24
Peak memory 185164 kb
Host smart-d7088ae5-9b90-409d-94f0-26ed46bd6dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308358513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3308358513
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1813275746
Short name T87
Test name
Test status
Simulation time 98152703 ps
CPU time 0.74 seconds
Started Jan 17 12:44:00 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 197048 kb
Host smart-02dc5e8f-9bc0-4212-8060-0165cd96ff40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813275746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1813275746
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.803210122
Short name T492
Test name
Test status
Simulation time 128690916 ps
CPU time 1.68 seconds
Started Jan 17 12:43:50 PM PST 24
Finished Jan 17 12:43:54 PM PST 24
Peak memory 200012 kb
Host smart-eb9e95c6-220d-4645-8e86-e7e6c3c40272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803210122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.803210122
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4026762623
Short name T1282
Test name
Test status
Simulation time 132334254 ps
CPU time 1.23 seconds
Started Jan 17 12:44:11 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 199212 kb
Host smart-b50a739d-cba0-409d-8f6f-03422f3fe7c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026762623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4026762623
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3194435913
Short name T46
Test name
Test status
Simulation time 50081798 ps
CPU time 1.4 seconds
Started Jan 17 12:44:16 PM PST 24
Finished Jan 17 12:44:18 PM PST 24
Peak memory 199952 kb
Host smart-06550708-f7a2-479e-8209-eaf3e1192483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194435913 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3194435913
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1277132045
Short name T1261
Test name
Test status
Simulation time 25329451 ps
CPU time 0.54 seconds
Started Jan 17 12:44:04 PM PST 24
Finished Jan 17 12:44:11 PM PST 24
Peak memory 195416 kb
Host smart-43da54d9-f106-432b-9a2f-7b3ab36f50aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277132045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1277132045
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2741286883
Short name T1251
Test name
Test status
Simulation time 10564693 ps
CPU time 0.64 seconds
Started Jan 17 12:44:02 PM PST 24
Finished Jan 17 12:44:10 PM PST 24
Peak memory 185168 kb
Host smart-a1dd7266-e162-4f17-9dc1-c20049ebd97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741286883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2741286883
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3168156692
Short name T473
Test name
Test status
Simulation time 14034315 ps
CPU time 0.64 seconds
Started Jan 17 12:44:17 PM PST 24
Finished Jan 17 12:44:19 PM PST 24
Peak memory 195832 kb
Host smart-d22e146e-9cd7-4518-95de-39a43f0b0d94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168156692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3168156692
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.706860020
Short name T491
Test name
Test status
Simulation time 41736609 ps
CPU time 1.94 seconds
Started Jan 17 12:44:03 PM PST 24
Finished Jan 17 12:44:12 PM PST 24
Peak memory 200076 kb
Host smart-d4a7083c-8673-49f4-becb-5029294f3b58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706860020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.706860020
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.567087579
Short name T1246
Test name
Test status
Simulation time 365842967 ps
CPU time 1.3 seconds
Started Jan 17 12:44:00 PM PST 24
Finished Jan 17 12:44:04 PM PST 24
Peak memory 199212 kb
Host smart-8e5a310e-8d92-4754-9938-e70a8a913057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567087579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.567087579
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.380853105
Short name T45
Test name
Test status
Simulation time 85240899 ps
CPU time 0.82 seconds
Started Jan 17 12:43:59 PM PST 24
Finished Jan 17 12:44:03 PM PST 24
Peak memory 198736 kb
Host smart-364a49c4-7bad-4a80-91b2-ab706143df5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380853105 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.380853105
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3214442129
Short name T52
Test name
Test status
Simulation time 15492999 ps
CPU time 0.63 seconds
Started Jan 17 12:43:57 PM PST 24
Finished Jan 17 12:44:01 PM PST 24
Peak memory 195568 kb
Host smart-cd55551f-57fb-4140-9574-ab7870ee811d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214442129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3214442129
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1551895524
Short name T1296
Test name
Test status
Simulation time 14438657 ps
CPU time 0.55 seconds
Started Jan 17 12:44:11 PM PST 24
Finished Jan 17 12:44:13 PM PST 24
Peak memory 185048 kb
Host smart-0195c9a4-cff0-4c61-8c50-964ce474d322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551895524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1551895524
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.248671322
Short name T62
Test name
Test status
Simulation time 19365703 ps
CPU time 0.7 seconds
Started Jan 17 12:44:13 PM PST 24
Finished Jan 17 12:44:15 PM PST 24
Peak memory 195568 kb
Host smart-cd1f6ad6-1620-4415-a21a-57272ec979ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248671322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.248671322
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.387574982
Short name T40
Test name
Test status
Simulation time 76791738 ps
CPU time 1.11 seconds
Started Jan 17 12:44:20 PM PST 24
Finished Jan 17 12:44:22 PM PST 24
Peak memory 200064 kb
Host smart-aa92bb0a-9921-41e8-ad46-bb30b43f6bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387574982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.387574982
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1778060682
Short name T1273
Test name
Test status
Simulation time 129617625 ps
CPU time 0.98 seconds
Started Jan 17 12:44:18 PM PST 24
Finished Jan 17 12:44:20 PM PST 24
Peak memory 198836 kb
Host smart-35cfadd3-be96-4640-9c66-8c1fffb7892b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778060682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1778060682
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.919857056
Short name T846
Test name
Test status
Simulation time 15250077 ps
CPU time 0.57 seconds
Started Jan 17 01:54:41 PM PST 24
Finished Jan 17 01:54:43 PM PST 24
Peak memory 195652 kb
Host smart-f9b438fb-51a2-4012-a2ee-2f7bae13eb2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919857056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.919857056
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.547235375
Short name T888
Test name
Test status
Simulation time 173356403343 ps
CPU time 104.14 seconds
Started Jan 17 01:54:31 PM PST 24
Finished Jan 17 01:56:23 PM PST 24
Peak memory 200244 kb
Host smart-ba786461-2ec9-4e71-8411-da71d4e136e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547235375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.547235375
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.310094068
Short name T268
Test name
Test status
Simulation time 20729473964 ps
CPU time 31.49 seconds
Started Jan 17 01:54:31 PM PST 24
Finished Jan 17 01:55:04 PM PST 24
Peak memory 199876 kb
Host smart-4642ad7b-f842-453b-9a4f-e6671e68877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310094068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.310094068
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3547436712
Short name T1000
Test name
Test status
Simulation time 58171556217 ps
CPU time 6.49 seconds
Started Jan 17 01:54:30 PM PST 24
Finished Jan 17 01:54:39 PM PST 24
Peak memory 199476 kb
Host smart-7130a8b9-7b8f-4c70-8244-7d99874c5771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547436712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3547436712
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.311355739
Short name T617
Test name
Test status
Simulation time 152930883741 ps
CPU time 242.93 seconds
Started Jan 17 01:54:32 PM PST 24
Finished Jan 17 01:58:41 PM PST 24
Peak memory 195940 kb
Host smart-676c62e2-2bc7-4240-a316-47a2ba32fd33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311355739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.311355739
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2573818832
Short name T416
Test name
Test status
Simulation time 250871847253 ps
CPU time 539.17 seconds
Started Jan 17 01:54:42 PM PST 24
Finished Jan 17 02:03:42 PM PST 24
Peak memory 200280 kb
Host smart-ed4314f1-b665-423e-9868-25e94e7b05c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573818832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2573818832
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1646125302
Short name T680
Test name
Test status
Simulation time 120374739592 ps
CPU time 341.57 seconds
Started Jan 17 01:54:40 PM PST 24
Finished Jan 17 02:00:23 PM PST 24
Peak memory 208736 kb
Host smart-2b6cce06-7987-46a0-a9a9-23aed211ed7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646125302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1646125302
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2821196148
Short name T850
Test name
Test status
Simulation time 28839089422 ps
CPU time 372.51 seconds
Started Jan 17 01:54:42 PM PST 24
Finished Jan 17 02:00:55 PM PST 24
Peak memory 200272 kb
Host smart-e6674c95-06c6-4501-a064-cf42ca853783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821196148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2821196148
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2904638690
Short name T494
Test name
Test status
Simulation time 1489103578 ps
CPU time 6.19 seconds
Started Jan 17 01:54:33 PM PST 24
Finished Jan 17 01:54:45 PM PST 24
Peak memory 198344 kb
Host smart-c48cf7b4-9f40-4816-b33f-8df48762d3bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904638690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2904638690
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2320794935
Short name T1174
Test name
Test status
Simulation time 178428281053 ps
CPU time 37.54 seconds
Started Jan 17 01:54:42 PM PST 24
Finished Jan 17 01:55:20 PM PST 24
Peak memory 200232 kb
Host smart-017bc4a3-ab42-44fc-9d5b-b63d09511d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320794935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2320794935
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2373860256
Short name T606
Test name
Test status
Simulation time 5983303769 ps
CPU time 8.77 seconds
Started Jan 17 01:54:40 PM PST 24
Finished Jan 17 01:54:49 PM PST 24
Peak memory 195956 kb
Host smart-5b3cf52d-8bca-4914-8cb3-b1a6308c3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373860256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2373860256
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.2656606257
Short name T1010
Test name
Test status
Simulation time 481036848 ps
CPU time 1.32 seconds
Started Jan 17 01:54:33 PM PST 24
Finished Jan 17 01:54:40 PM PST 24
Peak memory 198324 kb
Host smart-c79b6a5a-77d6-4bd1-9821-274fdce2d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656606257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2656606257
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.726724216
Short name T880
Test name
Test status
Simulation time 1074497976153 ps
CPU time 217.08 seconds
Started Jan 17 01:54:40 PM PST 24
Finished Jan 17 01:58:18 PM PST 24
Peak memory 208684 kb
Host smart-479d7b4c-0bbf-41ec-bac7-cac3802e75f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726724216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.726724216
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2752258414
Short name T82
Test name
Test status
Simulation time 70583196574 ps
CPU time 1102.49 seconds
Started Jan 17 01:54:43 PM PST 24
Finished Jan 17 02:13:06 PM PST 24
Peak memory 231148 kb
Host smart-520d0fb5-fc94-4ff6-a3f7-dbdf91f976af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752258414 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2752258414
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2001625967
Short name T1226
Test name
Test status
Simulation time 2462960571 ps
CPU time 1.84 seconds
Started Jan 17 01:54:39 PM PST 24
Finished Jan 17 01:54:42 PM PST 24
Peak memory 198464 kb
Host smart-cc0fec99-75a2-4699-928a-b37d1e1842f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001625967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2001625967
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.4197781516
Short name T656
Test name
Test status
Simulation time 28800818047 ps
CPU time 12.92 seconds
Started Jan 17 01:54:30 PM PST 24
Finished Jan 17 01:54:45 PM PST 24
Peak memory 200268 kb
Host smart-855c7533-16ec-41d1-842c-2280fc1889fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197781516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.4197781516
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1344305736
Short name T665
Test name
Test status
Simulation time 31188264 ps
CPU time 0.56 seconds
Started Jan 17 01:54:51 PM PST 24
Finished Jan 17 01:54:52 PM PST 24
Peak memory 195700 kb
Host smart-dcc0b7d4-2c06-418a-82a0-a79764fff040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344305736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1344305736
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.298598449
Short name T1042
Test name
Test status
Simulation time 49823292070 ps
CPU time 20.96 seconds
Started Jan 17 01:54:41 PM PST 24
Finished Jan 17 01:55:03 PM PST 24
Peak memory 200240 kb
Host smart-63fad1c0-e3bd-4f9f-99cc-10d44e45023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298598449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.298598449
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1730134163
Short name T1138
Test name
Test status
Simulation time 51929555133 ps
CPU time 83.34 seconds
Started Jan 17 01:54:46 PM PST 24
Finished Jan 17 01:56:12 PM PST 24
Peak memory 198432 kb
Host smart-2025dc31-ec4d-4342-b90d-b455c8956394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730134163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1730134163
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.3874797623
Short name T659
Test name
Test status
Simulation time 1239977352190 ps
CPU time 2068.44 seconds
Started Jan 17 01:54:41 PM PST 24
Finished Jan 17 02:29:11 PM PST 24
Peak memory 199880 kb
Host smart-eb6fb67b-feab-40c4-9cca-5ddb0731f002
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874797623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3874797623
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3766157337
Short name T1116
Test name
Test status
Simulation time 44686276715 ps
CPU time 243.21 seconds
Started Jan 17 01:54:48 PM PST 24
Finished Jan 17 01:58:53 PM PST 24
Peak memory 200252 kb
Host smart-81a16b50-f1a9-409b-a0fd-b5710b0de413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766157337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3766157337
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2237170840
Short name T628
Test name
Test status
Simulation time 1480302118 ps
CPU time 1.56 seconds
Started Jan 17 01:54:46 PM PST 24
Finished Jan 17 01:54:51 PM PST 24
Peak memory 197516 kb
Host smart-28d1a47c-cff2-4afa-87fc-c66e18095989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237170840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2237170840
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4175370245
Short name T423
Test name
Test status
Simulation time 443236314049 ps
CPU time 54.02 seconds
Started Jan 17 01:54:39 PM PST 24
Finished Jan 17 01:55:34 PM PST 24
Peak memory 200456 kb
Host smart-8f7e0c15-2874-4503-ad1c-a4a7ef260dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175370245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4175370245
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1944789654
Short name T667
Test name
Test status
Simulation time 25084963439 ps
CPU time 588.57 seconds
Started Jan 17 01:54:50 PM PST 24
Finished Jan 17 02:04:39 PM PST 24
Peak memory 200260 kb
Host smart-3176915e-6f2b-4182-b64b-347a9f28570e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944789654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1944789654
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.4282456076
Short name T736
Test name
Test status
Simulation time 4505394856 ps
CPU time 8.55 seconds
Started Jan 17 01:54:42 PM PST 24
Finished Jan 17 01:54:51 PM PST 24
Peak memory 198964 kb
Host smart-21818bf1-2f71-4a69-b59e-019c94dfc6c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282456076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4282456076
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2476509204
Short name T1194
Test name
Test status
Simulation time 102118350930 ps
CPU time 37.12 seconds
Started Jan 17 01:54:40 PM PST 24
Finished Jan 17 01:55:18 PM PST 24
Peak memory 200212 kb
Host smart-bfaaf810-d2d6-424a-9b73-f1d2b7b59947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476509204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2476509204
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1612601468
Short name T735
Test name
Test status
Simulation time 37188175781 ps
CPU time 51.14 seconds
Started Jan 17 01:54:42 PM PST 24
Finished Jan 17 01:55:34 PM PST 24
Peak memory 196016 kb
Host smart-4043a87d-a80b-4cc7-b105-6e473f1ef94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612601468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1612601468
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2794528219
Short name T94
Test name
Test status
Simulation time 308383733 ps
CPU time 0.87 seconds
Started Jan 17 01:54:49 PM PST 24
Finished Jan 17 01:54:51 PM PST 24
Peak memory 218792 kb
Host smart-90303bea-e178-4b12-b0f5-b8b51b0741fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794528219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2794528219
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1143909305
Short name T632
Test name
Test status
Simulation time 84229385 ps
CPU time 0.83 seconds
Started Jan 17 01:54:39 PM PST 24
Finished Jan 17 01:54:41 PM PST 24
Peak memory 196824 kb
Host smart-532d68e1-1a23-4d8b-af4f-54ec8ea89ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143909305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1143909305
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1182041836
Short name T861
Test name
Test status
Simulation time 358198489389 ps
CPU time 459.73 seconds
Started Jan 17 01:54:46 PM PST 24
Finished Jan 17 02:02:29 PM PST 24
Peak memory 213992 kb
Host smart-66b6344e-e979-4547-9302-4ea11b68fd31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182041836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1182041836
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1096461081
Short name T859
Test name
Test status
Simulation time 6547306276 ps
CPU time 1.74 seconds
Started Jan 17 01:54:39 PM PST 24
Finished Jan 17 01:54:42 PM PST 24
Peak memory 198948 kb
Host smart-918beb9a-bfee-471b-9088-6244a4d8ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096461081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1096461081
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4125622463
Short name T654
Test name
Test status
Simulation time 8364331125 ps
CPU time 12.87 seconds
Started Jan 17 01:54:39 PM PST 24
Finished Jan 17 01:54:53 PM PST 24
Peak memory 199980 kb
Host smart-19d512e6-30dd-4d0c-91f3-f1a4c8a2e31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125622463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4125622463
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1850998847
Short name T308
Test name
Test status
Simulation time 124611688813 ps
CPU time 102.66 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:57:24 PM PST 24
Peak memory 200244 kb
Host smart-a10ad278-0cf1-4d80-acef-1aec1006a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850998847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1850998847
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3167073531
Short name T136
Test name
Test status
Simulation time 26168261879 ps
CPU time 38.96 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 01:56:24 PM PST 24
Peak memory 200280 kb
Host smart-e96a1f26-1b29-4b22-85eb-4e8e3dc6e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167073531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3167073531
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3080239062
Short name T449
Test name
Test status
Simulation time 1816946241228 ps
CPU time 715.36 seconds
Started Jan 17 01:55:45 PM PST 24
Finished Jan 17 02:07:41 PM PST 24
Peak memory 200172 kb
Host smart-ebba36e6-3239-4645-8eb0-deba0c06201c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080239062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3080239062
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_loopback.3233742036
Short name T1036
Test name
Test status
Simulation time 5745079660 ps
CPU time 12.82 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 01:55:58 PM PST 24
Peak memory 199272 kb
Host smart-5761bedf-8fac-4679-86af-c651142aa165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233742036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3233742036
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1928966810
Short name T1135
Test name
Test status
Simulation time 10448891130 ps
CPU time 15.61 seconds
Started Jan 17 01:55:45 PM PST 24
Finished Jan 17 01:56:01 PM PST 24
Peak memory 194004 kb
Host smart-3263b390-97d6-4bb9-ac23-44719ff64ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928966810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1928966810
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3572513120
Short name T875
Test name
Test status
Simulation time 26742555134 ps
CPU time 690.27 seconds
Started Jan 17 01:55:42 PM PST 24
Finished Jan 17 02:07:13 PM PST 24
Peak memory 200260 kb
Host smart-b31a6bd2-0102-4463-a48e-38754c329f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572513120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3572513120
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1966804916
Short name T1158
Test name
Test status
Simulation time 3304458861 ps
CPU time 31.32 seconds
Started Jan 17 01:55:43 PM PST 24
Finished Jan 17 01:56:15 PM PST 24
Peak memory 199080 kb
Host smart-e75dd3ee-5830-421c-acad-75ae45bd4cd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966804916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1966804916
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2561125551
Short name T1077
Test name
Test status
Simulation time 108906708287 ps
CPU time 189.52 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:58:51 PM PST 24
Peak memory 199896 kb
Host smart-466de4d8-74a8-4b0f-8d6e-8b9ef8a8ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561125551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2561125551
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.948253557
Short name T796
Test name
Test status
Simulation time 4827523062 ps
CPU time 2.42 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 01:55:48 PM PST 24
Peak memory 195964 kb
Host smart-c8440dd1-1153-4cc8-9cd8-8afcf3a87e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948253557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.948253557
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4217464467
Short name T624
Test name
Test status
Simulation time 672876601 ps
CPU time 2.58 seconds
Started Jan 17 01:55:36 PM PST 24
Finished Jan 17 01:55:41 PM PST 24
Peak memory 198540 kb
Host smart-2b8f1867-e066-4b46-9af4-506bf7c42cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217464467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4217464467
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2205858358
Short name T434
Test name
Test status
Simulation time 7998987555 ps
CPU time 8.7 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 01:55:54 PM PST 24
Peak memory 200176 kb
Host smart-a42126ab-9b57-4654-9dc3-0e31218a8663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205858358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2205858358
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3136393639
Short name T1064
Test name
Test status
Simulation time 125985531495 ps
CPU time 30.84 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 01:56:16 PM PST 24
Peak memory 200204 kb
Host smart-96d1bd40-ca64-4feb-8e95-2ffd67d1ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136393639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3136393639
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4082133868
Short name T153
Test name
Test status
Simulation time 108849858519 ps
CPU time 29.05 seconds
Started Jan 17 02:03:04 PM PST 24
Finished Jan 17 02:03:36 PM PST 24
Peak memory 200236 kb
Host smart-75aa26e7-6780-4f5c-9fde-54262fb394bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082133868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4082133868
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2073887500
Short name T454
Test name
Test status
Simulation time 103050895610 ps
CPU time 346.02 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:08:53 PM PST 24
Peak memory 200184 kb
Host smart-67e26129-48c7-4199-8c35-c39dcecd733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073887500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2073887500
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2566836926
Short name T1016
Test name
Test status
Simulation time 92064936625 ps
CPU time 13.29 seconds
Started Jan 17 02:02:58 PM PST 24
Finished Jan 17 02:03:14 PM PST 24
Peak memory 198308 kb
Host smart-3d721349-8adb-435d-afc7-b3cbfb2c7419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566836926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2566836926
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.397802662
Short name T315
Test name
Test status
Simulation time 128429754302 ps
CPU time 46.53 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:03:53 PM PST 24
Peak memory 200164 kb
Host smart-98482c50-16c3-47d6-a74f-1b62afca2499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397802662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.397802662
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1229769551
Short name T213
Test name
Test status
Simulation time 267891802897 ps
CPU time 31.39 seconds
Started Jan 17 02:03:04 PM PST 24
Finished Jan 17 02:03:37 PM PST 24
Peak memory 200152 kb
Host smart-cb38640a-4788-4c02-b803-d0d8a9fb962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229769551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1229769551
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3492231292
Short name T647
Test name
Test status
Simulation time 52439479375 ps
CPU time 93.69 seconds
Started Jan 17 02:02:59 PM PST 24
Finished Jan 17 02:04:36 PM PST 24
Peak memory 200184 kb
Host smart-87b786c9-3c6c-4835-9900-a4b9fbd90657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492231292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3492231292
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3954924239
Short name T257
Test name
Test status
Simulation time 36249085923 ps
CPU time 28.3 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:03:35 PM PST 24
Peak memory 200256 kb
Host smart-37946800-b0ca-4c8d-8b4d-20ef32494a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954924239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3954924239
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2711505758
Short name T145
Test name
Test status
Simulation time 15059615055 ps
CPU time 7.75 seconds
Started Jan 17 02:02:58 PM PST 24
Finished Jan 17 02:03:09 PM PST 24
Peak memory 199816 kb
Host smart-806e3efb-6319-4cf3-a72a-ebe5eb309f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711505758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2711505758
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1870391109
Short name T141
Test name
Test status
Simulation time 15865432293 ps
CPU time 25.35 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:03:32 PM PST 24
Peak memory 199944 kb
Host smart-59e4e995-c423-4ffe-9956-817cf224237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870391109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1870391109
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4110160535
Short name T769
Test name
Test status
Simulation time 23228960 ps
CPU time 0.56 seconds
Started Jan 17 01:55:52 PM PST 24
Finished Jan 17 01:55:54 PM PST 24
Peak memory 195652 kb
Host smart-50ac51e9-b5e3-4687-99d1-c2e2a4107611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110160535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4110160535
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3124753539
Short name T286
Test name
Test status
Simulation time 143886498673 ps
CPU time 482.76 seconds
Started Jan 17 01:55:38 PM PST 24
Finished Jan 17 02:03:43 PM PST 24
Peak memory 200184 kb
Host smart-71d87da4-dff8-40ad-bfa4-582e021b0b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124753539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3124753539
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2610783722
Short name T677
Test name
Test status
Simulation time 58133801006 ps
CPU time 26.03 seconds
Started Jan 17 01:55:43 PM PST 24
Finished Jan 17 01:56:10 PM PST 24
Peak memory 200320 kb
Host smart-a0f20f4d-182f-4e15-b2cb-6a421511d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610783722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2610783722
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.395873209
Short name T771
Test name
Test status
Simulation time 78394709433 ps
CPU time 99.34 seconds
Started Jan 17 01:55:55 PM PST 24
Finished Jan 17 01:57:35 PM PST 24
Peak memory 200188 kb
Host smart-b2df8ef7-0119-423b-9078-4f39dce42ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395873209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.395873209
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2923606772
Short name T722
Test name
Test status
Simulation time 9411823520 ps
CPU time 9.03 seconds
Started Jan 17 01:55:52 PM PST 24
Finished Jan 17 01:56:03 PM PST 24
Peak memory 199552 kb
Host smart-a28b318a-9b64-4886-80ce-c4327aca9aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923606772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2923606772
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2147162378
Short name T149
Test name
Test status
Simulation time 102282273457 ps
CPU time 63.31 seconds
Started Jan 17 01:55:50 PM PST 24
Finished Jan 17 01:56:56 PM PST 24
Peak memory 208692 kb
Host smart-8c652b4d-fd44-4616-a9df-f36770920dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147162378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2147162378
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.360848738
Short name T447
Test name
Test status
Simulation time 24286922450 ps
CPU time 287.44 seconds
Started Jan 17 01:55:51 PM PST 24
Finished Jan 17 02:00:40 PM PST 24
Peak memory 200196 kb
Host smart-bf073b1a-ec0d-4fd0-9d8d-e2ace9488731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360848738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.360848738
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3515224065
Short name T698
Test name
Test status
Simulation time 1776525207 ps
CPU time 6.43 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 01:55:52 PM PST 24
Peak memory 198372 kb
Host smart-1ddeef15-e2d3-4a15-87e1-5a134ec5e368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515224065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3515224065
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1129811826
Short name T560
Test name
Test status
Simulation time 32654958573 ps
CPU time 59.06 seconds
Started Jan 17 01:55:53 PM PST 24
Finished Jan 17 01:56:53 PM PST 24
Peak memory 199948 kb
Host smart-28017e4a-88da-40c1-9d09-093a6bae8b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129811826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1129811826
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.15716145
Short name T575
Test name
Test status
Simulation time 3865380990 ps
CPU time 1.82 seconds
Started Jan 17 01:55:51 PM PST 24
Finished Jan 17 01:55:55 PM PST 24
Peak memory 195972 kb
Host smart-77c554da-0707-41b7-a7ed-4f729caae1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15716145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.15716145
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2337443344
Short name T630
Test name
Test status
Simulation time 110895441 ps
CPU time 0.92 seconds
Started Jan 17 01:55:39 PM PST 24
Finished Jan 17 01:55:41 PM PST 24
Peak memory 198240 kb
Host smart-9b094b21-90ab-4de3-a6d6-b412247e8061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337443344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2337443344
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1748280920
Short name T81
Test name
Test status
Simulation time 123796800152 ps
CPU time 252.32 seconds
Started Jan 17 01:55:51 PM PST 24
Finished Jan 17 02:00:05 PM PST 24
Peak memory 214352 kb
Host smart-344b5a41-478d-4fef-838f-a2f5a542f288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748280920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1748280920
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2731584663
Short name T933
Test name
Test status
Simulation time 486800803 ps
CPU time 2.18 seconds
Started Jan 17 01:55:54 PM PST 24
Finished Jan 17 01:55:57 PM PST 24
Peak memory 198676 kb
Host smart-9ad83a05-5eda-4841-9291-ae50b0bbe075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731584663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2731584663
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.489541021
Short name T418
Test name
Test status
Simulation time 17886168986 ps
CPU time 9.39 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:55:51 PM PST 24
Peak memory 196740 kb
Host smart-7c22154f-1c71-44f8-80b6-5eeef89f02ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489541021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.489541021
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1327867033
Short name T247
Test name
Test status
Simulation time 33543676276 ps
CPU time 11.99 seconds
Started Jan 17 02:03:02 PM PST 24
Finished Jan 17 02:03:16 PM PST 24
Peak memory 199492 kb
Host smart-469cf08f-5efe-4e2a-815b-bb181c4c4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327867033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1327867033
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1931498548
Short name T749
Test name
Test status
Simulation time 51714994060 ps
CPU time 92.72 seconds
Started Jan 17 02:03:08 PM PST 24
Finished Jan 17 02:04:41 PM PST 24
Peak memory 200224 kb
Host smart-89c41a4c-797a-44ff-bd19-d216650be6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931498548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1931498548
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3502994693
Short name T652
Test name
Test status
Simulation time 208981671540 ps
CPU time 159.2 seconds
Started Jan 17 02:03:06 PM PST 24
Finished Jan 17 02:05:47 PM PST 24
Peak memory 200044 kb
Host smart-d7b9975f-6d74-4d26-9dce-67209abd5e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502994693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3502994693
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.4240328863
Short name T1229
Test name
Test status
Simulation time 43285816440 ps
CPU time 40.38 seconds
Started Jan 17 02:03:08 PM PST 24
Finished Jan 17 02:03:49 PM PST 24
Peak memory 200284 kb
Host smart-f2a7b328-2030-469a-b39e-292dcf5e64f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240328863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4240328863
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.221404187
Short name T162
Test name
Test status
Simulation time 8055917997 ps
CPU time 13.38 seconds
Started Jan 17 02:03:07 PM PST 24
Finished Jan 17 02:03:21 PM PST 24
Peak memory 199696 kb
Host smart-6ed34747-aa50-4eb5-b767-6f2f0c22900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221404187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.221404187
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2359504123
Short name T1106
Test name
Test status
Simulation time 81228715549 ps
CPU time 144.94 seconds
Started Jan 17 02:03:12 PM PST 24
Finished Jan 17 02:05:41 PM PST 24
Peak memory 200280 kb
Host smart-ca8d72a5-6c28-4728-a60a-ffdbf79a8d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359504123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2359504123
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2344529111
Short name T296
Test name
Test status
Simulation time 53454095927 ps
CPU time 83.23 seconds
Started Jan 17 02:03:13 PM PST 24
Finished Jan 17 02:04:40 PM PST 24
Peak memory 199644 kb
Host smart-2337ba9a-b583-42cd-ade3-c762ff90b672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344529111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2344529111
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2271410447
Short name T871
Test name
Test status
Simulation time 13361608 ps
CPU time 0.63 seconds
Started Jan 17 01:55:55 PM PST 24
Finished Jan 17 01:55:56 PM PST 24
Peak memory 195660 kb
Host smart-0716197a-0f29-4c57-ab85-62fb5e6e97d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271410447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2271410447
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3862149383
Short name T705
Test name
Test status
Simulation time 193604481747 ps
CPU time 71.3 seconds
Started Jan 17 01:55:50 PM PST 24
Finished Jan 17 01:57:04 PM PST 24
Peak memory 199364 kb
Host smart-a2bc9ec4-191d-40bc-bc7f-9c29108c4d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862149383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3862149383
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.744335247
Short name T1067
Test name
Test status
Simulation time 42663755595 ps
CPU time 15.91 seconds
Started Jan 17 01:55:53 PM PST 24
Finished Jan 17 01:56:10 PM PST 24
Peak memory 200292 kb
Host smart-4aa30a2b-5e7a-4e2b-b598-5f672b2d7d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744335247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.744335247
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1107941162
Short name T126
Test name
Test status
Simulation time 449075886478 ps
CPU time 428.48 seconds
Started Jan 17 01:55:52 PM PST 24
Finished Jan 17 02:03:02 PM PST 24
Peak memory 200160 kb
Host smart-65c7dd62-2422-444b-9c4c-f2f3053c6d63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107941162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1107941162
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1425214037
Short name T1185
Test name
Test status
Simulation time 73004896520 ps
CPU time 582.91 seconds
Started Jan 17 01:55:58 PM PST 24
Finished Jan 17 02:05:46 PM PST 24
Peak memory 200248 kb
Host smart-e9976e17-19c8-48f0-a11f-58b9f4ca0602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425214037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1425214037
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3249055893
Short name T520
Test name
Test status
Simulation time 1936824995 ps
CPU time 4.27 seconds
Started Jan 17 01:55:51 PM PST 24
Finished Jan 17 01:55:57 PM PST 24
Peak memory 198452 kb
Host smart-0f7a7806-45ef-4188-8e32-e3f1c4b6e52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249055893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3249055893
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3471243139
Short name T1120
Test name
Test status
Simulation time 227758552247 ps
CPU time 55.51 seconds
Started Jan 17 01:55:53 PM PST 24
Finished Jan 17 01:56:49 PM PST 24
Peak memory 199896 kb
Host smart-2ec1072e-e6d1-4d57-a42a-152826a88e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471243139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3471243139
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.936745506
Short name T244
Test name
Test status
Simulation time 18274156278 ps
CPU time 1071.17 seconds
Started Jan 17 01:55:54 PM PST 24
Finished Jan 17 02:13:46 PM PST 24
Peak memory 200144 kb
Host smart-ae342f59-dd95-4fad-8c27-6d471e05535e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936745506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.936745506
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3634117434
Short name T743
Test name
Test status
Simulation time 5531553623 ps
CPU time 26.89 seconds
Started Jan 17 01:55:51 PM PST 24
Finished Jan 17 01:56:20 PM PST 24
Peak memory 199148 kb
Host smart-5c516851-da9d-4710-bfee-43ceaedc759d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3634117434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3634117434
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3719369553
Short name T439
Test name
Test status
Simulation time 42497942876 ps
CPU time 42.22 seconds
Started Jan 17 01:55:50 PM PST 24
Finished Jan 17 01:56:35 PM PST 24
Peak memory 199108 kb
Host smart-0b2c35c5-f0df-40f2-b68d-7176c81832d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719369553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3719369553
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1377488488
Short name T603
Test name
Test status
Simulation time 2154403233 ps
CPU time 2.19 seconds
Started Jan 17 01:55:51 PM PST 24
Finished Jan 17 01:55:55 PM PST 24
Peak memory 195800 kb
Host smart-6963a4e7-4852-4319-bbd5-8eaa8ac51ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377488488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1377488488
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1950589790
Short name T709
Test name
Test status
Simulation time 87059731 ps
CPU time 0.84 seconds
Started Jan 17 01:55:50 PM PST 24
Finished Jan 17 01:55:53 PM PST 24
Peak memory 196824 kb
Host smart-f98bab6f-4228-4d4a-aba3-1cffdf957d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950589790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1950589790
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2935022666
Short name T1111
Test name
Test status
Simulation time 196663156293 ps
CPU time 711.69 seconds
Started Jan 17 01:56:01 PM PST 24
Finished Jan 17 02:07:55 PM PST 24
Peak memory 200196 kb
Host smart-fd13d015-f8d0-4169-be7b-f0bc0d0972fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935022666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2935022666
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3403786181
Short name T1180
Test name
Test status
Simulation time 96351648959 ps
CPU time 418.96 seconds
Started Jan 17 01:56:01 PM PST 24
Finished Jan 17 02:03:02 PM PST 24
Peak memory 216996 kb
Host smart-42c94d73-60ee-47d2-8e92-1c7d7d05cc9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403786181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3403786181
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2313612859
Short name T17
Test name
Test status
Simulation time 2598952550 ps
CPU time 2.5 seconds
Started Jan 17 01:55:53 PM PST 24
Finished Jan 17 01:55:56 PM PST 24
Peak memory 198324 kb
Host smart-55b97aee-9b7c-4fb1-ba99-023718204ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313612859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2313612859
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3881929839
Short name T759
Test name
Test status
Simulation time 291625156978 ps
CPU time 160.28 seconds
Started Jan 17 01:55:49 PM PST 24
Finished Jan 17 01:58:33 PM PST 24
Peak memory 200256 kb
Host smart-ce76cd61-98c8-43be-9c6f-d6ca849a010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881929839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3881929839
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4057680157
Short name T148
Test name
Test status
Simulation time 186873949406 ps
CPU time 19.5 seconds
Started Jan 17 02:03:12 PM PST 24
Finished Jan 17 02:03:36 PM PST 24
Peak memory 199976 kb
Host smart-6f887eee-34b7-4742-b686-f8b847b81278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057680157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4057680157
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1402828042
Short name T196
Test name
Test status
Simulation time 48260593388 ps
CPU time 38.65 seconds
Started Jan 17 02:03:13 PM PST 24
Finished Jan 17 02:03:55 PM PST 24
Peak memory 199188 kb
Host smart-90e7ddc4-3893-4a8b-9241-58c6868d1b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402828042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1402828042
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2840988018
Short name T324
Test name
Test status
Simulation time 36913300247 ps
CPU time 72.34 seconds
Started Jan 17 02:03:11 PM PST 24
Finished Jan 17 02:04:28 PM PST 24
Peak memory 200196 kb
Host smart-e90dd787-9357-4b6e-948a-d490d5c52b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840988018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2840988018
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.325538621
Short name T994
Test name
Test status
Simulation time 36894829639 ps
CPU time 15.93 seconds
Started Jan 17 02:03:12 PM PST 24
Finished Jan 17 02:03:33 PM PST 24
Peak memory 200060 kb
Host smart-3d8d0a0b-8e87-4512-b1db-8bf092bedc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325538621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.325538621
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1751256293
Short name T240
Test name
Test status
Simulation time 57926393298 ps
CPU time 22.42 seconds
Started Jan 17 02:03:16 PM PST 24
Finished Jan 17 02:03:41 PM PST 24
Peak memory 200064 kb
Host smart-085d3a8c-f293-4139-9a02-c34bb75040b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751256293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1751256293
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2372043503
Short name T241
Test name
Test status
Simulation time 17350870104 ps
CPU time 31.26 seconds
Started Jan 17 02:03:17 PM PST 24
Finished Jan 17 02:03:50 PM PST 24
Peak memory 200216 kb
Host smart-f1390663-bc20-4d7d-a5c2-0150d4df84f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372043503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2372043503
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.4261970675
Short name T1053
Test name
Test status
Simulation time 16966797302 ps
CPU time 29.36 seconds
Started Jan 17 02:03:16 PM PST 24
Finished Jan 17 02:03:47 PM PST 24
Peak memory 200244 kb
Host smart-c8cdecd4-acfb-4b9d-b124-a5b79e15e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261970675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.4261970675
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3363804679
Short name T548
Test name
Test status
Simulation time 42617346334 ps
CPU time 18.46 seconds
Started Jan 17 02:03:18 PM PST 24
Finished Jan 17 02:03:38 PM PST 24
Peak memory 199428 kb
Host smart-86de62b6-48f8-432a-bbde-76b245d76fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363804679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3363804679
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.739693763
Short name T248
Test name
Test status
Simulation time 97679394391 ps
CPU time 44.77 seconds
Started Jan 17 02:03:24 PM PST 24
Finished Jan 17 02:04:09 PM PST 24
Peak memory 200200 kb
Host smart-d4a25c9e-2d61-493e-8bb6-2c27db76fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739693763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.739693763
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2999530288
Short name T498
Test name
Test status
Simulation time 121705985 ps
CPU time 0.54 seconds
Started Jan 17 01:56:03 PM PST 24
Finished Jan 17 01:56:05 PM PST 24
Peak memory 194620 kb
Host smart-1f852605-6696-46a3-b2da-06c0c2e0e4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999530288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2999530288
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.450330426
Short name T666
Test name
Test status
Simulation time 279097954888 ps
CPU time 384.93 seconds
Started Jan 17 01:55:56 PM PST 24
Finished Jan 17 02:02:24 PM PST 24
Peak memory 200272 kb
Host smart-7d85ee7e-112c-4d02-93df-56a0f910577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450330426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.450330426
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_intr.1927299710
Short name T987
Test name
Test status
Simulation time 43574279072 ps
CPU time 23.14 seconds
Started Jan 17 01:55:56 PM PST 24
Finished Jan 17 01:56:25 PM PST 24
Peak memory 200216 kb
Host smart-4462a9fc-f62a-488e-817e-68bbf4823ba4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927299710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1927299710
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3905099360
Short name T113
Test name
Test status
Simulation time 123776875746 ps
CPU time 309.12 seconds
Started Jan 17 01:56:03 PM PST 24
Finished Jan 17 02:01:13 PM PST 24
Peak memory 200228 kb
Host smart-2db6bb8f-ea67-4047-b3bc-764b5eca96a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905099360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3905099360
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3356423725
Short name T718
Test name
Test status
Simulation time 8905477171 ps
CPU time 5.25 seconds
Started Jan 17 01:55:59 PM PST 24
Finished Jan 17 01:56:08 PM PST 24
Peak memory 200244 kb
Host smart-179a7d27-c3ce-4e33-acd3-c9155b550575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356423725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3356423725
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3622629856
Short name T557
Test name
Test status
Simulation time 12760120115 ps
CPU time 25.09 seconds
Started Jan 17 01:55:59 PM PST 24
Finished Jan 17 01:56:28 PM PST 24
Peak memory 198660 kb
Host smart-1c438e51-eb06-412f-ba9d-c5b1ba7633ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622629856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3622629856
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1261035850
Short name T673
Test name
Test status
Simulation time 29878851450 ps
CPU time 483.98 seconds
Started Jan 17 01:56:02 PM PST 24
Finished Jan 17 02:04:08 PM PST 24
Peak memory 200208 kb
Host smart-3caae159-bbf0-4825-99ff-df6076b26981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1261035850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1261035850
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4063067469
Short name T725
Test name
Test status
Simulation time 3082107702 ps
CPU time 12.77 seconds
Started Jan 17 01:55:56 PM PST 24
Finished Jan 17 01:56:14 PM PST 24
Peak memory 198940 kb
Host smart-3d315db1-e49a-4798-a32e-fd8b874c3fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063067469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4063067469
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2029084070
Short name T1181
Test name
Test status
Simulation time 6462777700 ps
CPU time 1.25 seconds
Started Jan 17 01:55:59 PM PST 24
Finished Jan 17 01:56:05 PM PST 24
Peak memory 196012 kb
Host smart-cca0939f-c1f7-409c-bc92-40b24bce9cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029084070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2029084070
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.75136640
Short name T1196
Test name
Test status
Simulation time 302730380 ps
CPU time 1.04 seconds
Started Jan 17 01:55:56 PM PST 24
Finished Jan 17 01:56:02 PM PST 24
Peak memory 198160 kb
Host smart-dfa6da03-1211-4562-a4d3-015a20e15b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75136640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.75136640
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.956601050
Short name T1155
Test name
Test status
Simulation time 2588350412607 ps
CPU time 1250.13 seconds
Started Jan 17 01:56:03 PM PST 24
Finished Jan 17 02:16:55 PM PST 24
Peak memory 200524 kb
Host smart-01c4f1c8-dc89-40f9-8c20-c2514ff06d34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956601050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.956601050
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.891306811
Short name T960
Test name
Test status
Simulation time 171062091713 ps
CPU time 452.13 seconds
Started Jan 17 01:56:01 PM PST 24
Finished Jan 17 02:03:36 PM PST 24
Peak memory 225112 kb
Host smart-00b409f5-1403-483a-b568-19080d9169d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891306811 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.891306811
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.4149205246
Short name T1056
Test name
Test status
Simulation time 682967975 ps
CPU time 2.42 seconds
Started Jan 17 01:55:54 PM PST 24
Finished Jan 17 01:55:57 PM PST 24
Peak memory 200168 kb
Host smart-5a4ba1c6-0938-4380-98bf-569ebbc4794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149205246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4149205246
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3488395887
Short name T625
Test name
Test status
Simulation time 60578001509 ps
CPU time 64.35 seconds
Started Jan 17 01:56:01 PM PST 24
Finished Jan 17 01:57:08 PM PST 24
Peak memory 200168 kb
Host smart-ee2cf519-61b2-4059-b65d-e9a7ff5b25e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488395887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3488395887
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2135882457
Short name T1156
Test name
Test status
Simulation time 76466952172 ps
CPU time 35.28 seconds
Started Jan 17 02:03:24 PM PST 24
Finished Jan 17 02:04:00 PM PST 24
Peak memory 200284 kb
Host smart-c812ee35-763d-4071-89e9-7b50fef59fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135882457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2135882457
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2405479342
Short name T615
Test name
Test status
Simulation time 23174385560 ps
CPU time 42.39 seconds
Started Jan 17 02:03:26 PM PST 24
Finished Jan 17 02:04:09 PM PST 24
Peak memory 199872 kb
Host smart-bb36ebf7-1da8-4d1f-8c33-09c391d47061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405479342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2405479342
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.777670379
Short name T1058
Test name
Test status
Simulation time 21482485635 ps
CPU time 35.28 seconds
Started Jan 17 02:03:26 PM PST 24
Finished Jan 17 02:04:02 PM PST 24
Peak memory 199852 kb
Host smart-39a42942-d31f-439a-9520-c48cc5f1a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777670379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.777670379
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1957917442
Short name T133
Test name
Test status
Simulation time 42646932709 ps
CPU time 20.04 seconds
Started Jan 17 02:03:23 PM PST 24
Finished Jan 17 02:03:44 PM PST 24
Peak memory 200244 kb
Host smart-d6e5ff03-6bd6-4883-a1ce-b2e7692837a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957917442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1957917442
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1381414101
Short name T232
Test name
Test status
Simulation time 9135216524 ps
CPU time 16.74 seconds
Started Jan 17 02:03:32 PM PST 24
Finished Jan 17 02:03:49 PM PST 24
Peak memory 200220 kb
Host smart-bb438a6a-4894-4670-9969-aec13a7a9ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381414101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1381414101
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1629879926
Short name T176
Test name
Test status
Simulation time 61692754238 ps
CPU time 88.28 seconds
Started Jan 17 02:03:21 PM PST 24
Finished Jan 17 02:04:52 PM PST 24
Peak memory 200288 kb
Host smart-c89ef8aa-fbff-4b28-8a8e-08805ea51bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629879926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1629879926
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.779626739
Short name T1152
Test name
Test status
Simulation time 15841873026 ps
CPU time 23.46 seconds
Started Jan 17 02:03:20 PM PST 24
Finished Jan 17 02:03:46 PM PST 24
Peak memory 199732 kb
Host smart-d9d4a62d-feb1-428b-92c9-3fbb20afc153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779626739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.779626739
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.201154497
Short name T1023
Test name
Test status
Simulation time 209926120086 ps
CPU time 135.44 seconds
Started Jan 17 02:03:28 PM PST 24
Finished Jan 17 02:05:47 PM PST 24
Peak memory 199904 kb
Host smart-91f448a2-1ec0-4784-874a-ba657e9fdd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201154497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.201154497
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1965298752
Short name T541
Test name
Test status
Simulation time 18139445 ps
CPU time 0.55 seconds
Started Jan 17 01:56:11 PM PST 24
Finished Jan 17 01:56:12 PM PST 24
Peak memory 195584 kb
Host smart-4b09f1d1-71d6-455e-a98e-64097304b692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965298752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1965298752
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3936779222
Short name T820
Test name
Test status
Simulation time 70573688021 ps
CPU time 120.05 seconds
Started Jan 17 01:56:06 PM PST 24
Finished Jan 17 01:58:07 PM PST 24
Peak memory 200220 kb
Host smart-07bc94f7-2049-4728-9f2f-d1699551d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936779222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3936779222
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2109265185
Short name T1132
Test name
Test status
Simulation time 24721970330 ps
CPU time 35.25 seconds
Started Jan 17 01:56:05 PM PST 24
Finished Jan 17 01:56:41 PM PST 24
Peak memory 200232 kb
Host smart-8d33b6cf-a44a-4586-8303-d0dc43839df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109265185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2109265185
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3726984212
Short name T693
Test name
Test status
Simulation time 25811803888 ps
CPU time 73.96 seconds
Started Jan 17 01:56:02 PM PST 24
Finished Jan 17 01:57:18 PM PST 24
Peak memory 200212 kb
Host smart-b5db6a33-ad2d-4ce0-a545-ae5710d2ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726984212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3726984212
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.4220812393
Short name T1047
Test name
Test status
Simulation time 1233694406927 ps
CPU time 1602.48 seconds
Started Jan 17 01:56:02 PM PST 24
Finished Jan 17 02:22:46 PM PST 24
Peak memory 200272 kb
Host smart-c88fc426-83fd-43b1-8720-f50dd14aa7a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220812393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4220812393
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2540455270
Short name T511
Test name
Test status
Simulation time 75890891715 ps
CPU time 126.47 seconds
Started Jan 17 01:56:11 PM PST 24
Finished Jan 17 01:58:18 PM PST 24
Peak memory 200220 kb
Host smart-003bc74f-0852-49e1-baa5-b3cc012bc1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540455270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2540455270
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3863336399
Short name T954
Test name
Test status
Simulation time 2901663277 ps
CPU time 3.6 seconds
Started Jan 17 01:56:03 PM PST 24
Finished Jan 17 01:56:09 PM PST 24
Peak memory 197628 kb
Host smart-acecdc1a-8c7d-48cf-8a0d-d3bf7d3df77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863336399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3863336399
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1931297028
Short name T1115
Test name
Test status
Simulation time 93111262892 ps
CPU time 83.98 seconds
Started Jan 17 01:56:03 PM PST 24
Finished Jan 17 01:57:29 PM PST 24
Peak memory 200052 kb
Host smart-bc54e63b-c389-49f3-bfb6-8f42e2b1c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931297028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1931297028
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1395005449
Short name T545
Test name
Test status
Simulation time 18839071627 ps
CPU time 846.19 seconds
Started Jan 17 01:56:13 PM PST 24
Finished Jan 17 02:10:19 PM PST 24
Peak memory 200260 kb
Host smart-dd50d74c-c219-42b5-8634-db7617aba8c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395005449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1395005449
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.876841184
Short name T668
Test name
Test status
Simulation time 2219776942 ps
CPU time 10.92 seconds
Started Jan 17 01:56:02 PM PST 24
Finished Jan 17 01:56:15 PM PST 24
Peak memory 197980 kb
Host smart-f80933fc-512f-4fb2-b88d-98855804a0b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876841184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.876841184
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.248782507
Short name T908
Test name
Test status
Simulation time 178003920128 ps
CPU time 127.59 seconds
Started Jan 17 01:56:05 PM PST 24
Finished Jan 17 01:58:13 PM PST 24
Peak memory 200280 kb
Host smart-c359156c-bec4-4249-b552-43061932c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248782507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.248782507
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1110789369
Short name T961
Test name
Test status
Simulation time 1925799056 ps
CPU time 4 seconds
Started Jan 17 01:56:02 PM PST 24
Finished Jan 17 01:56:08 PM PST 24
Peak memory 195564 kb
Host smart-f56b3bf5-7968-42b8-84e0-e7c93081d4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110789369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1110789369
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2672707981
Short name T937
Test name
Test status
Simulation time 106111218 ps
CPU time 0.91 seconds
Started Jan 17 01:56:05 PM PST 24
Finished Jan 17 01:56:07 PM PST 24
Peak memory 196972 kb
Host smart-da1ddac0-d4c9-4cdf-8d74-8e2e59cc457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672707981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2672707981
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3992876316
Short name T442
Test name
Test status
Simulation time 5201156921 ps
CPU time 4.53 seconds
Started Jan 17 01:56:12 PM PST 24
Finished Jan 17 01:56:18 PM PST 24
Peak memory 200208 kb
Host smart-3b48e2e5-e5e0-492e-b0b1-e88a2bbe888a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992876316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3992876316
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2903714092
Short name T738
Test name
Test status
Simulation time 64520901776 ps
CPU time 388.61 seconds
Started Jan 17 01:56:13 PM PST 24
Finished Jan 17 02:02:42 PM PST 24
Peak memory 209980 kb
Host smart-620eaa18-2336-4289-8a1c-94726fc99f89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903714092 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2903714092
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.2204834680
Short name T642
Test name
Test status
Simulation time 1336116911 ps
CPU time 1.74 seconds
Started Jan 17 01:56:09 PM PST 24
Finished Jan 17 01:56:12 PM PST 24
Peak memory 198360 kb
Host smart-a7590339-3cf9-45ee-9d18-2662331fdcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204834680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.2204834680
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3137691570
Short name T825
Test name
Test status
Simulation time 103407467027 ps
CPU time 74.11 seconds
Started Jan 17 02:03:28 PM PST 24
Finished Jan 17 02:04:45 PM PST 24
Peak memory 200236 kb
Host smart-7bc22fa4-4196-45c0-bc63-53cd7e9ae598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137691570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3137691570
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.47362363
Short name T169
Test name
Test status
Simulation time 20930477318 ps
CPU time 36.7 seconds
Started Jan 17 02:03:27 PM PST 24
Finished Jan 17 02:04:04 PM PST 24
Peak memory 200424 kb
Host smart-5f98a7b1-8068-4315-abc6-09ade31fb4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47362363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.47362363
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4204158245
Short name T283
Test name
Test status
Simulation time 61054029290 ps
CPU time 26.17 seconds
Started Jan 17 02:03:27 PM PST 24
Finished Jan 17 02:03:54 PM PST 24
Peak memory 200220 kb
Host smart-9998fd75-204e-4c93-993f-e276cc4a2a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204158245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4204158245
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3293214159
Short name T685
Test name
Test status
Simulation time 128063041581 ps
CPU time 70.52 seconds
Started Jan 17 02:03:29 PM PST 24
Finished Jan 17 02:04:42 PM PST 24
Peak memory 199944 kb
Host smart-35e7aef2-2d7b-429d-a0c6-2006ee9ab8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293214159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3293214159
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.4213977899
Short name T1055
Test name
Test status
Simulation time 36376586052 ps
CPU time 18.81 seconds
Started Jan 17 02:03:26 PM PST 24
Finished Jan 17 02:03:46 PM PST 24
Peak memory 200288 kb
Host smart-eb15d7b1-91d5-40a5-bdf5-9b5dde9c4376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213977899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4213977899
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4200896976
Short name T331
Test name
Test status
Simulation time 66473106775 ps
CPU time 30.31 seconds
Started Jan 17 02:03:28 PM PST 24
Finished Jan 17 02:04:02 PM PST 24
Peak memory 200272 kb
Host smart-3ec12094-c4f5-4dbe-ad83-663d490baec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200896976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4200896976
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1766184474
Short name T1224
Test name
Test status
Simulation time 12695335 ps
CPU time 0.54 seconds
Started Jan 17 01:56:19 PM PST 24
Finished Jan 17 01:56:21 PM PST 24
Peak memory 195656 kb
Host smart-1f062866-ffff-44c4-842a-3a38fef45da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766184474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1766184474
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1617980772
Short name T899
Test name
Test status
Simulation time 60444757482 ps
CPU time 26.26 seconds
Started Jan 17 01:56:11 PM PST 24
Finished Jan 17 01:56:38 PM PST 24
Peak memory 200100 kb
Host smart-3a29e3d3-66b4-4401-8e2a-c36d13107463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617980772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1617980772
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3546538112
Short name T178
Test name
Test status
Simulation time 258194925306 ps
CPU time 89.59 seconds
Started Jan 17 01:56:12 PM PST 24
Finished Jan 17 01:57:42 PM PST 24
Peak memory 200172 kb
Host smart-aa76aa5e-d5a2-4ee6-adf0-aed81140f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546538112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3546538112
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1808465682
Short name T739
Test name
Test status
Simulation time 43068780229 ps
CPU time 34.2 seconds
Started Jan 17 01:56:13 PM PST 24
Finished Jan 17 01:56:47 PM PST 24
Peak memory 200204 kb
Host smart-708d64a7-a96f-4aa5-bdfc-193970786206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808465682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1808465682
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1412895505
Short name T730
Test name
Test status
Simulation time 356025679813 ps
CPU time 310.11 seconds
Started Jan 17 01:56:13 PM PST 24
Finished Jan 17 02:01:24 PM PST 24
Peak memory 200252 kb
Host smart-4a5b4438-bd40-4bb6-aa8b-5ce11f3f89c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412895505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1412895505
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1103019268
Short name T1043
Test name
Test status
Simulation time 272169593580 ps
CPU time 172.43 seconds
Started Jan 17 01:56:21 PM PST 24
Finished Jan 17 01:59:14 PM PST 24
Peak memory 200164 kb
Host smart-ed3856b9-2929-48ff-9f4b-8a560fd8de29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103019268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1103019268
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3592214102
Short name T1187
Test name
Test status
Simulation time 4102309116 ps
CPU time 6.27 seconds
Started Jan 17 01:56:21 PM PST 24
Finished Jan 17 01:56:28 PM PST 24
Peak memory 198644 kb
Host smart-dc83f110-b67b-4aa2-88fa-eac75a4cc50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592214102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3592214102
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1802478173
Short name T867
Test name
Test status
Simulation time 40007890396 ps
CPU time 64.58 seconds
Started Jan 17 01:56:12 PM PST 24
Finished Jan 17 01:57:18 PM PST 24
Peak memory 199696 kb
Host smart-89f5b4b5-7a7c-4c81-a11b-cbc6b5e58a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802478173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1802478173
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1552213595
Short name T740
Test name
Test status
Simulation time 17798392680 ps
CPU time 468.45 seconds
Started Jan 17 01:56:19 PM PST 24
Finished Jan 17 02:04:08 PM PST 24
Peak memory 200172 kb
Host smart-78426ba0-ae9d-4411-971d-7cfcdfa0ac38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552213595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1552213595
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.428858214
Short name T785
Test name
Test status
Simulation time 2912026371 ps
CPU time 28.33 seconds
Started Jan 17 01:56:12 PM PST 24
Finished Jan 17 01:56:41 PM PST 24
Peak memory 198860 kb
Host smart-3e6e898f-cf32-43bd-9821-30eaf250c44e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428858214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.428858214
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.611253693
Short name T1090
Test name
Test status
Simulation time 50341305152 ps
CPU time 88.27 seconds
Started Jan 17 01:56:13 PM PST 24
Finished Jan 17 01:57:42 PM PST 24
Peak memory 200016 kb
Host smart-bff053ea-4f5e-472a-8755-b6c22a71deed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611253693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.611253693
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3985271184
Short name T561
Test name
Test status
Simulation time 41469041655 ps
CPU time 19.21 seconds
Started Jan 17 01:56:14 PM PST 24
Finished Jan 17 01:56:34 PM PST 24
Peak memory 195808 kb
Host smart-31de46e8-cfb8-4078-849a-49a754c13931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985271184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3985271184
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3182300284
Short name T732
Test name
Test status
Simulation time 6039391644 ps
CPU time 9.03 seconds
Started Jan 17 01:56:12 PM PST 24
Finished Jan 17 01:56:22 PM PST 24
Peak memory 199712 kb
Host smart-231299a7-8e9c-407a-832d-633a66a6dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182300284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3182300284
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2687621111
Short name T267
Test name
Test status
Simulation time 275447143660 ps
CPU time 129.45 seconds
Started Jan 17 01:56:18 PM PST 24
Finished Jan 17 01:58:28 PM PST 24
Peak memory 208860 kb
Host smart-da9a641d-8a88-4646-a043-7d80503b2fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687621111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2687621111
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2034020417
Short name T568
Test name
Test status
Simulation time 1156436390 ps
CPU time 3.06 seconds
Started Jan 17 01:56:12 PM PST 24
Finished Jan 17 01:56:16 PM PST 24
Peak memory 198332 kb
Host smart-c5c966d1-413a-45b4-bf4a-c0f1881c8425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034020417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2034020417
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.751889178
Short name T997
Test name
Test status
Simulation time 116985924453 ps
CPU time 158.46 seconds
Started Jan 17 01:56:16 PM PST 24
Finished Jan 17 01:58:55 PM PST 24
Peak memory 200204 kb
Host smart-50f99f4f-b1fb-4fbe-b27f-8a4df395955a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751889178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.751889178
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3693717971
Short name T578
Test name
Test status
Simulation time 30561769073 ps
CPU time 30.88 seconds
Started Jan 17 02:03:29 PM PST 24
Finished Jan 17 02:04:02 PM PST 24
Peak memory 200232 kb
Host smart-7c91e050-2fc7-49d3-b571-08640927c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693717971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3693717971
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2719680029
Short name T260
Test name
Test status
Simulation time 44618768373 ps
CPU time 38.87 seconds
Started Jan 17 02:03:29 PM PST 24
Finished Jan 17 02:04:10 PM PST 24
Peak memory 200264 kb
Host smart-12a20316-80e0-421b-8dc2-30d86dfe696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719680029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2719680029
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.280008745
Short name T556
Test name
Test status
Simulation time 77469607179 ps
CPU time 294.45 seconds
Started Jan 17 02:03:33 PM PST 24
Finished Jan 17 02:08:29 PM PST 24
Peak memory 200212 kb
Host smart-bee9e773-0d53-4cff-8a6b-a3ccf9ec1cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280008745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.280008745
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.807510413
Short name T695
Test name
Test status
Simulation time 34484287537 ps
CPU time 19.29 seconds
Started Jan 17 02:03:35 PM PST 24
Finished Jan 17 02:03:55 PM PST 24
Peak memory 200276 kb
Host smart-a6bbdccc-feef-478e-97f1-27249abeed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807510413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.807510413
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3940456900
Short name T387
Test name
Test status
Simulation time 77064491676 ps
CPU time 35.66 seconds
Started Jan 17 02:03:32 PM PST 24
Finished Jan 17 02:04:09 PM PST 24
Peak memory 200276 kb
Host smart-11234e3b-2a93-4086-919a-c486b8c4be62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940456900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3940456900
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3526962592
Short name T369
Test name
Test status
Simulation time 19188511547 ps
CPU time 8.51 seconds
Started Jan 17 02:03:40 PM PST 24
Finished Jan 17 02:03:50 PM PST 24
Peak memory 200160 kb
Host smart-6ea6a592-2cbe-4c61-8f4e-4536f8a0b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526962592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3526962592
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.141595093
Short name T976
Test name
Test status
Simulation time 36933529 ps
CPU time 0.56 seconds
Started Jan 17 01:56:33 PM PST 24
Finished Jan 17 01:56:48 PM PST 24
Peak memory 195620 kb
Host smart-0dbb0a45-47a9-4f1a-80e5-96967bc2541c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141595093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.141595093
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4234784575
Short name T697
Test name
Test status
Simulation time 30794867564 ps
CPU time 28.43 seconds
Started Jan 17 01:56:22 PM PST 24
Finished Jan 17 01:56:51 PM PST 24
Peak memory 200224 kb
Host smart-9a46abdc-ba71-4217-9fe6-a4746f99502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234784575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4234784575
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2526345180
Short name T907
Test name
Test status
Simulation time 116586863551 ps
CPU time 25.92 seconds
Started Jan 17 01:56:21 PM PST 24
Finished Jan 17 01:56:48 PM PST 24
Peak memory 199276 kb
Host smart-83aadc46-93f3-4693-a2c6-030eeb8e3f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526345180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2526345180
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.3071929507
Short name T822
Test name
Test status
Simulation time 1088812027216 ps
CPU time 1934.55 seconds
Started Jan 17 01:56:19 PM PST 24
Finished Jan 17 02:28:34 PM PST 24
Peak memory 199824 kb
Host smart-7cbd497a-ec83-49b2-a969-04c09374d3e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071929507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3071929507
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2513630227
Short name T912
Test name
Test status
Simulation time 123455029553 ps
CPU time 329.15 seconds
Started Jan 17 01:56:33 PM PST 24
Finished Jan 17 02:02:17 PM PST 24
Peak memory 200200 kb
Host smart-1fa6c59c-748e-4e63-b03a-db0f62b77d68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513630227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2513630227
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.95819813
Short name T905
Test name
Test status
Simulation time 5283543168 ps
CPU time 9.52 seconds
Started Jan 17 01:56:20 PM PST 24
Finished Jan 17 01:56:30 PM PST 24
Peak memory 198668 kb
Host smart-7164132e-553a-4117-9b0f-0add5965760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95819813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.95819813
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.391734425
Short name T111
Test name
Test status
Simulation time 67829460805 ps
CPU time 63.7 seconds
Started Jan 17 01:56:21 PM PST 24
Finished Jan 17 01:57:25 PM PST 24
Peak memory 200152 kb
Host smart-de9f1cb2-70b1-4615-b8c3-8217180e63f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391734425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.391734425
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3023949141
Short name T1223
Test name
Test status
Simulation time 14992059827 ps
CPU time 843.04 seconds
Started Jan 17 01:56:35 PM PST 24
Finished Jan 17 02:10:50 PM PST 24
Peak memory 200180 kb
Host smart-ed702ea0-ac29-4b85-8cd1-ebc03aecb1bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023949141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3023949141
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1412515420
Short name T924
Test name
Test status
Simulation time 4420137795 ps
CPU time 37.15 seconds
Started Jan 17 01:56:20 PM PST 24
Finished Jan 17 01:56:58 PM PST 24
Peak memory 198524 kb
Host smart-797a8874-685f-488f-b527-dcdfc2d39a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412515420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1412515420
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1856343409
Short name T721
Test name
Test status
Simulation time 60823653568 ps
CPU time 22.44 seconds
Started Jan 17 01:56:20 PM PST 24
Finished Jan 17 01:56:43 PM PST 24
Peak memory 200192 kb
Host smart-126f01d2-5156-4ce6-80cc-ab8b515bc323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856343409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1856343409
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3009270746
Short name T529
Test name
Test status
Simulation time 2204154381 ps
CPU time 1.55 seconds
Started Jan 17 01:56:22 PM PST 24
Finished Jan 17 01:56:24 PM PST 24
Peak memory 195752 kb
Host smart-c5be2578-df87-406d-8566-86a39867d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009270746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3009270746
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2279798761
Short name T714
Test name
Test status
Simulation time 649394794 ps
CPU time 2.28 seconds
Started Jan 17 01:56:19 PM PST 24
Finished Jan 17 01:56:22 PM PST 24
Peak memory 198536 kb
Host smart-92519373-8778-4d25-8d8f-7e74d0ccd7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279798761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2279798761
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2758362827
Short name T1232
Test name
Test status
Simulation time 172198819244 ps
CPU time 665.56 seconds
Started Jan 17 01:56:32 PM PST 24
Finished Jan 17 02:07:53 PM PST 24
Peak memory 200208 kb
Host smart-aee19922-f9bd-434b-aead-334392efa3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758362827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2758362827
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.888216179
Short name T1150
Test name
Test status
Simulation time 43047401589 ps
CPU time 682.29 seconds
Started Jan 17 01:56:32 PM PST 24
Finished Jan 17 02:08:08 PM PST 24
Peak memory 210256 kb
Host smart-93b23d5f-dd63-4d85-91ca-21cb940313ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888216179 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.888216179
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.15094107
Short name T889
Test name
Test status
Simulation time 1921754235 ps
CPU time 1.86 seconds
Started Jan 17 01:56:24 PM PST 24
Finished Jan 17 01:56:26 PM PST 24
Peak memory 198416 kb
Host smart-81ea4dad-5f96-4e21-b010-b931f0e45e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15094107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.15094107
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3594770598
Short name T830
Test name
Test status
Simulation time 55636531180 ps
CPU time 98.88 seconds
Started Jan 17 01:56:24 PM PST 24
Finished Jan 17 01:58:03 PM PST 24
Peak memory 200208 kb
Host smart-5e2ec535-baa3-45c8-af4c-9fed4c377f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594770598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3594770598
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.4042780742
Short name T1079
Test name
Test status
Simulation time 55450729382 ps
CPU time 89.38 seconds
Started Jan 17 02:03:41 PM PST 24
Finished Jan 17 02:05:11 PM PST 24
Peak memory 200176 kb
Host smart-fc1da546-b252-4ad4-b457-adad7ecb9e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042780742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4042780742
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.558383687
Short name T342
Test name
Test status
Simulation time 20150941451 ps
CPU time 37.13 seconds
Started Jan 17 02:03:40 PM PST 24
Finished Jan 17 02:04:18 PM PST 24
Peak memory 200104 kb
Host smart-edd4aca7-e085-4c6b-8649-b663e9d6a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558383687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.558383687
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3890326045
Short name T285
Test name
Test status
Simulation time 100769765239 ps
CPU time 80.85 seconds
Started Jan 17 02:03:58 PM PST 24
Finished Jan 17 02:05:27 PM PST 24
Peak memory 200096 kb
Host smart-fb0fe93e-1100-4deb-892f-36fa18c0477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890326045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3890326045
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1442092574
Short name T973
Test name
Test status
Simulation time 34136278360 ps
CPU time 50.74 seconds
Started Jan 17 02:03:51 PM PST 24
Finished Jan 17 02:04:46 PM PST 24
Peak memory 200224 kb
Host smart-56e6ce7e-0d2c-405c-b862-1d5b778ed8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442092574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1442092574
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2179337071
Short name T236
Test name
Test status
Simulation time 15077036188 ps
CPU time 6.99 seconds
Started Jan 17 02:03:52 PM PST 24
Finished Jan 17 02:04:02 PM PST 24
Peak memory 199772 kb
Host smart-94e2f497-1a6e-4a8d-a23b-338959e09633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179337071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2179337071
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3489243144
Short name T175
Test name
Test status
Simulation time 93718209407 ps
CPU time 85.19 seconds
Started Jan 17 02:03:59 PM PST 24
Finished Jan 17 02:05:31 PM PST 24
Peak memory 200212 kb
Host smart-7691eed8-6db4-4218-af4d-f8e00c3e790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489243144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3489243144
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2744055923
Short name T694
Test name
Test status
Simulation time 18006891379 ps
CPU time 33.51 seconds
Started Jan 17 02:03:49 PM PST 24
Finished Jan 17 02:04:26 PM PST 24
Peak memory 200232 kb
Host smart-b57fb98e-4e5f-426e-949c-dbd5afcb67ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744055923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2744055923
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2341560978
Short name T775
Test name
Test status
Simulation time 45556145 ps
CPU time 0.59 seconds
Started Jan 17 01:56:36 PM PST 24
Finished Jan 17 01:56:48 PM PST 24
Peak memory 195636 kb
Host smart-c7578bef-f8f7-4f4e-b4e3-6ea3c1a56081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341560978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2341560978
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3344904876
Short name T1215
Test name
Test status
Simulation time 212435619593 ps
CPU time 85.75 seconds
Started Jan 17 01:56:33 PM PST 24
Finished Jan 17 01:58:13 PM PST 24
Peak memory 200220 kb
Host smart-fd4dc906-4515-4689-aa6e-da732f5a1607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344904876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3344904876
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.482068802
Short name T1203
Test name
Test status
Simulation time 110496180601 ps
CPU time 38.53 seconds
Started Jan 17 01:56:33 PM PST 24
Finished Jan 17 01:57:26 PM PST 24
Peak memory 200248 kb
Host smart-f0bcad73-3fe0-4b2b-aa8a-3a92b67f2184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482068802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.482068802
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.908902842
Short name T1228
Test name
Test status
Simulation time 33111018942 ps
CPU time 28.46 seconds
Started Jan 17 01:56:32 PM PST 24
Finished Jan 17 01:57:15 PM PST 24
Peak memory 200104 kb
Host smart-123ecc31-ae94-44ce-a54f-ecb7f5d3552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908902842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.908902842
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3123802880
Short name T457
Test name
Test status
Simulation time 994501644870 ps
CPU time 1636.83 seconds
Started Jan 17 01:56:35 PM PST 24
Finished Jan 17 02:24:04 PM PST 24
Peak memory 198364 kb
Host smart-57e8987c-965c-47ce-b087-0b342d5724d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123802880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3123802880
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2136336653
Short name T608
Test name
Test status
Simulation time 187414633552 ps
CPU time 183.03 seconds
Started Jan 17 01:56:35 PM PST 24
Finished Jan 17 01:59:51 PM PST 24
Peak memory 200268 kb
Host smart-0c003eaf-8fc8-49f1-b861-8dbec60a2940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136336653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2136336653
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2965770963
Short name T672
Test name
Test status
Simulation time 65460996386 ps
CPU time 115.71 seconds
Started Jan 17 01:56:35 PM PST 24
Finished Jan 17 01:58:43 PM PST 24
Peak memory 208760 kb
Host smart-e414711d-c9d8-4c56-8cc2-86966ecf279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965770963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2965770963
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.261492668
Short name T1243
Test name
Test status
Simulation time 9354506891 ps
CPU time 505.37 seconds
Started Jan 17 01:56:34 PM PST 24
Finished Jan 17 02:05:13 PM PST 24
Peak memory 200200 kb
Host smart-3b309a55-73a8-4a7c-8ef5-71b2277a4928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261492668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.261492668
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3972595536
Short name T715
Test name
Test status
Simulation time 879690217 ps
CPU time 8.14 seconds
Started Jan 17 01:56:33 PM PST 24
Finished Jan 17 01:56:55 PM PST 24
Peak memory 198424 kb
Host smart-e5d4b95c-7eec-463d-bfde-e4eb103db0c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972595536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3972595536
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3771141407
Short name T1071
Test name
Test status
Simulation time 54344664245 ps
CPU time 42.3 seconds
Started Jan 17 01:56:34 PM PST 24
Finished Jan 17 01:57:30 PM PST 24
Peak memory 199348 kb
Host smart-99cbb468-2bd0-41eb-9b43-94d4904ce07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771141407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3771141407
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3814291514
Short name T518
Test name
Test status
Simulation time 4915546781 ps
CPU time 1.78 seconds
Started Jan 17 01:56:31 PM PST 24
Finished Jan 17 01:56:34 PM PST 24
Peak memory 195956 kb
Host smart-ad63efed-c29d-4ef6-945d-b51f0b095965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814291514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3814291514
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3789271793
Short name T431
Test name
Test status
Simulation time 937739112 ps
CPU time 2.35 seconds
Started Jan 17 01:56:33 PM PST 24
Finished Jan 17 01:56:50 PM PST 24
Peak memory 199056 kb
Host smart-1a35dd06-7086-4196-be5a-d2607df11f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789271793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3789271793
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2576729388
Short name T356
Test name
Test status
Simulation time 163209181057 ps
CPU time 53.39 seconds
Started Jan 17 01:56:40 PM PST 24
Finished Jan 17 01:57:41 PM PST 24
Peak memory 199728 kb
Host smart-dfb2718c-738d-44a2-a2f2-864f3ac7a47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576729388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2576729388
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.887024180
Short name T853
Test name
Test status
Simulation time 24391047748 ps
CPU time 259.61 seconds
Started Jan 17 01:56:30 PM PST 24
Finished Jan 17 02:00:51 PM PST 24
Peak memory 208672 kb
Host smart-2018d727-82ed-4745-8fc0-4b6733ee32ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887024180 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.887024180
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2467204654
Short name T857
Test name
Test status
Simulation time 587292172 ps
CPU time 1.94 seconds
Started Jan 17 01:56:33 PM PST 24
Finished Jan 17 01:56:49 PM PST 24
Peak memory 198388 kb
Host smart-8936d97e-ab8b-4ff3-bbfe-8002d6aca3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467204654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2467204654
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1284420207
Short name T1097
Test name
Test status
Simulation time 22702983950 ps
CPU time 34.9 seconds
Started Jan 17 01:56:34 PM PST 24
Finished Jan 17 01:57:23 PM PST 24
Peak memory 200184 kb
Host smart-75817736-f8ab-4614-916d-ecb71f58ac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284420207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1284420207
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1656839227
Short name T357
Test name
Test status
Simulation time 34209928945 ps
CPU time 25.17 seconds
Started Jan 17 02:03:52 PM PST 24
Finished Jan 17 02:04:21 PM PST 24
Peak memory 200232 kb
Host smart-6bf6e076-a5ec-4e22-b49c-e61e18d91bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656839227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1656839227
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3425240715
Short name T1072
Test name
Test status
Simulation time 66421584524 ps
CPU time 106.3 seconds
Started Jan 17 02:03:51 PM PST 24
Finished Jan 17 02:05:41 PM PST 24
Peak memory 200244 kb
Host smart-9376551f-c756-42a2-8e1c-217ee8ff49b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425240715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3425240715
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.447613532
Short name T1076
Test name
Test status
Simulation time 23825257137 ps
CPU time 25.51 seconds
Started Jan 17 02:03:51 PM PST 24
Finished Jan 17 02:04:21 PM PST 24
Peak memory 199992 kb
Host smart-5e603c45-05d4-4336-9492-f66e0d3486dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447613532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.447613532
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.283696534
Short name T543
Test name
Test status
Simulation time 9768709157 ps
CPU time 10.18 seconds
Started Jan 17 02:03:47 PM PST 24
Finished Jan 17 02:03:58 PM PST 24
Peak memory 198068 kb
Host smart-5cfc332c-c446-49a8-a835-3140d8c5fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283696534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.283696534
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2137254521
Short name T834
Test name
Test status
Simulation time 29000360092 ps
CPU time 34.16 seconds
Started Jan 17 02:03:51 PM PST 24
Finished Jan 17 02:04:29 PM PST 24
Peak memory 200240 kb
Host smart-485aa4c4-2dfa-4744-95b0-cc1830a5bb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137254521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2137254521
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.686163883
Short name T536
Test name
Test status
Simulation time 6449506292 ps
CPU time 11.23 seconds
Started Jan 17 02:03:58 PM PST 24
Finished Jan 17 02:04:17 PM PST 24
Peak memory 198916 kb
Host smart-6f1a07d0-8909-489e-be3e-57770274b126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686163883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.686163883
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.286593220
Short name T806
Test name
Test status
Simulation time 43272560 ps
CPU time 0.55 seconds
Started Jan 17 01:56:36 PM PST 24
Finished Jan 17 01:56:48 PM PST 24
Peak memory 195652 kb
Host smart-5dcd5440-29a8-4767-ae77-681633612a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286593220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.286593220
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1772355502
Short name T273
Test name
Test status
Simulation time 252576862221 ps
CPU time 122 seconds
Started Jan 17 01:56:41 PM PST 24
Finished Jan 17 01:58:49 PM PST 24
Peak memory 200144 kb
Host smart-58ed6173-f09b-4e79-8964-798b8fbfd602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772355502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1772355502
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2977032595
Short name T348
Test name
Test status
Simulation time 131818813353 ps
CPU time 112.65 seconds
Started Jan 17 01:56:40 PM PST 24
Finished Jan 17 01:58:40 PM PST 24
Peak memory 200264 kb
Host smart-cbbd8eb9-1009-4507-961e-1c1240b039d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977032595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2977032595
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2187313809
Short name T333
Test name
Test status
Simulation time 12404675238 ps
CPU time 9.48 seconds
Started Jan 17 01:56:36 PM PST 24
Finished Jan 17 01:56:57 PM PST 24
Peak memory 199560 kb
Host smart-22b6d0e2-36df-449f-a657-0f11223a60d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187313809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2187313809
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2051066993
Short name T706
Test name
Test status
Simulation time 40844492938 ps
CPU time 27.33 seconds
Started Jan 17 01:56:45 PM PST 24
Finished Jan 17 01:57:15 PM PST 24
Peak memory 199052 kb
Host smart-ff4200fb-417a-4857-91c1-31be33069b7b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051066993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2051066993
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1032257543
Short name T1148
Test name
Test status
Simulation time 62841307437 ps
CPU time 479.25 seconds
Started Jan 17 01:56:38 PM PST 24
Finished Jan 17 02:04:47 PM PST 24
Peak memory 200280 kb
Host smart-1502df06-4533-478f-8c4e-7f43cee432f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032257543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1032257543
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1863569859
Short name T499
Test name
Test status
Simulation time 7914768957 ps
CPU time 15.43 seconds
Started Jan 17 01:56:41 PM PST 24
Finished Jan 17 01:57:03 PM PST 24
Peak memory 199308 kb
Host smart-c748bb9e-fdfb-4ad4-b08a-124a083874ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863569859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1863569859
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2029491529
Short name T225
Test name
Test status
Simulation time 70448539560 ps
CPU time 29.5 seconds
Started Jan 17 01:56:38 PM PST 24
Finished Jan 17 01:57:17 PM PST 24
Peak memory 199388 kb
Host smart-b8c25d8d-5a7c-4de8-ac54-2ceb781497ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029491529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2029491529
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.904773120
Short name T1141
Test name
Test status
Simulation time 174796627313 ps
CPU time 48.16 seconds
Started Jan 17 01:56:39 PM PST 24
Finished Jan 17 01:57:35 PM PST 24
Peak memory 199336 kb
Host smart-f82f0da2-1b7f-4f57-844e-a9eca3b2fe35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904773120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.904773120
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1250500659
Short name T688
Test name
Test status
Simulation time 5771124857 ps
CPU time 5.41 seconds
Started Jan 17 01:56:45 PM PST 24
Finished Jan 17 01:56:53 PM PST 24
Peak memory 195944 kb
Host smart-205138c8-23a3-45c3-92a6-ed60cc8f3298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250500659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1250500659
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4092708745
Short name T1176
Test name
Test status
Simulation time 489527828 ps
CPU time 2.33 seconds
Started Jan 17 01:56:34 PM PST 24
Finished Jan 17 01:56:50 PM PST 24
Peak memory 198276 kb
Host smart-3334538f-07a3-498f-b453-57cadfaaaa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092708745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4092708745
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2016087440
Short name T294
Test name
Test status
Simulation time 81411694582 ps
CPU time 888.95 seconds
Started Jan 17 01:56:36 PM PST 24
Finished Jan 17 02:11:36 PM PST 24
Peak memory 200332 kb
Host smart-84d25ead-dbf9-4c2a-b7c1-0bbff9cc622f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016087440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2016087440
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.564834349
Short name T428
Test name
Test status
Simulation time 857483449 ps
CPU time 2.42 seconds
Started Jan 17 01:56:40 PM PST 24
Finished Jan 17 01:56:50 PM PST 24
Peak memory 197764 kb
Host smart-08cf1649-ac7d-44b0-8374-6549f5490f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564834349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.564834349
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1351096764
Short name T855
Test name
Test status
Simulation time 102933429653 ps
CPU time 257.73 seconds
Started Jan 17 01:56:45 PM PST 24
Finished Jan 17 02:01:06 PM PST 24
Peak memory 200128 kb
Host smart-7b13c97e-cd32-4456-bc41-5b3635d2b30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351096764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1351096764
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.757003261
Short name T200
Test name
Test status
Simulation time 84694595658 ps
CPU time 24.58 seconds
Started Jan 17 02:03:56 PM PST 24
Finished Jan 17 02:04:28 PM PST 24
Peak memory 200168 kb
Host smart-a0880450-2fe0-4347-bb6d-398fb02c2525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757003261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.757003261
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3829858516
Short name T690
Test name
Test status
Simulation time 17710188987 ps
CPU time 29.29 seconds
Started Jan 17 02:03:54 PM PST 24
Finished Jan 17 02:04:25 PM PST 24
Peak memory 200216 kb
Host smart-ff484eb7-89a3-490c-b55d-f81e9fa8c505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829858516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3829858516
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3107616472
Short name T1103
Test name
Test status
Simulation time 99069707441 ps
CPU time 43.41 seconds
Started Jan 17 02:04:00 PM PST 24
Finished Jan 17 02:04:49 PM PST 24
Peak memory 200236 kb
Host smart-46867157-4624-4cff-b22c-395e5fe26b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107616472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3107616472
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.303873629
Short name T856
Test name
Test status
Simulation time 125377925784 ps
CPU time 54.42 seconds
Started Jan 17 02:03:54 PM PST 24
Finished Jan 17 02:04:50 PM PST 24
Peak memory 200220 kb
Host smart-84530914-5b10-4c28-83a8-b7c11996787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303873629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.303873629
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.203939514
Short name T1086
Test name
Test status
Simulation time 64300455919 ps
CPU time 110.43 seconds
Started Jan 17 02:04:01 PM PST 24
Finished Jan 17 02:05:56 PM PST 24
Peak memory 200172 kb
Host smart-e612b026-edf9-47e9-81d0-be2b56941b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203939514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.203939514
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2709491085
Short name T1034
Test name
Test status
Simulation time 124905521413 ps
CPU time 50.43 seconds
Started Jan 17 02:03:59 PM PST 24
Finished Jan 17 02:04:56 PM PST 24
Peak memory 200188 kb
Host smart-7755c628-37b1-4d71-a6ee-5db453a043b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709491085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2709491085
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4202138128
Short name T1238
Test name
Test status
Simulation time 84646617302 ps
CPU time 66.32 seconds
Started Jan 17 02:03:58 PM PST 24
Finished Jan 17 02:05:12 PM PST 24
Peak memory 200268 kb
Host smart-9e507007-cac5-4635-b5a0-ecd573c4314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202138128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4202138128
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2365283826
Short name T187
Test name
Test status
Simulation time 210366873403 ps
CPU time 347.64 seconds
Started Jan 17 02:03:53 PM PST 24
Finished Jan 17 02:09:44 PM PST 24
Peak memory 199784 kb
Host smart-37a78d34-5102-4be3-8837-3996169db8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365283826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2365283826
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2552267149
Short name T515
Test name
Test status
Simulation time 22611551 ps
CPU time 0.56 seconds
Started Jan 17 01:56:44 PM PST 24
Finished Jan 17 01:56:48 PM PST 24
Peak memory 195584 kb
Host smart-a9ec2278-48e8-4c7e-8215-e7307b3312a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552267149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2552267149
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.95536140
Short name T1078
Test name
Test status
Simulation time 33146941298 ps
CPU time 49.69 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 01:57:37 PM PST 24
Peak memory 200228 kb
Host smart-3f43962d-14d7-43a0-a95f-9f063ff65941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95536140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.95536140
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3026568630
Short name T318
Test name
Test status
Simulation time 134988992302 ps
CPU time 191.34 seconds
Started Jan 17 01:56:45 PM PST 24
Finished Jan 17 01:59:59 PM PST 24
Peak memory 200292 kb
Host smart-edef7737-838e-4211-8561-ed55996c4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026568630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3026568630
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2069271588
Short name T30
Test name
Test status
Simulation time 162530419746 ps
CPU time 71.73 seconds
Started Jan 17 01:56:45 PM PST 24
Finished Jan 17 01:57:59 PM PST 24
Peak memory 200168 kb
Host smart-9c573d07-009d-4107-a78a-eea2171d2a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069271588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2069271588
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3564712247
Short name T885
Test name
Test status
Simulation time 766200981145 ps
CPU time 297.67 seconds
Started Jan 17 01:56:42 PM PST 24
Finished Jan 17 02:01:45 PM PST 24
Peak memory 200208 kb
Host smart-d71cfd21-2a7d-42d8-aed9-827fc6a5db1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564712247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3564712247
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3923456822
Short name T1087
Test name
Test status
Simulation time 65731945115 ps
CPU time 256.29 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 02:01:04 PM PST 24
Peak memory 200180 kb
Host smart-f93afbd2-a3d9-4108-b52e-fae1bfe4b22d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923456822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3923456822
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3862617412
Short name T104
Test name
Test status
Simulation time 9847958630 ps
CPU time 13.43 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 01:57:01 PM PST 24
Peak memory 199276 kb
Host smart-b07f3f7f-2670-46b5-84a3-dfcf990b7cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862617412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3862617412
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.34848239
Short name T902
Test name
Test status
Simulation time 65468376162 ps
CPU time 89.89 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 01:58:18 PM PST 24
Peak memory 199276 kb
Host smart-bfbb5068-a16a-49dc-975d-943a4db0aee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34848239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.34848239
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.359589333
Short name T982
Test name
Test status
Simulation time 1874674585 ps
CPU time 37.11 seconds
Started Jan 17 01:56:44 PM PST 24
Finished Jan 17 01:57:25 PM PST 24
Peak memory 199988 kb
Host smart-21dbfcfd-4692-4a46-88d4-a7b204309815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359589333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.359589333
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1870544656
Short name T966
Test name
Test status
Simulation time 4256875817 ps
CPU time 9.78 seconds
Started Jan 17 01:56:48 PM PST 24
Finished Jan 17 01:56:59 PM PST 24
Peak memory 198416 kb
Host smart-2abd0230-e8ba-41fa-8949-ab083d7c0b4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870544656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1870544656
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2476304062
Short name T385
Test name
Test status
Simulation time 59807402003 ps
CPU time 19.16 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 01:57:07 PM PST 24
Peak memory 198820 kb
Host smart-c78d7c10-39a5-4dbf-9c44-b57785ce1c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476304062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2476304062
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4159565547
Short name T1004
Test name
Test status
Simulation time 3293495110 ps
CPU time 1.79 seconds
Started Jan 17 01:56:45 PM PST 24
Finished Jan 17 01:56:49 PM PST 24
Peak memory 195728 kb
Host smart-27258187-03d4-4637-af33-74b5f5c3d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159565547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4159565547
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2356649770
Short name T432
Test name
Test status
Simulation time 727454049 ps
CPU time 1.6 seconds
Started Jan 17 01:56:37 PM PST 24
Finished Jan 17 01:56:49 PM PST 24
Peak memory 198556 kb
Host smart-ea5164ab-c076-4569-ac05-93bf76edb751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356649770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2356649770
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.4126790834
Short name T1031
Test name
Test status
Simulation time 1257689024038 ps
CPU time 468.71 seconds
Started Jan 17 01:56:42 PM PST 24
Finished Jan 17 02:04:36 PM PST 24
Peak memory 216868 kb
Host smart-f717af2d-b605-4359-919d-67fdac64756e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126790834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.4126790834
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.52495757
Short name T824
Test name
Test status
Simulation time 59580429060 ps
CPU time 238.52 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 02:00:46 PM PST 24
Peak memory 208492 kb
Host smart-6c4d7f4b-cee0-424c-9b4c-58da5c9ec18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52495757 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.52495757
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2214063062
Short name T840
Test name
Test status
Simulation time 7452990976 ps
CPU time 12.62 seconds
Started Jan 17 01:56:44 PM PST 24
Finished Jan 17 01:57:00 PM PST 24
Peak memory 199628 kb
Host smart-4126068e-23f2-41f4-825e-11f70e09c81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214063062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2214063062
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3435356728
Short name T455
Test name
Test status
Simulation time 150258008600 ps
CPU time 312.37 seconds
Started Jan 17 01:56:35 PM PST 24
Finished Jan 17 02:02:00 PM PST 24
Peak memory 200252 kb
Host smart-2417f507-3383-40fc-99ff-3b67942c2bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435356728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3435356728
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1149208631
Short name T703
Test name
Test status
Simulation time 27205419098 ps
CPU time 11.04 seconds
Started Jan 17 02:03:55 PM PST 24
Finished Jan 17 02:04:08 PM PST 24
Peak memory 200132 kb
Host smart-2623b7a4-d926-42cb-8684-b9e38ffe845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149208631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1149208631
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2692722259
Short name T170
Test name
Test status
Simulation time 17851927851 ps
CPU time 29.33 seconds
Started Jan 17 02:03:57 PM PST 24
Finished Jan 17 02:04:35 PM PST 24
Peak memory 199468 kb
Host smart-d2ec4600-5e13-4fd9-aafe-31fff28160aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692722259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2692722259
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3797054224
Short name T1062
Test name
Test status
Simulation time 8611949185 ps
CPU time 16.3 seconds
Started Jan 17 02:03:57 PM PST 24
Finished Jan 17 02:04:22 PM PST 24
Peak memory 200216 kb
Host smart-57994701-e758-4aca-b9d9-950f941a2eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797054224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3797054224
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3751172101
Short name T127
Test name
Test status
Simulation time 74988940714 ps
CPU time 41.41 seconds
Started Jan 17 02:03:56 PM PST 24
Finished Jan 17 02:04:45 PM PST 24
Peak memory 200288 kb
Host smart-b136e912-2929-4fe2-a961-e8ea3d6038d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751172101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3751172101
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.580644048
Short name T839
Test name
Test status
Simulation time 51815925082 ps
CPU time 19.87 seconds
Started Jan 17 02:04:01 PM PST 24
Finished Jan 17 02:04:26 PM PST 24
Peak memory 200060 kb
Host smart-a6c09aff-fba0-4c42-a964-d2b770c7226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580644048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.580644048
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2505153762
Short name T301
Test name
Test status
Simulation time 80671316858 ps
CPU time 259.49 seconds
Started Jan 17 02:03:58 PM PST 24
Finished Jan 17 02:08:25 PM PST 24
Peak memory 200272 kb
Host smart-a538482b-d9be-4b08-a793-c00eab9cb32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505153762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2505153762
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1633042617
Short name T860
Test name
Test status
Simulation time 15645206809 ps
CPU time 22.82 seconds
Started Jan 17 02:03:56 PM PST 24
Finished Jan 17 02:04:26 PM PST 24
Peak memory 199844 kb
Host smart-8a849a06-b133-42db-b505-01b4aa332877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633042617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1633042617
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3018218299
Short name T692
Test name
Test status
Simulation time 17848460 ps
CPU time 0.56 seconds
Started Jan 17 01:54:51 PM PST 24
Finished Jan 17 01:54:53 PM PST 24
Peak memory 195648 kb
Host smart-e8858b0e-2041-4c6f-93e9-b4ec62cc8c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018218299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3018218299
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1832976616
Short name T1242
Test name
Test status
Simulation time 165094223641 ps
CPU time 83.71 seconds
Started Jan 17 01:54:45 PM PST 24
Finished Jan 17 01:56:10 PM PST 24
Peak memory 200188 kb
Host smart-fa773733-1edb-4645-af1c-62aded6918a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832976616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1832976616
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1236774261
Short name T901
Test name
Test status
Simulation time 245314394875 ps
CPU time 411.16 seconds
Started Jan 17 01:54:58 PM PST 24
Finished Jan 17 02:01:51 PM PST 24
Peak memory 200148 kb
Host smart-348cc36b-57be-49d8-ad34-69f7baa69f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236774261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1236774261
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1943611984
Short name T366
Test name
Test status
Simulation time 19165780795 ps
CPU time 16.32 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 01:55:16 PM PST 24
Peak memory 200264 kb
Host smart-87d68d67-19a8-4dfa-ad48-ee5023b60ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943611984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1943611984
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3188359305
Short name T460
Test name
Test status
Simulation time 644090014631 ps
CPU time 112.23 seconds
Started Jan 17 01:54:55 PM PST 24
Finished Jan 17 01:56:50 PM PST 24
Peak memory 199164 kb
Host smart-f8951a17-7fa0-45d6-9673-f9f11678e108
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188359305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3188359305
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_loopback.2868007630
Short name T501
Test name
Test status
Simulation time 7885857128 ps
CPU time 14.27 seconds
Started Jan 17 01:55:01 PM PST 24
Finished Jan 17 01:55:16 PM PST 24
Peak memory 199492 kb
Host smart-2f913d03-f33c-438f-a1a9-956fb5a21986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868007630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2868007630
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3025177923
Short name T799
Test name
Test status
Simulation time 176719630847 ps
CPU time 95.27 seconds
Started Jan 17 01:55:00 PM PST 24
Finished Jan 17 01:56:36 PM PST 24
Peak memory 208764 kb
Host smart-89c9d952-61b4-4a51-af39-bcac158dd7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025177923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3025177923
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2850864726
Short name T881
Test name
Test status
Simulation time 11145489995 ps
CPU time 572.43 seconds
Started Jan 17 01:54:53 PM PST 24
Finished Jan 17 02:04:27 PM PST 24
Peak memory 200260 kb
Host smart-2d324315-52c5-4b90-8ffb-a25e1f9078ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2850864726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2850864726
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.378717409
Short name T944
Test name
Test status
Simulation time 3683713593 ps
CPU time 7.67 seconds
Started Jan 17 01:54:51 PM PST 24
Finished Jan 17 01:55:00 PM PST 24
Peak memory 199580 kb
Host smart-a2322167-32b5-46e2-b46e-6e06ac297256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378717409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.378717409
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3547201353
Short name T764
Test name
Test status
Simulation time 1271037459 ps
CPU time 1.16 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 01:55:01 PM PST 24
Peak memory 195696 kb
Host smart-fc03d4cc-e693-43d7-b610-811fe888ac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547201353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3547201353
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3524823689
Short name T103
Test name
Test status
Simulation time 73209204 ps
CPU time 0.73 seconds
Started Jan 17 01:54:51 PM PST 24
Finished Jan 17 01:54:52 PM PST 24
Peak memory 217752 kb
Host smart-8151df16-be21-4f95-96dc-1355e5147e08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524823689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3524823689
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.844451157
Short name T444
Test name
Test status
Simulation time 5986475511 ps
CPU time 10.1 seconds
Started Jan 17 01:54:49 PM PST 24
Finished Jan 17 01:55:00 PM PST 24
Peak memory 199664 kb
Host smart-7f8397b4-0301-4db9-9b5b-5ed287c86d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844451157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.844451157
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.169125001
Short name T279
Test name
Test status
Simulation time 174254412440 ps
CPU time 342.26 seconds
Started Jan 17 01:54:57 PM PST 24
Finished Jan 17 02:00:41 PM PST 24
Peak memory 208676 kb
Host smart-28c77d3e-9c69-42e5-bfed-e12b82d5b627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169125001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.169125001
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1020921946
Short name T462
Test name
Test status
Simulation time 21792447296 ps
CPU time 179.05 seconds
Started Jan 17 01:54:55 PM PST 24
Finished Jan 17 01:57:57 PM PST 24
Peak memory 209680 kb
Host smart-097c396d-011d-4022-92c1-af863444a003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020921946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1020921946
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.4080542294
Short name T959
Test name
Test status
Simulation time 1197076126 ps
CPU time 3.59 seconds
Started Jan 17 01:54:53 PM PST 24
Finished Jan 17 01:54:59 PM PST 24
Peak memory 198456 kb
Host smart-f5e6ab12-1ab3-4011-a3b4-71d2bb6979ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080542294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.4080542294
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1304984280
Short name T1127
Test name
Test status
Simulation time 26429715513 ps
CPU time 12.35 seconds
Started Jan 17 01:54:46 PM PST 24
Finished Jan 17 01:55:00 PM PST 24
Peak memory 198904 kb
Host smart-19c5e40a-a6b7-4dbf-a4af-a72beac5746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304984280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1304984280
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1775910601
Short name T788
Test name
Test status
Simulation time 56450050 ps
CPU time 0.54 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:57:05 PM PST 24
Peak memory 195692 kb
Host smart-183efd99-5317-4be3-80a3-299b92e5bbe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775910601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1775910601
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.330625514
Short name T1014
Test name
Test status
Simulation time 37070737763 ps
CPU time 55.35 seconds
Started Jan 17 01:56:53 PM PST 24
Finished Jan 17 01:57:49 PM PST 24
Peak memory 200196 kb
Host smart-c29dbcf7-b594-4379-bf74-53367d5cbb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330625514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.330625514
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3877573786
Short name T226
Test name
Test status
Simulation time 121762283898 ps
CPU time 39.63 seconds
Started Jan 17 01:56:58 PM PST 24
Finished Jan 17 01:57:44 PM PST 24
Peak memory 200044 kb
Host smart-7f9ed38d-e154-4fd0-b041-28f212fc7877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877573786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3877573786
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.2944130043
Short name T877
Test name
Test status
Simulation time 68079763118 ps
CPU time 62.87 seconds
Started Jan 17 01:56:55 PM PST 24
Finished Jan 17 01:57:58 PM PST 24
Peak memory 200204 kb
Host smart-e53e26a7-6122-4a65-9418-72d111375ec1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944130043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2944130043
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4080424186
Short name T669
Test name
Test status
Simulation time 60119305787 ps
CPU time 456.99 seconds
Started Jan 17 01:56:55 PM PST 24
Finished Jan 17 02:04:35 PM PST 24
Peak memory 200188 kb
Host smart-066db44b-ad1b-4d3d-8341-f65dd6550068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080424186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4080424186
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.913257137
Short name T613
Test name
Test status
Simulation time 9535330116 ps
CPU time 6.58 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:57:09 PM PST 24
Peak memory 199628 kb
Host smart-d3e65be2-2f7a-41f6-bf97-72679859fe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913257137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.913257137
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.216923764
Short name T600
Test name
Test status
Simulation time 53812334682 ps
CPU time 85.65 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:58:29 PM PST 24
Peak memory 208624 kb
Host smart-5609bb09-3f41-44b6-9dc0-69135e757613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216923764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.216923764
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.4135234779
Short name T984
Test name
Test status
Simulation time 7610090627 ps
CPU time 421.85 seconds
Started Jan 17 01:56:57 PM PST 24
Finished Jan 17 02:04:06 PM PST 24
Peak memory 200260 kb
Host smart-9ddd0173-e527-4005-9cc5-50955133d751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135234779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4135234779
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1418881111
Short name T1217
Test name
Test status
Simulation time 2046826457 ps
CPU time 11.66 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:57:15 PM PST 24
Peak memory 197976 kb
Host smart-4a372d64-8156-47c5-b594-f1906e22d7b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418881111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1418881111
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.384014897
Short name T1198
Test name
Test status
Simulation time 6049759424 ps
CPU time 9.89 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:57:14 PM PST 24
Peak memory 198220 kb
Host smart-963c7db6-5741-41ec-aace-7d7747b8d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384014897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.384014897
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2598213312
Short name T512
Test name
Test status
Simulation time 2847944846 ps
CPU time 4.9 seconds
Started Jan 17 01:56:54 PM PST 24
Finished Jan 17 01:57:00 PM PST 24
Peak memory 195680 kb
Host smart-7118174c-245c-46bf-aeda-943ff3abdd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598213312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2598213312
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4240385614
Short name T411
Test name
Test status
Simulation time 5731532540 ps
CPU time 12.88 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 01:57:01 PM PST 24
Peak memory 198972 kb
Host smart-ad3ba65c-7d0d-4e88-91ef-7352cad566c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240385614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4240385614
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2312232706
Short name T794
Test name
Test status
Simulation time 99032935989 ps
CPU time 178.3 seconds
Started Jan 17 01:56:54 PM PST 24
Finished Jan 17 01:59:53 PM PST 24
Peak memory 200188 kb
Host smart-34e9e7d1-13a7-4592-a606-3c3e86677998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312232706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2312232706
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.49540254
Short name T970
Test name
Test status
Simulation time 55024284287 ps
CPU time 289.82 seconds
Started Jan 17 01:56:54 PM PST 24
Finished Jan 17 02:01:45 PM PST 24
Peak memory 212616 kb
Host smart-e1a53660-d47f-4e84-9028-70775a6acba0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49540254 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.49540254
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.779921857
Short name T643
Test name
Test status
Simulation time 1453642527 ps
CPU time 2.29 seconds
Started Jan 17 01:56:55 PM PST 24
Finished Jan 17 01:57:02 PM PST 24
Peak memory 198424 kb
Host smart-ecb7605f-24a6-4afe-b059-c33e9f523ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779921857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.779921857
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3498371553
Short name T1129
Test name
Test status
Simulation time 131583184989 ps
CPU time 134.66 seconds
Started Jan 17 01:56:43 PM PST 24
Finished Jan 17 01:59:02 PM PST 24
Peak memory 200220 kb
Host smart-46254a72-f076-4054-98cd-df0c63e33e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498371553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3498371553
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.853870626
Short name T675
Test name
Test status
Simulation time 30220580571 ps
CPU time 33.88 seconds
Started Jan 17 02:03:55 PM PST 24
Finished Jan 17 02:04:30 PM PST 24
Peak memory 200200 kb
Host smart-05690fca-2df7-4066-a5bd-70b8847434fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853870626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.853870626
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3764022991
Short name T112
Test name
Test status
Simulation time 8256269599 ps
CPU time 14.34 seconds
Started Jan 17 02:04:05 PM PST 24
Finished Jan 17 02:04:24 PM PST 24
Peak memory 200256 kb
Host smart-cbbadcad-06e2-46b6-b3dc-84221b5434c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764022991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3764022991
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1282746342
Short name T1040
Test name
Test status
Simulation time 34461545341 ps
CPU time 26.81 seconds
Started Jan 17 02:04:00 PM PST 24
Finished Jan 17 02:04:32 PM PST 24
Peak memory 199748 kb
Host smart-56ce1798-aad1-4177-9521-611161632d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282746342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1282746342
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3977040349
Short name T256
Test name
Test status
Simulation time 26272962900 ps
CPU time 64.83 seconds
Started Jan 17 02:04:04 PM PST 24
Finished Jan 17 02:05:14 PM PST 24
Peak memory 200236 kb
Host smart-bf90ffb9-1779-4f58-bece-8fd5d106a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977040349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3977040349
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.727519403
Short name T594
Test name
Test status
Simulation time 145079720837 ps
CPU time 15.55 seconds
Started Jan 17 02:04:01 PM PST 24
Finished Jan 17 02:04:21 PM PST 24
Peak memory 200184 kb
Host smart-bec2a999-972a-42d4-b6f9-5021d68fbc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727519403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.727519403
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2735314624
Short name T325
Test name
Test status
Simulation time 36181474546 ps
CPU time 63.22 seconds
Started Jan 17 02:03:59 PM PST 24
Finished Jan 17 02:05:09 PM PST 24
Peak memory 200220 kb
Host smart-d182827b-7c8c-4dfb-8130-63c1d6ec89a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735314624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2735314624
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3536899186
Short name T326
Test name
Test status
Simulation time 89642935985 ps
CPU time 16.8 seconds
Started Jan 17 02:04:00 PM PST 24
Finished Jan 17 02:04:23 PM PST 24
Peak memory 200240 kb
Host smart-9565b1eb-7edb-43ec-bdc2-953e2391eb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536899186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3536899186
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.4070015875
Short name T142
Test name
Test status
Simulation time 79926048050 ps
CPU time 116.87 seconds
Started Jan 17 02:04:01 PM PST 24
Finished Jan 17 02:06:03 PM PST 24
Peak memory 200204 kb
Host smart-dbd8d8f1-312f-4a31-acb1-5bb3b9c880d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070015875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4070015875
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1195771635
Short name T1001
Test name
Test status
Simulation time 14862928 ps
CPU time 0.57 seconds
Started Jan 17 01:57:02 PM PST 24
Finished Jan 17 01:57:07 PM PST 24
Peak memory 195584 kb
Host smart-fc600477-27c7-49b1-9b12-aa341ec63b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195771635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1195771635
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3988105861
Short name T968
Test name
Test status
Simulation time 50871396035 ps
CPU time 40.69 seconds
Started Jan 17 01:56:55 PM PST 24
Finished Jan 17 01:57:39 PM PST 24
Peak memory 200300 kb
Host smart-bf826e5e-4591-4d40-b5f8-da331b47486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988105861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3988105861
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1617004569
Short name T373
Test name
Test status
Simulation time 133130167300 ps
CPU time 200.04 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 02:00:23 PM PST 24
Peak memory 200260 kb
Host smart-3d1920c9-88a3-417d-b5cd-aeb16afd130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617004569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1617004569
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2146887376
Short name T155
Test name
Test status
Simulation time 86386479471 ps
CPU time 33.49 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:57:37 PM PST 24
Peak memory 199928 kb
Host smart-3cbbe3d6-2650-4185-a0f2-84aeb7f6e158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146887376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2146887376
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3857501531
Short name T923
Test name
Test status
Simulation time 91916934564 ps
CPU time 509.99 seconds
Started Jan 17 01:57:01 PM PST 24
Finished Jan 17 02:05:35 PM PST 24
Peak memory 200228 kb
Host smart-23aabaa2-e698-4149-8753-1e9966e0038d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857501531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3857501531
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2001752632
Short name T1161
Test name
Test status
Simulation time 6825275259 ps
CPU time 14.64 seconds
Started Jan 17 01:57:03 PM PST 24
Finished Jan 17 01:57:21 PM PST 24
Peak memory 200152 kb
Host smart-55a83f89-c06e-4bce-85cb-ba12d3388189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001752632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2001752632
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.580037526
Short name T1125
Test name
Test status
Simulation time 2839798137 ps
CPU time 5.43 seconds
Started Jan 17 01:56:54 PM PST 24
Finished Jan 17 01:57:00 PM PST 24
Peak memory 194044 kb
Host smart-eb6f7889-a2db-4660-ae63-0bdc6c072eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580037526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.580037526
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.4065323690
Short name T728
Test name
Test status
Simulation time 31723064068 ps
CPU time 415.85 seconds
Started Jan 17 01:56:59 PM PST 24
Finished Jan 17 02:04:01 PM PST 24
Peak memory 200180 kb
Host smart-4a8d7d9f-4a8f-4109-854a-d1315c465bce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065323690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4065323690
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2036327760
Short name T601
Test name
Test status
Simulation time 2958354395 ps
CPU time 10.36 seconds
Started Jan 17 01:56:54 PM PST 24
Finished Jan 17 01:57:06 PM PST 24
Peak memory 198244 kb
Host smart-dfbedcd4-779b-4887-9d4f-262054827e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036327760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2036327760
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2240675586
Short name T408
Test name
Test status
Simulation time 33049251903 ps
CPU time 53.05 seconds
Started Jan 17 01:56:56 PM PST 24
Finished Jan 17 01:57:57 PM PST 24
Peak memory 200092 kb
Host smart-1d3ef7a7-f5d6-44c6-902a-a00386f2a730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240675586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2240675586
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1135071785
Short name T106
Test name
Test status
Simulation time 5594196700 ps
CPU time 9.97 seconds
Started Jan 17 01:56:55 PM PST 24
Finished Jan 17 01:57:11 PM PST 24
Peak memory 196124 kb
Host smart-4a699135-ac27-4818-970e-c8ae24e70abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135071785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1135071785
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.943713417
Short name T510
Test name
Test status
Simulation time 496784343 ps
CPU time 2.49 seconds
Started Jan 17 01:56:54 PM PST 24
Finished Jan 17 01:56:57 PM PST 24
Peak memory 198592 kb
Host smart-fe201082-a797-4123-9316-e5ead1bec0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943713417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.943713417
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.817317914
Short name T424
Test name
Test status
Simulation time 1104052765722 ps
CPU time 1755.71 seconds
Started Jan 17 01:57:00 PM PST 24
Finished Jan 17 02:26:21 PM PST 24
Peak memory 208700 kb
Host smart-d757059b-2a3a-4b36-9214-c1337073c2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817317914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.817317914
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2891046577
Short name T789
Test name
Test status
Simulation time 81391367078 ps
CPU time 96.87 seconds
Started Jan 17 01:57:01 PM PST 24
Finished Jan 17 01:58:42 PM PST 24
Peak memory 208540 kb
Host smart-234687d1-ad7d-42e8-beee-772a95842574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891046577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2891046577
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1856828359
Short name T996
Test name
Test status
Simulation time 1988450752 ps
CPU time 2.51 seconds
Started Jan 17 01:57:00 PM PST 24
Finished Jan 17 01:57:08 PM PST 24
Peak memory 198816 kb
Host smart-94e7dff4-4860-4d4f-9385-b6e604e9c40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856828359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1856828359
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2105133047
Short name T868
Test name
Test status
Simulation time 199881609965 ps
CPU time 150.35 seconds
Started Jan 17 01:56:54 PM PST 24
Finished Jan 17 01:59:25 PM PST 24
Peak memory 200224 kb
Host smart-f6093c1c-f4cb-4ee3-ab38-bd1e73dc38a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105133047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2105133047
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1252076108
Short name T163
Test name
Test status
Simulation time 88209845845 ps
CPU time 141.16 seconds
Started Jan 17 02:04:05 PM PST 24
Finished Jan 17 02:06:31 PM PST 24
Peak memory 200184 kb
Host smart-917ea7d1-d8ba-40ca-a79c-4088307d867f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252076108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1252076108
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2394263019
Short name T985
Test name
Test status
Simulation time 102116820973 ps
CPU time 44.44 seconds
Started Jan 17 02:04:05 PM PST 24
Finished Jan 17 02:04:54 PM PST 24
Peak memory 200212 kb
Host smart-de8b8626-7ffd-4ca3-8cd1-3194b7e07a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394263019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2394263019
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2816503989
Short name T156
Test name
Test status
Simulation time 57253739446 ps
CPU time 23.62 seconds
Started Jan 17 02:04:06 PM PST 24
Finished Jan 17 02:04:34 PM PST 24
Peak memory 200276 kb
Host smart-da371a18-6bbd-4736-afbb-8160ea8992de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816503989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2816503989
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.608632933
Short name T19
Test name
Test status
Simulation time 36259552410 ps
CPU time 15.91 seconds
Started Jan 17 02:04:06 PM PST 24
Finished Jan 17 02:04:26 PM PST 24
Peak memory 199716 kb
Host smart-daaa0119-4471-41dd-9f64-37019b80b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608632933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.608632933
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.456613268
Short name T320
Test name
Test status
Simulation time 166008806448 ps
CPU time 39.26 seconds
Started Jan 17 02:04:08 PM PST 24
Finished Jan 17 02:04:50 PM PST 24
Peak memory 198052 kb
Host smart-2f997ba8-b824-4ebf-ace5-44cd7ef79cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456613268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.456613268
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1467684872
Short name T284
Test name
Test status
Simulation time 293448486120 ps
CPU time 54 seconds
Started Jan 17 02:04:08 PM PST 24
Finished Jan 17 02:05:04 PM PST 24
Peak memory 200236 kb
Host smart-aa1f2046-7b77-4473-887b-edd71697137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467684872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1467684872
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.637688901
Short name T177
Test name
Test status
Simulation time 28959992979 ps
CPU time 38.98 seconds
Started Jan 17 02:04:06 PM PST 24
Finished Jan 17 02:04:49 PM PST 24
Peak memory 200208 kb
Host smart-2187070b-c0b2-44be-9a0d-4aa8758931a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637688901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.637688901
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2658342832
Short name T138
Test name
Test status
Simulation time 17640363009 ps
CPU time 27.58 seconds
Started Jan 17 02:04:06 PM PST 24
Finished Jan 17 02:04:38 PM PST 24
Peak memory 200240 kb
Host smart-d1ad104d-3fa3-42fe-b816-2d38ffde57bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658342832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2658342832
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3997810771
Short name T292
Test name
Test status
Simulation time 192475465333 ps
CPU time 333.14 seconds
Started Jan 17 02:04:08 PM PST 24
Finished Jan 17 02:09:44 PM PST 24
Peak memory 200292 kb
Host smart-93d9243e-0b96-40e2-9b7e-97ecc6efeeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997810771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3997810771
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1106159662
Short name T1195
Test name
Test status
Simulation time 11604190 ps
CPU time 0.56 seconds
Started Jan 17 01:57:15 PM PST 24
Finished Jan 17 01:57:18 PM PST 24
Peak memory 194776 kb
Host smart-5b75c1e2-3bc7-41d7-a20c-983b5554fd4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106159662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1106159662
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2625380880
Short name T762
Test name
Test status
Simulation time 45572077752 ps
CPU time 40.2 seconds
Started Jan 17 01:57:01 PM PST 24
Finished Jan 17 01:57:46 PM PST 24
Peak memory 200192 kb
Host smart-7aa6be3a-6481-4a95-8a18-17301852a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625380880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2625380880
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1913977630
Short name T919
Test name
Test status
Simulation time 63387246867 ps
CPU time 92.56 seconds
Started Jan 17 01:57:02 PM PST 24
Finished Jan 17 01:58:39 PM PST 24
Peak memory 200232 kb
Host smart-d30f6705-c817-4aa0-b538-3699095e8656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913977630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1913977630
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3235761932
Short name T461
Test name
Test status
Simulation time 85426611091 ps
CPU time 28.79 seconds
Started Jan 17 01:57:00 PM PST 24
Finished Jan 17 01:57:34 PM PST 24
Peak memory 199348 kb
Host smart-24232e09-293f-4490-b211-41fe08d84db7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235761932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3235761932
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2963914894
Short name T419
Test name
Test status
Simulation time 50781930290 ps
CPU time 589.95 seconds
Started Jan 17 01:57:12 PM PST 24
Finished Jan 17 02:07:03 PM PST 24
Peak memory 200232 kb
Host smart-1bb6bdae-d4e8-430a-ba76-7fc1b6022558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963914894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2963914894
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3174763639
Short name T931
Test name
Test status
Simulation time 10609779840 ps
CPU time 22.97 seconds
Started Jan 17 01:57:16 PM PST 24
Finished Jan 17 01:57:41 PM PST 24
Peak memory 200168 kb
Host smart-130ea6ca-b186-4fe7-b1e0-d4fb9694aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174763639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3174763639
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1153440257
Short name T913
Test name
Test status
Simulation time 43113534661 ps
CPU time 35.12 seconds
Started Jan 17 01:57:04 PM PST 24
Finished Jan 17 01:57:42 PM PST 24
Peak memory 199192 kb
Host smart-5ea2370e-f6a4-49b4-a52f-7b3c4e9966b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153440257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1153440257
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2697761875
Short name T513
Test name
Test status
Simulation time 3883490573 ps
CPU time 201.96 seconds
Started Jan 17 01:57:14 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 200060 kb
Host smart-f9dc0840-362a-43b9-866b-5ce5c725c5b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697761875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2697761875
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1430681719
Short name T530
Test name
Test status
Simulation time 2577711785 ps
CPU time 12.25 seconds
Started Jan 17 01:57:02 PM PST 24
Finished Jan 17 01:57:18 PM PST 24
Peak memory 198776 kb
Host smart-7430e9c4-750e-4dae-9464-e3b69a2066aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430681719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1430681719
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.3484410764
Short name T644
Test name
Test status
Simulation time 33410477202 ps
CPU time 16.05 seconds
Started Jan 17 01:57:03 PM PST 24
Finished Jan 17 01:57:22 PM PST 24
Peak memory 200184 kb
Host smart-174c5576-ba4d-4c79-a175-b9211635bac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484410764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3484410764
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2035211459
Short name T662
Test name
Test status
Simulation time 2498787679 ps
CPU time 1.1 seconds
Started Jan 17 01:57:01 PM PST 24
Finished Jan 17 01:57:07 PM PST 24
Peak memory 195708 kb
Host smart-35e85b0d-2641-4859-8717-abb7be45231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035211459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2035211459
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1482786924
Short name T717
Test name
Test status
Simulation time 303864796 ps
CPU time 1.67 seconds
Started Jan 17 01:57:00 PM PST 24
Finished Jan 17 01:57:07 PM PST 24
Peak memory 199104 kb
Host smart-a40e29df-e335-4f62-b06b-4cbc7cc2d15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482786924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1482786924
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1374725416
Short name T1204
Test name
Test status
Simulation time 466663598965 ps
CPU time 755.96 seconds
Started Jan 17 01:57:13 PM PST 24
Finished Jan 17 02:09:51 PM PST 24
Peak memory 200128 kb
Host smart-2298fef4-2380-4847-a1ae-f7319344a08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374725416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1374725416
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2763250692
Short name T1045
Test name
Test status
Simulation time 230266973467 ps
CPU time 824.88 seconds
Started Jan 17 01:57:16 PM PST 24
Finished Jan 17 02:11:03 PM PST 24
Peak memory 224828 kb
Host smart-ac382ca6-68d5-4605-b17b-cf508473677e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763250692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2763250692
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3994330038
Short name T832
Test name
Test status
Simulation time 771302300 ps
CPU time 2.46 seconds
Started Jan 17 01:57:16 PM PST 24
Finished Jan 17 01:57:21 PM PST 24
Peak memory 198136 kb
Host smart-912d2911-d0e7-4e58-bdf8-4ed8fd778ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994330038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3994330038
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3214462914
Short name T1165
Test name
Test status
Simulation time 101259891839 ps
CPU time 34.88 seconds
Started Jan 17 01:57:06 PM PST 24
Finished Jan 17 01:57:43 PM PST 24
Peak memory 200200 kb
Host smart-d300a448-7c64-48dc-a4a6-8e4f1178b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214462914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3214462914
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2410807465
Short name T117
Test name
Test status
Simulation time 16122583816 ps
CPU time 30.75 seconds
Started Jan 17 02:04:06 PM PST 24
Finished Jan 17 02:04:41 PM PST 24
Peak memory 200196 kb
Host smart-94984478-4044-4bce-a993-e8eb69482122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410807465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2410807465
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.358941917
Short name T134
Test name
Test status
Simulation time 60683215078 ps
CPU time 50.69 seconds
Started Jan 17 02:04:05 PM PST 24
Finished Jan 17 02:05:00 PM PST 24
Peak memory 200108 kb
Host smart-1a5a0b6d-e062-414c-8b89-74ca0b3b4425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358941917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.358941917
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2103005880
Short name T1050
Test name
Test status
Simulation time 70559519015 ps
CPU time 27.28 seconds
Started Jan 17 02:04:11 PM PST 24
Finished Jan 17 02:04:40 PM PST 24
Peak memory 200256 kb
Host smart-994121c3-3f13-45f1-9c96-b2cb435a5ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103005880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2103005880
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1525312430
Short name T295
Test name
Test status
Simulation time 26924027427 ps
CPU time 22.96 seconds
Started Jan 17 02:04:11 PM PST 24
Finished Jan 17 02:04:35 PM PST 24
Peak memory 200288 kb
Host smart-d70cd605-6cda-4422-b877-29a74be05b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525312430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1525312430
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.568359974
Short name T211
Test name
Test status
Simulation time 24986174259 ps
CPU time 41.26 seconds
Started Jan 17 02:04:17 PM PST 24
Finished Jan 17 02:05:01 PM PST 24
Peak memory 200188 kb
Host smart-984f8e88-8cf3-46ab-bf89-f7b71322e5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568359974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.568359974
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1630639151
Short name T222
Test name
Test status
Simulation time 24321477906 ps
CPU time 28.04 seconds
Started Jan 17 02:04:12 PM PST 24
Finished Jan 17 02:04:41 PM PST 24
Peak memory 200308 kb
Host smart-d43f5de6-244c-4d5b-abc5-414d3e01c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630639151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1630639151
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.205460007
Short name T862
Test name
Test status
Simulation time 104244698855 ps
CPU time 42.28 seconds
Started Jan 17 02:04:21 PM PST 24
Finished Jan 17 02:05:04 PM PST 24
Peak memory 198408 kb
Host smart-2d98e177-302d-44ed-9ed4-0c8c85debf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205460007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.205460007
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.276228895
Short name T1231
Test name
Test status
Simulation time 12356290969 ps
CPU time 20.65 seconds
Started Jan 17 02:04:17 PM PST 24
Finished Jan 17 02:04:40 PM PST 24
Peak memory 200172 kb
Host smart-c723d459-b791-42af-9937-71f7b39e5531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276228895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.276228895
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1211251195
Short name T627
Test name
Test status
Simulation time 46104575 ps
CPU time 0.56 seconds
Started Jan 17 01:57:19 PM PST 24
Finished Jan 17 01:57:30 PM PST 24
Peak memory 195656 kb
Host smart-915c22a8-05f0-49f8-93fa-250cefa8e8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211251195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1211251195
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2581222479
Short name T1119
Test name
Test status
Simulation time 50863017632 ps
CPU time 74.54 seconds
Started Jan 17 01:57:14 PM PST 24
Finished Jan 17 01:58:31 PM PST 24
Peak memory 200244 kb
Host smart-df00f113-c6a9-4ef2-b7f6-1da8b0c9720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581222479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2581222479
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1739057486
Short name T1124
Test name
Test status
Simulation time 13345627046 ps
CPU time 13 seconds
Started Jan 17 01:57:11 PM PST 24
Finished Jan 17 01:57:25 PM PST 24
Peak memory 199592 kb
Host smart-7c841734-265b-47a3-abbb-6a0e12ed57be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739057486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1739057486
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.253016114
Short name T938
Test name
Test status
Simulation time 55045507416 ps
CPU time 25.07 seconds
Started Jan 17 01:57:13 PM PST 24
Finished Jan 17 01:57:38 PM PST 24
Peak memory 200016 kb
Host smart-88ad0ff7-2d9a-47e9-aaab-ece2e3bf5ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253016114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.253016114
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4271562792
Short name T1104
Test name
Test status
Simulation time 39758787634 ps
CPU time 58.98 seconds
Started Jan 17 01:57:13 PM PST 24
Finished Jan 17 01:58:13 PM PST 24
Peak memory 197180 kb
Host smart-2660d54b-9ab5-4a30-a15d-86586bb8e9c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271562792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4271562792
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2532900605
Short name T748
Test name
Test status
Simulation time 111760778134 ps
CPU time 295.28 seconds
Started Jan 17 01:57:17 PM PST 24
Finished Jan 17 02:02:15 PM PST 24
Peak memory 200284 kb
Host smart-e4592aba-0d06-42a6-a830-269f3fa10337
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532900605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2532900605
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.200117920
Short name T1057
Test name
Test status
Simulation time 3353847928 ps
CPU time 1.83 seconds
Started Jan 17 01:57:15 PM PST 24
Finished Jan 17 01:57:20 PM PST 24
Peak memory 198040 kb
Host smart-4919d17d-7567-4307-a6b3-164e9b16c95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200117920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.200117920
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1784420115
Short name T580
Test name
Test status
Simulation time 8299980532 ps
CPU time 6.63 seconds
Started Jan 17 01:57:14 PM PST 24
Finished Jan 17 01:57:23 PM PST 24
Peak memory 194968 kb
Host smart-8eee4d8a-7594-43b3-afe5-eabe2ebd50c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784420115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1784420115
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3520846570
Short name T1037
Test name
Test status
Simulation time 23488906699 ps
CPU time 1356.72 seconds
Started Jan 17 01:57:18 PM PST 24
Finished Jan 17 02:19:56 PM PST 24
Peak memory 200208 kb
Host smart-14f57b59-4231-4996-9386-6e4d95a4ad23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3520846570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3520846570
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1544699018
Short name T746
Test name
Test status
Simulation time 91033276722 ps
CPU time 28.04 seconds
Started Jan 17 01:57:15 PM PST 24
Finished Jan 17 01:57:46 PM PST 24
Peak memory 199312 kb
Host smart-65d3de51-427d-4915-ab9a-cd7b215809c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544699018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1544699018
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2332124107
Short name T1183
Test name
Test status
Simulation time 5397769747 ps
CPU time 8.63 seconds
Started Jan 17 01:57:16 PM PST 24
Finished Jan 17 01:57:27 PM PST 24
Peak memory 195992 kb
Host smart-74e8ba2c-3a1f-4141-9498-dc12c4bc8e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332124107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2332124107
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4277651243
Short name T11
Test name
Test status
Simulation time 533282467 ps
CPU time 1.67 seconds
Started Jan 17 01:57:14 PM PST 24
Finished Jan 17 01:57:18 PM PST 24
Peak memory 198312 kb
Host smart-d729bc56-ddb8-4fc8-8bbd-074de2a33272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277651243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4277651243
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2635801584
Short name T756
Test name
Test status
Simulation time 82479772134 ps
CPU time 301.33 seconds
Started Jan 17 01:57:15 PM PST 24
Finished Jan 17 02:02:19 PM PST 24
Peak memory 216704 kb
Host smart-a44a46b2-1841-46b3-b11c-a067c54ee13b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635801584 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2635801584
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.408357276
Short name T823
Test name
Test status
Simulation time 1676418612 ps
CPU time 1.65 seconds
Started Jan 17 01:57:17 PM PST 24
Finished Jan 17 01:57:21 PM PST 24
Peak memory 198372 kb
Host smart-c28980b5-5af4-42d7-98ef-951d113782a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408357276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.408357276
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1580040029
Short name T604
Test name
Test status
Simulation time 57804996961 ps
CPU time 48.54 seconds
Started Jan 17 01:57:13 PM PST 24
Finished Jan 17 01:58:02 PM PST 24
Peak memory 200268 kb
Host smart-76c0dc63-587f-4e40-ae5b-3893a56646b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580040029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1580040029
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3084782733
Short name T317
Test name
Test status
Simulation time 9291657022 ps
CPU time 15.43 seconds
Started Jan 17 02:04:22 PM PST 24
Finished Jan 17 02:04:40 PM PST 24
Peak memory 199480 kb
Host smart-d7be87ad-0a2d-44e1-9ef1-a44f60637c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084782733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3084782733
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3907570837
Short name T883
Test name
Test status
Simulation time 21421790202 ps
CPU time 33.09 seconds
Started Jan 17 02:04:21 PM PST 24
Finished Jan 17 02:04:55 PM PST 24
Peak memory 200260 kb
Host smart-98ceeb13-1755-4294-9526-aa36cbfb2f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907570837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3907570837
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2872863018
Short name T210
Test name
Test status
Simulation time 88096407292 ps
CPU time 147.29 seconds
Started Jan 17 02:04:17 PM PST 24
Finished Jan 17 02:06:47 PM PST 24
Peak memory 200160 kb
Host smart-c9b3c344-e569-4715-8aa9-dcf02a89b6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872863018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2872863018
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1996944816
Short name T118
Test name
Test status
Simulation time 10404904284 ps
CPU time 14.7 seconds
Started Jan 17 02:04:17 PM PST 24
Finished Jan 17 02:04:34 PM PST 24
Peak memory 200000 kb
Host smart-81e8ec05-0ffd-4411-b159-a62137447528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996944816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1996944816
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3450555675
Short name T684
Test name
Test status
Simulation time 23181063320 ps
CPU time 10.07 seconds
Started Jan 17 02:04:18 PM PST 24
Finished Jan 17 02:04:30 PM PST 24
Peak memory 200008 kb
Host smart-cdc29548-75a0-4e7e-9f2d-8c56c79bd58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450555675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3450555675
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2171904200
Short name T108
Test name
Test status
Simulation time 236452955998 ps
CPU time 209.25 seconds
Started Jan 17 02:04:20 PM PST 24
Finished Jan 17 02:07:50 PM PST 24
Peak memory 199792 kb
Host smart-e2e77098-0e6f-461b-9567-814f34ee70ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171904200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2171904200
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3482554920
Short name T934
Test name
Test status
Simulation time 23301191232 ps
CPU time 12.21 seconds
Started Jan 17 02:04:17 PM PST 24
Finished Jan 17 02:04:32 PM PST 24
Peak memory 200300 kb
Host smart-b92ca5bf-46b1-4e4f-9aec-2ca98435882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482554920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3482554920
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3288816918
Short name T1059
Test name
Test status
Simulation time 116112393834 ps
CPU time 167.12 seconds
Started Jan 17 02:04:19 PM PST 24
Finished Jan 17 02:07:07 PM PST 24
Peak memory 200208 kb
Host smart-a1876c53-539c-4949-9f58-2068aa68e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288816918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3288816918
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3603981420
Short name T379
Test name
Test status
Simulation time 68341083719 ps
CPU time 51.22 seconds
Started Jan 17 02:04:41 PM PST 24
Finished Jan 17 02:05:33 PM PST 24
Peak memory 200176 kb
Host smart-a30e0f60-cb02-4f35-8d02-5ce20fe8f1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603981420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3603981420
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1826920017
Short name T100
Test name
Test status
Simulation time 29950146 ps
CPU time 0.54 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:00:24 PM PST 24
Peak memory 195664 kb
Host smart-67522fb2-f777-4452-b664-6e229fdd2237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826920017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1826920017
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2992785665
Short name T219
Test name
Test status
Simulation time 37645301196 ps
CPU time 32.02 seconds
Started Jan 17 01:57:17 PM PST 24
Finished Jan 17 01:57:51 PM PST 24
Peak memory 200224 kb
Host smart-ddfd75e2-858d-4bbc-9872-5b183ffd4c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992785665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2992785665
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3220250854
Short name T1175
Test name
Test status
Simulation time 191202151870 ps
CPU time 306.45 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:05:29 PM PST 24
Peak memory 199320 kb
Host smart-5fc656f5-b359-4500-b55a-8b5fc70ce2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220250854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3220250854
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.592960945
Short name T1094
Test name
Test status
Simulation time 149384547596 ps
CPU time 219.97 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:04:03 PM PST 24
Peak memory 198752 kb
Host smart-a0432560-cfa9-4788-bde4-8ad550431ee9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592960945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.592960945
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3835992900
Short name T927
Test name
Test status
Simulation time 154716878177 ps
CPU time 145.81 seconds
Started Jan 17 02:00:15 PM PST 24
Finished Jan 17 02:02:47 PM PST 24
Peak memory 200240 kb
Host smart-68072ac8-3772-40e2-b7af-8847318cfb6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835992900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3835992900
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2183423156
Short name T505
Test name
Test status
Simulation time 7922506142 ps
CPU time 26.81 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:01:02 PM PST 24
Peak memory 198860 kb
Host smart-e66dfc93-00b2-4e40-82ec-7fe1e3e49a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183423156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2183423156
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1630169102
Short name T1237
Test name
Test status
Simulation time 84810125441 ps
CPU time 37.82 seconds
Started Jan 17 02:00:25 PM PST 24
Finished Jan 17 02:01:08 PM PST 24
Peak memory 208664 kb
Host smart-3708a673-1a1c-4476-afb8-0ae590b6f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630169102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1630169102
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2970802748
Short name T602
Test name
Test status
Simulation time 12784062776 ps
CPU time 345.84 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:06:09 PM PST 24
Peak memory 200200 kb
Host smart-4feb0f69-6ce6-4abc-87f9-3d986e0d680b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2970802748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2970802748
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3412082448
Short name T514
Test name
Test status
Simulation time 3797272715 ps
CPU time 18.44 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:00:40 PM PST 24
Peak memory 199104 kb
Host smart-f2ca2416-9275-4469-9a1a-95cf8136410e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412082448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3412082448
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2468341195
Short name T826
Test name
Test status
Simulation time 162933968146 ps
CPU time 104.33 seconds
Started Jan 17 02:00:19 PM PST 24
Finished Jan 17 02:02:06 PM PST 24
Peak memory 200280 kb
Host smart-0c806dc7-cd7e-4408-8ccc-720ff3e0ceaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468341195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2468341195
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3719313434
Short name T622
Test name
Test status
Simulation time 43937102152 ps
CPU time 61.6 seconds
Started Jan 17 02:00:20 PM PST 24
Finished Jan 17 02:01:23 PM PST 24
Peak memory 195712 kb
Host smart-71d3b17b-1e12-4d90-9cd0-c523b92575a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719313434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3719313434
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3786687887
Short name T657
Test name
Test status
Simulation time 6288777542 ps
CPU time 6.88 seconds
Started Jan 17 01:57:19 PM PST 24
Finished Jan 17 01:57:27 PM PST 24
Peak memory 200176 kb
Host smart-12f26500-561a-4997-bfcf-f75b08459808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786687887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3786687887
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1441053690
Short name T708
Test name
Test status
Simulation time 136920274428 ps
CPU time 503.5 seconds
Started Jan 17 02:00:23 PM PST 24
Finished Jan 17 02:08:47 PM PST 24
Peak memory 208688 kb
Host smart-3490be62-cbdb-4f6e-a973-53e5f81ac99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441053690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1441053690
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1180538549
Short name T577
Test name
Test status
Simulation time 31005903730 ps
CPU time 405.4 seconds
Started Jan 17 02:00:20 PM PST 24
Finished Jan 17 02:07:07 PM PST 24
Peak memory 216908 kb
Host smart-4c226b2f-5fa5-4a47-bf13-c077ce02d19d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180538549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1180538549
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3231717465
Short name T847
Test name
Test status
Simulation time 1793600982 ps
CPU time 1.83 seconds
Started Jan 17 02:00:25 PM PST 24
Finished Jan 17 02:00:32 PM PST 24
Peak memory 198244 kb
Host smart-539be5f6-5818-4bfe-add8-5f997caf2a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231717465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3231717465
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4103851432
Short name T633
Test name
Test status
Simulation time 41663062171 ps
CPU time 59.84 seconds
Started Jan 17 01:57:16 PM PST 24
Finished Jan 17 01:58:19 PM PST 24
Peak memory 200128 kb
Host smart-1e65b52c-354b-4966-bb76-3c6a71b5d8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103851432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4103851432
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3902772452
Short name T339
Test name
Test status
Simulation time 48232181444 ps
CPU time 75.6 seconds
Started Jan 17 02:04:32 PM PST 24
Finished Jan 17 02:05:53 PM PST 24
Peak memory 200236 kb
Host smart-e641c7d5-0933-47ed-b6e5-eb59514960c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902772452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3902772452
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3072043057
Short name T1005
Test name
Test status
Simulation time 79720032466 ps
CPU time 80.61 seconds
Started Jan 17 02:04:34 PM PST 24
Finished Jan 17 02:05:58 PM PST 24
Peak memory 200208 kb
Host smart-bed4d464-861e-4db4-b6de-1bbf197aaef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072043057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3072043057
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.253005308
Short name T229
Test name
Test status
Simulation time 268348703271 ps
CPU time 94.71 seconds
Started Jan 17 02:04:34 PM PST 24
Finished Jan 17 02:06:12 PM PST 24
Peak memory 200120 kb
Host smart-d081e9d3-fc2d-4d74-9c11-7529ac1c279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253005308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.253005308
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2344803279
Short name T297
Test name
Test status
Simulation time 139256129972 ps
CPU time 59.38 seconds
Started Jan 17 02:04:35 PM PST 24
Finished Jan 17 02:05:37 PM PST 24
Peak memory 200200 kb
Host smart-6cf60e0b-7f38-48b2-92a9-e24b72064974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344803279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2344803279
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.122142560
Short name T258
Test name
Test status
Simulation time 31974410896 ps
CPU time 65 seconds
Started Jan 17 02:04:36 PM PST 24
Finished Jan 17 02:05:43 PM PST 24
Peak memory 200136 kb
Host smart-b86a063d-6517-44b4-990a-8b7de8cc3e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122142560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.122142560
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1356576898
Short name T978
Test name
Test status
Simulation time 201388118154 ps
CPU time 19.54 seconds
Started Jan 17 02:04:32 PM PST 24
Finished Jan 17 02:04:57 PM PST 24
Peak memory 199700 kb
Host smart-e86d5700-5339-4fac-9b67-4bc37e8432da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356576898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1356576898
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.922155150
Short name T1170
Test name
Test status
Simulation time 90165155379 ps
CPU time 144.41 seconds
Started Jan 17 02:04:36 PM PST 24
Finished Jan 17 02:07:02 PM PST 24
Peak memory 200252 kb
Host smart-28fd656c-5a7b-4024-92b5-df9771df7fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922155150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.922155150
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.105798687
Short name T747
Test name
Test status
Simulation time 15768213 ps
CPU time 0.56 seconds
Started Jan 17 02:00:32 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 195636 kb
Host smart-9b31df45-70e5-4bd8-b8ae-5df01744b19f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105798687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.105798687
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2161115582
Short name T14
Test name
Test status
Simulation time 25946655127 ps
CPU time 20.77 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:00:53 PM PST 24
Peak memory 200188 kb
Host smart-9bfd8b4e-2f61-4f17-b0bb-1ec932b43589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161115582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2161115582
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.68861425
Short name T731
Test name
Test status
Simulation time 151556315825 ps
CPU time 226.46 seconds
Started Jan 17 02:00:27 PM PST 24
Finished Jan 17 02:04:18 PM PST 24
Peak memory 199944 kb
Host smart-2ed0d595-5279-487f-801f-455d4540e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68861425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.68861425
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1764709480
Short name T661
Test name
Test status
Simulation time 27093126186 ps
CPU time 12.67 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:00:44 PM PST 24
Peak memory 199936 kb
Host smart-8c62d112-0383-4818-991b-667a71aea4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764709480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1764709480
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1048037587
Short name T752
Test name
Test status
Simulation time 266381851318 ps
CPU time 416.05 seconds
Started Jan 17 02:00:34 PM PST 24
Finished Jan 17 02:07:35 PM PST 24
Peak memory 200156 kb
Host smart-5efc224b-87d0-4ab7-bd08-3cd20a590ea8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048037587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1048037587
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2517651349
Short name T1144
Test name
Test status
Simulation time 293877952305 ps
CPU time 238.5 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:04:30 PM PST 24
Peak memory 200244 kb
Host smart-ef4ba607-9fe7-4f49-9c2d-29331fb16a81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517651349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2517651349
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.776202174
Short name T983
Test name
Test status
Simulation time 8438018639 ps
CPU time 4.62 seconds
Started Jan 17 02:00:27 PM PST 24
Finished Jan 17 02:00:36 PM PST 24
Peak memory 198420 kb
Host smart-d960b2b2-effc-4029-bba7-086d11d78fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776202174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.776202174
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2504675144
Short name T784
Test name
Test status
Simulation time 1327188597 ps
CPU time 3.16 seconds
Started Jan 17 02:00:32 PM PST 24
Finished Jan 17 02:00:39 PM PST 24
Peak memory 197200 kb
Host smart-21a3492c-0724-4656-a7a9-e3d43b73ff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504675144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2504675144
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3381095179
Short name T925
Test name
Test status
Simulation time 8788304291 ps
CPU time 554.7 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:09:47 PM PST 24
Peak memory 200200 kb
Host smart-63991994-a62d-4423-ab90-3211f46a86bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381095179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3381095179
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1075070883
Short name T360
Test name
Test status
Simulation time 11644914132 ps
CPU time 9.88 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:44 PM PST 24
Peak memory 199976 kb
Host smart-d3d3cede-5cc5-4ae2-b44e-d004ebaaafa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075070883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1075070883
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.538606122
Short name T1075
Test name
Test status
Simulation time 32655156437 ps
CPU time 6.89 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:42 PM PST 24
Peak memory 196024 kb
Host smart-8934c3f1-15b7-464e-95dc-e453beaefa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538606122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.538606122
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2414132768
Short name T765
Test name
Test status
Simulation time 6160597603 ps
CPU time 5.01 seconds
Started Jan 17 02:00:23 PM PST 24
Finished Jan 17 02:00:29 PM PST 24
Peak memory 199648 kb
Host smart-5f216805-a8d8-4326-b056-b64de111b949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414132768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2414132768
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2377982221
Short name T195
Test name
Test status
Simulation time 243181596239 ps
CPU time 124.59 seconds
Started Jan 17 02:00:11 PM PST 24
Finished Jan 17 02:02:17 PM PST 24
Peak memory 200200 kb
Host smart-29a7eaf9-1c87-46a0-9e76-12f56dcbe729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377982221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2377982221
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1399186567
Short name T399
Test name
Test status
Simulation time 96027294234 ps
CPU time 134.3 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:02:46 PM PST 24
Peak memory 204876 kb
Host smart-82769711-6b0a-4d77-ba06-9536d338fe1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399186567 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1399186567
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1833829618
Short name T31
Test name
Test status
Simulation time 1323213597 ps
CPU time 2.01 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:00:34 PM PST 24
Peak memory 198448 kb
Host smart-800b0244-573e-4203-9e38-965df49bfe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833829618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1833829618
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2859989297
Short name T700
Test name
Test status
Simulation time 68234054303 ps
CPU time 110.03 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:02:22 PM PST 24
Peak memory 200232 kb
Host smart-c401ee6b-7ae5-4fd4-a43a-2084402eb82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859989297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2859989297
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4049904488
Short name T287
Test name
Test status
Simulation time 184723249028 ps
CPU time 330.62 seconds
Started Jan 17 02:04:33 PM PST 24
Finished Jan 17 02:10:08 PM PST 24
Peak memory 200156 kb
Host smart-f799b640-1de6-420c-85ca-00469856f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049904488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4049904488
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2032571914
Short name T186
Test name
Test status
Simulation time 28709841965 ps
CPU time 53.28 seconds
Started Jan 17 02:04:34 PM PST 24
Finished Jan 17 02:05:31 PM PST 24
Peak memory 200196 kb
Host smart-a88c9389-a955-4dcb-8a13-c5e299ec7e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032571914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2032571914
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3900879361
Short name T1080
Test name
Test status
Simulation time 62238035283 ps
CPU time 51.09 seconds
Started Jan 17 02:04:35 PM PST 24
Finished Jan 17 02:05:29 PM PST 24
Peak memory 199828 kb
Host smart-ba75a65f-0330-426c-997d-ec4bd98a184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900879361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3900879361
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.872802739
Short name T363
Test name
Test status
Simulation time 68649621906 ps
CPU time 39.11 seconds
Started Jan 17 02:04:37 PM PST 24
Finished Jan 17 02:05:18 PM PST 24
Peak memory 200260 kb
Host smart-0b4f30e2-2515-4520-937d-afbbf979c842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872802739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.872802739
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.934635229
Short name T218
Test name
Test status
Simulation time 22360371434 ps
CPU time 26.49 seconds
Started Jan 17 02:04:32 PM PST 24
Finished Jan 17 02:05:02 PM PST 24
Peak memory 200212 kb
Host smart-452f0fa1-e88e-45bc-8d1c-66ba8e860c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934635229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.934635229
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1249409854
Short name T570
Test name
Test status
Simulation time 61544078674 ps
CPU time 50.81 seconds
Started Jan 17 02:04:33 PM PST 24
Finished Jan 17 02:05:28 PM PST 24
Peak memory 200272 kb
Host smart-297f97c1-2ffd-49aa-b4ed-a93c04183850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249409854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1249409854
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.274796339
Short name T1013
Test name
Test status
Simulation time 9655360656 ps
CPU time 4.33 seconds
Started Jan 17 02:04:29 PM PST 24
Finished Jan 17 02:04:35 PM PST 24
Peak memory 197232 kb
Host smart-ac269c58-fdde-4b2a-85fd-109c5ea520ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274796339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.274796339
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2121816611
Short name T779
Test name
Test status
Simulation time 101654976709 ps
CPU time 301.93 seconds
Started Jan 17 02:04:44 PM PST 24
Finished Jan 17 02:09:46 PM PST 24
Peak memory 200260 kb
Host smart-43836b57-f443-496d-9a3f-92cffb328bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121816611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2121816611
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.746129109
Short name T576
Test name
Test status
Simulation time 12680093 ps
CPU time 0.56 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:00:40 PM PST 24
Peak memory 195652 kb
Host smart-47c593c2-e763-4b50-97ec-1d1e7d3e750b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746129109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.746129109
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.715411645
Short name T355
Test name
Test status
Simulation time 138944626434 ps
CPU time 205.81 seconds
Started Jan 17 02:00:32 PM PST 24
Finished Jan 17 02:04:03 PM PST 24
Peak memory 200268 kb
Host smart-5964b317-ceca-456b-9165-9676fe3aead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715411645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.715411645
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.168047053
Short name T1052
Test name
Test status
Simulation time 40430666804 ps
CPU time 29.96 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:01:02 PM PST 24
Peak memory 200136 kb
Host smart-8538cbad-3dd1-4c27-ac10-968a3c34ba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168047053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.168047053
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2546224471
Short name T831
Test name
Test status
Simulation time 43724214947 ps
CPU time 12.6 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:00:44 PM PST 24
Peak memory 199584 kb
Host smart-daeeb5d1-40bd-4637-9947-5157274fdeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546224471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2546224471
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3541231795
Short name T567
Test name
Test status
Simulation time 381123990977 ps
CPU time 291.06 seconds
Started Jan 17 02:00:32 PM PST 24
Finished Jan 17 02:05:29 PM PST 24
Peak memory 200260 kb
Host smart-840c58db-38b3-4b62-b9c6-8e93f3624608
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541231795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3541231795
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1351970202
Short name T1159
Test name
Test status
Simulation time 165618796192 ps
CPU time 251.13 seconds
Started Jan 17 02:00:41 PM PST 24
Finished Jan 17 02:04:58 PM PST 24
Peak memory 200188 kb
Host smart-290398cc-d551-499b-ac51-477dbdc13bf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351970202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1351970202
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2400576738
Short name T770
Test name
Test status
Simulation time 1587704284 ps
CPU time 4.41 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:00:36 PM PST 24
Peak memory 198488 kb
Host smart-ffea45a5-eb87-4b6e-80c4-7bb932c0dfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400576738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2400576738
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.1003310863
Short name T1035
Test name
Test status
Simulation time 45854978435 ps
CPU time 80.74 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:01:53 PM PST 24
Peak memory 198800 kb
Host smart-157f08dc-bfd2-4f03-af45-5bbfd2c83d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003310863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1003310863
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.433991208
Short name T646
Test name
Test status
Simulation time 18163347604 ps
CPU time 449.75 seconds
Started Jan 17 02:00:38 PM PST 24
Finished Jan 17 02:08:10 PM PST 24
Peak memory 199988 kb
Host smart-7ecab330-25e6-443e-909b-e863cb07a9e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433991208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.433991208
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2884214408
Short name T1131
Test name
Test status
Simulation time 3209971259 ps
CPU time 23.87 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:00:56 PM PST 24
Peak memory 198656 kb
Host smart-b27f2c07-8ad0-46a4-beeb-b7afa3d1a5ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884214408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2884214408
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3899338465
Short name T783
Test name
Test status
Simulation time 1537757995 ps
CPU time 3.3 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:00:43 PM PST 24
Peak memory 195792 kb
Host smart-2462eb10-5901-4d8a-951a-d556052aa067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899338465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3899338465
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3547292260
Short name T586
Test name
Test status
Simulation time 91379443 ps
CPU time 0.84 seconds
Started Jan 17 01:59:38 PM PST 24
Finished Jan 17 01:59:40 PM PST 24
Peak memory 197840 kb
Host smart-a5fde1cc-4088-4665-a609-7025d7476e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547292260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3547292260
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3560131281
Short name T683
Test name
Test status
Simulation time 73537846527 ps
CPU time 24.06 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:01:00 PM PST 24
Peak memory 200068 kb
Host smart-3ae1ce3b-ff91-45e5-8aea-9f202855a76c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560131281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3560131281
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.851937355
Short name T528
Test name
Test status
Simulation time 6900254976 ps
CPU time 8.74 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:00:41 PM PST 24
Peak memory 200280 kb
Host smart-fa0fcb7a-8ee2-4081-aef0-a7a4c2ba7f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851937355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.851937355
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2786937271
Short name T164
Test name
Test status
Simulation time 12722472261 ps
CPU time 19.74 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:00:52 PM PST 24
Peak memory 199668 kb
Host smart-7f9822e2-adb8-42f0-b7d5-ef2715a640be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786937271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2786937271
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.492254187
Short name T579
Test name
Test status
Simulation time 17459612254 ps
CPU time 27.49 seconds
Started Jan 17 02:04:46 PM PST 24
Finished Jan 17 02:05:14 PM PST 24
Peak memory 200180 kb
Host smart-bc45e52e-d71e-4056-8dd7-f455170c8c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492254187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.492254187
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2062855625
Short name T123
Test name
Test status
Simulation time 89173148655 ps
CPU time 142.2 seconds
Started Jan 17 02:04:44 PM PST 24
Finished Jan 17 02:07:06 PM PST 24
Peak memory 200256 kb
Host smart-988d230c-58ec-485b-81bd-5c986f65b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062855625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2062855625
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2314038968
Short name T1095
Test name
Test status
Simulation time 114559306691 ps
CPU time 57.32 seconds
Started Jan 17 02:04:45 PM PST 24
Finished Jan 17 02:05:43 PM PST 24
Peak memory 198588 kb
Host smart-631d273a-3857-44d9-92c2-84f2bd91b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314038968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2314038968
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.186943985
Short name T263
Test name
Test status
Simulation time 40162895005 ps
CPU time 15.97 seconds
Started Jan 17 02:04:48 PM PST 24
Finished Jan 17 02:05:04 PM PST 24
Peak memory 199600 kb
Host smart-6444d393-bb36-4556-869f-1904ded12b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186943985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.186943985
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2810321212
Short name T337
Test name
Test status
Simulation time 52764716692 ps
CPU time 28.96 seconds
Started Jan 17 02:04:46 PM PST 24
Finished Jan 17 02:05:16 PM PST 24
Peak memory 200284 kb
Host smart-8b4e6049-fb34-4fef-8628-10bbe4b1d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810321212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2810321212
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1108938696
Short name T753
Test name
Test status
Simulation time 28101529336 ps
CPU time 40.23 seconds
Started Jan 17 02:04:48 PM PST 24
Finished Jan 17 02:05:29 PM PST 24
Peak memory 200008 kb
Host smart-47891745-7c88-40ab-8d5d-2dfe3035d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108938696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1108938696
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3158881168
Short name T215
Test name
Test status
Simulation time 254861520694 ps
CPU time 100.08 seconds
Started Jan 17 02:04:46 PM PST 24
Finished Jan 17 02:06:27 PM PST 24
Peak memory 200152 kb
Host smart-df171398-7d18-4074-91e4-4a2e63a6aa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158881168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3158881168
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3713458696
Short name T1205
Test name
Test status
Simulation time 48370522008 ps
CPU time 34.26 seconds
Started Jan 17 02:04:47 PM PST 24
Finished Jan 17 02:05:22 PM PST 24
Peak memory 200080 kb
Host smart-f59eefeb-1dac-4c65-9bdd-5766ea034883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713458696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3713458696
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2448033190
Short name T804
Test name
Test status
Simulation time 132625759626 ps
CPU time 151.92 seconds
Started Jan 17 02:04:43 PM PST 24
Finished Jan 17 02:07:16 PM PST 24
Peak memory 200224 kb
Host smart-97939ce5-941c-41c3-afa8-7ed588f04b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448033190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2448033190
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2588545050
Short name T193
Test name
Test status
Simulation time 110253253684 ps
CPU time 42.66 seconds
Started Jan 17 02:04:47 PM PST 24
Finished Jan 17 02:05:30 PM PST 24
Peak memory 200252 kb
Host smart-6348d3d0-4509-40d3-acd5-e936b8e05cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588545050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2588545050
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4213302986
Short name T101
Test name
Test status
Simulation time 50456392 ps
CPU time 0.54 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:36 PM PST 24
Peak memory 195668 kb
Host smart-a80d707b-c4b6-4f7e-a48c-f9a0dd64c134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213302986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4213302986
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2262591407
Short name T637
Test name
Test status
Simulation time 116798375859 ps
CPU time 165.5 seconds
Started Jan 17 02:00:38 PM PST 24
Finished Jan 17 02:03:26 PM PST 24
Peak memory 200260 kb
Host smart-3e6e5c2e-f503-495e-926b-3d771776c8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262591407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2262591407
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2520533285
Short name T977
Test name
Test status
Simulation time 50900201344 ps
CPU time 43.3 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:01:05 PM PST 24
Peak memory 200224 kb
Host smart-23cec5b7-8051-439f-ac92-f11e19c71134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520533285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2520533285
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3269526036
Short name T963
Test name
Test status
Simulation time 25700773945 ps
CPU time 44.47 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:01:07 PM PST 24
Peak memory 200204 kb
Host smart-f29b0537-9fb6-4fbb-bb01-d3ae1f430827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269526036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3269526036
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1345173261
Short name T781
Test name
Test status
Simulation time 1011484871260 ps
CPU time 416.75 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:07:19 PM PST 24
Peak memory 200024 kb
Host smart-811fe058-5668-43bb-ac3c-aa78589de79e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345173261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1345173261
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2508082610
Short name T538
Test name
Test status
Simulation time 109218697787 ps
CPU time 324.55 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:05:47 PM PST 24
Peak memory 200248 kb
Host smart-db20b113-925b-4ea5-8ead-6a6b413fb10c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508082610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2508082610
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3263552550
Short name T1032
Test name
Test status
Simulation time 8414112658 ps
CPU time 4.31 seconds
Started Jan 17 02:00:24 PM PST 24
Finished Jan 17 02:00:35 PM PST 24
Peak memory 198352 kb
Host smart-2d7706da-2e7f-41a1-b27f-e414d17b67ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263552550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3263552550
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2088440696
Short name T808
Test name
Test status
Simulation time 90586406983 ps
CPU time 167.68 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:03:23 PM PST 24
Peak memory 208656 kb
Host smart-9e4d307e-dba7-4a54-8387-b604e1f91f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088440696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2088440696
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3446590535
Short name T1197
Test name
Test status
Simulation time 149890881539 ps
CPU time 73.25 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:01:46 PM PST 24
Peak memory 199420 kb
Host smart-4075ce64-08b5-41e2-93ef-307aa84a060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446590535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3446590535
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3584146984
Short name T986
Test name
Test status
Simulation time 34860042440 ps
CPU time 13.12 seconds
Started Jan 17 02:00:25 PM PST 24
Finished Jan 17 02:00:44 PM PST 24
Peak memory 196124 kb
Host smart-5dd84f00-ec42-4ea0-a891-a161970f4f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584146984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3584146984
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.323617157
Short name T777
Test name
Test status
Simulation time 248797858 ps
CPU time 2.16 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:00:42 PM PST 24
Peak memory 198584 kb
Host smart-a48cf8dc-6279-453f-9b4a-94c2bb34f0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323617157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.323617157
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1049839368
Short name T1081
Test name
Test status
Simulation time 139941051160 ps
CPU time 216.03 seconds
Started Jan 17 02:00:26 PM PST 24
Finished Jan 17 02:04:07 PM PST 24
Peak memory 200468 kb
Host smart-08ec4fa0-3dc2-4823-881e-3ad727d71ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049839368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1049839368
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1832446801
Short name T648
Test name
Test status
Simulation time 75338493353 ps
CPU time 771.39 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:13:24 PM PST 24
Peak memory 225080 kb
Host smart-3940d658-0132-48c3-b11a-4779b9a548ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832446801 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1832446801
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1481304450
Short name T742
Test name
Test status
Simulation time 845556693 ps
CPU time 4.03 seconds
Started Jan 17 02:00:26 PM PST 24
Finished Jan 17 02:00:35 PM PST 24
Peak memory 198648 kb
Host smart-2bbad527-d768-4a58-adb5-1806b43921b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481304450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1481304450
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.71961680
Short name T1083
Test name
Test status
Simulation time 37213438701 ps
CPU time 15.98 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:52 PM PST 24
Peak memory 200268 kb
Host smart-9d238e6b-0e50-4896-834f-e4808ac74b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71961680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.71961680
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2090883397
Short name T958
Test name
Test status
Simulation time 30369528578 ps
CPU time 14.7 seconds
Started Jan 17 02:04:49 PM PST 24
Finished Jan 17 02:05:05 PM PST 24
Peak memory 200248 kb
Host smart-47596f8b-aabe-46ff-b433-8da2a30e63cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090883397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2090883397
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4249000022
Short name T144
Test name
Test status
Simulation time 221051427392 ps
CPU time 59.38 seconds
Started Jan 17 02:04:49 PM PST 24
Finished Jan 17 02:05:49 PM PST 24
Peak memory 200276 kb
Host smart-53637bb7-6ed8-4185-898a-6b2549be1d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249000022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4249000022
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2345473641
Short name T231
Test name
Test status
Simulation time 23938720746 ps
CPU time 44.74 seconds
Started Jan 17 02:04:55 PM PST 24
Finished Jan 17 02:05:41 PM PST 24
Peak memory 200208 kb
Host smart-d432e572-3f03-4986-ad39-d3208d9530f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345473641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2345473641
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.314165644
Short name T362
Test name
Test status
Simulation time 11267546233 ps
CPU time 11.96 seconds
Started Jan 17 02:04:55 PM PST 24
Finished Jan 17 02:05:08 PM PST 24
Peak memory 200168 kb
Host smart-aac0366c-b07c-49aa-ad98-82a2a8beec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314165644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.314165644
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2711719501
Short name T766
Test name
Test status
Simulation time 56961862527 ps
CPU time 136.46 seconds
Started Jan 17 02:04:58 PM PST 24
Finished Jan 17 02:07:18 PM PST 24
Peak memory 200236 kb
Host smart-97114ac2-9d4c-40b7-913a-64f453222ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711719501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2711719501
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.4014601972
Short name T664
Test name
Test status
Simulation time 41392153454 ps
CPU time 17.12 seconds
Started Jan 17 02:04:57 PM PST 24
Finished Jan 17 02:05:18 PM PST 24
Peak memory 200272 kb
Host smart-665c5295-ffb8-412d-aa73-9dc396ed1fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014601972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4014601972
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2019685119
Short name T216
Test name
Test status
Simulation time 56989331977 ps
CPU time 23.93 seconds
Started Jan 17 02:05:00 PM PST 24
Finished Jan 17 02:05:29 PM PST 24
Peak memory 200252 kb
Host smart-52d5abbe-6d05-4669-85b3-31345f317908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019685119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2019685119
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3942629134
Short name T171
Test name
Test status
Simulation time 12284818511 ps
CPU time 7.81 seconds
Started Jan 17 02:04:56 PM PST 24
Finished Jan 17 02:05:06 PM PST 24
Peak memory 200256 kb
Host smart-f4649b65-34b0-488d-bf49-680fe5c1f2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942629134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3942629134
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3180528454
Short name T495
Test name
Test status
Simulation time 38161535 ps
CPU time 0.55 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:00:33 PM PST 24
Peak memory 195600 kb
Host smart-d1ee5a2c-3f5d-453b-b541-9d58cde986b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180528454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3180528454
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.764205972
Short name T811
Test name
Test status
Simulation time 278362836118 ps
CPU time 124.75 seconds
Started Jan 17 02:00:04 PM PST 24
Finished Jan 17 02:02:10 PM PST 24
Peak memory 200148 kb
Host smart-5812ccef-45a7-4fb8-905f-7abd90389327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764205972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.764205972
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2636168770
Short name T1100
Test name
Test status
Simulation time 33137783818 ps
CPU time 8.75 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:00:40 PM PST 24
Peak memory 198028 kb
Host smart-fd05fee3-40ef-4795-8a82-1e99f468f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636168770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2636168770
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4120341729
Short name T571
Test name
Test status
Simulation time 138019375200 ps
CPU time 45.47 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:01:25 PM PST 24
Peak memory 200232 kb
Host smart-8786d413-aa05-4000-a254-f8c39718ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120341729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4120341729
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3363411250
Short name T573
Test name
Test status
Simulation time 1361154101883 ps
CPU time 1188.16 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:20:20 PM PST 24
Peak memory 199544 kb
Host smart-3275a339-f39c-40a8-9eff-7f493e4e482b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363411250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3363411250
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1234311569
Short name T949
Test name
Test status
Simulation time 216931770203 ps
CPU time 299.95 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:05:32 PM PST 24
Peak memory 200180 kb
Host smart-43d1e1fc-dc98-48a8-9276-7fcc401b1108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234311569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1234311569
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2642591394
Short name T1211
Test name
Test status
Simulation time 6053184426 ps
CPU time 10.12 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:46 PM PST 24
Peak memory 198512 kb
Host smart-55ebec70-8137-4280-bf21-e701b7fd9c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642591394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2642591394
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1345098045
Short name T918
Test name
Test status
Simulation time 80406604364 ps
CPU time 148.27 seconds
Started Jan 17 02:00:33 PM PST 24
Finished Jan 17 02:03:07 PM PST 24
Peak memory 200048 kb
Host smart-2c399002-c148-4b77-afcf-c8b62f2b07c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345098045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1345098045
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1794080911
Short name T1134
Test name
Test status
Simulation time 21860334732 ps
CPU time 308.62 seconds
Started Jan 17 02:00:41 PM PST 24
Finished Jan 17 02:05:55 PM PST 24
Peak memory 200144 kb
Host smart-635566c6-0945-4b95-bca2-92e296a10043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794080911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1794080911
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1565551418
Short name T1218
Test name
Test status
Simulation time 1256920818 ps
CPU time 6.32 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 198408 kb
Host smart-9ffea6a2-7462-412b-9c76-6caaea6c6d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565551418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1565551418
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2370833609
Short name T872
Test name
Test status
Simulation time 13081235077 ps
CPU time 6.14 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 199312 kb
Host smart-9650762d-507a-455e-b9a6-d730f730b403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370833609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2370833609
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3504570
Short name T1208
Test name
Test status
Simulation time 4054186866 ps
CPU time 2.25 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:00:34 PM PST 24
Peak memory 195980 kb
Host smart-9ed27d1c-fab2-4ffa-86aa-0205f381acf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3504570
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3129241357
Short name T591
Test name
Test status
Simulation time 449795771 ps
CPU time 2.06 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 198056 kb
Host smart-3db3958d-fd8a-4ba0-856c-015c62d3fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129241357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3129241357
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1758206497
Short name T1054
Test name
Test status
Simulation time 548745465607 ps
CPU time 313.25 seconds
Started Jan 17 02:00:35 PM PST 24
Finished Jan 17 02:05:53 PM PST 24
Peak memory 200196 kb
Host smart-2e13764a-5428-4eb1-90da-44e63bd1ac5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758206497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1758206497
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1932988433
Short name T631
Test name
Test status
Simulation time 46675517721 ps
CPU time 128.28 seconds
Started Jan 17 02:00:41 PM PST 24
Finished Jan 17 02:02:55 PM PST 24
Peak memory 210808 kb
Host smart-e1afbb38-53de-43be-97d4-f6ca4949c1d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932988433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1932988433
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2193340082
Short name T1027
Test name
Test status
Simulation time 1418804746 ps
CPU time 2.9 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:39 PM PST 24
Peak memory 198816 kb
Host smart-e387f431-1276-4460-833d-70d85d3367d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193340082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2193340082
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.899069692
Short name T991
Test name
Test status
Simulation time 16211111410 ps
CPU time 6.85 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:00:39 PM PST 24
Peak memory 200248 kb
Host smart-cb4a208a-7f24-4833-94e3-8c44cc98b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899069692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.899069692
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1607857015
Short name T124
Test name
Test status
Simulation time 107649610791 ps
CPU time 174.88 seconds
Started Jan 17 02:05:04 PM PST 24
Finished Jan 17 02:08:01 PM PST 24
Peak memory 200264 kb
Host smart-2efebbfa-2f2b-42c3-896a-2532ea88c4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607857015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1607857015
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1790201854
Short name T626
Test name
Test status
Simulation time 17104143738 ps
CPU time 26.99 seconds
Started Jan 17 02:04:57 PM PST 24
Finished Jan 17 02:05:27 PM PST 24
Peak memory 200212 kb
Host smart-5786a961-283c-4cc7-b5e5-85d1cd1f7717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790201854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1790201854
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3602831638
Short name T181
Test name
Test status
Simulation time 50166669375 ps
CPU time 80.2 seconds
Started Jan 17 02:04:55 PM PST 24
Finished Jan 17 02:06:16 PM PST 24
Peak memory 200168 kb
Host smart-7156b9ff-0f8d-45b0-82d6-4cff3023a97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602831638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3602831638
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3583484431
Short name T288
Test name
Test status
Simulation time 24132734452 ps
CPU time 36.92 seconds
Started Jan 17 02:04:57 PM PST 24
Finished Jan 17 02:05:38 PM PST 24
Peak memory 200236 kb
Host smart-5eb2e095-fd7d-444d-bf45-bd9db0c0fb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583484431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3583484431
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2879238185
Short name T334
Test name
Test status
Simulation time 43652040280 ps
CPU time 23.37 seconds
Started Jan 17 02:04:56 PM PST 24
Finished Jan 17 02:05:20 PM PST 24
Peak memory 200212 kb
Host smart-5e1cbfd0-4d12-44f3-a250-197fd81ceabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879238185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2879238185
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.799963280
Short name T391
Test name
Test status
Simulation time 13051653951 ps
CPU time 39.53 seconds
Started Jan 17 02:04:55 PM PST 24
Finished Jan 17 02:05:36 PM PST 24
Peak memory 200216 kb
Host smart-db74aff0-4bf0-4e6d-876e-ab0fcc823989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799963280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.799963280
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3054443561
Short name T782
Test name
Test status
Simulation time 73960007062 ps
CPU time 34.22 seconds
Started Jan 17 02:04:56 PM PST 24
Finished Jan 17 02:05:33 PM PST 24
Peak memory 199284 kb
Host smart-39e578df-53e7-423a-9276-11aa366e5053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054443561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3054443561
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1693668107
Short name T964
Test name
Test status
Simulation time 19886428996 ps
CPU time 11.11 seconds
Started Jan 17 02:04:56 PM PST 24
Finished Jan 17 02:05:10 PM PST 24
Peak memory 200132 kb
Host smart-b22118fe-e3b6-4a79-a6ce-55cb623103c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693668107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1693668107
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2118324439
Short name T353
Test name
Test status
Simulation time 125148375922 ps
CPU time 59.34 seconds
Started Jan 17 02:04:59 PM PST 24
Finished Jan 17 02:06:04 PM PST 24
Peak memory 199888 kb
Host smart-3f9cfef6-5ef5-459b-b777-38230455a97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118324439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2118324439
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.788676213
Short name T599
Test name
Test status
Simulation time 11722074 ps
CPU time 0.56 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:00:23 PM PST 24
Peak memory 195668 kb
Host smart-f03d3866-984e-492e-8eda-ff6c49781500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788676213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.788676213
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2159593589
Short name T1216
Test name
Test status
Simulation time 239714522483 ps
CPU time 399.99 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:07:16 PM PST 24
Peak memory 200244 kb
Host smart-33f12581-001f-41de-8f04-a05ac853bbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159593589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2159593589
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1098510291
Short name T1051
Test name
Test status
Simulation time 68935797510 ps
CPU time 113.89 seconds
Started Jan 17 02:00:32 PM PST 24
Finished Jan 17 02:02:30 PM PST 24
Peak memory 200212 kb
Host smart-608c6976-3810-4738-a7c1-8d113dec7618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098510291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1098510291
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1368216225
Short name T151
Test name
Test status
Simulation time 138242689188 ps
CPU time 21.52 seconds
Started Jan 17 02:00:37 PM PST 24
Finished Jan 17 02:01:01 PM PST 24
Peak memory 200216 kb
Host smart-54f6cbac-a78a-4e47-98ec-13b3cc6607cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368216225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1368216225
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3668942979
Short name T1234
Test name
Test status
Simulation time 70021689250 ps
CPU time 82.29 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:02:02 PM PST 24
Peak memory 199940 kb
Host smart-511beabb-cf78-47e7-8a60-b9fc67bbc884
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668942979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3668942979
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2483040773
Short name T497
Test name
Test status
Simulation time 194144297985 ps
CPU time 120.61 seconds
Started Jan 17 02:00:37 PM PST 24
Finished Jan 17 02:02:41 PM PST 24
Peak memory 200164 kb
Host smart-88809676-f145-46ba-aafa-0229d789e1da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483040773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2483040773
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.78193353
Short name T525
Test name
Test status
Simulation time 4456144892 ps
CPU time 7.55 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:00:47 PM PST 24
Peak memory 199216 kb
Host smart-32858960-100f-466c-8d88-37756d70ef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78193353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.78193353
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.790052433
Short name T132
Test name
Test status
Simulation time 150007481186 ps
CPU time 65.57 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:01:45 PM PST 24
Peak memory 199440 kb
Host smart-54021cb6-556c-415e-8500-f93a02f228a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790052433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.790052433
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1966481316
Short name T758
Test name
Test status
Simulation time 127027557217 ps
CPU time 197.88 seconds
Started Jan 17 02:00:37 PM PST 24
Finished Jan 17 02:03:58 PM PST 24
Peak memory 200080 kb
Host smart-ec361ded-dac7-4e8a-80be-531eb2216b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966481316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1966481316
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.745305252
Short name T1186
Test name
Test status
Simulation time 4222629891 ps
CPU time 2.14 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:00:42 PM PST 24
Peak memory 195920 kb
Host smart-a05416f8-57fd-4537-b902-56f502a1a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745305252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.745305252
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2216487788
Short name T1182
Test name
Test status
Simulation time 295532906 ps
CPU time 1.7 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:36 PM PST 24
Peak memory 198480 kb
Host smart-89dbb11f-ffc7-49a2-9cc5-05a08de0c4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216487788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2216487788
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3538320163
Short name T167
Test name
Test status
Simulation time 234944314335 ps
CPU time 201.82 seconds
Started Jan 17 02:00:35 PM PST 24
Finished Jan 17 02:04:01 PM PST 24
Peak memory 200112 kb
Host smart-ce3af99e-0079-4bbf-8cb1-730a8df8b023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538320163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3538320163
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3136577582
Short name T928
Test name
Test status
Simulation time 43568784653 ps
CPU time 591.32 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:10:31 PM PST 24
Peak memory 203692 kb
Host smart-fb149305-c3b7-4b33-a781-7d9a770e2151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136577582 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3136577582
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1409728767
Short name T1178
Test name
Test status
Simulation time 447742303 ps
CPU time 1.64 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:00:41 PM PST 24
Peak memory 198436 kb
Host smart-a1b02012-4e54-4b51-b9e8-45bf9563a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409728767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1409728767
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.949642101
Short name T745
Test name
Test status
Simulation time 23433551995 ps
CPU time 39.22 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:01:19 PM PST 24
Peak memory 200268 kb
Host smart-2bed9061-bca3-454a-bfdc-4e22e0f9c1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949642101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.949642101
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2945229631
Short name T336
Test name
Test status
Simulation time 37164726869 ps
CPU time 16.28 seconds
Started Jan 17 02:04:55 PM PST 24
Finished Jan 17 02:05:12 PM PST 24
Peak memory 199532 kb
Host smart-fc3acfaf-b0c9-44d0-979b-d17795dcc86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945229631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2945229631
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3833162923
Short name T1130
Test name
Test status
Simulation time 144226085446 ps
CPU time 595.69 seconds
Started Jan 17 02:04:58 PM PST 24
Finished Jan 17 02:14:57 PM PST 24
Peak memory 200256 kb
Host smart-47b67c1a-5aa8-4b85-91f4-0e5d9bca0451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833162923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3833162923
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.876347225
Short name T564
Test name
Test status
Simulation time 49671077868 ps
CPU time 18.09 seconds
Started Jan 17 02:04:57 PM PST 24
Finished Jan 17 02:05:19 PM PST 24
Peak memory 197836 kb
Host smart-ca8c44d3-3873-421a-892c-40c0c3e7fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876347225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.876347225
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2454226708
Short name T965
Test name
Test status
Simulation time 4441013077 ps
CPU time 7.85 seconds
Started Jan 17 02:04:58 PM PST 24
Finished Jan 17 02:05:09 PM PST 24
Peak memory 199224 kb
Host smart-192e4586-7760-44b1-9fd5-e0308be1a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454226708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2454226708
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3456823441
Short name T316
Test name
Test status
Simulation time 109912690306 ps
CPU time 24.18 seconds
Started Jan 17 02:04:59 PM PST 24
Finished Jan 17 02:05:29 PM PST 24
Peak memory 198788 kb
Host smart-304a75ab-ab1d-4d67-8830-0ee019d8eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456823441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3456823441
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1744289392
Short name T252
Test name
Test status
Simulation time 47962854757 ps
CPU time 41.8 seconds
Started Jan 17 02:05:03 PM PST 24
Finished Jan 17 02:05:47 PM PST 24
Peak memory 199808 kb
Host smart-e2e49921-8750-4ce1-97df-5ec9e02d0b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744289392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1744289392
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.778538405
Short name T122
Test name
Test status
Simulation time 159354867375 ps
CPU time 52.8 seconds
Started Jan 17 02:05:06 PM PST 24
Finished Jan 17 02:06:00 PM PST 24
Peak memory 200248 kb
Host smart-2a29bd74-789e-467a-8161-9a01ab8e723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778538405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.778538405
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3839514297
Short name T1191
Test name
Test status
Simulation time 77548033354 ps
CPU time 191.34 seconds
Started Jan 17 02:05:07 PM PST 24
Finished Jan 17 02:08:19 PM PST 24
Peak memory 200448 kb
Host smart-3f844a14-f3d8-48ca-8500-3c205f6ee182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839514297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3839514297
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3757405462
Short name T246
Test name
Test status
Simulation time 153178474152 ps
CPU time 218.65 seconds
Started Jan 17 02:05:06 PM PST 24
Finished Jan 17 02:08:46 PM PST 24
Peak memory 200248 kb
Host smart-c0b1a959-c439-40cc-af42-437d883a502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757405462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3757405462
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4170782164
Short name T1192
Test name
Test status
Simulation time 12733537 ps
CPU time 0.56 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 01:55:00 PM PST 24
Peak memory 195656 kb
Host smart-2e42dbb8-616d-41ac-8ab2-509ff8ebb458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170782164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4170782164
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1212736241
Short name T430
Test name
Test status
Simulation time 70863569069 ps
CPU time 36.45 seconds
Started Jan 17 01:54:54 PM PST 24
Finished Jan 17 01:55:34 PM PST 24
Peak memory 200188 kb
Host smart-c96202a2-4614-4759-8a0e-574b2f9a9b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212736241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1212736241
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.648582546
Short name T790
Test name
Test status
Simulation time 59477926844 ps
CPU time 21.98 seconds
Started Jan 17 01:54:54 PM PST 24
Finished Jan 17 01:55:19 PM PST 24
Peak memory 199980 kb
Host smart-b4bdaa4e-fd7a-4624-8d35-317df6e27b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648582546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.648582546
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.620664726
Short name T435
Test name
Test status
Simulation time 60141660045 ps
CPU time 26.69 seconds
Started Jan 17 01:54:58 PM PST 24
Finished Jan 17 01:55:26 PM PST 24
Peak memory 200140 kb
Host smart-b480dc5b-6f7b-4692-9692-f4a0ea8d78b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620664726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.620664726
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3583395914
Short name T1046
Test name
Test status
Simulation time 80348971585 ps
CPU time 258.34 seconds
Started Jan 17 01:54:54 PM PST 24
Finished Jan 17 01:59:16 PM PST 24
Peak memory 200280 kb
Host smart-3b37c7a8-02d3-47ea-b3ca-ae99e98ebd20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583395914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3583395914
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1623103154
Short name T952
Test name
Test status
Simulation time 8651604341 ps
CPU time 15.91 seconds
Started Jan 17 01:55:00 PM PST 24
Finished Jan 17 01:55:17 PM PST 24
Peak memory 198252 kb
Host smart-06194d9a-8c0c-4bf6-bda6-407c3626eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623103154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1623103154
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3526825607
Short name T1099
Test name
Test status
Simulation time 91731457828 ps
CPU time 44.96 seconds
Started Jan 17 01:55:01 PM PST 24
Finished Jan 17 01:55:47 PM PST 24
Peak memory 200424 kb
Host smart-bab98994-18a5-4254-b3c7-a8dace84d20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526825607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3526825607
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3282917036
Short name T1109
Test name
Test status
Simulation time 10289318839 ps
CPU time 226.48 seconds
Started Jan 17 01:54:58 PM PST 24
Finished Jan 17 01:58:46 PM PST 24
Peak memory 200224 kb
Host smart-06e38015-847b-4d73-897c-5d50ce5e5d29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282917036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3282917036
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.4083633886
Short name T562
Test name
Test status
Simulation time 3037498448 ps
CPU time 21.78 seconds
Started Jan 17 01:54:58 PM PST 24
Finished Jan 17 01:55:21 PM PST 24
Peak memory 198396 kb
Host smart-2ccde3c4-dc0a-46e6-960b-71e645dd155e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083633886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.4083633886
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2154414338
Short name T1003
Test name
Test status
Simulation time 120002368373 ps
CPU time 159.48 seconds
Started Jan 17 01:54:54 PM PST 24
Finished Jan 17 01:57:37 PM PST 24
Peak memory 200380 kb
Host smart-0bf76148-c646-4a1d-ad81-8c368107007a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154414338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2154414338
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2656058269
Short name T916
Test name
Test status
Simulation time 571044984 ps
CPU time 1.49 seconds
Started Jan 17 01:54:57 PM PST 24
Finished Jan 17 01:55:00 PM PST 24
Peak memory 195664 kb
Host smart-af28369f-a76c-4500-917d-0c19380108ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656058269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2656058269
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3907146161
Short name T102
Test name
Test status
Simulation time 133738610 ps
CPU time 0.79 seconds
Started Jan 17 01:55:03 PM PST 24
Finished Jan 17 01:55:05 PM PST 24
Peak memory 217800 kb
Host smart-ddb93ff0-11d2-428d-9c5f-e29283e3f8bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907146161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3907146161
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.4184197352
Short name T598
Test name
Test status
Simulation time 108464264 ps
CPU time 0.99 seconds
Started Jan 17 01:55:01 PM PST 24
Finished Jan 17 01:55:03 PM PST 24
Peak memory 198104 kb
Host smart-a50cbf8d-278b-4da8-a4bf-7ade9748168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184197352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4184197352
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2341257219
Short name T979
Test name
Test status
Simulation time 28123791506 ps
CPU time 327.92 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 02:00:28 PM PST 24
Peak memory 208596 kb
Host smart-d0953ddf-03b9-4849-8e04-fd275c249956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341257219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2341257219
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2676404777
Short name T574
Test name
Test status
Simulation time 966674418 ps
CPU time 1.62 seconds
Started Jan 17 01:54:58 PM PST 24
Finished Jan 17 01:55:01 PM PST 24
Peak memory 198532 kb
Host smart-e0e742f0-5fdf-494a-9aae-1df679aea15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676404777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2676404777
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2875457831
Short name T882
Test name
Test status
Simulation time 59018511867 ps
CPU time 174.38 seconds
Started Jan 17 01:54:53 PM PST 24
Finished Jan 17 01:57:48 PM PST 24
Peak memory 200280 kb
Host smart-90a185d2-2e30-4216-8c05-32fe7f4dc56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875457831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2875457831
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2506139496
Short name T524
Test name
Test status
Simulation time 20056303 ps
CPU time 0.56 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:00:32 PM PST 24
Peak memory 195644 kb
Host smart-b7971c40-5483-4aee-a502-f402b45bb4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506139496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2506139496
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.4052401051
Short name T921
Test name
Test status
Simulation time 117159757518 ps
CPU time 177.77 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:03:20 PM PST 24
Peak memory 200296 kb
Host smart-aa86728f-e04f-4e62-8740-f809b2ad0ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052401051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.4052401051
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3678318257
Short name T967
Test name
Test status
Simulation time 252166070102 ps
CPU time 23.3 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:57 PM PST 24
Peak memory 200196 kb
Host smart-ebbdcab6-9d1a-452f-9723-95a2c77640f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678318257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3678318257
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1048553044
Short name T270
Test name
Test status
Simulation time 22138657128 ps
CPU time 8.71 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:00:31 PM PST 24
Peak memory 200236 kb
Host smart-0c2fc39a-ba37-4419-b0e7-2f5835ad8066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048553044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1048553044
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.210478857
Short name T726
Test name
Test status
Simulation time 40372820300 ps
CPU time 42.91 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:01:05 PM PST 24
Peak memory 199484 kb
Host smart-9591ff02-81e6-470b-a900-365725a5eee8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210478857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.210478857
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3555880490
Short name T549
Test name
Test status
Simulation time 89418713166 ps
CPU time 530.35 seconds
Started Jan 17 01:59:43 PM PST 24
Finished Jan 17 02:08:38 PM PST 24
Peak memory 200240 kb
Host smart-3756551e-add8-4c44-a8b5-a1f81666a826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3555880490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3555880490
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1934383188
Short name T876
Test name
Test status
Simulation time 6388570762 ps
CPU time 1.73 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:00:33 PM PST 24
Peak memory 198032 kb
Host smart-6dae78b4-68cc-42be-84d4-e8d01fa179c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934383188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1934383188
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1129232210
Short name T614
Test name
Test status
Simulation time 71305211248 ps
CPU time 74.39 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:01:36 PM PST 24
Peak memory 199736 kb
Host smart-35055c94-07a1-45b4-9fe3-ec62c2be98f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129232210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1129232210
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.252808872
Short name T755
Test name
Test status
Simulation time 20555041280 ps
CPU time 175.84 seconds
Started Jan 17 01:59:40 PM PST 24
Finished Jan 17 02:02:43 PM PST 24
Peak memory 200284 kb
Host smart-a5e69cee-2d43-47f7-8fe5-918136c8ad31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252808872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.252808872
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1357799912
Short name T962
Test name
Test status
Simulation time 3062500433 ps
CPU time 5.57 seconds
Started Jan 17 02:00:19 PM PST 24
Finished Jan 17 02:00:27 PM PST 24
Peak memory 198588 kb
Host smart-cd8db158-6ab8-4af7-9e2f-1e694cad7a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357799912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1357799912
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.862988021
Short name T311
Test name
Test status
Simulation time 62044985847 ps
CPU time 24.35 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:00:46 PM PST 24
Peak memory 199400 kb
Host smart-ffcd0f4a-ef65-4fbb-866c-dd5f563afcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862988021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.862988021
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3968429971
Short name T988
Test name
Test status
Simulation time 3180012380 ps
CPU time 1.72 seconds
Started Jan 17 02:00:25 PM PST 24
Finished Jan 17 02:00:33 PM PST 24
Peak memory 195740 kb
Host smart-5fb10ee6-f6c0-48f5-a563-0e933c90f442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968429971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3968429971
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3807485018
Short name T507
Test name
Test status
Simulation time 448289676 ps
CPU time 2.21 seconds
Started Jan 17 02:00:32 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 199572 kb
Host smart-b82e288c-f2e1-40b7-bfc2-4c943b110741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807485018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3807485018
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2358575918
Short name T655
Test name
Test status
Simulation time 2804526202 ps
CPU time 3.39 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:00:35 PM PST 24
Peak memory 198912 kb
Host smart-6346e8e1-00ec-4805-bda8-0fb2fc3b8cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358575918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2358575918
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3266085161
Short name T563
Test name
Test status
Simulation time 214816178294 ps
CPU time 131.9 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:02:45 PM PST 24
Peak memory 200212 kb
Host smart-aee3aa3c-6ded-4f91-8928-54c712a3cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266085161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3266085161
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1977578513
Short name T1171
Test name
Test status
Simulation time 28236904 ps
CPU time 0.52 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:00:32 PM PST 24
Peak memory 194604 kb
Host smart-b6b38852-604b-4745-b88c-66fac39c1f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977578513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1977578513
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.412703100
Short name T696
Test name
Test status
Simulation time 89946026762 ps
CPU time 126.16 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:02:38 PM PST 24
Peak memory 200224 kb
Host smart-3bc76d4e-2c52-4a52-b3b1-52d9cd6c2485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412703100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.412703100
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.4025748354
Short name T689
Test name
Test status
Simulation time 176659806052 ps
CPU time 146.69 seconds
Started Jan 17 02:00:23 PM PST 24
Finished Jan 17 02:02:50 PM PST 24
Peak memory 199532 kb
Host smart-8e971aa2-d79c-4856-81ce-3a67814fd3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025748354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4025748354
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2564837234
Short name T835
Test name
Test status
Simulation time 6557436576 ps
CPU time 5.9 seconds
Started Jan 17 02:00:21 PM PST 24
Finished Jan 17 02:00:28 PM PST 24
Peak memory 198892 kb
Host smart-0df7e317-83b3-4e07-bb20-b26b83951b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564837234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2564837234
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1677941620
Short name T870
Test name
Test status
Simulation time 795160353092 ps
CPU time 1236.61 seconds
Started Jan 17 02:00:24 PM PST 24
Finished Jan 17 02:21:04 PM PST 24
Peak memory 199876 kb
Host smart-2561a6c9-46e9-4577-b062-dade81c6f8ea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677941620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1677941620
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1954996598
Short name T1029
Test name
Test status
Simulation time 123883586148 ps
CPU time 158.1 seconds
Started Jan 17 02:00:26 PM PST 24
Finished Jan 17 02:03:09 PM PST 24
Peak memory 200132 kb
Host smart-0f72c991-86f9-445f-8666-70324807890d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954996598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1954996598
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3450969290
Short name T527
Test name
Test status
Simulation time 4023480517 ps
CPU time 5.22 seconds
Started Jan 17 02:00:26 PM PST 24
Finished Jan 17 02:00:36 PM PST 24
Peak memory 199640 kb
Host smart-5b5d6db1-5730-4e09-8072-4bb2f80e2fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450969290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3450969290
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.681809067
Short name T440
Test name
Test status
Simulation time 31030892638 ps
CPU time 10.11 seconds
Started Jan 17 02:00:23 PM PST 24
Finished Jan 17 02:00:34 PM PST 24
Peak memory 196276 kb
Host smart-0205be00-c71e-4abc-bc69-c1c1ed9cf429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681809067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.681809067
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3126985126
Short name T550
Test name
Test status
Simulation time 39387419870 ps
CPU time 1996.16 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:33:48 PM PST 24
Peak memory 200172 kb
Host smart-ac5b415b-b894-4318-9664-c79c4aee246d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3126985126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3126985126
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3396946676
Short name T531
Test name
Test status
Simulation time 3487651231 ps
CPU time 35.4 seconds
Started Jan 17 02:00:24 PM PST 24
Finished Jan 17 02:00:59 PM PST 24
Peak memory 199080 kb
Host smart-b9d71739-ed09-49a6-b093-0aeeb7dbec36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396946676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3396946676
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.814890044
Short name T201
Test name
Test status
Simulation time 43708629909 ps
CPU time 65.38 seconds
Started Jan 17 02:00:33 PM PST 24
Finished Jan 17 02:01:44 PM PST 24
Peak memory 200220 kb
Host smart-c684e3b8-5bdd-4a8f-950d-210ccb777bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814890044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.814890044
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2909199792
Short name T555
Test name
Test status
Simulation time 26650384604 ps
CPU time 43.7 seconds
Started Jan 17 02:00:32 PM PST 24
Finished Jan 17 02:01:21 PM PST 24
Peak memory 196012 kb
Host smart-13c5e1d4-959d-4c59-a43b-a0346404fe91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909199792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2909199792
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2172442343
Short name T1038
Test name
Test status
Simulation time 303816021 ps
CPU time 1.03 seconds
Started Jan 17 02:00:36 PM PST 24
Finished Jan 17 02:00:41 PM PST 24
Peak memory 199252 kb
Host smart-0e1f1b5f-f45d-4536-bef8-1380efc2b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172442343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2172442343
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3030874895
Short name T629
Test name
Test status
Simulation time 903772034699 ps
CPU time 2062.35 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:34:54 PM PST 24
Peak memory 200196 kb
Host smart-44473e0b-eaf9-445c-8a39-6436a47422bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030874895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3030874895
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3839426431
Short name T547
Test name
Test status
Simulation time 7293606813 ps
CPU time 45.12 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:01:17 PM PST 24
Peak memory 200260 kb
Host smart-dada9981-ae10-453b-83ea-369f5d008670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839426431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3839426431
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.695638642
Short name T887
Test name
Test status
Simulation time 35480817875 ps
CPU time 23.88 seconds
Started Jan 17 02:00:23 PM PST 24
Finished Jan 17 02:00:47 PM PST 24
Peak memory 199936 kb
Host smart-caa8245f-c567-47c5-8158-7692a90f5c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695638642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.695638642
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3177584521
Short name T682
Test name
Test status
Simulation time 13198247 ps
CPU time 0.55 seconds
Started Jan 17 02:00:23 PM PST 24
Finished Jan 17 02:00:24 PM PST 24
Peak memory 195684 kb
Host smart-e7c68a2a-6684-4248-a1e8-4e38751b19f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177584521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3177584521
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4289438509
Short name T456
Test name
Test status
Simulation time 322975772003 ps
CPU time 135.75 seconds
Started Jan 17 02:00:28 PM PST 24
Finished Jan 17 02:02:47 PM PST 24
Peak memory 200224 kb
Host smart-1ceda9ca-4d93-480f-ae77-8c81ec947677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289438509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4289438509
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3659524885
Short name T757
Test name
Test status
Simulation time 17573492842 ps
CPU time 28.59 seconds
Started Jan 17 02:00:24 PM PST 24
Finished Jan 17 02:00:59 PM PST 24
Peak memory 199360 kb
Host smart-e3642faa-26d4-44bd-a6d3-3b59ca5a0fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659524885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3659524885
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.875624704
Short name T793
Test name
Test status
Simulation time 283745271647 ps
CPU time 109.73 seconds
Started Jan 17 02:00:22 PM PST 24
Finished Jan 17 02:02:13 PM PST 24
Peak memory 200180 kb
Host smart-14027f00-9fe7-43ab-8fe6-f10d51c2522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875624704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.875624704
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1644923632
Short name T733
Test name
Test status
Simulation time 908461714791 ps
CPU time 1631.28 seconds
Started Jan 17 02:00:26 PM PST 24
Finished Jan 17 02:27:42 PM PST 24
Peak memory 198776 kb
Host smart-15007e7d-86f5-45ae-9c66-4111c0e7db57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644923632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1644923632
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2771376920
Short name T842
Test name
Test status
Simulation time 139723598995 ps
CPU time 918.77 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:15:51 PM PST 24
Peak memory 200280 kb
Host smart-84b257b6-3754-44e0-be45-05459d327428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771376920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2771376920
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2239763047
Short name T863
Test name
Test status
Simulation time 3594646834 ps
CPU time 8.36 seconds
Started Jan 17 02:00:27 PM PST 24
Finished Jan 17 02:00:39 PM PST 24
Peak memory 199420 kb
Host smart-fb9dcd95-a450-43c0-b00e-6bc5f3b8e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239763047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2239763047
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1132924500
Short name T616
Test name
Test status
Simulation time 137598518989 ps
CPU time 66.71 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:01:38 PM PST 24
Peak memory 199684 kb
Host smart-5c494ddc-2882-4e7f-9a43-7e68ef623cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132924500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1132924500
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2979038256
Short name T565
Test name
Test status
Simulation time 21074370819 ps
CPU time 74.34 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:01:46 PM PST 24
Peak memory 200248 kb
Host smart-bf0b4d72-3637-4e22-aef1-fa46b0e7c7d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979038256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2979038256
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.598020248
Short name T990
Test name
Test status
Simulation time 3374314580 ps
CPU time 13.19 seconds
Started Jan 17 02:00:27 PM PST 24
Finished Jan 17 02:00:44 PM PST 24
Peak memory 197544 kb
Host smart-c4a2175c-fee6-4a31-b83e-8f21a4e90ccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598020248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.598020248
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.40424002
Short name T595
Test name
Test status
Simulation time 40041735107 ps
CPU time 75.32 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:01:51 PM PST 24
Peak memory 200176 kb
Host smart-631fb04f-e921-4fed-9e5d-2fa5dafd1123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40424002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.40424002
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.23157514
Short name T1105
Test name
Test status
Simulation time 2069224629 ps
CPU time 2.27 seconds
Started Jan 17 02:00:26 PM PST 24
Finished Jan 17 02:00:33 PM PST 24
Peak memory 195612 kb
Host smart-c4b74696-d6ee-4aaa-9fec-dedfb8e23a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23157514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.23157514
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.153985804
Short name T809
Test name
Test status
Simulation time 897795116 ps
CPU time 2.65 seconds
Started Jan 17 02:00:27 PM PST 24
Finished Jan 17 02:00:34 PM PST 24
Peak memory 199372 kb
Host smart-603bc6f3-b6e9-464d-935b-7f5a61aabb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153985804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.153985804
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2416289543
Short name T803
Test name
Test status
Simulation time 74233917694 ps
CPU time 1123.34 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:19:15 PM PST 24
Peak memory 216516 kb
Host smart-6a5e341c-d723-4821-9a40-8fa7d3eb8703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416289543 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2416289543
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1825887557
Short name T589
Test name
Test status
Simulation time 2723996979 ps
CPU time 2.09 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 198808 kb
Host smart-68d63bc1-285b-4643-9c98-d1a62e34f9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825887557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1825887557
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.4172300113
Short name T838
Test name
Test status
Simulation time 115111706011 ps
CPU time 139.66 seconds
Started Jan 17 02:00:26 PM PST 24
Finished Jan 17 02:02:51 PM PST 24
Peak memory 200172 kb
Host smart-85376383-7da0-4805-870b-7ae7da9f0b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172300113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4172300113
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3096649738
Short name T619
Test name
Test status
Simulation time 155846175 ps
CPU time 0.54 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:00:58 PM PST 24
Peak memory 194608 kb
Host smart-ecbe267d-ddf7-44c3-b08c-36291779e011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096649738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3096649738
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3942147135
Short name T640
Test name
Test status
Simulation time 38519966893 ps
CPU time 60.16 seconds
Started Jan 17 02:00:30 PM PST 24
Finished Jan 17 02:01:32 PM PST 24
Peak memory 199608 kb
Host smart-33f29e55-4f4a-4669-a6d3-3e253c97adf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942147135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3942147135
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1882254768
Short name T707
Test name
Test status
Simulation time 76811620295 ps
CPU time 141.1 seconds
Started Jan 17 02:00:27 PM PST 24
Finished Jan 17 02:02:52 PM PST 24
Peak memory 199724 kb
Host smart-2d5f4687-7844-470f-8b99-01d2a6b6df77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882254768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1882254768
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1672321259
Short name T1122
Test name
Test status
Simulation time 21862041948 ps
CPU time 26.43 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:01:01 PM PST 24
Peak memory 199772 kb
Host smart-33f4f507-7760-4bd2-9a97-e881e7359dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672321259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1672321259
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.3314925528
Short name T314
Test name
Test status
Simulation time 79125775729 ps
CPU time 604.39 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:11:05 PM PST 24
Peak memory 200164 kb
Host smart-4f6d43db-8c24-4bc6-8f22-d380fad81828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314925528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3314925528
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.350471739
Short name T1169
Test name
Test status
Simulation time 2068439099 ps
CPU time 1.06 seconds
Started Jan 17 02:00:39 PM PST 24
Finished Jan 17 02:00:46 PM PST 24
Peak memory 196964 kb
Host smart-a4a0469f-f30a-47b2-8901-d2f066968f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350471739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.350471739
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2793412830
Short name T413
Test name
Test status
Simulation time 136480300922 ps
CPU time 212.45 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:04:07 PM PST 24
Peak memory 200432 kb
Host smart-ce05e9a0-356b-4678-8fd0-ae75c2027fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793412830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2793412830
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.558912140
Short name T590
Test name
Test status
Simulation time 23134467771 ps
CPU time 1175.87 seconds
Started Jan 17 02:00:43 PM PST 24
Finished Jan 17 02:20:23 PM PST 24
Peak memory 199828 kb
Host smart-714624f9-3ad5-4707-85ec-0f05334e7bad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558912140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.558912140
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3272348718
Short name T895
Test name
Test status
Simulation time 2184706732 ps
CPU time 5.44 seconds
Started Jan 17 02:00:31 PM PST 24
Finished Jan 17 02:00:40 PM PST 24
Peak memory 198388 kb
Host smart-ffabedac-811c-4e16-a054-163c48dc0142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272348718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3272348718
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.990638305
Short name T734
Test name
Test status
Simulation time 36646810261 ps
CPU time 29.71 seconds
Started Jan 17 02:00:43 PM PST 24
Finished Jan 17 02:01:17 PM PST 24
Peak memory 198764 kb
Host smart-aae10a2b-5421-45de-90fb-e54c417917e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990638305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.990638305
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2481565196
Short name T1126
Test name
Test status
Simulation time 5691716892 ps
CPU time 8.8 seconds
Started Jan 17 02:00:37 PM PST 24
Finished Jan 17 02:00:49 PM PST 24
Peak memory 196060 kb
Host smart-073bbcae-1818-4769-bcba-e374dac6e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481565196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2481565196
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2178543979
Short name T922
Test name
Test status
Simulation time 6273161214 ps
CPU time 29.05 seconds
Started Jan 17 02:00:35 PM PST 24
Finished Jan 17 02:01:08 PM PST 24
Peak memory 199828 kb
Host smart-0ef53736-50cd-44a1-9ff0-1e99a008cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178543979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2178543979
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.396625531
Short name T367
Test name
Test status
Simulation time 593847997504 ps
CPU time 455.89 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:08:30 PM PST 24
Peak memory 200196 kb
Host smart-eff9fa6f-5983-40ed-80f2-a4013f97d818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396625531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.396625531
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1034146599
Short name T27
Test name
Test status
Simulation time 48002784141 ps
CPU time 413.76 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:07:51 PM PST 24
Peak memory 215812 kb
Host smart-0d0e9c97-0114-444d-bf5f-a3771b2c2a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034146599 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1034146599
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3570168183
Short name T818
Test name
Test status
Simulation time 7029396552 ps
CPU time 15.72 seconds
Started Jan 17 02:00:43 PM PST 24
Finished Jan 17 02:01:03 PM PST 24
Peak memory 199652 kb
Host smart-d6cc8936-a701-44ae-b66e-f2456a3790a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570168183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3570168183
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2487684282
Short name T939
Test name
Test status
Simulation time 11127135728 ps
CPU time 18.88 seconds
Started Jan 17 02:00:29 PM PST 24
Finished Jan 17 02:00:51 PM PST 24
Peak memory 198104 kb
Host smart-1f90ee7d-10f8-49ec-bffb-b6aa95254a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487684282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2487684282
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1893030608
Short name T588
Test name
Test status
Simulation time 13869358 ps
CPU time 0.58 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:00:57 PM PST 24
Peak memory 195268 kb
Host smart-10274b3e-c623-4acf-b615-b8edd509a440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893030608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1893030608
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2048518802
Short name T441
Test name
Test status
Simulation time 56561160330 ps
CPU time 78.53 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:02:13 PM PST 24
Peak memory 200232 kb
Host smart-26349fad-3ffd-43fb-8e84-7f175fe1e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048518802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2048518802
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3561943321
Short name T125
Test name
Test status
Simulation time 174717336502 ps
CPU time 61.73 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:01:58 PM PST 24
Peak memory 200312 kb
Host smart-98e51618-6347-4a5f-af4a-b3b6a8bc25c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561943321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3561943321
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.860072482
Short name T174
Test name
Test status
Simulation time 14129805689 ps
CPU time 74.66 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:02:09 PM PST 24
Peak memory 200160 kb
Host smart-fe57888a-a7e6-4cf9-8f16-346349ad09e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860072482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.860072482
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.736086500
Short name T1177
Test name
Test status
Simulation time 229885450111 ps
CPU time 93.29 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:02:29 PM PST 24
Peak memory 199336 kb
Host smart-5a1ae852-8a15-4bae-a959-12da125f43f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736086500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.736086500
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2301144852
Short name T701
Test name
Test status
Simulation time 100924421258 ps
CPU time 253.69 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:05:14 PM PST 24
Peak memory 200272 kb
Host smart-cf8abdbb-2cce-4ce7-ba9d-069c7db1f58f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301144852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2301144852
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2250135064
Short name T1233
Test name
Test status
Simulation time 35796102864 ps
CPU time 21.26 seconds
Started Jan 17 02:00:51 PM PST 24
Finished Jan 17 02:01:15 PM PST 24
Peak memory 198876 kb
Host smart-73ddb502-17dc-4ffa-b091-73d9f30f1e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250135064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2250135064
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3004357252
Short name T1147
Test name
Test status
Simulation time 28490701333 ps
CPU time 354.57 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:06:54 PM PST 24
Peak memory 200256 kb
Host smart-49a375b9-b472-4a0f-aca9-cfe088fbe132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004357252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3004357252
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1545084454
Short name T713
Test name
Test status
Simulation time 1547781619 ps
CPU time 6.24 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:01:05 PM PST 24
Peak memory 198432 kb
Host smart-ab7f370f-19d9-450e-885f-7494f3fc4e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545084454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1545084454
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3831551056
Short name T182
Test name
Test status
Simulation time 157036903915 ps
CPU time 48.35 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:01:48 PM PST 24
Peak memory 200224 kb
Host smart-05ff1b7c-dd53-4918-a3fc-400ffeefd17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831551056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3831551056
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3554238878
Short name T833
Test name
Test status
Simulation time 3599346422 ps
CPU time 2.16 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:00:56 PM PST 24
Peak memory 195696 kb
Host smart-51348435-cf25-4927-9c1a-58f386d0212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554238878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3554238878
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3722927982
Short name T553
Test name
Test status
Simulation time 274140902 ps
CPU time 1.04 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:00:57 PM PST 24
Peak memory 198192 kb
Host smart-46e7c441-2f7c-4fed-8ca8-a049a8486d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722927982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3722927982
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3782333249
Short name T272
Test name
Test status
Simulation time 48901603989 ps
CPU time 21.89 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:01:16 PM PST 24
Peak memory 200200 kb
Host smart-4702d725-7627-4b19-8eb0-e19f20c934a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782333249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3782333249
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1431665690
Short name T869
Test name
Test status
Simulation time 616756177 ps
CPU time 1.98 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:00:56 PM PST 24
Peak memory 198988 kb
Host smart-9b2d8a62-b129-4c89-8454-3dc22c872b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431665690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1431665690
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.42146043
Short name T816
Test name
Test status
Simulation time 35215230321 ps
CPU time 33.45 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:01:33 PM PST 24
Peak memory 200232 kb
Host smart-3bb6ff95-d73b-45fa-814c-38be4c3a12e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42146043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.42146043
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.708238177
Short name T763
Test name
Test status
Simulation time 89760402 ps
CPU time 0.52 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:00:57 PM PST 24
Peak memory 195656 kb
Host smart-1a4debe9-fe40-4109-85c0-365622fd4c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708238177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.708238177
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.4082501225
Short name T1133
Test name
Test status
Simulation time 94414772065 ps
CPU time 11.83 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:01:05 PM PST 24
Peak memory 199820 kb
Host smart-84ed8f93-9722-4d91-b6fd-943fc07fb5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082501225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.4082501225
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.515676653
Short name T1221
Test name
Test status
Simulation time 12780792688 ps
CPU time 13.22 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:01:07 PM PST 24
Peak memory 199332 kb
Host smart-23cf367b-792b-44e3-b22e-a7eeea9756df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515676653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.515676653
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3104781367
Short name T214
Test name
Test status
Simulation time 6307428784 ps
CPU time 13.6 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:01:13 PM PST 24
Peak memory 199956 kb
Host smart-910b2a22-93aa-4044-b495-e859ce86b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104781367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3104781367
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.4015367882
Short name T946
Test name
Test status
Simulation time 20936864407 ps
CPU time 7.78 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:01:03 PM PST 24
Peak memory 196732 kb
Host smart-11ace8ca-09cf-4118-9328-ac19b32dd070
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015367882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.4015367882
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2685002357
Short name T542
Test name
Test status
Simulation time 95229337368 ps
CPU time 248.26 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:05:02 PM PST 24
Peak memory 200184 kb
Host smart-c4ee6323-2d80-49c8-a359-3ed6b6738e4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685002357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2685002357
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1801518905
Short name T807
Test name
Test status
Simulation time 6843702817 ps
CPU time 6.35 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:01:01 PM PST 24
Peak memory 197572 kb
Host smart-97854c0b-8fc3-49c5-8269-e9679419354d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801518905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1801518905
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2790104022
Short name T20
Test name
Test status
Simulation time 90475495065 ps
CPU time 43.98 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:01:38 PM PST 24
Peak memory 200060 kb
Host smart-7d867188-4ad4-4dac-bca2-fde98e2943bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790104022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2790104022
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1441664005
Short name T609
Test name
Test status
Simulation time 15494400325 ps
CPU time 172.48 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:03:53 PM PST 24
Peak memory 200176 kb
Host smart-5e7cc2d1-8155-4da4-b5b3-79f1911d23f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441664005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1441664005
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3287137333
Short name T551
Test name
Test status
Simulation time 2009090093 ps
CPU time 19.55 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:01:16 PM PST 24
Peak memory 197888 kb
Host smart-1ba449dd-43c5-4c3e-a921-701ad8956e9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287137333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3287137333
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2135962624
Short name T898
Test name
Test status
Simulation time 143313466011 ps
CPU time 41.67 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:01:39 PM PST 24
Peak memory 200236 kb
Host smart-179e12b4-ff77-46d6-accf-816b4c9e08aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135962624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2135962624
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1489565947
Short name T947
Test name
Test status
Simulation time 721666063 ps
CPU time 1.19 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:01:01 PM PST 24
Peak memory 195652 kb
Host smart-3553afad-5329-4761-8de6-b1ea0f74757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489565947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1489565947
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1616696572
Short name T1236
Test name
Test status
Simulation time 448286089 ps
CPU time 2 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:00:58 PM PST 24
Peak memory 198452 kb
Host smart-cd1933a0-7e4f-462c-a6e0-3342d35f8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616696572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1616696572
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3579036040
Short name T981
Test name
Test status
Simulation time 7183832625 ps
CPU time 210.56 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:04:26 PM PST 24
Peak memory 200340 kb
Host smart-4ccac406-460b-4a74-8596-8d597693616a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579036040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3579036040
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2322922851
Short name T1153
Test name
Test status
Simulation time 1092542342 ps
CPU time 1.58 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:01:02 PM PST 24
Peak memory 196648 kb
Host smart-be0bf3fd-4558-45a0-b4da-82af69a12025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322922851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2322922851
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3927458052
Short name T866
Test name
Test status
Simulation time 106969484384 ps
CPU time 130.07 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:03:05 PM PST 24
Peak memory 200212 kb
Host smart-45cbfa78-ab65-44b1-8f78-087ab3ae1b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927458052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3927458052
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1981431046
Short name T829
Test name
Test status
Simulation time 27149669 ps
CPU time 0.56 seconds
Started Jan 17 02:01:00 PM PST 24
Finished Jan 17 02:01:02 PM PST 24
Peak memory 195696 kb
Host smart-50686944-03af-4583-a823-aecfd191fd7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981431046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1981431046
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2450516653
Short name T116
Test name
Test status
Simulation time 149548806639 ps
CPU time 63.97 seconds
Started Jan 17 02:01:00 PM PST 24
Finished Jan 17 02:02:06 PM PST 24
Peak memory 200244 kb
Host smart-1f2719b1-63f1-4e15-9712-128415de3057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450516653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2450516653
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2930960165
Short name T879
Test name
Test status
Simulation time 16955298665 ps
CPU time 31.73 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:01:28 PM PST 24
Peak memory 200184 kb
Host smart-6a56bfd2-1937-4e9a-925d-67fe084e9aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930960165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2930960165
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3656193488
Short name T199
Test name
Test status
Simulation time 31134679609 ps
CPU time 32.67 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:01:32 PM PST 24
Peak memory 200284 kb
Host smart-005219b3-48a0-4730-9722-3150bbab49ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656193488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3656193488
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.4112964374
Short name T1085
Test name
Test status
Simulation time 58360423019 ps
CPU time 32 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:01:32 PM PST 24
Peak memory 200224 kb
Host smart-4be0018c-9eae-4af0-bbfe-e2fab82c423b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112964374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.4112964374
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2954658362
Short name T612
Test name
Test status
Simulation time 77033818712 ps
CPU time 407.95 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:07:42 PM PST 24
Peak memory 200224 kb
Host smart-ee97e80c-5634-4c71-b17a-f401ae4c2cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2954658362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2954658362
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.899967231
Short name T827
Test name
Test status
Simulation time 3665849342 ps
CPU time 6.32 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:01:06 PM PST 24
Peak memory 198156 kb
Host smart-4c5e1200-25c2-4188-bb35-8715631c5b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899967231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.899967231
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.13535955
Short name T1002
Test name
Test status
Simulation time 67938232363 ps
CPU time 60.17 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:01:54 PM PST 24
Peak memory 200020 kb
Host smart-ee2ed9fb-2170-495d-a378-e5ecdedb64de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13535955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.13535955
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3097613844
Short name T649
Test name
Test status
Simulation time 4323469135 ps
CPU time 241.16 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:05:02 PM PST 24
Peak memory 200224 kb
Host smart-767568f9-c419-4c0c-83f6-2351d9c238a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097613844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3097613844
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.897799245
Short name T493
Test name
Test status
Simulation time 3495213275 ps
CPU time 5.94 seconds
Started Jan 17 02:00:57 PM PST 24
Finished Jan 17 02:01:07 PM PST 24
Peak memory 198660 kb
Host smart-36f20b21-8616-44c9-bc49-80c896989a43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=897799245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.897799245
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1469930160
Short name T443
Test name
Test status
Simulation time 36489664232 ps
CPU time 31.73 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:01:27 PM PST 24
Peak memory 196096 kb
Host smart-e7ebf87c-bcb0-4d8b-b384-d12a0e57f3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469930160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1469930160
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1715649076
Short name T1146
Test name
Test status
Simulation time 534033034 ps
CPU time 2.59 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:00:59 PM PST 24
Peak memory 198132 kb
Host smart-62c6b1f2-20fa-43bb-8a62-6fce5851d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715649076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1715649076
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2768143975
Short name T873
Test name
Test status
Simulation time 159697617476 ps
CPU time 2264.54 seconds
Started Jan 17 02:01:00 PM PST 24
Finished Jan 17 02:38:47 PM PST 24
Peak memory 200256 kb
Host smart-dc113757-ef10-4fe0-ad0b-20f87bce1066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768143975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2768143975
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2250598134
Short name T254
Test name
Test status
Simulation time 25471813456 ps
CPU time 242.06 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:05:02 PM PST 24
Peak memory 211828 kb
Host smart-07e2245a-19e6-4013-8129-81527848429b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250598134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2250598134
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.4056156959
Short name T1096
Test name
Test status
Simulation time 1330611724 ps
CPU time 2.99 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:00:58 PM PST 24
Peak memory 198280 kb
Host smart-99d55f3f-73a6-47fd-86f9-3fe43e9c25c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056156959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.4056156959
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.281704187
Short name T969
Test name
Test status
Simulation time 216745082153 ps
CPU time 49.27 seconds
Started Jan 17 02:00:51 PM PST 24
Finished Jan 17 02:01:43 PM PST 24
Peak memory 200232 kb
Host smart-20c6faf9-c353-44ed-90bc-5121b09e529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281704187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.281704187
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.693518568
Short name T593
Test name
Test status
Simulation time 13504063 ps
CPU time 0.54 seconds
Started Jan 17 02:01:07 PM PST 24
Finished Jan 17 02:01:11 PM PST 24
Peak memory 194752 kb
Host smart-bd8ac381-00a2-41eb-97d4-eff2438384ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693518568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.693518568
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1655682921
Short name T1151
Test name
Test status
Simulation time 41638798233 ps
CPU time 37.67 seconds
Started Jan 17 02:00:52 PM PST 24
Finished Jan 17 02:01:31 PM PST 24
Peak memory 200232 kb
Host smart-85568dbe-9b23-4d9c-9147-2a4cd1cec2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655682921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1655682921
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.224475659
Short name T802
Test name
Test status
Simulation time 33595908226 ps
CPU time 35.23 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:01:33 PM PST 24
Peak memory 200084 kb
Host smart-17564ecb-5af8-402e-b758-b763dc2061f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224475659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.224475659
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1320749282
Short name T166
Test name
Test status
Simulation time 13172548304 ps
CPU time 22.43 seconds
Started Jan 17 02:01:01 PM PST 24
Finished Jan 17 02:01:24 PM PST 24
Peak memory 199996 kb
Host smart-b87c7034-4ab9-41db-b731-1ca0f6d9b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320749282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1320749282
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.580211191
Short name T1168
Test name
Test status
Simulation time 20678584344 ps
CPU time 29.63 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:01:29 PM PST 24
Peak memory 197868 kb
Host smart-fa376be9-8ff1-4cfc-992f-ce1331fdea21
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580211191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.580211191
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2501093089
Short name T1019
Test name
Test status
Simulation time 88337801702 ps
CPU time 499.87 seconds
Started Jan 17 02:01:04 PM PST 24
Finished Jan 17 02:09:25 PM PST 24
Peak memory 200276 kb
Host smart-19685972-1fe4-4151-96d9-b7409806d206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2501093089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2501093089
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1308996833
Short name T502
Test name
Test status
Simulation time 5476909516 ps
CPU time 12.25 seconds
Started Jan 17 02:01:04 PM PST 24
Finished Jan 17 02:01:17 PM PST 24
Peak memory 199480 kb
Host smart-4194fe8f-2440-45da-91f1-c8056aa98c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308996833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1308996833
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2137345390
Short name T1145
Test name
Test status
Simulation time 276593553 ps
CPU time 0.99 seconds
Started Jan 17 02:01:02 PM PST 24
Finished Jan 17 02:01:04 PM PST 24
Peak memory 193820 kb
Host smart-73b654c8-f2b2-450e-8d96-048022df3e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137345390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2137345390
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.761590904
Short name T592
Test name
Test status
Simulation time 16620320481 ps
CPU time 489.97 seconds
Started Jan 17 02:01:03 PM PST 24
Finished Jan 17 02:09:14 PM PST 24
Peak memory 200232 kb
Host smart-7bcc1eef-c111-4035-9422-eeb3079e74a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761590904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.761590904
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2610563804
Short name T920
Test name
Test status
Simulation time 2204112380 ps
CPU time 13.46 seconds
Started Jan 17 02:01:01 PM PST 24
Finished Jan 17 02:01:16 PM PST 24
Peak memory 198452 kb
Host smart-bb5b6479-3ef0-47ee-b37f-524ac6ed533b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610563804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2610563804
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3466242704
Short name T814
Test name
Test status
Simulation time 69787282095 ps
CPU time 58.64 seconds
Started Jan 17 02:01:03 PM PST 24
Finished Jan 17 02:02:02 PM PST 24
Peak memory 200316 kb
Host smart-ddadec9b-f59b-43ef-b247-82407c6b69a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466242704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3466242704
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3567127173
Short name T641
Test name
Test status
Simulation time 3867385209 ps
CPU time 7.37 seconds
Started Jan 17 02:01:04 PM PST 24
Finished Jan 17 02:01:12 PM PST 24
Peak memory 196044 kb
Host smart-bfb349c7-4a54-4141-96da-25415e623504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567127173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3567127173
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1667301332
Short name T929
Test name
Test status
Simulation time 666730256 ps
CPU time 2.32 seconds
Started Jan 17 02:00:54 PM PST 24
Finished Jan 17 02:01:00 PM PST 24
Peak memory 198052 kb
Host smart-b1fc8730-f0a9-4332-90ac-75440c9e5e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667301332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1667301332
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1738735457
Short name T1189
Test name
Test status
Simulation time 891386075713 ps
CPU time 383.34 seconds
Started Jan 17 02:01:10 PM PST 24
Finished Jan 17 02:07:37 PM PST 24
Peak memory 208624 kb
Host smart-f49d47c2-319e-4f6c-a01e-26406acbb6a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738735457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1738735457
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2226927991
Short name T751
Test name
Test status
Simulation time 48244675222 ps
CPU time 254.27 seconds
Started Jan 17 02:01:04 PM PST 24
Finished Jan 17 02:05:19 PM PST 24
Peak memory 212284 kb
Host smart-7a2076f4-cb4f-4e7c-9a81-7c7dd985eaf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226927991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2226927991
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3910262804
Short name T891
Test name
Test status
Simulation time 779964394 ps
CPU time 1.71 seconds
Started Jan 17 02:00:56 PM PST 24
Finished Jan 17 02:01:02 PM PST 24
Peak memory 200132 kb
Host smart-4225c85f-b9c2-4c0b-ad62-5ca91f4da860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910262804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3910262804
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1528259347
Short name T1188
Test name
Test status
Simulation time 19533849175 ps
CPU time 38.35 seconds
Started Jan 17 02:01:00 PM PST 24
Finished Jan 17 02:01:40 PM PST 24
Peak memory 200244 kb
Host smart-04a566e1-edf7-47dd-9390-f7ec39830b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528259347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1528259347
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2226725482
Short name T719
Test name
Test status
Simulation time 54421589 ps
CPU time 0.55 seconds
Started Jan 17 02:00:53 PM PST 24
Finished Jan 17 02:00:57 PM PST 24
Peak memory 195412 kb
Host smart-5926b44d-94c1-4e68-86c3-34d390766f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226725482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2226725482
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1670255661
Short name T237
Test name
Test status
Simulation time 63279491449 ps
CPU time 46.88 seconds
Started Jan 17 02:01:04 PM PST 24
Finished Jan 17 02:01:52 PM PST 24
Peak memory 200176 kb
Host smart-867c9c02-0e10-48c2-87e2-9607c0d518a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670255661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1670255661
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3882873261
Short name T750
Test name
Test status
Simulation time 124415595878 ps
CPU time 52.26 seconds
Started Jan 17 02:01:00 PM PST 24
Finished Jan 17 02:01:54 PM PST 24
Peak memory 200236 kb
Host smart-0ffcb5de-dd74-491b-8c7a-fc4bf689ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882873261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3882873261
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4267527658
Short name T702
Test name
Test status
Simulation time 50644303345 ps
CPU time 74.01 seconds
Started Jan 17 02:01:00 PM PST 24
Finished Jan 17 02:02:16 PM PST 24
Peak memory 199820 kb
Host smart-e40a3e4c-3308-4150-86c6-a1feba895082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267527658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4267527658
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2385482798
Short name T582
Test name
Test status
Simulation time 236172946458 ps
CPU time 323.75 seconds
Started Jan 17 02:01:15 PM PST 24
Finished Jan 17 02:06:55 PM PST 24
Peak memory 200220 kb
Host smart-0f03f5c4-3dd2-46a2-8d3e-fadb9559a887
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385482798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2385482798
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.416098273
Short name T436
Test name
Test status
Simulation time 113081319350 ps
CPU time 339.34 seconds
Started Jan 17 02:00:55 PM PST 24
Finished Jan 17 02:06:39 PM PST 24
Peak memory 200216 kb
Host smart-49c314c8-1758-4294-9045-0da3d6f426a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416098273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.416098273
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.853793641
Short name T1222
Test name
Test status
Simulation time 1839423725 ps
CPU time 3.6 seconds
Started Jan 17 02:01:15 PM PST 24
Finished Jan 17 02:01:34 PM PST 24
Peak memory 197016 kb
Host smart-42ce6a21-c005-485c-bec7-603f5d074e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853793641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.853793641
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3062824527
Short name T160
Test name
Test status
Simulation time 50186504675 ps
CPU time 87.26 seconds
Started Jan 17 02:01:05 PM PST 24
Finished Jan 17 02:02:33 PM PST 24
Peak memory 209300 kb
Host smart-131cd1ce-fba1-477d-81a9-8ffb19c915cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062824527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3062824527
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2090454616
Short name T605
Test name
Test status
Simulation time 17943969889 ps
CPU time 262.63 seconds
Started Jan 17 02:01:16 PM PST 24
Finished Jan 17 02:05:53 PM PST 24
Peak memory 200100 kb
Host smart-7d7d45d3-8572-422f-8d47-4b05577545f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090454616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2090454616
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2869245820
Short name T909
Test name
Test status
Simulation time 2103743050 ps
CPU time 21.57 seconds
Started Jan 17 02:01:13 PM PST 24
Finished Jan 17 02:01:51 PM PST 24
Peak memory 198356 kb
Host smart-938012e8-55ff-4dde-8ae2-7048c283504d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869245820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2869245820
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.371363079
Short name T398
Test name
Test status
Simulation time 34353993935 ps
CPU time 14.55 seconds
Started Jan 17 02:01:04 PM PST 24
Finished Jan 17 02:01:20 PM PST 24
Peak memory 198964 kb
Host smart-70be0d97-60b4-4f54-9578-c328c622bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371363079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.371363079
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3939244855
Short name T607
Test name
Test status
Simulation time 43483494731 ps
CPU time 14.64 seconds
Started Jan 17 02:01:16 PM PST 24
Finished Jan 17 02:01:45 PM PST 24
Peak memory 195856 kb
Host smart-592ab2f8-f3e0-45d5-b538-58eca07cf765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939244855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3939244855
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2158079095
Short name T1206
Test name
Test status
Simulation time 6048443352 ps
CPU time 13.9 seconds
Started Jan 17 02:01:07 PM PST 24
Finished Jan 17 02:01:25 PM PST 24
Peak memory 200212 kb
Host smart-0fedff71-eb41-4d35-b3fb-a029148b3225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158079095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2158079095
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3469699377
Short name T1024
Test name
Test status
Simulation time 1250622857 ps
CPU time 4.81 seconds
Started Jan 17 02:01:14 PM PST 24
Finished Jan 17 02:01:35 PM PST 24
Peak memory 198704 kb
Host smart-9ce5a1b3-2761-4c16-8aa5-c91d494c4dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469699377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3469699377
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2506124894
Short name T228
Test name
Test status
Simulation time 69692826989 ps
CPU time 28.18 seconds
Started Jan 17 02:01:14 PM PST 24
Finished Jan 17 02:01:59 PM PST 24
Peak memory 200164 kb
Host smart-762adbe0-53f1-4c23-a8e2-e030e6ad83ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506124894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2506124894
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2350086507
Short name T1220
Test name
Test status
Simulation time 20513159 ps
CPU time 0.54 seconds
Started Jan 17 02:01:23 PM PST 24
Finished Jan 17 02:01:33 PM PST 24
Peak memory 195628 kb
Host smart-35d84d86-f1f9-43e5-ae39-515331fb3633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350086507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2350086507
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.971931878
Short name T893
Test name
Test status
Simulation time 153036466375 ps
CPU time 149.77 seconds
Started Jan 17 02:01:06 PM PST 24
Finished Jan 17 02:03:37 PM PST 24
Peak memory 200252 kb
Host smart-dc0d49ad-260c-4ff0-9457-5e814900da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971931878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.971931878
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2796277397
Short name T1199
Test name
Test status
Simulation time 30139675072 ps
CPU time 14.04 seconds
Started Jan 17 02:01:07 PM PST 24
Finished Jan 17 02:01:24 PM PST 24
Peak memory 199632 kb
Host smart-6545d22b-8d0a-4b48-8237-ac2f2bee69a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796277397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2796277397
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1132585170
Short name T930
Test name
Test status
Simulation time 117553302944 ps
CPU time 197.95 seconds
Started Jan 17 02:01:16 PM PST 24
Finished Jan 17 02:04:49 PM PST 24
Peak memory 199876 kb
Host smart-eddeb007-56ad-4a81-97bf-1d2d96dfeef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132585170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1132585170
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2673779477
Short name T445
Test name
Test status
Simulation time 855709191388 ps
CPU time 448.96 seconds
Started Jan 17 02:01:06 PM PST 24
Finished Jan 17 02:08:37 PM PST 24
Peak memory 199796 kb
Host smart-31af81ba-38ea-4ae7-a91d-211e9cbe35a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673779477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2673779477
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2990431944
Short name T894
Test name
Test status
Simulation time 71181082911 ps
CPU time 458.8 seconds
Started Jan 17 02:01:17 PM PST 24
Finished Jan 17 02:09:10 PM PST 24
Peak memory 200280 kb
Host smart-b69142fa-2d45-4654-876b-f7bdc00ba3a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990431944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2990431944
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1781966908
Short name T957
Test name
Test status
Simulation time 5637452218 ps
CPU time 5.94 seconds
Started Jan 17 02:01:19 PM PST 24
Finished Jan 17 02:01:37 PM PST 24
Peak memory 198944 kb
Host smart-f39b28c8-6865-49b7-97e0-a5b7895a3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781966908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1781966908
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1941377337
Short name T980
Test name
Test status
Simulation time 9485841671 ps
CPU time 17 seconds
Started Jan 17 02:01:24 PM PST 24
Finished Jan 17 02:01:50 PM PST 24
Peak memory 198292 kb
Host smart-693536f0-00fc-4bef-a245-64ee89ad5ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941377337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1941377337
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2759842677
Short name T1162
Test name
Test status
Simulation time 4966446519 ps
CPU time 240.17 seconds
Started Jan 17 02:01:13 PM PST 24
Finished Jan 17 02:05:29 PM PST 24
Peak memory 200172 kb
Host smart-4eeb2043-eec7-4b3d-b27d-88fea49cd4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759842677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2759842677
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1881181257
Short name T674
Test name
Test status
Simulation time 3198803660 ps
CPU time 18.51 seconds
Started Jan 17 02:01:08 PM PST 24
Finished Jan 17 02:01:30 PM PST 24
Peak memory 198984 kb
Host smart-afe6ece6-3e74-4a92-8adb-1c201d62303d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881181257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1881181257
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1695917300
Short name T1068
Test name
Test status
Simulation time 20251171520 ps
CPU time 15.3 seconds
Started Jan 17 02:01:15 PM PST 24
Finished Jan 17 02:01:46 PM PST 24
Peak memory 200220 kb
Host smart-31ac9642-b90a-4b9c-98c4-f5106d48f496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695917300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1695917300
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2785793616
Short name T1041
Test name
Test status
Simulation time 4992436353 ps
CPU time 4.43 seconds
Started Jan 17 02:01:15 PM PST 24
Finished Jan 17 02:01:35 PM PST 24
Peak memory 196004 kb
Host smart-5d842d77-a550-4545-be99-881a95c85da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785793616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2785793616
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1593257768
Short name T1241
Test name
Test status
Simulation time 512178477 ps
CPU time 2.17 seconds
Started Jan 17 02:01:04 PM PST 24
Finished Jan 17 02:01:08 PM PST 24
Peak memory 198864 kb
Host smart-acff7731-f4e1-4b52-9e79-a68be86319f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593257768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1593257768
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1524159935
Short name T1012
Test name
Test status
Simulation time 193006770439 ps
CPU time 375.71 seconds
Started Jan 17 02:01:20 PM PST 24
Finished Jan 17 02:07:47 PM PST 24
Peak memory 199492 kb
Host smart-dc8ba0c9-2bd6-41b2-8ce7-899417f1e81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524159935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1524159935
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1872950665
Short name T650
Test name
Test status
Simulation time 771626791 ps
CPU time 2.96 seconds
Started Jan 17 02:01:17 PM PST 24
Finished Jan 17 02:01:34 PM PST 24
Peak memory 198336 kb
Host smart-4f1c99b4-6e21-4bc3-964d-bb684a8af2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872950665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1872950665
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1104137376
Short name T427
Test name
Test status
Simulation time 83439730789 ps
CPU time 59.52 seconds
Started Jan 17 02:01:07 PM PST 24
Finished Jan 17 02:02:11 PM PST 24
Peak memory 200192 kb
Host smart-5d912d95-6cd5-4bbf-8cbf-6b8c2b19fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104137376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1104137376
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2682931784
Short name T583
Test name
Test status
Simulation time 24253632 ps
CPU time 0.52 seconds
Started Jan 17 01:55:00 PM PST 24
Finished Jan 17 01:55:01 PM PST 24
Peak memory 194716 kb
Host smart-dbf8e2a2-4aa8-4544-b0dc-346e462d4344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682931784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2682931784
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3581812515
Short name T585
Test name
Test status
Simulation time 70721858122 ps
CPU time 102.68 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 01:56:43 PM PST 24
Peak memory 200216 kb
Host smart-073d0972-12bf-418f-9a9f-13cc24e99ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581812515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3581812515
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.332345666
Short name T313
Test name
Test status
Simulation time 54874705198 ps
CPU time 41.45 seconds
Started Jan 17 01:55:10 PM PST 24
Finished Jan 17 01:55:52 PM PST 24
Peak memory 200352 kb
Host smart-2bfe4ab8-f8b4-4de0-beff-72d62a071e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332345666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.332345666
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1005238338
Short name T1060
Test name
Test status
Simulation time 43336039657 ps
CPU time 71.25 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 01:56:11 PM PST 24
Peak memory 199768 kb
Host smart-7796cd11-a0fc-4cac-847d-cbb76d630cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005238338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1005238338
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.4105043380
Short name T1069
Test name
Test status
Simulation time 2605167900 ps
CPU time 1.32 seconds
Started Jan 17 01:55:10 PM PST 24
Finished Jan 17 01:55:12 PM PST 24
Peak memory 196172 kb
Host smart-4ae074fa-9f70-4358-a4c0-a7260ad200fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105043380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.4105043380
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1109219012
Short name T911
Test name
Test status
Simulation time 112883947792 ps
CPU time 235.96 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 01:58:56 PM PST 24
Peak memory 200280 kb
Host smart-596e3f01-53b1-485f-ad3a-db5e25d55f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109219012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1109219012
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2626944481
Short name T1225
Test name
Test status
Simulation time 2384665269 ps
CPU time 2.62 seconds
Started Jan 17 01:55:04 PM PST 24
Finished Jan 17 01:55:08 PM PST 24
Peak memory 198472 kb
Host smart-58270cef-b8f9-47c4-9a86-b3b4398cb8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626944481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2626944481
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2656633637
Short name T1163
Test name
Test status
Simulation time 78044658331 ps
CPU time 28.67 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 01:55:29 PM PST 24
Peak memory 199408 kb
Host smart-5253f870-56b9-450d-8dae-87171f0ecd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656633637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2656633637
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.739999243
Short name T269
Test name
Test status
Simulation time 20003825091 ps
CPU time 1207.34 seconds
Started Jan 17 01:55:02 PM PST 24
Finished Jan 17 02:15:10 PM PST 24
Peak memory 200284 kb
Host smart-2e505d6b-ec5e-4bb3-83d4-c90e19e1fc60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739999243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.739999243
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.247316428
Short name T1139
Test name
Test status
Simulation time 2146886970 ps
CPU time 6.63 seconds
Started Jan 17 01:55:11 PM PST 24
Finished Jan 17 01:55:18 PM PST 24
Peak memory 198524 kb
Host smart-1769e098-8547-4317-b688-670b858db2db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247316428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.247316428
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3674134869
Short name T1022
Test name
Test status
Simulation time 40778735633 ps
CPU time 62.18 seconds
Started Jan 17 01:55:01 PM PST 24
Finished Jan 17 01:56:04 PM PST 24
Peak memory 199496 kb
Host smart-79eeb935-bfaa-4676-922d-97732b00eff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674134869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3674134869
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.4100816824
Short name T526
Test name
Test status
Simulation time 47824674612 ps
CPU time 18.93 seconds
Started Jan 17 01:55:15 PM PST 24
Finished Jan 17 01:55:35 PM PST 24
Peak memory 196124 kb
Host smart-be3f3c27-8ba7-4b5b-a60c-a0b331dd5f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100816824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.4100816824
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2948614548
Short name T95
Test name
Test status
Simulation time 241789321 ps
CPU time 0.88 seconds
Started Jan 17 01:55:09 PM PST 24
Finished Jan 17 01:55:11 PM PST 24
Peak memory 218888 kb
Host smart-1ea3d5de-9afe-428d-aa12-60e8c50ff9d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948614548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2948614548
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.123595575
Short name T1020
Test name
Test status
Simulation time 5732169144 ps
CPU time 9.17 seconds
Started Jan 17 01:55:10 PM PST 24
Finished Jan 17 01:55:20 PM PST 24
Peak memory 199968 kb
Host smart-ed154bab-f3d0-4f02-8a31-9b3d71c0e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123595575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.123595575
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.484473096
Short name T374
Test name
Test status
Simulation time 493672644345 ps
CPU time 750.68 seconds
Started Jan 17 01:55:00 PM PST 24
Finished Jan 17 02:07:32 PM PST 24
Peak memory 200252 kb
Host smart-01b4a1e1-024d-40aa-ae86-e90e9d31c4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484473096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.484473096
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3217379112
Short name T389
Test name
Test status
Simulation time 121975458352 ps
CPU time 305.83 seconds
Started Jan 17 01:54:59 PM PST 24
Finished Jan 17 02:00:06 PM PST 24
Peak memory 216992 kb
Host smart-2f8f7d43-a6ae-4609-bcae-6ebb02fec326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217379112 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3217379112
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.515784772
Short name T1212
Test name
Test status
Simulation time 1296009684 ps
CPU time 2.31 seconds
Started Jan 17 01:55:03 PM PST 24
Finished Jan 17 01:55:06 PM PST 24
Peak memory 198800 kb
Host smart-f98f06af-1933-4e88-8f35-387b03bd8123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515784772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.515784772
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1770314213
Short name T791
Test name
Test status
Simulation time 53891174167 ps
CPU time 164.67 seconds
Started Jan 17 01:55:04 PM PST 24
Finished Jan 17 01:57:50 PM PST 24
Peak memory 200188 kb
Host smart-7599e452-8827-40a1-8d3e-d2cfb2b09fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770314213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1770314213
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3379189902
Short name T865
Test name
Test status
Simulation time 34822951 ps
CPU time 0.56 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:01:32 PM PST 24
Peak memory 195876 kb
Host smart-30fcda90-fbd3-46e5-bb5c-3cec6a31e719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379189902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3379189902
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.330528319
Short name T261
Test name
Test status
Simulation time 35318898704 ps
CPU time 34.42 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:02:06 PM PST 24
Peak memory 200276 kb
Host smart-f5b2fbb5-210b-471a-badd-396fbd67156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330528319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.330528319
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3180905007
Short name T1018
Test name
Test status
Simulation time 273764756382 ps
CPU time 42.68 seconds
Started Jan 17 02:01:20 PM PST 24
Finished Jan 17 02:02:14 PM PST 24
Peak memory 199572 kb
Host smart-53384308-3464-41fe-afe0-1407e663f9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180905007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3180905007
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3748434621
Short name T458
Test name
Test status
Simulation time 17511800222 ps
CPU time 28.17 seconds
Started Jan 17 02:01:19 PM PST 24
Finished Jan 17 02:01:59 PM PST 24
Peak memory 197124 kb
Host smart-bb98d354-1d8b-4f97-a2b8-4772d9cd5c04
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748434621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3748434621
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3054776819
Short name T854
Test name
Test status
Simulation time 155905353326 ps
CPU time 1303.7 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:23:17 PM PST 24
Peak memory 200232 kb
Host smart-d39a00a7-6137-4972-9a48-82fcde3ee451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054776819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3054776819
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.979723457
Short name T1066
Test name
Test status
Simulation time 5022808875 ps
CPU time 11.17 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:01:42 PM PST 24
Peak memory 198656 kb
Host smart-224345be-88e0-41b1-90eb-950924a3e66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979723457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.979723457
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.196867442
Short name T995
Test name
Test status
Simulation time 16459041999 ps
CPU time 28.34 seconds
Started Jan 17 02:01:22 PM PST 24
Finished Jan 17 02:02:00 PM PST 24
Peak memory 198164 kb
Host smart-b62f753a-ee75-4b1c-9caf-f5c6d6a59a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196867442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.196867442
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1229967488
Short name T955
Test name
Test status
Simulation time 9783502340 ps
CPU time 519.71 seconds
Started Jan 17 02:01:29 PM PST 24
Finished Jan 17 02:10:13 PM PST 24
Peak memory 200204 kb
Host smart-7ff48426-7526-4225-8552-ddac6c952290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229967488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1229967488
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2929840244
Short name T1209
Test name
Test status
Simulation time 2803513110 ps
CPU time 16.75 seconds
Started Jan 17 02:01:23 PM PST 24
Finished Jan 17 02:01:49 PM PST 24
Peak memory 198884 kb
Host smart-7764c8ca-35fb-4463-a372-0f6a4850f61f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929840244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2929840244
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3987701823
Short name T761
Test name
Test status
Simulation time 201340149285 ps
CPU time 89.28 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:03:01 PM PST 24
Peak memory 199068 kb
Host smart-9148f00e-8704-416f-bae5-2552280b2de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987701823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3987701823
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2299054344
Short name T503
Test name
Test status
Simulation time 1395849977 ps
CPU time 2.87 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:01:34 PM PST 24
Peak memory 195640 kb
Host smart-21e12378-1490-4311-8a08-a44082b2a998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299054344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2299054344
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.495708353
Short name T704
Test name
Test status
Simulation time 128282812 ps
CPU time 1.17 seconds
Started Jan 17 02:01:22 PM PST 24
Finished Jan 17 02:01:33 PM PST 24
Peak memory 198180 kb
Host smart-023271fc-4edc-4726-b6da-e31c3c335a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495708353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.495708353
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1288463744
Short name T83
Test name
Test status
Simulation time 32890483750 ps
CPU time 138.38 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:03:50 PM PST 24
Peak memory 216188 kb
Host smart-45245904-400e-48bf-99c6-c85a499631a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288463744 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1288463744
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3833896344
Short name T903
Test name
Test status
Simulation time 601765826 ps
CPU time 3.24 seconds
Started Jan 17 02:01:22 PM PST 24
Finished Jan 17 02:01:35 PM PST 24
Peak memory 199584 kb
Host smart-d9588e49-dfb8-4351-a0e0-6e34d2ac88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833896344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3833896344
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1549995522
Short name T810
Test name
Test status
Simulation time 4723136879 ps
CPU time 7.81 seconds
Started Jan 17 02:01:22 PM PST 24
Finished Jan 17 02:01:40 PM PST 24
Peak memory 196928 kb
Host smart-8c66d6c4-5dbb-49e0-be17-7a830a6e4bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549995522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1549995522
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.529961559
Short name T516
Test name
Test status
Simulation time 11635639 ps
CPU time 0.56 seconds
Started Jan 17 02:01:44 PM PST 24
Finished Jan 17 02:01:49 PM PST 24
Peak memory 195656 kb
Host smart-73eaa210-efe0-4158-b0ed-e4b706cab83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529961559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.529961559
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.344244739
Short name T679
Test name
Test status
Simulation time 44695437683 ps
CPU time 23.81 seconds
Started Jan 17 02:01:22 PM PST 24
Finished Jan 17 02:01:55 PM PST 24
Peak memory 200164 kb
Host smart-cfa786f3-4b83-4b96-b12a-7f011903c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344244739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.344244739
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.569801781
Short name T109
Test name
Test status
Simulation time 60912306091 ps
CPU time 97.35 seconds
Started Jan 17 02:01:23 PM PST 24
Finished Jan 17 02:03:09 PM PST 24
Peak memory 199976 kb
Host smart-24209945-4208-4845-892e-4be555a2da4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569801781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.569801781
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2928267785
Short name T150
Test name
Test status
Simulation time 169256041773 ps
CPU time 31.7 seconds
Started Jan 17 02:01:32 PM PST 24
Finished Jan 17 02:02:06 PM PST 24
Peak memory 200152 kb
Host smart-fc202775-80b6-468c-9e44-0cae20ddb592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928267785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2928267785
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2307286715
Short name T760
Test name
Test status
Simulation time 172526186988 ps
CPU time 282.95 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:06:16 PM PST 24
Peak memory 199056 kb
Host smart-4306c9fb-793e-436e-842f-03f170ebff97
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307286715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2307286715
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.850506551
Short name T1214
Test name
Test status
Simulation time 87651308747 ps
CPU time 539.96 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:10:33 PM PST 24
Peak memory 200104 kb
Host smart-211c5c0e-e63e-4f71-977a-c3c304cd17c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850506551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.850506551
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.888063399
Short name T540
Test name
Test status
Simulation time 500591675 ps
CPU time 0.87 seconds
Started Jan 17 02:01:34 PM PST 24
Finished Jan 17 02:01:37 PM PST 24
Peak memory 195924 kb
Host smart-2839e42e-1925-4cd1-aa38-df3cc489c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888063399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.888063399
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1941211596
Short name T658
Test name
Test status
Simulation time 127788709229 ps
CPU time 101.72 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:03:15 PM PST 24
Peak memory 208620 kb
Host smart-4b0f4761-037e-48e0-9aba-438cc7f188a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941211596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1941211596
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.70525574
Short name T815
Test name
Test status
Simulation time 12729883544 ps
CPU time 196.57 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:04:50 PM PST 24
Peak memory 200212 kb
Host smart-01fc8c11-ba58-4767-a091-a7b2ed8a78cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70525574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.70525574
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3058187408
Short name T1219
Test name
Test status
Simulation time 1523296154 ps
CPU time 15.62 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:01:49 PM PST 24
Peak memory 198228 kb
Host smart-3301e5ef-8ff0-4db0-bd1b-f6b0fd0c6762
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058187408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3058187408
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.203754731
Short name T948
Test name
Test status
Simulation time 13759562694 ps
CPU time 22.1 seconds
Started Jan 17 02:01:34 PM PST 24
Finished Jan 17 02:01:58 PM PST 24
Peak memory 198976 kb
Host smart-11307ca2-0628-4365-9dc7-0ce6995c6f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203754731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.203754731
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3475304276
Short name T663
Test name
Test status
Simulation time 31003125043 ps
CPU time 51.59 seconds
Started Jan 17 02:01:32 PM PST 24
Finished Jan 17 02:02:26 PM PST 24
Peak memory 195752 kb
Host smart-87e897af-bb7c-4af3-94e1-7fdcc4ea84ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475304276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3475304276
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.4268422489
Short name T534
Test name
Test status
Simulation time 6046470902 ps
CPU time 6.8 seconds
Started Jan 17 02:01:22 PM PST 24
Finished Jan 17 02:01:39 PM PST 24
Peak memory 199692 kb
Host smart-25753300-7762-4bfd-81a9-1ea7dfe29065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268422489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.4268422489
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.4242925708
Short name T1101
Test name
Test status
Simulation time 333129677727 ps
CPU time 983.75 seconds
Started Jan 17 02:01:35 PM PST 24
Finished Jan 17 02:18:01 PM PST 24
Peak memory 200180 kb
Host smart-447a18e5-b1fe-4fb2-adfc-6bd2f4b0b37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242925708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4242925708
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1598351593
Short name T299
Test name
Test status
Simulation time 37659905535 ps
CPU time 375.05 seconds
Started Jan 17 02:01:39 PM PST 24
Finished Jan 17 02:07:56 PM PST 24
Peak memory 215120 kb
Host smart-700397eb-9275-4143-b1a6-77b77735100e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598351593 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1598351593
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.50135272
Short name T508
Test name
Test status
Simulation time 1636329831 ps
CPU time 3.6 seconds
Started Jan 17 02:01:29 PM PST 24
Finished Jan 17 02:01:37 PM PST 24
Peak memory 198644 kb
Host smart-32f31c44-e389-4107-a920-4a47affdae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50135272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.50135272
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.586258026
Short name T420
Test name
Test status
Simulation time 209016700830 ps
CPU time 37.01 seconds
Started Jan 17 02:01:21 PM PST 24
Finished Jan 17 02:02:08 PM PST 24
Peak memory 200256 kb
Host smart-f1661a73-8e21-4659-8301-131d8b82d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586258026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.586258026
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4059272572
Short name T727
Test name
Test status
Simulation time 19069378 ps
CPU time 0.55 seconds
Started Jan 17 02:01:31 PM PST 24
Finished Jan 17 02:01:34 PM PST 24
Peak memory 195656 kb
Host smart-52039a08-c19a-4e71-97a3-0e59607e7d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059272572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4059272572
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.371885217
Short name T943
Test name
Test status
Simulation time 46348667366 ps
CPU time 40.32 seconds
Started Jan 17 02:01:31 PM PST 24
Finished Jan 17 02:02:14 PM PST 24
Peak memory 200244 kb
Host smart-5ef8f195-c398-4271-8948-8c21be37b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371885217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.371885217
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3929074098
Short name T945
Test name
Test status
Simulation time 16243351249 ps
CPU time 36 seconds
Started Jan 17 02:01:26 PM PST 24
Finished Jan 17 02:02:09 PM PST 24
Peak memory 200236 kb
Host smart-b3385a9e-baa1-46a9-b40e-722a5bd15943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929074098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3929074098
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.673628700
Short name T22
Test name
Test status
Simulation time 253391690688 ps
CPU time 183.59 seconds
Started Jan 17 02:01:35 PM PST 24
Finished Jan 17 02:04:40 PM PST 24
Peak memory 199856 kb
Host smart-9efedb45-224b-4b58-8bd4-8858be63cb51
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673628700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.673628700
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4189502706
Short name T1210
Test name
Test status
Simulation time 138717693882 ps
CPU time 135.19 seconds
Started Jan 17 02:01:26 PM PST 24
Finished Jan 17 02:03:48 PM PST 24
Peak memory 200292 kb
Host smart-b99d429f-af19-476c-ae76-499d4f934af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189502706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4189502706
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1244585938
Short name T1098
Test name
Test status
Simulation time 452138882 ps
CPU time 1.28 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:01:34 PM PST 24
Peak memory 195776 kb
Host smart-80b37097-4414-49ae-bd0e-5b74a10a2503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244585938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1244585938
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1386684737
Short name T951
Test name
Test status
Simulation time 52072903678 ps
CPU time 111.29 seconds
Started Jan 17 02:01:25 PM PST 24
Finished Jan 17 02:03:24 PM PST 24
Peak memory 198536 kb
Host smart-90e58be0-6407-4977-8485-813f08f3a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386684737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1386684737
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1043388669
Short name T651
Test name
Test status
Simulation time 9589505112 ps
CPU time 478.03 seconds
Started Jan 17 02:01:32 PM PST 24
Finished Jan 17 02:09:33 PM PST 24
Peak memory 200244 kb
Host smart-030e13c8-ed6e-4673-876c-ccec113feb40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043388669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1043388669
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3443333649
Short name T1143
Test name
Test status
Simulation time 1987989779 ps
CPU time 5.29 seconds
Started Jan 17 02:01:29 PM PST 24
Finished Jan 17 02:01:39 PM PST 24
Peak memory 198400 kb
Host smart-8f2e429a-2d35-45a3-8aaa-1ddca37ae644
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443333649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3443333649
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3255174906
Short name T849
Test name
Test status
Simulation time 53483448092 ps
CPU time 34.98 seconds
Started Jan 17 02:01:31 PM PST 24
Finished Jan 17 02:02:09 PM PST 24
Peak memory 200200 kb
Host smart-2ec24ffc-f082-4541-bc77-72792e00e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255174906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3255174906
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.194861560
Short name T1026
Test name
Test status
Simulation time 7019658725 ps
CPU time 2.54 seconds
Started Jan 17 02:01:26 PM PST 24
Finished Jan 17 02:01:35 PM PST 24
Peak memory 196024 kb
Host smart-c151139b-0f9d-4e61-8532-9de846beca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194861560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.194861560
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2141092930
Short name T926
Test name
Test status
Simulation time 710408900 ps
CPU time 1.55 seconds
Started Jan 17 02:01:32 PM PST 24
Finished Jan 17 02:01:36 PM PST 24
Peak memory 198108 kb
Host smart-9017c069-de95-4915-ac6f-8267e95073d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141092930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2141092930
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2463976064
Short name T1074
Test name
Test status
Simulation time 47671871748 ps
CPU time 395.14 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:08:08 PM PST 24
Peak memory 200256 kb
Host smart-61630f42-513c-4344-b4e3-3ee7e27cf049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463976064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2463976064
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3942677312
Short name T446
Test name
Test status
Simulation time 18780947503 ps
CPU time 217.05 seconds
Started Jan 17 02:01:40 PM PST 24
Finished Jan 17 02:05:19 PM PST 24
Peak memory 216528 kb
Host smart-a5f7a55b-9739-4a04-b212-be0c89ed8848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942677312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3942677312
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1646778288
Short name T618
Test name
Test status
Simulation time 1022328436 ps
CPU time 1.35 seconds
Started Jan 17 02:01:32 PM PST 24
Finished Jan 17 02:01:36 PM PST 24
Peak memory 198012 kb
Host smart-7a1208f9-68b2-4398-b64a-1460207a26c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646778288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1646778288
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4127158860
Short name T1006
Test name
Test status
Simulation time 26700134486 ps
CPU time 44.67 seconds
Started Jan 17 02:01:30 PM PST 24
Finished Jan 17 02:02:18 PM PST 24
Peak memory 200192 kb
Host smart-8b01c5cb-3961-4583-9404-61da68b6f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127158860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4127158860
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1217099065
Short name T623
Test name
Test status
Simulation time 49383906 ps
CPU time 0.56 seconds
Started Jan 17 02:01:49 PM PST 24
Finished Jan 17 02:01:54 PM PST 24
Peak memory 195504 kb
Host smart-07ccfd38-eee3-4eee-8f59-5e7db2b6433f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217099065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1217099065
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2266409674
Short name T1137
Test name
Test status
Simulation time 222658959515 ps
CPU time 56.84 seconds
Started Jan 17 02:01:37 PM PST 24
Finished Jan 17 02:02:35 PM PST 24
Peak memory 200104 kb
Host smart-b5a56627-ef8f-4fdb-95e6-49d9dce19fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266409674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2266409674
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3383198736
Short name T290
Test name
Test status
Simulation time 39947857150 ps
CPU time 15.78 seconds
Started Jan 17 02:01:31 PM PST 24
Finished Jan 17 02:01:50 PM PST 24
Peak memory 199908 kb
Host smart-c782548f-6bd4-426e-8cf5-2398dcb222c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383198736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3383198736
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.247955772
Short name T409
Test name
Test status
Simulation time 126816879900 ps
CPU time 388.72 seconds
Started Jan 17 02:01:39 PM PST 24
Finished Jan 17 02:08:09 PM PST 24
Peak memory 200216 kb
Host smart-ba6269d6-9234-4701-9378-1778a5b19963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247955772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.247955772
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1725670429
Short name T848
Test name
Test status
Simulation time 6119992945 ps
CPU time 11.82 seconds
Started Jan 17 02:01:46 PM PST 24
Finished Jan 17 02:02:02 PM PST 24
Peak memory 197188 kb
Host smart-53f22c8f-c9e8-4772-aa26-27970792d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725670429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1725670429
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.578409798
Short name T554
Test name
Test status
Simulation time 183978369889 ps
CPU time 90.14 seconds
Started Jan 17 02:01:41 PM PST 24
Finished Jan 17 02:03:13 PM PST 24
Peak memory 208688 kb
Host smart-f43aa61b-d923-4157-a8d4-6d5a35fc5c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578409798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.578409798
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1830569325
Short name T1240
Test name
Test status
Simulation time 20781629520 ps
CPU time 238.58 seconds
Started Jan 17 02:01:42 PM PST 24
Finished Jan 17 02:05:42 PM PST 24
Peak memory 199988 kb
Host smart-44783f38-8b5f-4e8a-97a5-cfe29ab67fcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830569325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1830569325
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2734322450
Short name T851
Test name
Test status
Simulation time 2810953488 ps
CPU time 11.51 seconds
Started Jan 17 02:01:38 PM PST 24
Finished Jan 17 02:01:50 PM PST 24
Peak memory 198820 kb
Host smart-13470266-e0bb-4b01-ab4f-ea784cf8711b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734322450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2734322450
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1326331840
Short name T1149
Test name
Test status
Simulation time 70287091402 ps
CPU time 109.02 seconds
Started Jan 17 02:01:39 PM PST 24
Finished Jan 17 02:03:30 PM PST 24
Peak memory 200196 kb
Host smart-464df899-03eb-42ab-8885-3c4a9716e3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326331840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1326331840
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.758906665
Short name T1160
Test name
Test status
Simulation time 6014553563 ps
CPU time 3.19 seconds
Started Jan 17 02:01:42 PM PST 24
Finished Jan 17 02:01:46 PM PST 24
Peak memory 195912 kb
Host smart-d95bd28a-dbc4-44c9-811d-b2348870470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758906665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.758906665
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3367550293
Short name T712
Test name
Test status
Simulation time 6291055120 ps
CPU time 16.27 seconds
Started Jan 17 02:01:26 PM PST 24
Finished Jan 17 02:01:49 PM PST 24
Peak memory 198992 kb
Host smart-d4e77ab3-4e2a-4782-a1e6-00863286669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367550293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3367550293
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3984224518
Short name T205
Test name
Test status
Simulation time 144659420807 ps
CPU time 238.39 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:05:49 PM PST 24
Peak memory 200420 kb
Host smart-dd08a67d-8140-421b-89c3-b46905e6badf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984224518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3984224518
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1739141888
Short name T1007
Test name
Test status
Simulation time 7626669678 ps
CPU time 77.52 seconds
Started Jan 17 02:01:46 PM PST 24
Finished Jan 17 02:03:08 PM PST 24
Peak memory 208860 kb
Host smart-7187289f-0076-42d4-aa6a-59d975c6aab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739141888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1739141888
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.253384851
Short name T904
Test name
Test status
Simulation time 2487273406 ps
CPU time 3.33 seconds
Started Jan 17 02:01:40 PM PST 24
Finished Jan 17 02:01:45 PM PST 24
Peak memory 198872 kb
Host smart-21336cfe-2c2f-4f75-8977-13410629f58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253384851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.253384851
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.4119064063
Short name T1118
Test name
Test status
Simulation time 103309655427 ps
CPU time 68.97 seconds
Started Jan 17 02:01:27 PM PST 24
Finished Jan 17 02:02:42 PM PST 24
Peak memory 200184 kb
Host smart-5a2e032c-a453-4213-816f-3b44020529d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119064063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.4119064063
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1188407335
Short name T504
Test name
Test status
Simulation time 61606939 ps
CPU time 0.54 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:01:51 PM PST 24
Peak memory 194648 kb
Host smart-13e03df1-1649-467a-85bf-e5c8ae29bcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188407335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1188407335
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1669234511
Short name T532
Test name
Test status
Simulation time 50911739800 ps
CPU time 74.93 seconds
Started Jan 17 02:01:37 PM PST 24
Finished Jan 17 02:02:54 PM PST 24
Peak memory 200244 kb
Host smart-648a23bb-07f1-4412-b8de-8ea5533695ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669234511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1669234511
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.990825298
Short name T741
Test name
Test status
Simulation time 242143035903 ps
CPU time 34.56 seconds
Started Jan 17 02:01:41 PM PST 24
Finished Jan 17 02:02:17 PM PST 24
Peak memory 199988 kb
Host smart-cf52110b-0921-45f6-b3fe-ad203e614d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990825298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.990825298
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1426444470
Short name T190
Test name
Test status
Simulation time 19961011044 ps
CPU time 17.03 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:02:07 PM PST 24
Peak memory 200004 kb
Host smart-e32e4684-bac5-413e-97bb-8bce0301f788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426444470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1426444470
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1972210154
Short name T234
Test name
Test status
Simulation time 110898397403 ps
CPU time 178.88 seconds
Started Jan 17 02:01:38 PM PST 24
Finished Jan 17 02:04:38 PM PST 24
Peak memory 200040 kb
Host smart-98467bb0-ea2c-41ab-9a79-f9500d2d6273
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972210154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1972210154
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.3944993975
Short name T1107
Test name
Test status
Simulation time 86007827133 ps
CPU time 410.16 seconds
Started Jan 17 02:01:46 PM PST 24
Finished Jan 17 02:08:41 PM PST 24
Peak memory 200244 kb
Host smart-8f5876b7-a5b5-4635-b735-3fcd9cf3628d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944993975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3944993975
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3765129742
Short name T678
Test name
Test status
Simulation time 14450607233 ps
CPU time 2.56 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:01:53 PM PST 24
Peak memory 199160 kb
Host smart-0717dd78-e5b9-4da2-ae87-75e7b661bdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765129742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3765129742
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2452641133
Short name T878
Test name
Test status
Simulation time 95384737868 ps
CPU time 198.24 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:05:08 PM PST 24
Peak memory 208564 kb
Host smart-0f7b12e0-c3dc-4e83-86a5-8b6b49d0b9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452641133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2452641133
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2660148371
Short name T935
Test name
Test status
Simulation time 5174896209 ps
CPU time 10.27 seconds
Started Jan 17 02:01:39 PM PST 24
Finished Jan 17 02:01:51 PM PST 24
Peak memory 198924 kb
Host smart-50bbe3b4-3ac4-4013-90f5-05abdf7d09d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660148371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2660148371
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.4204706985
Short name T359
Test name
Test status
Simulation time 28365434397 ps
CPU time 23.46 seconds
Started Jan 17 02:01:47 PM PST 24
Finished Jan 17 02:02:16 PM PST 24
Peak memory 199984 kb
Host smart-cb429fd9-ad1e-4b4f-9094-556ec10ce407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204706985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4204706985
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3446426979
Short name T1164
Test name
Test status
Simulation time 1339801696 ps
CPU time 1.71 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:01:52 PM PST 24
Peak memory 195620 kb
Host smart-274d7d77-54c5-4868-88f7-b6b1d77c27a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446426979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3446426979
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3299661677
Short name T1167
Test name
Test status
Simulation time 5426469320 ps
CPU time 19.37 seconds
Started Jan 17 02:01:39 PM PST 24
Finished Jan 17 02:02:01 PM PST 24
Peak memory 199056 kb
Host smart-c93a4aa9-ca18-44ee-85b1-00651f40bb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299661677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3299661677
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1251122955
Short name T587
Test name
Test status
Simulation time 25944655191 ps
CPU time 27.59 seconds
Started Jan 17 02:01:47 PM PST 24
Finished Jan 17 02:02:21 PM PST 24
Peak memory 200188 kb
Host smart-e5301852-a977-4855-a71f-382b8997b782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251122955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1251122955
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.749893077
Short name T1110
Test name
Test status
Simulation time 6205163537 ps
CPU time 27.25 seconds
Started Jan 17 02:01:44 PM PST 24
Finished Jan 17 02:02:17 PM PST 24
Peak memory 199728 kb
Host smart-d4987423-9137-4ad9-855b-886b184b87bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749893077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.749893077
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.445048708
Short name T596
Test name
Test status
Simulation time 36980347692 ps
CPU time 33.52 seconds
Started Jan 17 02:01:39 PM PST 24
Finished Jan 17 02:02:15 PM PST 24
Peak memory 200244 kb
Host smart-324d72d0-749b-4050-8c63-0e9ce70ad265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445048708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.445048708
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.565939908
Short name T852
Test name
Test status
Simulation time 13725805 ps
CPU time 0.58 seconds
Started Jan 17 02:01:50 PM PST 24
Finished Jan 17 02:01:56 PM PST 24
Peak memory 195608 kb
Host smart-7fd82cd5-8170-46a0-9523-f9462735567a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565939908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.565939908
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.350066859
Short name T671
Test name
Test status
Simulation time 49256718654 ps
CPU time 15.88 seconds
Started Jan 17 02:01:47 PM PST 24
Finished Jan 17 02:02:09 PM PST 24
Peak memory 200040 kb
Host smart-2fff374a-b5cd-476d-87d1-bc8b65c0187f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350066859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.350066859
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2270401784
Short name T204
Test name
Test status
Simulation time 126044049196 ps
CPU time 139.28 seconds
Started Jan 17 02:01:47 PM PST 24
Finished Jan 17 02:04:12 PM PST 24
Peak memory 199980 kb
Host smart-55a6b444-3dfd-48b3-afff-8049f543c745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270401784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2270401784
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2698722179
Short name T221
Test name
Test status
Simulation time 10563556010 ps
CPU time 15.99 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:02:06 PM PST 24
Peak memory 199436 kb
Host smart-8b061ec7-cd01-48ba-bb65-87804d7056b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698722179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2698722179
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.244337364
Short name T837
Test name
Test status
Simulation time 1148501374414 ps
CPU time 1593.01 seconds
Started Jan 17 02:01:51 PM PST 24
Finished Jan 17 02:28:29 PM PST 24
Peak memory 200156 kb
Host smart-9b299ec7-c127-4849-b4d1-a8240a11484e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244337364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.244337364
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.405915130
Short name T772
Test name
Test status
Simulation time 163279613782 ps
CPU time 942.63 seconds
Started Jan 17 02:01:48 PM PST 24
Finished Jan 17 02:17:36 PM PST 24
Peak memory 200160 kb
Host smart-2146f6fd-a19f-4c7c-bf30-64d58caab979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405915130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.405915130
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.4277582396
Short name T792
Test name
Test status
Simulation time 5619985992 ps
CPU time 5.67 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:01:56 PM PST 24
Peak memory 198244 kb
Host smart-8ea50322-240a-4ad9-9ca5-8f3d77989aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277582396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4277582396
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1749127173
Short name T209
Test name
Test status
Simulation time 75822489981 ps
CPU time 60.13 seconds
Started Jan 17 02:01:49 PM PST 24
Finished Jan 17 02:02:54 PM PST 24
Peak memory 208464 kb
Host smart-6d60ae02-c1b0-4e2f-a0dc-c88c58bf5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749127173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1749127173
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.586642230
Short name T546
Test name
Test status
Simulation time 18425003640 ps
CPU time 112.86 seconds
Started Jan 17 02:01:47 PM PST 24
Finished Jan 17 02:03:46 PM PST 24
Peak memory 200224 kb
Host smart-f4d89489-1d69-4134-a021-4dfdcd72488e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586642230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.586642230
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2798829958
Short name T670
Test name
Test status
Simulation time 3724914409 ps
CPU time 13.85 seconds
Started Jan 17 02:01:46 PM PST 24
Finished Jan 17 02:02:04 PM PST 24
Peak memory 199008 kb
Host smart-6dd72cd2-3e3c-4c90-966d-b5c1d3eddb58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798829958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2798829958
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.353763155
Short name T1113
Test name
Test status
Simulation time 71132424639 ps
CPU time 23.09 seconds
Started Jan 17 02:01:47 PM PST 24
Finished Jan 17 02:02:16 PM PST 24
Peak memory 200184 kb
Host smart-8bc5fd6a-9211-49fc-b06a-898cc0df4c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353763155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.353763155
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2275271666
Short name T653
Test name
Test status
Simulation time 4849677438 ps
CPU time 7.69 seconds
Started Jan 17 02:01:45 PM PST 24
Finished Jan 17 02:01:58 PM PST 24
Peak memory 195992 kb
Host smart-da413b36-9636-45d5-a1f5-afec44c9efc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275271666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2275271666
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1333600382
Short name T581
Test name
Test status
Simulation time 109534726 ps
CPU time 0.82 seconds
Started Jan 17 02:01:51 PM PST 24
Finished Jan 17 02:01:57 PM PST 24
Peak memory 197088 kb
Host smart-b20d891f-0fb0-430b-9207-6a0df28f2238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333600382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1333600382
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2741561937
Short name T774
Test name
Test status
Simulation time 191811939384 ps
CPU time 892.74 seconds
Started Jan 17 02:01:46 PM PST 24
Finished Jan 17 02:16:43 PM PST 24
Peak memory 225752 kb
Host smart-b49e6275-8b50-425f-be3c-20b22005864c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741561937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2741561937
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3497164711
Short name T569
Test name
Test status
Simulation time 561566709 ps
CPU time 1.74 seconds
Started Jan 17 02:01:46 PM PST 24
Finished Jan 17 02:01:52 PM PST 24
Peak memory 198276 kb
Host smart-de9c022e-5d16-4c19-81e1-6b649fbfdb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497164711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3497164711
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3671388144
Short name T415
Test name
Test status
Simulation time 75347534103 ps
CPU time 35.46 seconds
Started Jan 17 02:01:46 PM PST 24
Finished Jan 17 02:02:26 PM PST 24
Peak memory 200204 kb
Host smart-c784090d-1d9c-45a4-a1ba-baf468357cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671388144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3671388144
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.823634264
Short name T1039
Test name
Test status
Simulation time 38968155 ps
CPU time 0.54 seconds
Started Jan 17 02:01:58 PM PST 24
Finished Jan 17 02:01:59 PM PST 24
Peak memory 194764 kb
Host smart-39b8001e-6036-4e30-81eb-82516d12407d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823634264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.823634264
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4206767910
Short name T129
Test name
Test status
Simulation time 190972364564 ps
CPU time 80.48 seconds
Started Jan 17 02:01:53 PM PST 24
Finished Jan 17 02:03:16 PM PST 24
Peak memory 200180 kb
Host smart-62cd36e4-05d8-4f4a-85ed-2e5d3585b090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206767910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4206767910
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.186596855
Short name T1128
Test name
Test status
Simulation time 31871141943 ps
CPU time 51.62 seconds
Started Jan 17 02:01:49 PM PST 24
Finished Jan 17 02:02:46 PM PST 24
Peak memory 199968 kb
Host smart-69407b9a-986b-450b-a3fc-7818f5a68df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186596855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.186596855
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.593718745
Short name T1082
Test name
Test status
Simulation time 338644039297 ps
CPU time 260.63 seconds
Started Jan 17 02:01:50 PM PST 24
Finished Jan 17 02:06:16 PM PST 24
Peak memory 200228 kb
Host smart-415d3076-9196-477c-a2c4-4a6b1ffe9e4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593718745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.593718745
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.105739046
Short name T506
Test name
Test status
Simulation time 182263972830 ps
CPU time 138.2 seconds
Started Jan 17 02:01:56 PM PST 24
Finished Jan 17 02:04:15 PM PST 24
Peak memory 200160 kb
Host smart-0937d8ba-de72-47e0-bd47-3f8c778f5ff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105739046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.105739046
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2301088956
Short name T711
Test name
Test status
Simulation time 4628672627 ps
CPU time 1.85 seconds
Started Jan 17 02:01:56 PM PST 24
Finished Jan 17 02:02:00 PM PST 24
Peak memory 198504 kb
Host smart-9951ad92-35c4-41d0-b6c0-9b9f0e0a7d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301088956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2301088956
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3846595469
Short name T1121
Test name
Test status
Simulation time 20896592648 ps
CPU time 17.6 seconds
Started Jan 17 02:01:49 PM PST 24
Finished Jan 17 02:02:12 PM PST 24
Peak memory 199420 kb
Host smart-943854fc-e7ae-40fc-921e-18c5da462513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846595469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3846595469
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3729638652
Short name T801
Test name
Test status
Simulation time 22192120965 ps
CPU time 1048.5 seconds
Started Jan 17 02:01:59 PM PST 24
Finished Jan 17 02:19:29 PM PST 24
Peak memory 200204 kb
Host smart-586292d3-ec07-47aa-8a48-1afbad031ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729638652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3729638652
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.404953354
Short name T942
Test name
Test status
Simulation time 1288515718 ps
CPU time 1.3 seconds
Started Jan 17 02:01:49 PM PST 24
Finished Jan 17 02:01:55 PM PST 24
Peak memory 195560 kb
Host smart-6d84a05e-62b6-4092-b398-a5717310bfb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404953354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.404953354
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.699960683
Short name T634
Test name
Test status
Simulation time 43454512576 ps
CPU time 25.15 seconds
Started Jan 17 02:01:50 PM PST 24
Finished Jan 17 02:02:20 PM PST 24
Peak memory 200080 kb
Host smart-8fdce224-9cda-48ce-a031-9bd0b37150df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699960683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.699960683
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2530550560
Short name T500
Test name
Test status
Simulation time 4886128884 ps
CPU time 6.02 seconds
Started Jan 17 02:01:59 PM PST 24
Finished Jan 17 02:02:07 PM PST 24
Peak memory 195996 kb
Host smart-c9927271-9f94-47e6-9106-d2342b39d0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530550560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2530550560
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3302722909
Short name T780
Test name
Test status
Simulation time 334472175 ps
CPU time 1.13 seconds
Started Jan 17 02:01:50 PM PST 24
Finished Jan 17 02:01:55 PM PST 24
Peak memory 198088 kb
Host smart-dd377e69-b56b-48f9-85c7-465a7e7c9fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302722909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3302722909
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1090344806
Short name T716
Test name
Test status
Simulation time 160257924441 ps
CPU time 989.84 seconds
Started Jan 17 02:01:56 PM PST 24
Finished Jan 17 02:18:28 PM PST 24
Peak memory 224848 kb
Host smart-05eab0d2-1f10-4307-837d-ead5f9441854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090344806 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1090344806
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2059313449
Short name T687
Test name
Test status
Simulation time 626538550 ps
CPU time 2 seconds
Started Jan 17 02:01:51 PM PST 24
Finished Jan 17 02:01:58 PM PST 24
Peak memory 198424 kb
Host smart-d451f574-4eef-41e1-8ce4-9b4da05b38e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059313449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2059313449
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2288706229
Short name T724
Test name
Test status
Simulation time 8461548997 ps
CPU time 4.69 seconds
Started Jan 17 02:01:48 PM PST 24
Finished Jan 17 02:01:59 PM PST 24
Peak memory 197372 kb
Host smart-03100fba-9ace-415f-abde-f97ce7ef2059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288706229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2288706229
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2739303063
Short name T812
Test name
Test status
Simulation time 104529331 ps
CPU time 0.55 seconds
Started Jan 17 02:02:13 PM PST 24
Finished Jan 17 02:02:15 PM PST 24
Peak memory 195668 kb
Host smart-c14b785b-5570-4aee-991f-0132ce361a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739303063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2739303063
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.435693669
Short name T346
Test name
Test status
Simulation time 156106078436 ps
CPU time 137.03 seconds
Started Jan 17 02:02:04 PM PST 24
Finished Jan 17 02:04:22 PM PST 24
Peak memory 200176 kb
Host smart-e5d067ee-2621-4175-b1e0-e18b60adad7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435693669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.435693669
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2504624973
Short name T24
Test name
Test status
Simulation time 27408595906 ps
CPU time 21.35 seconds
Started Jan 17 02:02:12 PM PST 24
Finished Jan 17 02:02:34 PM PST 24
Peak memory 200144 kb
Host smart-35bb6a13-55d8-42c3-ba94-2b4cc10141b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504624973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2504624973
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3239241158
Short name T161
Test name
Test status
Simulation time 132172853748 ps
CPU time 213.48 seconds
Started Jan 17 02:02:04 PM PST 24
Finished Jan 17 02:05:39 PM PST 24
Peak memory 200236 kb
Host smart-c0f0963d-25d5-4b96-8e0e-2ab82c9e369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239241158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3239241158
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3763140018
Short name T1154
Test name
Test status
Simulation time 149964579567 ps
CPU time 208.8 seconds
Started Jan 17 02:02:12 PM PST 24
Finished Jan 17 02:05:42 PM PST 24
Peak memory 197748 kb
Host smart-04b8a061-4111-47b0-a269-e3c155475a8d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763140018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3763140018
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.465968157
Short name T1015
Test name
Test status
Simulation time 66771473274 ps
CPU time 415.43 seconds
Started Jan 17 02:02:10 PM PST 24
Finished Jan 17 02:09:07 PM PST 24
Peak memory 200196 kb
Host smart-49a744bc-ed4d-4bc1-8ecb-811072b34b2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465968157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.465968157
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1543701717
Short name T519
Test name
Test status
Simulation time 7399958617 ps
CPU time 4.72 seconds
Started Jan 17 02:02:04 PM PST 24
Finished Jan 17 02:02:10 PM PST 24
Peak memory 197848 kb
Host smart-a3c8ec4e-11e8-4f83-a811-ae751b0eda16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543701717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1543701717
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2491302726
Short name T128
Test name
Test status
Simulation time 84058824245 ps
CPU time 68.13 seconds
Started Jan 17 02:02:06 PM PST 24
Finished Jan 17 02:03:15 PM PST 24
Peak memory 200484 kb
Host smart-19bacbc7-20cc-4c07-99f6-37957de41f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491302726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2491302726
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3675172919
Short name T537
Test name
Test status
Simulation time 1718078533 ps
CPU time 56.13 seconds
Started Jan 17 02:02:05 PM PST 24
Finished Jan 17 02:03:02 PM PST 24
Peak memory 200156 kb
Host smart-a7653fc7-92b2-4448-ba98-841186a11e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675172919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3675172919
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3532068509
Short name T1190
Test name
Test status
Simulation time 1287540984 ps
CPU time 1.84 seconds
Started Jan 17 02:02:06 PM PST 24
Finished Jan 17 02:02:09 PM PST 24
Peak memory 197840 kb
Host smart-25c93746-a8e9-44c6-ab45-2b82a0ad4cc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532068509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3532068509
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2994115085
Short name T874
Test name
Test status
Simulation time 146468089935 ps
CPU time 141.29 seconds
Started Jan 17 02:02:12 PM PST 24
Finished Jan 17 02:04:34 PM PST 24
Peak memory 199040 kb
Host smart-960b9be6-5420-4fb7-aa8f-76acc4a27003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994115085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2994115085
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3984523418
Short name T572
Test name
Test status
Simulation time 2616729074 ps
CPU time 2.74 seconds
Started Jan 17 02:02:06 PM PST 24
Finished Jan 17 02:02:10 PM PST 24
Peak memory 195712 kb
Host smart-2ada2aff-5403-4ee1-9705-af0df8161916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984523418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3984523418
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3284541042
Short name T611
Test name
Test status
Simulation time 605329737 ps
CPU time 3.37 seconds
Started Jan 17 02:01:59 PM PST 24
Finished Jan 17 02:02:05 PM PST 24
Peak memory 198720 kb
Host smart-e2b62b26-ca6d-4c1d-8644-95e6f4aa4cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284541042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3284541042
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3063031458
Short name T235
Test name
Test status
Simulation time 784649825786 ps
CPU time 2960.44 seconds
Started Jan 17 02:02:10 PM PST 24
Finished Jan 17 02:51:31 PM PST 24
Peak memory 200204 kb
Host smart-d68251bf-6ac3-4def-8c48-66960eb8c486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063031458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3063031458
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.4086693914
Short name T639
Test name
Test status
Simulation time 297882453073 ps
CPU time 284.17 seconds
Started Jan 17 02:02:10 PM PST 24
Finished Jan 17 02:06:55 PM PST 24
Peak memory 225156 kb
Host smart-298d7d9e-6f4a-4a68-960e-7e3baaccc15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086693914 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.4086693914
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3672170663
Short name T940
Test name
Test status
Simulation time 1029249594 ps
CPU time 1.69 seconds
Started Jan 17 02:02:08 PM PST 24
Finished Jan 17 02:02:10 PM PST 24
Peak memory 198536 kb
Host smart-78d4cfda-9446-415f-aecb-6b13921e2801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672170663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3672170663
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.975768162
Short name T1025
Test name
Test status
Simulation time 379596497942 ps
CPU time 142.05 seconds
Started Jan 17 02:02:00 PM PST 24
Finished Jan 17 02:04:24 PM PST 24
Peak memory 200252 kb
Host smart-922f06f6-f187-48b5-aab4-6a1f31c6e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975768162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.975768162
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3336686008
Short name T517
Test name
Test status
Simulation time 41241538 ps
CPU time 0.55 seconds
Started Jan 17 02:02:28 PM PST 24
Finished Jan 17 02:02:35 PM PST 24
Peak memory 195640 kb
Host smart-46c1f8bf-6cca-4023-bb9f-29e2db960d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336686008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3336686008
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2886371913
Short name T345
Test name
Test status
Simulation time 154242240755 ps
CPU time 221.13 seconds
Started Jan 17 02:02:11 PM PST 24
Finished Jan 17 02:05:53 PM PST 24
Peak memory 200312 kb
Host smart-fda99130-f12e-4ff1-a757-3bb86e0eb7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886371913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2886371913
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.66980504
Short name T382
Test name
Test status
Simulation time 219949234080 ps
CPU time 57.85 seconds
Started Jan 17 02:02:11 PM PST 24
Finished Jan 17 02:03:09 PM PST 24
Peak memory 200180 kb
Host smart-2b158622-bae5-4520-af46-44219e76f67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66980504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.66980504
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1970081755
Short name T1227
Test name
Test status
Simulation time 24033354004 ps
CPU time 8.46 seconds
Started Jan 17 02:02:31 PM PST 24
Finished Jan 17 02:02:50 PM PST 24
Peak memory 199624 kb
Host smart-07f8f6f7-7e81-4431-995e-3581121bc77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970081755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1970081755
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1142445341
Short name T886
Test name
Test status
Simulation time 36608706195 ps
CPU time 75.15 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:03:57 PM PST 24
Peak memory 199664 kb
Host smart-1a12fbb3-6e3b-448e-a873-4a26722bf029
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142445341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1142445341
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2554945966
Short name T676
Test name
Test status
Simulation time 59953777081 ps
CPU time 416.71 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:09:39 PM PST 24
Peak memory 200232 kb
Host smart-1f670fd6-53c7-4f68-a051-e03f40a56a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554945966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2554945966
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2839415104
Short name T105
Test name
Test status
Simulation time 2956748659 ps
CPU time 2.77 seconds
Started Jan 17 02:02:28 PM PST 24
Finished Jan 17 02:02:39 PM PST 24
Peak memory 199832 kb
Host smart-4b92b0c8-e083-4477-afdf-c37cb752d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839415104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2839415104
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.232047197
Short name T744
Test name
Test status
Simulation time 235592632729 ps
CPU time 51.64 seconds
Started Jan 17 02:02:18 PM PST 24
Finished Jan 17 02:03:13 PM PST 24
Peak memory 199448 kb
Host smart-52ad1a34-47d9-4c9d-b821-324a07a1145c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232047197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.232047197
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2418776237
Short name T509
Test name
Test status
Simulation time 12145945829 ps
CPU time 59.91 seconds
Started Jan 17 02:02:20 PM PST 24
Finished Jan 17 02:03:26 PM PST 24
Peak memory 200180 kb
Host smart-9f34d102-4b55-4d0f-afcb-36953d94c183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418776237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2418776237
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2077328575
Short name T265
Test name
Test status
Simulation time 95347841008 ps
CPU time 143.77 seconds
Started Jan 17 02:02:29 PM PST 24
Finished Jan 17 02:05:01 PM PST 24
Peak memory 200220 kb
Host smart-7b2aa97d-7e44-421f-a37d-eb21fe1bf378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077328575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2077328575
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3372052310
Short name T971
Test name
Test status
Simulation time 4792085245 ps
CPU time 4.71 seconds
Started Jan 17 02:02:28 PM PST 24
Finished Jan 17 02:02:41 PM PST 24
Peak memory 196012 kb
Host smart-a0b13a86-b45a-40c5-a15e-812c0d420d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372052310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3372052310
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2788891992
Short name T975
Test name
Test status
Simulation time 5674841102 ps
CPU time 16.73 seconds
Started Jan 17 02:02:08 PM PST 24
Finished Jan 17 02:02:25 PM PST 24
Peak memory 199444 kb
Host smart-6782614e-b3bb-4b43-9ff2-fd432b9785e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788891992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2788891992
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.320659637
Short name T1239
Test name
Test status
Simulation time 2485340654355 ps
CPU time 561.72 seconds
Started Jan 17 02:02:27 PM PST 24
Finished Jan 17 02:11:52 PM PST 24
Peak memory 200204 kb
Host smart-33039836-662e-427c-8305-03daa5fda865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320659637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.320659637
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2475759452
Short name T1179
Test name
Test status
Simulation time 19018158691 ps
CPU time 231.69 seconds
Started Jan 17 02:02:27 PM PST 24
Finished Jan 17 02:06:22 PM PST 24
Peak memory 216932 kb
Host smart-2c292c8f-defe-424e-ac8b-b1a1c6097012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475759452 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2475759452
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1256552113
Short name T813
Test name
Test status
Simulation time 641560069 ps
CPU time 2.27 seconds
Started Jan 17 02:02:29 PM PST 24
Finished Jan 17 02:02:39 PM PST 24
Peak memory 198800 kb
Host smart-5d7bcb7b-9007-4d7a-b74f-0001a1b28f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256552113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1256552113
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.161547210
Short name T154
Test name
Test status
Simulation time 69518606615 ps
CPU time 56.59 seconds
Started Jan 17 02:02:14 PM PST 24
Finished Jan 17 02:03:12 PM PST 24
Peak memory 200248 kb
Host smart-f6cb3cb3-aef6-4af5-a55b-90e5f7f1d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161547210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.161547210
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3247572665
Short name T99
Test name
Test status
Simulation time 12370053 ps
CPU time 0.59 seconds
Started Jan 17 02:02:30 PM PST 24
Finished Jan 17 02:02:38 PM PST 24
Peak memory 195636 kb
Host smart-a466043d-a10c-4e2c-a359-09fe5c0d7fb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247572665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3247572665
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1377101090
Short name T380
Test name
Test status
Simulation time 57440318702 ps
CPU time 19.39 seconds
Started Jan 17 02:02:36 PM PST 24
Finished Jan 17 02:03:01 PM PST 24
Peak memory 200264 kb
Host smart-3eb06752-ffbe-49f4-877d-936f1974c02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377101090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1377101090
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2862832510
Short name T817
Test name
Test status
Simulation time 230937201396 ps
CPU time 52.78 seconds
Started Jan 17 02:02:36 PM PST 24
Finished Jan 17 02:03:35 PM PST 24
Peak memory 200240 kb
Host smart-7b802540-e407-4165-8051-f10b6be7353b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862832510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2862832510
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.658343061
Short name T1065
Test name
Test status
Simulation time 217233702098 ps
CPU time 84.61 seconds
Started Jan 17 02:02:38 PM PST 24
Finished Jan 17 02:04:08 PM PST 24
Peak memory 200220 kb
Host smart-b60b491b-7a0f-48f3-9efd-c458a2679d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658343061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.658343061
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3703046024
Short name T1008
Test name
Test status
Simulation time 1153176858920 ps
CPU time 948.51 seconds
Started Jan 17 02:02:29 PM PST 24
Finished Jan 17 02:18:25 PM PST 24
Peak memory 200180 kb
Host smart-0bd119d0-4158-44bb-89ca-eeae5ac985ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703046024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3703046024
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3817936911
Short name T776
Test name
Test status
Simulation time 366174635820 ps
CPU time 125.61 seconds
Started Jan 17 02:02:25 PM PST 24
Finished Jan 17 02:04:35 PM PST 24
Peak memory 200180 kb
Host smart-c8bf86cb-e383-4df5-983e-0ad33ff3e006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817936911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3817936911
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.941775995
Short name T584
Test name
Test status
Simulation time 9535763072 ps
CPU time 23.54 seconds
Started Jan 17 02:02:32 PM PST 24
Finished Jan 17 02:03:05 PM PST 24
Peak memory 199820 kb
Host smart-17313825-b796-4fbd-aa67-e98c5bf5a2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941775995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.941775995
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3270955469
Short name T638
Test name
Test status
Simulation time 117942264754 ps
CPU time 48.83 seconds
Started Jan 17 02:02:26 PM PST 24
Finished Jan 17 02:03:19 PM PST 24
Peak memory 200524 kb
Host smart-d94561fa-7195-46b5-b191-ccc3f46fa61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270955469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3270955469
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.469685023
Short name T686
Test name
Test status
Simulation time 26096944393 ps
CPU time 1361.09 seconds
Started Jan 17 02:02:27 PM PST 24
Finished Jan 17 02:25:12 PM PST 24
Peak memory 200160 kb
Host smart-23e40b90-7013-41a5-b7b0-92e6d61aee4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469685023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.469685023
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2218405273
Short name T533
Test name
Test status
Simulation time 124774979 ps
CPU time 1 seconds
Started Jan 17 02:02:35 PM PST 24
Finished Jan 17 02:02:43 PM PST 24
Peak memory 198008 kb
Host smart-00ca1b8b-55e9-43c0-bce6-6c2d9a7439b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2218405273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2218405273
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2400369102
Short name T329
Test name
Test status
Simulation time 150917608198 ps
CPU time 160.79 seconds
Started Jan 17 02:02:30 PM PST 24
Finished Jan 17 02:05:18 PM PST 24
Peak memory 199596 kb
Host smart-660fc03c-0daa-4aef-8e98-406ca9688792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400369102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2400369102
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.993328731
Short name T836
Test name
Test status
Simulation time 76735196131 ps
CPU time 13.91 seconds
Started Jan 17 02:02:29 PM PST 24
Finished Jan 17 02:02:51 PM PST 24
Peak memory 195728 kb
Host smart-5dc1d057-846e-4fcd-9a56-0a5651362dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993328731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.993328731
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2319548122
Short name T1049
Test name
Test status
Simulation time 533484019 ps
CPU time 3.19 seconds
Started Jan 17 02:02:31 PM PST 24
Finished Jan 17 02:02:45 PM PST 24
Peak memory 198732 kb
Host smart-b9b16c37-6582-4358-853f-b9c9dad9f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319548122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2319548122
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4189580072
Short name T635
Test name
Test status
Simulation time 365828406 ps
CPU time 1.4 seconds
Started Jan 17 02:02:32 PM PST 24
Finished Jan 17 02:02:43 PM PST 24
Peak memory 198648 kb
Host smart-f025838c-7399-4d85-9f42-81b6ec93f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189580072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4189580072
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.291901983
Short name T1044
Test name
Test status
Simulation time 128576048839 ps
CPU time 53.99 seconds
Started Jan 17 02:02:32 PM PST 24
Finished Jan 17 02:03:36 PM PST 24
Peak memory 200284 kb
Host smart-aac0de60-49da-4193-8fba-9e11e4238ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291901983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.291901983
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2927567994
Short name T993
Test name
Test status
Simulation time 14365414 ps
CPU time 0.59 seconds
Started Jan 17 01:55:11 PM PST 24
Finished Jan 17 01:55:12 PM PST 24
Peak memory 195656 kb
Host smart-7638bb71-967a-4e96-a33c-8db1b976d83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927567994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2927567994
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1924969533
Short name T539
Test name
Test status
Simulation time 31055625013 ps
CPU time 49.68 seconds
Started Jan 17 01:55:07 PM PST 24
Finished Jan 17 01:55:58 PM PST 24
Peak memory 200212 kb
Host smart-8c1181b9-2de7-4f98-b22f-9ea85625088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924969533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1924969533
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3884142122
Short name T645
Test name
Test status
Simulation time 110180648621 ps
CPU time 86.57 seconds
Started Jan 17 01:55:11 PM PST 24
Finished Jan 17 01:56:38 PM PST 24
Peak memory 200248 kb
Host smart-00e5d98b-2746-4ada-b725-c622ee70cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884142122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3884142122
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.357276958
Short name T323
Test name
Test status
Simulation time 16647167378 ps
CPU time 28.88 seconds
Started Jan 17 01:55:09 PM PST 24
Finished Jan 17 01:55:39 PM PST 24
Peak memory 200176 kb
Host smart-02d8f28f-1a0c-4868-be73-8d36909d67b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357276958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.357276958
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1290336503
Short name T1202
Test name
Test status
Simulation time 278274863563 ps
CPU time 501.69 seconds
Started Jan 17 01:55:06 PM PST 24
Finished Jan 17 02:03:28 PM PST 24
Peak memory 199724 kb
Host smart-6130a82b-013d-43a5-be2f-19b458a83cd0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290336503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1290336503
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3677905042
Short name T1093
Test name
Test status
Simulation time 51138356661 ps
CPU time 324.23 seconds
Started Jan 17 01:55:06 PM PST 24
Finished Jan 17 02:00:31 PM PST 24
Peak memory 200284 kb
Host smart-908fce6a-d84f-4340-8929-117ba366f500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677905042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3677905042
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2431468115
Short name T1063
Test name
Test status
Simulation time 7806882945 ps
CPU time 5.04 seconds
Started Jan 17 01:55:07 PM PST 24
Finished Jan 17 01:55:13 PM PST 24
Peak memory 199252 kb
Host smart-db326846-b3f3-42fa-bcfb-920ba3aaa1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431468115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2431468115
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3161156468
Short name T768
Test name
Test status
Simulation time 202882385073 ps
CPU time 88.1 seconds
Started Jan 17 01:55:07 PM PST 24
Finished Jan 17 01:56:36 PM PST 24
Peak memory 200088 kb
Host smart-c508d73f-8fc2-4456-9a7a-83f9444cb415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161156468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3161156468
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2815654533
Short name T845
Test name
Test status
Simulation time 25574207801 ps
CPU time 1317.22 seconds
Started Jan 17 01:55:06 PM PST 24
Finished Jan 17 02:17:04 PM PST 24
Peak memory 200256 kb
Host smart-b1e5e9be-cf9c-4712-9591-2a7efaa88619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815654533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2815654533
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2016758438
Short name T107
Test name
Test status
Simulation time 3161756213 ps
CPU time 24.45 seconds
Started Jan 17 01:55:09 PM PST 24
Finished Jan 17 01:55:34 PM PST 24
Peak memory 199120 kb
Host smart-0cf013fb-7274-4d0c-80bd-cffc74fb3f3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016758438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2016758438
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1923564349
Short name T274
Test name
Test status
Simulation time 19558709257 ps
CPU time 8.67 seconds
Started Jan 17 01:55:04 PM PST 24
Finished Jan 17 01:55:14 PM PST 24
Peak memory 198108 kb
Host smart-eb6c536d-ed28-4864-9120-e61c83390bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923564349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1923564349
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3298371400
Short name T110
Test name
Test status
Simulation time 2068651639 ps
CPU time 2.38 seconds
Started Jan 17 01:55:08 PM PST 24
Finished Jan 17 01:55:11 PM PST 24
Peak memory 195656 kb
Host smart-ab6fbf6a-e03f-4c97-8af4-f6b6470eb484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298371400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3298371400
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.408705659
Short name T778
Test name
Test status
Simulation time 515735866 ps
CPU time 1.25 seconds
Started Jan 17 01:55:10 PM PST 24
Finished Jan 17 01:55:12 PM PST 24
Peak memory 199256 kb
Host smart-c4fee338-4a4c-43fb-9c4a-e632a7a42f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408705659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.408705659
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.570904195
Short name T384
Test name
Test status
Simulation time 187329054118 ps
CPU time 489.25 seconds
Started Jan 17 01:55:07 PM PST 24
Finished Jan 17 02:03:17 PM PST 24
Peak memory 225112 kb
Host smart-84ca0024-ef54-44e7-a12e-ff1f3c1e6bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570904195 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.570904195
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3748534619
Short name T1117
Test name
Test status
Simulation time 884578153 ps
CPU time 2.68 seconds
Started Jan 17 01:55:07 PM PST 24
Finished Jan 17 01:55:11 PM PST 24
Peak memory 198568 kb
Host smart-c4de9b96-5719-4d0f-9d4a-36c3c3e78486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748534619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3748534619
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3045082079
Short name T1173
Test name
Test status
Simulation time 55108995431 ps
CPU time 94.01 seconds
Started Jan 17 01:55:11 PM PST 24
Finished Jan 17 01:56:46 PM PST 24
Peak memory 200268 kb
Host smart-1e70ae0f-5883-4ea9-a656-37465d01d7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045082079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3045082079
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3736428536
Short name T950
Test name
Test status
Simulation time 38564681397 ps
CPU time 16.3 seconds
Started Jan 17 02:02:29 PM PST 24
Finished Jan 17 02:02:53 PM PST 24
Peak memory 200024 kb
Host smart-2b7fe441-35f8-4163-a422-55c84da6200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736428536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3736428536
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.956911129
Short name T552
Test name
Test status
Simulation time 18965163641 ps
CPU time 189.81 seconds
Started Jan 17 02:02:30 PM PST 24
Finished Jan 17 02:05:47 PM PST 24
Peak memory 210516 kb
Host smart-416e19a5-82ec-4ad6-abca-3c85c1536ae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956911129 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.956911129
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.624903649
Short name T1061
Test name
Test status
Simulation time 246717353089 ps
CPU time 206.84 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:06:09 PM PST 24
Peak memory 200132 kb
Host smart-bbc4e5dc-edc9-4fa6-ab09-6b722920a151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624903649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.624903649
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3345542661
Short name T25
Test name
Test status
Simulation time 253665656572 ps
CPU time 585.44 seconds
Started Jan 17 02:02:27 PM PST 24
Finished Jan 17 02:12:16 PM PST 24
Peak memory 225120 kb
Host smart-93fc2e0c-6caa-4b12-8bfb-93f9f68b2776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345542661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3345542661
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3215429089
Short name T390
Test name
Test status
Simulation time 86622706441 ps
CPU time 71.78 seconds
Started Jan 17 02:02:25 PM PST 24
Finished Jan 17 02:03:41 PM PST 24
Peak memory 200224 kb
Host smart-c9b1029c-a8ed-44a3-95fc-d8ef8e40a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215429089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3215429089
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3754752694
Short name T426
Test name
Test status
Simulation time 16982862066 ps
CPU time 228.72 seconds
Started Jan 17 02:02:27 PM PST 24
Finished Jan 17 02:06:19 PM PST 24
Peak memory 208504 kb
Host smart-1ec7d112-7d77-449b-bd36-e486471fdb1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754752694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3754752694
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1757747767
Short name T1157
Test name
Test status
Simulation time 87693659267 ps
CPU time 132.59 seconds
Started Jan 17 02:02:31 PM PST 24
Finished Jan 17 02:04:54 PM PST 24
Peak memory 200216 kb
Host smart-eddedc1d-967f-4e77-8cd3-c92af8fd14fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757747767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1757747767
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3773317000
Short name T1011
Test name
Test status
Simulation time 25423430930 ps
CPU time 42.83 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:03:25 PM PST 24
Peak memory 200256 kb
Host smart-3f5472de-0811-42ff-a056-c7f54d0b4b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773317000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3773317000
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1368264295
Short name T767
Test name
Test status
Simulation time 231017193167 ps
CPU time 815.92 seconds
Started Jan 17 02:02:32 PM PST 24
Finished Jan 17 02:16:18 PM PST 24
Peak memory 215848 kb
Host smart-331d40e7-aa24-4287-ad52-666f24ad2bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368264295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1368264295
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.670414207
Short name T158
Test name
Test status
Simulation time 19742382005 ps
CPU time 13.51 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:02:55 PM PST 24
Peak memory 200192 kb
Host smart-20f40a51-d66e-416a-b1c0-e1bb60235128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670414207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.670414207
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1192966486
Short name T795
Test name
Test status
Simulation time 44225519576 ps
CPU time 661.92 seconds
Started Jan 17 02:02:36 PM PST 24
Finished Jan 17 02:13:44 PM PST 24
Peak memory 209144 kb
Host smart-c4725f09-d3aa-4bd8-8551-df1c65c04137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192966486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1192966486
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.336250071
Short name T974
Test name
Test status
Simulation time 11227470803 ps
CPU time 4.12 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:02:46 PM PST 24
Peak memory 200228 kb
Host smart-b937f996-f4bb-43d5-b561-28fd0fbc0cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336250071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.336250071
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.906497601
Short name T620
Test name
Test status
Simulation time 60495877833 ps
CPU time 878.02 seconds
Started Jan 17 02:02:36 PM PST 24
Finished Jan 17 02:17:20 PM PST 24
Peak memory 216984 kb
Host smart-895f596e-4385-4226-9138-5797337ea0d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906497601 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.906497601
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2182228129
Short name T184
Test name
Test status
Simulation time 37039024485 ps
CPU time 57.25 seconds
Started Jan 17 02:02:32 PM PST 24
Finished Jan 17 02:03:39 PM PST 24
Peak memory 200284 kb
Host smart-8c5d23e2-24e3-4cbf-a453-2fb72bb51518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182228129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2182228129
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2441351533
Short name T1070
Test name
Test status
Simulation time 104856336786 ps
CPU time 1194.48 seconds
Started Jan 17 02:02:41 PM PST 24
Finished Jan 17 02:22:39 PM PST 24
Peak memory 228840 kb
Host smart-7fa2ff33-5433-4977-b7fb-15f9ba0d6583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441351533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2441351533
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.178729398
Short name T421
Test name
Test status
Simulation time 34074934987 ps
CPU time 22.98 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:03:05 PM PST 24
Peak memory 200244 kb
Host smart-314fddfa-45f9-47ec-ad5e-fca866347f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178729398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.178729398
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2826356719
Short name T915
Test name
Test status
Simulation time 20996340083 ps
CPU time 154.47 seconds
Started Jan 17 02:02:41 PM PST 24
Finished Jan 17 02:05:19 PM PST 24
Peak memory 208800 kb
Host smart-d4e2c46e-40f8-4629-a011-13365a49425d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826356719 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2826356719
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.4291437340
Short name T135
Test name
Test status
Simulation time 29114976859 ps
CPU time 19.45 seconds
Started Jan 17 02:02:34 PM PST 24
Finished Jan 17 02:03:01 PM PST 24
Peak memory 200236 kb
Host smart-ec31e58e-1d5a-4d13-9ba6-8ad4ba59dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291437340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4291437340
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3637415970
Short name T691
Test name
Test status
Simulation time 21655848 ps
CPU time 0.56 seconds
Started Jan 17 01:55:18 PM PST 24
Finished Jan 17 01:55:19 PM PST 24
Peak memory 195648 kb
Host smart-007bb81f-962e-4d99-b634-2c3534eeec2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637415970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3637415970
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1836302837
Short name T1172
Test name
Test status
Simulation time 36556969430 ps
CPU time 16.92 seconds
Started Jan 17 01:55:14 PM PST 24
Finished Jan 17 01:55:32 PM PST 24
Peak memory 200172 kb
Host smart-a4f786eb-9fb6-4d9b-917b-6aeb0d06d256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836302837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1836302837
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2242234664
Short name T13
Test name
Test status
Simulation time 99681316925 ps
CPU time 171.22 seconds
Started Jan 17 01:55:18 PM PST 24
Finished Jan 17 01:58:10 PM PST 24
Peak memory 200084 kb
Host smart-f4cbd33e-8029-411d-a85c-15d7ac63afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242234664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2242234664
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4122389654
Short name T805
Test name
Test status
Simulation time 38999475630 ps
CPU time 14.48 seconds
Started Jan 17 01:55:16 PM PST 24
Finished Jan 17 01:55:31 PM PST 24
Peak memory 198472 kb
Host smart-0faa3eec-0108-4ce8-a9a1-2c11f8fad2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122389654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4122389654
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3788565951
Short name T437
Test name
Test status
Simulation time 355262817623 ps
CPU time 100.38 seconds
Started Jan 17 01:55:17 PM PST 24
Finished Jan 17 01:56:58 PM PST 24
Peak memory 200196 kb
Host smart-786ed75f-d105-480b-832e-89fd3f756445
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788565951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3788565951
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3932569930
Short name T699
Test name
Test status
Simulation time 31085471015 ps
CPU time 140.66 seconds
Started Jan 17 01:55:17 PM PST 24
Finished Jan 17 01:57:38 PM PST 24
Peak memory 200140 kb
Host smart-8c6bb1c1-3b6e-4316-9905-0aed71f6aa3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932569930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3932569930
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3038507205
Short name T914
Test name
Test status
Simulation time 2151797925 ps
CPU time 4.56 seconds
Started Jan 17 01:55:17 PM PST 24
Finished Jan 17 01:55:23 PM PST 24
Peak memory 197292 kb
Host smart-b6408e18-3644-4e37-b4fe-a6d2969e230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038507205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3038507205
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2706112623
Short name T1207
Test name
Test status
Simulation time 81618536157 ps
CPU time 135.14 seconds
Started Jan 17 01:55:15 PM PST 24
Finished Jan 17 01:57:31 PM PST 24
Peak memory 199576 kb
Host smart-5c030386-27fb-4990-b4a3-e06fac317793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706112623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2706112623
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.298099305
Short name T897
Test name
Test status
Simulation time 16902215540 ps
CPU time 448.16 seconds
Started Jan 17 01:55:17 PM PST 24
Finished Jan 17 02:02:45 PM PST 24
Peak memory 200276 kb
Host smart-7fae8ba9-3f45-4e4d-9b9a-5160d9332f56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=298099305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.298099305
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.212859028
Short name T535
Test name
Test status
Simulation time 1171994954 ps
CPU time 1.64 seconds
Started Jan 17 01:55:15 PM PST 24
Finished Jan 17 01:55:17 PM PST 24
Peak memory 196716 kb
Host smart-196fe50f-910c-40ca-9ec7-543fe24cf01f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212859028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.212859028
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.336333508
Short name T397
Test name
Test status
Simulation time 131854275674 ps
CPU time 48.8 seconds
Started Jan 17 01:55:15 PM PST 24
Finished Jan 17 01:56:05 PM PST 24
Peak memory 200220 kb
Host smart-0523cb72-66bb-44b4-aabc-d4400e70cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336333508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.336333508
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.4214140827
Short name T972
Test name
Test status
Simulation time 3026600724 ps
CPU time 1.52 seconds
Started Jan 17 01:55:16 PM PST 24
Finished Jan 17 01:55:18 PM PST 24
Peak memory 195844 kb
Host smart-a4537231-e3b5-425d-aac8-244ea6104e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214140827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.4214140827
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.53965745
Short name T896
Test name
Test status
Simulation time 693659103 ps
CPU time 1.76 seconds
Started Jan 17 01:55:08 PM PST 24
Finished Jan 17 01:55:10 PM PST 24
Peak memory 198652 kb
Host smart-a5781ea4-cd85-4853-b4d5-60e9d1d0bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53965745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.53965745
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1792620020
Short name T319
Test name
Test status
Simulation time 195399296538 ps
CPU time 327.56 seconds
Started Jan 17 01:55:19 PM PST 24
Finished Jan 17 02:00:48 PM PST 24
Peak memory 200196 kb
Host smart-9ad49995-2faf-4f8f-b40e-dab439363e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792620020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1792620020
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.4157891494
Short name T1091
Test name
Test status
Simulation time 8368887195 ps
CPU time 11.23 seconds
Started Jan 17 01:55:15 PM PST 24
Finished Jan 17 01:55:27 PM PST 24
Peak memory 199640 kb
Host smart-2026796b-f1ab-4842-b518-777256e75750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157891494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.4157891494
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.675825615
Short name T797
Test name
Test status
Simulation time 34423391779 ps
CPU time 58.49 seconds
Started Jan 17 01:55:20 PM PST 24
Finished Jan 17 01:56:19 PM PST 24
Peak memory 200220 kb
Host smart-74c88014-f17e-412c-a7f1-0719556a1d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675825615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.675825615
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2099228213
Short name T350
Test name
Test status
Simulation time 117970725304 ps
CPU time 38.46 seconds
Started Jan 17 02:02:32 PM PST 24
Finished Jan 17 02:03:20 PM PST 24
Peak memory 200192 kb
Host smart-dc0cfd83-6943-428e-aff9-7fa9ec5a2c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099228213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2099228213
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.392635971
Short name T433
Test name
Test status
Simulation time 39398187784 ps
CPU time 486.13 seconds
Started Jan 17 02:02:33 PM PST 24
Finished Jan 17 02:10:48 PM PST 24
Peak memory 215392 kb
Host smart-690a2730-bbae-48f3-b0ca-7b99262d3938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392635971 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.392635971
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2813567339
Short name T173
Test name
Test status
Simulation time 82852488587 ps
CPU time 113.41 seconds
Started Jan 17 02:02:39 PM PST 24
Finished Jan 17 02:04:37 PM PST 24
Peak memory 200184 kb
Host smart-be99e5cc-317c-40a0-a889-a23071bd9373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813567339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2813567339
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2581855773
Short name T992
Test name
Test status
Simulation time 37744656608 ps
CPU time 248.68 seconds
Started Jan 17 02:02:37 PM PST 24
Finished Jan 17 02:06:52 PM PST 24
Peak memory 216704 kb
Host smart-0ca006f4-8da9-4540-8453-35052f6cb727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581855773 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2581855773
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.226469882
Short name T276
Test name
Test status
Simulation time 16167729148 ps
CPU time 45.79 seconds
Started Jan 17 02:02:41 PM PST 24
Finished Jan 17 02:03:30 PM PST 24
Peak memory 200220 kb
Host smart-f95d9393-83b0-405d-b60f-6ec4486e2499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226469882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.226469882
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.23424648
Short name T522
Test name
Test status
Simulation time 16779613027 ps
CPU time 198.88 seconds
Started Jan 17 02:02:38 PM PST 24
Finished Jan 17 02:06:03 PM PST 24
Peak memory 216940 kb
Host smart-81fa0109-e795-4413-816c-f7163d2bd78a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23424648 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.23424648
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1263699522
Short name T115
Test name
Test status
Simulation time 138203289170 ps
CPU time 31.44 seconds
Started Jan 17 02:02:36 PM PST 24
Finished Jan 17 02:03:13 PM PST 24
Peak memory 200284 kb
Host smart-fe2f7c06-7113-4414-bc4f-1f2d0261e0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263699522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1263699522
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2817844058
Short name T305
Test name
Test status
Simulation time 42568204643 ps
CPU time 75.02 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:04:00 PM PST 24
Peak memory 199724 kb
Host smart-3b850599-893e-42fa-b89b-c33329748f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817844058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2817844058
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.124510266
Short name T1088
Test name
Test status
Simulation time 56019450410 ps
CPU time 547.32 seconds
Started Jan 17 02:02:40 PM PST 24
Finished Jan 17 02:11:51 PM PST 24
Peak memory 216900 kb
Host smart-64c818f9-afab-4e5d-bced-c557236638c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124510266 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.124510266
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.671434772
Short name T729
Test name
Test status
Simulation time 10047463112 ps
CPU time 17.34 seconds
Started Jan 17 02:02:38 PM PST 24
Finished Jan 17 02:03:01 PM PST 24
Peak memory 200192 kb
Host smart-e88501c0-9a69-4edd-af5b-e0cc163db4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671434772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.671434772
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.24979348
Short name T281
Test name
Test status
Simulation time 324959014781 ps
CPU time 978.59 seconds
Started Jan 17 02:02:43 PM PST 24
Finished Jan 17 02:19:04 PM PST 24
Peak memory 225268 kb
Host smart-81cac74c-c37a-4117-8028-07fc1cacbdb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24979348 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.24979348
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2263392439
Short name T754
Test name
Test status
Simulation time 94717082203 ps
CPU time 163.76 seconds
Started Jan 17 02:02:40 PM PST 24
Finished Jan 17 02:05:28 PM PST 24
Peak memory 200252 kb
Host smart-b2fc2ac6-9795-47a0-81be-6ff8e92fedea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263392439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2263392439
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2186922246
Short name T1017
Test name
Test status
Simulation time 42598691380 ps
CPU time 970.82 seconds
Started Jan 17 02:02:43 PM PST 24
Finished Jan 17 02:18:56 PM PST 24
Peak memory 208568 kb
Host smart-089ddc08-a41e-432c-bec8-55edcfba189b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186922246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2186922246
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3749170987
Short name T821
Test name
Test status
Simulation time 19158359207 ps
CPU time 165.3 seconds
Started Jan 17 02:02:37 PM PST 24
Finished Jan 17 02:05:28 PM PST 24
Peak memory 216940 kb
Host smart-1d8ff62c-d195-40da-93c9-8b5584fcb1f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749170987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3749170987
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1546068123
Short name T1193
Test name
Test status
Simulation time 87179571055 ps
CPU time 1110.95 seconds
Started Jan 17 02:02:38 PM PST 24
Finished Jan 17 02:21:15 PM PST 24
Peak memory 216728 kb
Host smart-2197cb7f-0e54-444b-96cd-ecd519ee8867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546068123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1546068123
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.124143023
Short name T1073
Test name
Test status
Simulation time 71341238547 ps
CPU time 13 seconds
Started Jan 17 02:02:40 PM PST 24
Finished Jan 17 02:02:57 PM PST 24
Peak memory 198568 kb
Host smart-a6bfea70-32c2-4c9c-910a-c6a26bbf55d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124143023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.124143023
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2697250319
Short name T710
Test name
Test status
Simulation time 16112428058 ps
CPU time 169.09 seconds
Started Jan 17 02:02:37 PM PST 24
Finished Jan 17 02:05:33 PM PST 24
Peak memory 216896 kb
Host smart-155ad22f-a0bb-472a-8611-849dcd9553e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697250319 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2697250319
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1914004049
Short name T843
Test name
Test status
Simulation time 21240010 ps
CPU time 0.54 seconds
Started Jan 17 01:55:24 PM PST 24
Finished Jan 17 01:55:28 PM PST 24
Peak memory 195688 kb
Host smart-ad7fb3a4-2473-4273-9f8f-53d342fa4898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914004049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1914004049
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1696953986
Short name T259
Test name
Test status
Simulation time 61624295915 ps
CPU time 91.22 seconds
Started Jan 17 01:55:17 PM PST 24
Finished Jan 17 01:56:49 PM PST 24
Peak memory 200208 kb
Host smart-1beb513f-a2af-489c-92fb-0096b9dc0010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696953986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1696953986
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.464253436
Short name T371
Test name
Test status
Simulation time 241806695238 ps
CPU time 63.5 seconds
Started Jan 17 01:55:18 PM PST 24
Finished Jan 17 01:56:22 PM PST 24
Peak memory 199540 kb
Host smart-d8742c34-c205-46c3-8140-c2ee924fdf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464253436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.464253436
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.2822383385
Short name T1136
Test name
Test status
Simulation time 466326723215 ps
CPU time 637.01 seconds
Started Jan 17 01:55:19 PM PST 24
Finished Jan 17 02:05:57 PM PST 24
Peak memory 200248 kb
Host smart-be57bd5a-b172-4eda-946c-98e9e1c2b2ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822383385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2822383385
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.126161071
Short name T451
Test name
Test status
Simulation time 45518805044 ps
CPU time 90.24 seconds
Started Jan 17 01:55:23 PM PST 24
Finished Jan 17 01:56:56 PM PST 24
Peak memory 200280 kb
Host smart-a39491f8-f22c-469e-a1bd-ae4c107f8bc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126161071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.126161071
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2294319683
Short name T900
Test name
Test status
Simulation time 3870317079 ps
CPU time 9.4 seconds
Started Jan 17 01:55:25 PM PST 24
Finished Jan 17 01:55:38 PM PST 24
Peak memory 198504 kb
Host smart-a7398a9e-82a6-499c-af24-d8d1802d4e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294319683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2294319683
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1500961636
Short name T1201
Test name
Test status
Simulation time 58118038811 ps
CPU time 100.35 seconds
Started Jan 17 01:55:16 PM PST 24
Finished Jan 17 01:56:56 PM PST 24
Peak memory 208716 kb
Host smart-754f90db-32a0-4df3-bff0-2985268587cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500961636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1500961636
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2844934013
Short name T936
Test name
Test status
Simulation time 16064768952 ps
CPU time 175.44 seconds
Started Jan 17 01:55:26 PM PST 24
Finished Jan 17 01:58:25 PM PST 24
Peak memory 200196 kb
Host smart-1ce90708-91dc-451e-8bd2-fc9a79dae44c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2844934013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2844934013
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.920224624
Short name T1140
Test name
Test status
Simulation time 118839187021 ps
CPU time 187.53 seconds
Started Jan 17 01:55:25 PM PST 24
Finished Jan 17 01:58:37 PM PST 24
Peak memory 199900 kb
Host smart-56da07b2-fe89-4755-ab9f-e5cc9ff77b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920224624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.920224624
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1655765541
Short name T1184
Test name
Test status
Simulation time 4265801468 ps
CPU time 2.13 seconds
Started Jan 17 01:55:26 PM PST 24
Finished Jan 17 01:55:32 PM PST 24
Peak memory 196072 kb
Host smart-fea4469a-bf76-4593-8db7-dbd8d4114488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655765541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1655765541
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2813112320
Short name T844
Test name
Test status
Simulation time 164766103 ps
CPU time 0.78 seconds
Started Jan 17 01:55:15 PM PST 24
Finished Jan 17 01:55:17 PM PST 24
Peak memory 196740 kb
Host smart-4c9969a8-9eb5-4dac-97af-8943168de350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813112320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2813112320
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.4046442490
Short name T172
Test name
Test status
Simulation time 164808586824 ps
CPU time 55.81 seconds
Started Jan 17 01:55:26 PM PST 24
Finished Jan 17 01:56:26 PM PST 24
Peak memory 200488 kb
Host smart-d049b885-2e59-4ee2-b425-4cf0f9360bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046442490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.4046442490
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1865855451
Short name T448
Test name
Test status
Simulation time 86121191762 ps
CPU time 1699.08 seconds
Started Jan 17 01:55:27 PM PST 24
Finished Jan 17 02:23:49 PM PST 24
Peak memory 228024 kb
Host smart-1a041a1d-fa2c-4c17-be75-a48983a381e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865855451 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1865855451
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.170087991
Short name T636
Test name
Test status
Simulation time 8703803620 ps
CPU time 7.31 seconds
Started Jan 17 01:55:25 PM PST 24
Finished Jan 17 01:55:36 PM PST 24
Peak memory 199864 kb
Host smart-6b66b792-e5b6-426c-9b8f-a4977b7813ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170087991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.170087991
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2749382329
Short name T720
Test name
Test status
Simulation time 36276541562 ps
CPU time 17.79 seconds
Started Jan 17 01:55:18 PM PST 24
Finished Jan 17 01:55:37 PM PST 24
Peak memory 199384 kb
Host smart-ea25bfa3-2814-41de-8375-a0136d46e152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749382329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2749382329
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.237635130
Short name T207
Test name
Test status
Simulation time 19108473806 ps
CPU time 17.19 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:03:02 PM PST 24
Peak memory 200228 kb
Host smart-59a2bd17-25a4-4e7b-9f84-06fa7e16a630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237635130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.237635130
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1440809118
Short name T1092
Test name
Test status
Simulation time 37693568018 ps
CPU time 170.57 seconds
Started Jan 17 02:02:37 PM PST 24
Finished Jan 17 02:05:34 PM PST 24
Peak memory 209440 kb
Host smart-3123ebd6-4498-4760-9ce0-5dcaa13dfa95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440809118 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1440809118
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3209724395
Short name T275
Test name
Test status
Simulation time 20843014976 ps
CPU time 16.38 seconds
Started Jan 17 02:02:40 PM PST 24
Finished Jan 17 02:03:00 PM PST 24
Peak memory 200272 kb
Host smart-e382a769-52e1-414c-acc1-c2063b06d847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209724395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3209724395
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3811203754
Short name T429
Test name
Test status
Simulation time 69527399247 ps
CPU time 199.04 seconds
Started Jan 17 02:02:39 PM PST 24
Finished Jan 17 02:06:03 PM PST 24
Peak memory 216920 kb
Host smart-54b5b18e-1e9c-4046-b5dc-ddf011a6fa7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811203754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3811203754
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.997240020
Short name T377
Test name
Test status
Simulation time 245450596413 ps
CPU time 240.05 seconds
Started Jan 17 02:02:44 PM PST 24
Finished Jan 17 02:06:46 PM PST 24
Peak memory 200204 kb
Host smart-2e241b0d-a55e-47e4-a3e6-6e1267b85e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997240020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.997240020
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.910639654
Short name T828
Test name
Test status
Simulation time 67669746177 ps
CPU time 193.88 seconds
Started Jan 17 02:02:43 PM PST 24
Finished Jan 17 02:05:59 PM PST 24
Peak memory 216976 kb
Host smart-7994baec-1a66-4446-9953-a949b71e9fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910639654 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.910639654
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2585317583
Short name T681
Test name
Test status
Simulation time 34848369765 ps
CPU time 15.6 seconds
Started Jan 17 02:02:43 PM PST 24
Finished Jan 17 02:03:01 PM PST 24
Peak memory 200276 kb
Host smart-e3a81bc0-9ea7-4517-a331-7ed9e6e13d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585317583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2585317583
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2351607885
Short name T989
Test name
Test status
Simulation time 93615913412 ps
CPU time 347.47 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:08:32 PM PST 24
Peak memory 216920 kb
Host smart-245c8d66-f0fc-4c80-beca-8fee640ea065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351607885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2351607885
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.145153669
Short name T906
Test name
Test status
Simulation time 413143292598 ps
CPU time 749.22 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:15:14 PM PST 24
Peak memory 224700 kb
Host smart-0ee4f21a-a841-4272-aed8-0ec1faba4fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145153669 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.145153669
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1865635584
Short name T271
Test name
Test status
Simulation time 328708929244 ps
CPU time 44.22 seconds
Started Jan 17 02:02:39 PM PST 24
Finished Jan 17 02:03:28 PM PST 24
Peak memory 200272 kb
Host smart-d19bd7ea-cd87-4b32-aa7d-0a45298441eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865635584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1865635584
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2457720241
Short name T892
Test name
Test status
Simulation time 509385011972 ps
CPU time 338.72 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:08:24 PM PST 24
Peak memory 216976 kb
Host smart-bf602959-2222-4b80-86c6-98e5944126c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457720241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2457720241
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2188210946
Short name T1033
Test name
Test status
Simulation time 48408492079 ps
CPU time 908.83 seconds
Started Jan 17 02:02:43 PM PST 24
Finished Jan 17 02:17:54 PM PST 24
Peak memory 225180 kb
Host smart-78e356ad-ac61-4ad9-86ba-a0ef33007066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188210946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2188210946
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.576835689
Short name T1089
Test name
Test status
Simulation time 75977796265 ps
CPU time 33.55 seconds
Started Jan 17 02:02:42 PM PST 24
Finished Jan 17 02:03:18 PM PST 24
Peak memory 200100 kb
Host smart-2373595a-0c0d-469f-bd3d-b5cfadab3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576835689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.576835689
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.4226097811
Short name T884
Test name
Test status
Simulation time 15659027173 ps
CPU time 204.24 seconds
Started Jan 17 02:02:41 PM PST 24
Finished Jan 17 02:06:09 PM PST 24
Peak memory 209916 kb
Host smart-39c75e25-71f2-4807-9583-534b4f4effa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226097811 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.4226097811
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1436930536
Short name T786
Test name
Test status
Simulation time 124510232889 ps
CPU time 50.08 seconds
Started Jan 17 02:02:41 PM PST 24
Finished Jan 17 02:03:35 PM PST 24
Peak memory 200268 kb
Host smart-2de686fa-c74a-4c91-87da-408d92c91918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436930536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1436930536
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1893696489
Short name T392
Test name
Test status
Simulation time 365407910145 ps
CPU time 1102.87 seconds
Started Jan 17 02:02:44 PM PST 24
Finished Jan 17 02:21:09 PM PST 24
Peak memory 217008 kb
Host smart-071a79b5-9433-4f9a-b291-d549f36bf1b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893696489 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1893696489
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1125658307
Short name T1123
Test name
Test status
Simulation time 52547570 ps
CPU time 0.55 seconds
Started Jan 17 01:55:35 PM PST 24
Finished Jan 17 01:55:39 PM PST 24
Peak memory 195620 kb
Host smart-4aaecd73-995d-4428-a508-3eab47aafa41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125658307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1125658307
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.400129792
Short name T1114
Test name
Test status
Simulation time 35337853252 ps
CPU time 73.02 seconds
Started Jan 17 01:55:25 PM PST 24
Finished Jan 17 01:56:42 PM PST 24
Peak memory 200212 kb
Host smart-b3c327fc-9ebd-44cd-a691-dfe16d8df2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400129792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.400129792
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3452760399
Short name T559
Test name
Test status
Simulation time 23463875363 ps
CPU time 36.99 seconds
Started Jan 17 01:55:24 PM PST 24
Finished Jan 17 01:56:04 PM PST 24
Peak memory 200276 kb
Host smart-a092bd3f-636a-4d93-af70-405632fee5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452760399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3452760399
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3927768068
Short name T349
Test name
Test status
Simulation time 70296750648 ps
CPU time 100.94 seconds
Started Jan 17 01:55:25 PM PST 24
Finished Jan 17 01:57:09 PM PST 24
Peak memory 199800 kb
Host smart-a2e66172-8f4f-4fd8-9dd5-083102e50751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927768068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3927768068
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2577877633
Short name T723
Test name
Test status
Simulation time 43667634699 ps
CPU time 73.96 seconds
Started Jan 17 01:55:26 PM PST 24
Finished Jan 17 01:56:43 PM PST 24
Peak memory 198460 kb
Host smart-dc1cc91d-6180-45c2-86c0-58d9942b25e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577877633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2577877633
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.628431904
Short name T1166
Test name
Test status
Simulation time 122755614937 ps
CPU time 292.65 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 02:00:38 PM PST 24
Peak memory 200192 kb
Host smart-79f3a485-46c9-4772-bfaa-70a501de74b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628431904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.628431904
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3276796123
Short name T1230
Test name
Test status
Simulation time 1327406271 ps
CPU time 2.53 seconds
Started Jan 17 01:55:38 PM PST 24
Finished Jan 17 01:55:42 PM PST 24
Peak memory 198320 kb
Host smart-c565395f-8b46-404f-b9db-55978d833576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276796123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3276796123
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2431370045
Short name T1142
Test name
Test status
Simulation time 127961091353 ps
CPU time 119.8 seconds
Started Jan 17 01:55:24 PM PST 24
Finished Jan 17 01:57:28 PM PST 24
Peak memory 200524 kb
Host smart-e67d30f8-c1a7-46df-9b5a-06947524201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431370045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2431370045
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1342485530
Short name T566
Test name
Test status
Simulation time 28166204526 ps
CPU time 395.51 seconds
Started Jan 17 01:55:44 PM PST 24
Finished Jan 17 02:02:20 PM PST 24
Peak memory 200188 kb
Host smart-472d5249-2b95-48df-9e64-41de915d4c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342485530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1342485530
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2395290213
Short name T1102
Test name
Test status
Simulation time 2970072864 ps
CPU time 5.28 seconds
Started Jan 17 01:55:26 PM PST 24
Finished Jan 17 01:55:35 PM PST 24
Peak memory 198268 kb
Host smart-e52643dc-3a92-43fe-9c58-2f8161e32af6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2395290213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2395290213
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3497944847
Short name T864
Test name
Test status
Simulation time 22172205387 ps
CPU time 33.92 seconds
Started Jan 17 01:55:36 PM PST 24
Finished Jan 17 01:56:12 PM PST 24
Peak memory 200152 kb
Host smart-801f6119-ae57-4489-a349-212761da718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497944847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3497944847
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.64445038
Short name T798
Test name
Test status
Simulation time 7140913741 ps
CPU time 3.8 seconds
Started Jan 17 01:55:25 PM PST 24
Finished Jan 17 01:55:33 PM PST 24
Peak memory 196080 kb
Host smart-8d439a29-a18e-4f15-bcb0-bf8a7c0ac53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64445038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.64445038
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.401787245
Short name T1112
Test name
Test status
Simulation time 5555828058 ps
CPU time 12.92 seconds
Started Jan 17 01:55:25 PM PST 24
Finished Jan 17 01:55:41 PM PST 24
Peak memory 198988 kb
Host smart-22244a17-a652-44dc-9399-d41c69ba6d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401787245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.401787245
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1682370520
Short name T610
Test name
Test status
Simulation time 820272981907 ps
CPU time 657.68 seconds
Started Jan 17 01:55:41 PM PST 24
Finished Jan 17 02:06:40 PM PST 24
Peak memory 200448 kb
Host smart-1142d123-d25d-4908-8d64-282425c979c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682370520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1682370520
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1883767862
Short name T185
Test name
Test status
Simulation time 85382886408 ps
CPU time 1415.56 seconds
Started Jan 17 01:55:36 PM PST 24
Finished Jan 17 02:19:14 PM PST 24
Peak memory 225592 kb
Host smart-ae138c8b-860c-4d76-a981-893004a94c14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883767862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1883767862
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.719323972
Short name T544
Test name
Test status
Simulation time 1082453331 ps
CPU time 1.66 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:55:43 PM PST 24
Peak memory 198260 kb
Host smart-ca51bf10-fcd7-4129-a267-d599027f9912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719323972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.719323972
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1988703823
Short name T998
Test name
Test status
Simulation time 47982430101 ps
CPU time 32.66 seconds
Started Jan 17 01:55:23 PM PST 24
Finished Jan 17 01:55:59 PM PST 24
Peak memory 200212 kb
Host smart-6db14d59-7b01-4e53-82cd-5c3a8e0ebf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988703823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1988703823
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4227031659
Short name T932
Test name
Test status
Simulation time 22752460951 ps
CPU time 19.54 seconds
Started Jan 17 02:02:40 PM PST 24
Finished Jan 17 02:03:03 PM PST 24
Peak memory 200276 kb
Host smart-00461108-9b04-47c1-a41a-9d96fc1cdf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227031659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4227031659
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3184479692
Short name T302
Test name
Test status
Simulation time 311921383113 ps
CPU time 247.06 seconds
Started Jan 17 02:02:47 PM PST 24
Finished Jan 17 02:06:55 PM PST 24
Peak memory 209556 kb
Host smart-9ca9ac13-c93f-4af3-a3ed-db3dd184de6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184479692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3184479692
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1386927005
Short name T328
Test name
Test status
Simulation time 27958094659 ps
CPU time 16.84 seconds
Started Jan 17 02:02:48 PM PST 24
Finished Jan 17 02:03:10 PM PST 24
Peak memory 200276 kb
Host smart-e17731ee-9638-421d-8cc0-51f67b13a2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386927005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1386927005
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1616566280
Short name T364
Test name
Test status
Simulation time 34815450715 ps
CPU time 193.1 seconds
Started Jan 17 02:02:47 PM PST 24
Finished Jan 17 02:06:02 PM PST 24
Peak memory 210456 kb
Host smart-4ee10930-7a8a-4032-a591-11d450381a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616566280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1616566280
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3943834297
Short name T250
Test name
Test status
Simulation time 9707492611 ps
CPU time 16.88 seconds
Started Jan 17 02:02:46 PM PST 24
Finished Jan 17 02:03:05 PM PST 24
Peak memory 199956 kb
Host smart-3e5ed500-c4c4-4c78-b207-577cb60a1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943834297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3943834297
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1669787522
Short name T395
Test name
Test status
Simulation time 203380196166 ps
CPU time 22.91 seconds
Started Jan 17 02:02:51 PM PST 24
Finished Jan 17 02:03:19 PM PST 24
Peak memory 200240 kb
Host smart-6b96ddbf-c2e4-4755-8876-c6e8f5a439dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669787522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1669787522
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2908525031
Short name T453
Test name
Test status
Simulation time 90703451576 ps
CPU time 364.69 seconds
Started Jan 17 02:02:48 PM PST 24
Finished Jan 17 02:08:54 PM PST 24
Peak memory 208576 kb
Host smart-68279f68-511c-413d-a656-9672018560d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908525031 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2908525031
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4248951840
Short name T1108
Test name
Test status
Simulation time 42534748527 ps
CPU time 38.89 seconds
Started Jan 17 02:02:51 PM PST 24
Finished Jan 17 02:03:35 PM PST 24
Peak memory 199984 kb
Host smart-0276835b-c9d0-4bbf-a122-1ce237a988a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248951840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4248951840
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2421215167
Short name T558
Test name
Test status
Simulation time 107704950820 ps
CPU time 606.92 seconds
Started Jan 17 02:02:48 PM PST 24
Finished Jan 17 02:12:57 PM PST 24
Peak memory 208500 kb
Host smart-2f26e644-3e70-4061-b14a-4f46f034c9ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421215167 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2421215167
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2448727343
Short name T239
Test name
Test status
Simulation time 111780755335 ps
CPU time 49.18 seconds
Started Jan 17 02:02:53 PM PST 24
Finished Jan 17 02:03:46 PM PST 24
Peak memory 200248 kb
Host smart-54b61689-952a-4f10-873c-485b8625cb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448727343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2448727343
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2192873337
Short name T344
Test name
Test status
Simulation time 623234989406 ps
CPU time 559.04 seconds
Started Jan 17 02:02:49 PM PST 24
Finished Jan 17 02:12:13 PM PST 24
Peak memory 212092 kb
Host smart-e18d33d3-a972-4f16-ac2e-5da2f3019503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192873337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2192873337
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.4233060504
Short name T197
Test name
Test status
Simulation time 191891895551 ps
CPU time 16.71 seconds
Started Jan 17 02:02:49 PM PST 24
Finished Jan 17 02:03:12 PM PST 24
Peak memory 199944 kb
Host smart-e8d1b499-e34a-47ab-9280-8c8ed90f2fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233060504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4233060504
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.779004001
Short name T322
Test name
Test status
Simulation time 16385796445 ps
CPU time 203.12 seconds
Started Jan 17 02:02:56 PM PST 24
Finished Jan 17 02:06:22 PM PST 24
Peak memory 208460 kb
Host smart-3563135b-4238-456c-bcfb-ba64b9f256af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779004001 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.779004001
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.533791676
Short name T277
Test name
Test status
Simulation time 43889028961 ps
CPU time 15.5 seconds
Started Jan 17 02:02:56 PM PST 24
Finished Jan 17 02:03:14 PM PST 24
Peak memory 200056 kb
Host smart-96fde057-e746-4554-b654-bed1d184055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533791676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.533791676
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.428311690
Short name T450
Test name
Test status
Simulation time 70852160946 ps
CPU time 902.66 seconds
Started Jan 17 02:02:54 PM PST 24
Finished Jan 17 02:18:00 PM PST 24
Peak memory 226280 kb
Host smart-8f331b49-c29b-40a2-a94b-0b39d9d6c23e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428311690 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.428311690
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.848943545
Short name T143
Test name
Test status
Simulation time 118621021636 ps
CPU time 51.04 seconds
Started Jan 17 02:02:54 PM PST 24
Finished Jan 17 02:03:49 PM PST 24
Peak memory 200172 kb
Host smart-1fa1dcc6-c7d8-489b-933e-87a82f38f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848943545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.848943545
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1448533632
Short name T84
Test name
Test status
Simulation time 47814561572 ps
CPU time 217.47 seconds
Started Jan 17 02:02:53 PM PST 24
Finished Jan 17 02:06:34 PM PST 24
Peak memory 216716 kb
Host smart-5d412e05-080a-4678-a051-b1a5bf7da2d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448533632 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1448533632
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1965300840
Short name T523
Test name
Test status
Simulation time 16420707 ps
CPU time 0.57 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:55:42 PM PST 24
Peak memory 195644 kb
Host smart-e4020cdd-cddb-4601-9cb0-9ea1fd5762f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965300840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1965300840
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3257593106
Short name T956
Test name
Test status
Simulation time 151660951446 ps
CPU time 92.21 seconds
Started Jan 17 01:55:31 PM PST 24
Finished Jan 17 01:57:10 PM PST 24
Peak memory 200240 kb
Host smart-0295f59d-e474-4599-8aa7-9c38942934f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257593106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3257593106
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2849380741
Short name T1200
Test name
Test status
Simulation time 95191922151 ps
CPU time 165.59 seconds
Started Jan 17 01:55:35 PM PST 24
Finished Jan 17 01:58:24 PM PST 24
Peak memory 200152 kb
Host smart-2086b8dc-3dc5-4d1a-82b2-101555915cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849380741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2849380741
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2986429725
Short name T773
Test name
Test status
Simulation time 575121055988 ps
CPU time 974.6 seconds
Started Jan 17 01:55:32 PM PST 24
Finished Jan 17 02:11:53 PM PST 24
Peak memory 200256 kb
Host smart-4d58a31a-1ac2-4b25-988c-64714a331c32
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986429725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2986429725
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2825047110
Short name T521
Test name
Test status
Simulation time 150700523536 ps
CPU time 815.79 seconds
Started Jan 17 01:55:38 PM PST 24
Finished Jan 17 02:09:15 PM PST 24
Peak memory 200272 kb
Host smart-6513e3b6-94e0-4f01-96aa-7db22f7f4272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825047110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2825047110
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4125234102
Short name T941
Test name
Test status
Simulation time 5609595205 ps
CPU time 3.89 seconds
Started Jan 17 01:55:41 PM PST 24
Finished Jan 17 01:55:46 PM PST 24
Peak memory 198800 kb
Host smart-04134d35-e0f1-462e-b68b-625abc44149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125234102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4125234102
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1701322261
Short name T858
Test name
Test status
Simulation time 7241693954 ps
CPU time 12.08 seconds
Started Jan 17 01:55:35 PM PST 24
Finished Jan 17 01:55:50 PM PST 24
Peak memory 195504 kb
Host smart-8f8104b1-0dc1-49a8-bc8b-241f3781af97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701322261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1701322261
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.485808414
Short name T819
Test name
Test status
Simulation time 22700941164 ps
CPU time 588.35 seconds
Started Jan 17 01:55:37 PM PST 24
Finished Jan 17 02:05:27 PM PST 24
Peak memory 200216 kb
Host smart-99085e3c-9348-432a-b4bf-7b8a82e1b305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485808414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.485808414
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.193053062
Short name T917
Test name
Test status
Simulation time 1171242164 ps
CPU time 8.1 seconds
Started Jan 17 01:55:37 PM PST 24
Finished Jan 17 01:55:46 PM PST 24
Peak memory 197956 kb
Host smart-3ff26b66-cc43-4170-a42d-13cdea19d7a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193053062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.193053062
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3541665421
Short name T189
Test name
Test status
Simulation time 52132451945 ps
CPU time 26.25 seconds
Started Jan 17 01:55:38 PM PST 24
Finished Jan 17 01:56:05 PM PST 24
Peak memory 199496 kb
Host smart-6f0abcd8-c0be-4dd1-bc66-88c9a056732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541665421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3541665421
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.4276990541
Short name T597
Test name
Test status
Simulation time 43552382103 ps
CPU time 9.7 seconds
Started Jan 17 01:55:39 PM PST 24
Finished Jan 17 01:55:50 PM PST 24
Peak memory 195700 kb
Host smart-ae2a3b9f-3088-4871-b489-439ab7ee0b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276990541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4276990541
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1849429852
Short name T737
Test name
Test status
Simulation time 249351078 ps
CPU time 1.28 seconds
Started Jan 17 01:55:42 PM PST 24
Finished Jan 17 01:55:44 PM PST 24
Peak memory 199176 kb
Host smart-2037728f-9e04-41e2-b2bb-a635d7e46295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849429852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1849429852
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3062188009
Short name T800
Test name
Test status
Simulation time 4949315844816 ps
CPU time 8473.79 seconds
Started Jan 17 01:55:37 PM PST 24
Finished Jan 17 04:16:53 PM PST 24
Peak memory 200248 kb
Host smart-57d50d8c-587a-4b3e-969c-4fa3d4cf8a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062188009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3062188009
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2376931731
Short name T890
Test name
Test status
Simulation time 19773173144 ps
CPU time 116.43 seconds
Started Jan 17 01:55:40 PM PST 24
Finished Jan 17 01:57:37 PM PST 24
Peak memory 215808 kb
Host smart-9f6bf1cd-b1cf-4821-8f14-0c04fd7af65e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376931731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2376931731
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1839043406
Short name T1021
Test name
Test status
Simulation time 940853835 ps
CPU time 3.07 seconds
Started Jan 17 01:55:39 PM PST 24
Finished Jan 17 01:55:43 PM PST 24
Peak memory 198812 kb
Host smart-11442cc7-fe4d-481e-a801-272a688ffa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839043406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1839043406
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.672042623
Short name T787
Test name
Test status
Simulation time 1157332330 ps
CPU time 2.53 seconds
Started Jan 17 01:55:33 PM PST 24
Finished Jan 17 01:55:41 PM PST 24
Peak memory 196156 kb
Host smart-88ff87d5-fddf-4c9c-9e79-c27b62872716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672042623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.672042623
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2813050616
Short name T1213
Test name
Test status
Simulation time 109241141533 ps
CPU time 22.52 seconds
Started Jan 17 02:02:55 PM PST 24
Finished Jan 17 02:03:21 PM PST 24
Peak memory 200232 kb
Host smart-75bc3b7a-bec4-4991-af75-02aadc4152a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813050616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2813050616
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2492664188
Short name T1030
Test name
Test status
Simulation time 70849817707 ps
CPU time 215.49 seconds
Started Jan 17 02:02:53 PM PST 24
Finished Jan 17 02:06:33 PM PST 24
Peak memory 216708 kb
Host smart-898c2d78-35ee-42f5-8aba-04af2b2e4d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492664188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2492664188
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.746886681
Short name T841
Test name
Test status
Simulation time 128567136054 ps
CPU time 214.74 seconds
Started Jan 17 02:02:58 PM PST 24
Finished Jan 17 02:06:36 PM PST 24
Peak memory 200160 kb
Host smart-d8d0787e-0fef-4d13-b971-e8975c7bca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746886681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.746886681
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2177323933
Short name T203
Test name
Test status
Simulation time 39232849413 ps
CPU time 696.55 seconds
Started Jan 17 02:02:55 PM PST 24
Finished Jan 17 02:14:35 PM PST 24
Peak memory 208560 kb
Host smart-a4b25bc4-3501-4377-a6c2-a8a5b930c762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177323933 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2177323933
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3530914091
Short name T159
Test name
Test status
Simulation time 93018633360 ps
CPU time 50.56 seconds
Started Jan 17 02:02:57 PM PST 24
Finished Jan 17 02:03:50 PM PST 24
Peak memory 200272 kb
Host smart-beba5b44-b5bc-46ca-8378-ec8dcd76bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530914091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3530914091
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3331357210
Short name T425
Test name
Test status
Simulation time 38959950617 ps
CPU time 104.04 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:04:51 PM PST 24
Peak memory 211484 kb
Host smart-c511edf5-fc3d-41a3-aa3f-b3227aae46f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331357210 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3331357210
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.767631271
Short name T621
Test name
Test status
Simulation time 11160203417 ps
CPU time 22.21 seconds
Started Jan 17 02:02:54 PM PST 24
Finished Jan 17 02:03:19 PM PST 24
Peak memory 199936 kb
Host smart-5acc1709-3b05-49cf-8b4a-246aa3d06b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767631271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.767631271
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2089459492
Short name T999
Test name
Test status
Simulation time 70331135544 ps
CPU time 197.5 seconds
Started Jan 17 02:02:56 PM PST 24
Finished Jan 17 02:06:16 PM PST 24
Peak memory 208488 kb
Host smart-8c27f5d4-5bba-466d-8ce8-9ca4e7e724f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089459492 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2089459492
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1195073489
Short name T1048
Test name
Test status
Simulation time 23307020286 ps
CPU time 6.46 seconds
Started Jan 17 02:02:53 PM PST 24
Finished Jan 17 02:03:04 PM PST 24
Peak memory 200208 kb
Host smart-ba06bbeb-45a0-4e16-a785-d53bcc19c03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195073489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1195073489
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2365821654
Short name T361
Test name
Test status
Simulation time 165785372638 ps
CPU time 990.04 seconds
Started Jan 17 02:02:57 PM PST 24
Finished Jan 17 02:19:30 PM PST 24
Peak memory 224800 kb
Host smart-78d6eda7-8b6d-4c90-aa18-0fe0e7fc8172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365821654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2365821654
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1600277263
Short name T1084
Test name
Test status
Simulation time 56280068226 ps
CPU time 49.19 seconds
Started Jan 17 02:02:53 PM PST 24
Finished Jan 17 02:03:46 PM PST 24
Peak memory 200040 kb
Host smart-5647fd10-391e-4f63-9de0-b22c1cee4b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600277263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1600277263
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1680653327
Short name T910
Test name
Test status
Simulation time 38589323223 ps
CPU time 478.83 seconds
Started Jan 17 02:02:57 PM PST 24
Finished Jan 17 02:11:00 PM PST 24
Peak memory 216140 kb
Host smart-ae5aafcc-97a9-4d7a-9129-a0bc489958ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680653327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1680653327
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.4255955382
Short name T660
Test name
Test status
Simulation time 65594299593 ps
CPU time 59.7 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:04:06 PM PST 24
Peak memory 200232 kb
Host smart-cceb3db4-4b0c-43ca-ab74-33df607f19a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255955382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4255955382
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3005094141
Short name T452
Test name
Test status
Simulation time 51443950867 ps
CPU time 598.92 seconds
Started Jan 17 02:03:00 PM PST 24
Finished Jan 17 02:13:02 PM PST 24
Peak memory 216380 kb
Host smart-b25cadef-8ad3-47e8-b06b-c705a847dd2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005094141 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3005094141
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2936117372
Short name T1009
Test name
Test status
Simulation time 231471811982 ps
CPU time 139.55 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:05:26 PM PST 24
Peak memory 200120 kb
Host smart-b3c04f16-c1ad-492a-a599-dced6608422b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936117372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2936117372
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3322696900
Short name T1028
Test name
Test status
Simulation time 298043742465 ps
CPU time 1007.83 seconds
Started Jan 17 02:03:02 PM PST 24
Finished Jan 17 02:19:52 PM PST 24
Peak memory 216656 kb
Host smart-91a96fc0-e8f5-4e6e-9ecc-b940466108a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322696900 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3322696900
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1604415803
Short name T332
Test name
Test status
Simulation time 52155241864 ps
CPU time 21.07 seconds
Started Jan 17 02:02:59 PM PST 24
Finished Jan 17 02:03:23 PM PST 24
Peak memory 200280 kb
Host smart-44693bf1-37de-468b-be90-1a74183a6716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604415803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1604415803
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.559611981
Short name T393
Test name
Test status
Simulation time 69001347308 ps
CPU time 734.41 seconds
Started Jan 17 02:03:05 PM PST 24
Finished Jan 17 02:15:21 PM PST 24
Peak memory 216228 kb
Host smart-4366bdd2-ce2e-497d-83da-d22934560f24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559611981 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.559611981
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3297619416
Short name T953
Test name
Test status
Simulation time 103558791164 ps
CPU time 42.01 seconds
Started Jan 17 02:03:03 PM PST 24
Finished Jan 17 02:03:47 PM PST 24
Peak memory 200164 kb
Host smart-222ec12e-fcc2-4bad-b5a4-4b7832921c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297619416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3297619416
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1700213988
Short name T412
Test name
Test status
Simulation time 49088367698 ps
CPU time 843.82 seconds
Started Jan 17 02:03:06 PM PST 24
Finished Jan 17 02:17:12 PM PST 24
Peak memory 216696 kb
Host smart-fc52e462-ed62-43ff-bc14-581a5355634e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700213988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1700213988
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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