Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	135380	1			T3	8		T4	8		T7	8
all_values[1]	135380	1			T3	8		T4	8		T7	8
all_values[2]	135380	1			T3	8		T4	8		T7	8
all_values[3]	135380	1			T3	8		T4	8		T7	8
all_values[4]	135380	1			T3	8		T4	8		T7	8
all_values[5]	135380	1			T3	8		T4	8		T7	8
all_values[6]	135380	1			T3	8		T4	8		T7	8
all_values[7]	135380	1			T3	8		T4	8		T7	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

549266

1

T3

37

T4

28

T7

45

auto[1]

533774

1

T3

27

T4

36

T7

19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066379

1

T3

43

T4

28

T7

35

auto[1]

16661

1

T3

21

T4

36

T7

29

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	70423	1			T3	5		T4	5		T7	2
all_values[0]	auto[0]	auto[1]	2543	1			T4	1		T7	4		T46	1
all_values[0]	auto[1]	auto[0]	60135	1			T3	2		T4	1		T8	1
all_values[0]	auto[1]	auto[1]	2279	1			T3	1		T4	1		T7	2
all_values[1]	auto[0]	auto[0]	67285	1			T3	5		T4	1		T7	7
all_values[1]	auto[0]	auto[1]	2455	1			T4	2		T8	3		T45	3
all_values[1]	auto[1]	auto[0]	63505	1			T3	3		T4	3		T8	1
all_values[1]	auto[1]	auto[1]	2135	1			T4	2		T7	1		T46	4
all_values[2]	auto[0]	auto[0]	65655	1			T3	4		T4	1		T7	2
all_values[2]	auto[0]	auto[1]	2456	1			T3	2		T4	2		T7	2
all_values[2]	auto[1]	auto[0]	65067	1			T4	3		T7	1		T45	4
all_values[2]	auto[1]	auto[1]	2202	1			T3	2		T4	2		T7	3
all_values[3]	auto[0]	auto[0]	64987	1			T4	2		T7	5		T8	2
all_values[3]	auto[0]	auto[1]	228	1			T3	3		T4	5		T7	1
all_values[3]	auto[1]	auto[0]	69958	1			T3	3		T7	2		T8	1
all_values[3]	auto[1]	auto[1]	207	1			T3	2		T4	1		T8	2
all_values[4]	auto[0]	auto[0]	67662	1			T3	5		T7	2		T8	1
all_values[4]	auto[0]	auto[1]	522	1			T4	2		T7	3		T8	4
all_values[4]	auto[1]	auto[0]	66847	1			T3	3		T4	3		T7	1
all_values[4]	auto[1]	auto[1]	349	1			T4	3		T7	2		T45	2
all_values[5]	auto[0]	auto[0]	70718	1			T3	3		T4	1		T7	1
all_values[5]	auto[0]	auto[1]	158	1			T3	1		T7	6		T8	3
all_values[5]	auto[1]	auto[0]	64329	1			T3	1		T4	3		T7	1
all_values[5]	auto[1]	auto[1]	175	1			T3	3		T4	4		T8	1
all_values[6]	auto[0]	auto[0]	66190	1			T3	3		T4	1		T7	2
all_values[6]	auto[0]	auto[1]	158	1			T3	3		T4	1		T7	2
all_values[6]	auto[1]	auto[0]	68867	1			T4	2		T7	3		T8	1
all_values[6]	auto[1]	auto[1]	165	1			T3	2		T4	4		T7	1
all_values[7]	auto[0]	auto[0]	67537	1			T3	2		T4	1		T7	5
all_values[7]	auto[0]	auto[1]	289	1			T3	1		T4	3		T7	1
all_values[7]	auto[1]	auto[0]	67214	1			T3	4		T4	1		T7	1
all_values[7]	auto[1]	auto[1]	340	1			T3	1		T4	3		T7	1