Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2546

1

T1

1

T2

2

T3

1

auto[UartRx]

2546

1

T1

1

T2

2

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4496	1			T1	2		T2	4		T3	2
values[1]	34	1			T17	1		T21	1		T31	2
values[2]	39	1			T31	1		T295	2		T319	1
values[3]	60	1			T17	1		T21	1		T31	1
values[4]	56	1			T21	1		T32	1		T132	1
values[5]	73	1			T17	2		T21	2		T31	1
values[6]	56	1			T21	1		T32	1		T132	3
values[7]	47	1			T21	1		T422	2		T319	1
values[8]	61	1			T32	3		T295	1		T422	2
values[9]	54	1			T32	1		T132	1		T404	1
values[10]	89	1			T17	1		T31	2		T32	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2338	1			T1	1		T2	2		T3	1
auto[UartTx]	values[1]	10	1			T17	1		T61	1		T442	1
auto[UartTx]	values[2]	18	1			T31	1		T295	1		T342	1
auto[UartTx]	values[3]	21	1			T404	1		T295	1		T247	1
auto[UartTx]	values[4]	19	1			T438	1		T443	1		T444	1
auto[UartTx]	values[5]	25	1			T31	1		T422	1		T319	2
auto[UartTx]	values[6]	16	1			T21	1		T132	1		T445	1
auto[UartTx]	values[7]	18	1			T422	1		T247	1		T62	1
auto[UartTx]	values[8]	18	1			T295	1		T422	1		T409	1
auto[UartTx]	values[9]	18	1			T438	1		T289	1		T446	1
auto[UartTx]	values[10]	35	1			T31	1		T32	1		T132	1
auto[UartRx]	values[0]	2158	1			T1	1		T2	2		T3	1
auto[UartRx]	values[1]	24	1			T21	1		T31	2		T32	1
auto[UartRx]	values[2]	21	1			T295	1		T319	1		T417	1
auto[UartRx]	values[3]	39	1			T17	1		T21	1		T31	1
auto[UartRx]	values[4]	37	1			T21	1		T32	1		T132	1
auto[UartRx]	values[5]	48	1			T17	2		T21	2		T295	1
auto[UartRx]	values[6]	40	1			T32	1		T132	2		T404	1
auto[UartRx]	values[7]	29	1			T21	1		T422	1		T319	1
auto[UartRx]	values[8]	43	1			T32	3		T422	1		T61	2
auto[UartRx]	values[9]	36	1			T32	1		T132	1		T404	1
auto[UartRx]	values[10]	54	1			T17	1		T31	1		T32	1