Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1888	1			T12	9		T13	1		T17	2
auto[BaudRate115200]	2159	1			T11	1		T12	6		T19	2
auto[BaudRate230400]	1955	1			T12	6		T13	2		T17	6
auto[BaudRate128Kbps]	1969	1			T12	3		T13	3		T19	2
auto[BaudRate256Kbps]	2158	1			T12	6		T13	1		T19	1
auto[BaudRate1Mbps]	1685	1			T11	1		T12	3		T19	1
auto[BaudRate1p5Mbps]	1258	1			T22	2		T39	1		T101	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1208	1			T13	7		T157	9		T447	7
freqs[25]	1164	1			T94	7		T15	32		T26	4
freqs[48]	505	1			T39	9		T419	2		T221	8
freqs[50]	353	1			T20	2		T92	7		T95	10
freqs[100]	1055	1			T101	10		T103	19		T410	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	160	1			T13	1		T157	3		T447	2
auto[BaudRate9600]	freqs[25]	178	1			T94	2		T15	3		T26	1
auto[BaudRate9600]	freqs[48]	78	1			T39	2		T419	1		T221	2
auto[BaudRate9600]	freqs[50]	51	1			T92	1		T95	2		T340	1
auto[BaudRate9600]	freqs[100]	139	1			T101	2		T103	6		T124	3
auto[BaudRate115200]	freqs[24]	200	1			T157	2		T447	5		T109	2
auto[BaudRate115200]	freqs[25]	207	1			T94	2		T15	4		T26	3
auto[BaudRate115200]	freqs[48]	74	1			T39	1		T221	1		T448	1
auto[BaudRate115200]	freqs[50]	64	1			T20	1		T92	2		T449	4
auto[BaudRate115200]	freqs[100]	176	1			T103	1		T410	1		T121	3
auto[BaudRate230400]	freqs[24]	187	1			T13	2		T157	1		T109	3
auto[BaudRate230400]	freqs[25]	190	1			T15	7		T198	2		T440	1
auto[BaudRate230400]	freqs[48]	71	1			T39	2		T319	6		T201	1
auto[BaudRate230400]	freqs[50]	51	1			T92	1		T95	2		T450	1
auto[BaudRate230400]	freqs[100]	165	1			T101	1		T103	3		T410	1
auto[BaudRate128Kbps]	freqs[24]	176	1			T13	3		T157	1		T435	1
auto[BaudRate128Kbps]	freqs[25]	197	1			T94	1		T15	2		T198	1
auto[BaudRate128Kbps]	freqs[48]	88	1			T39	1		T221	1		T319	2
auto[BaudRate128Kbps]	freqs[50]	47	1			T340	1		T451	3		T237	2
auto[BaudRate128Kbps]	freqs[100]	124	1			T101	2		T103	2		T439	1
auto[BaudRate256Kbps]	freqs[24]	186	1			T13	1		T157	2		T452	1
auto[BaudRate256Kbps]	freqs[25]	137	1			T94	2		T15	7		T198	2
auto[BaudRate256Kbps]	freqs[48]	56	1			T39	1		T221	2		T319	4
auto[BaudRate256Kbps]	freqs[50]	54	1			T20	1		T92	1		T95	1
auto[BaudRate256Kbps]	freqs[100]	155	1			T101	3		T103	2		T402	1
auto[BaudRate1Mbps]	freqs[24]	190	1			T109	5		T112	2		T412	2
auto[BaudRate1Mbps]	freqs[25]	171	1			T15	7		T408	2		T404	5
auto[BaudRate1Mbps]	freqs[48]	69	1			T39	1		T319	7		T119	5
auto[BaudRate1Mbps]	freqs[50]	47	1			T92	2		T95	3		T450	1
auto[BaudRate1Mbps]	freqs[100]	138	1			T103	4		T135	1		T402	4
auto[BaudRate1p5Mbps]	freqs[25]	84	1			T15	2		T275	2		T342	15
auto[BaudRate1p5Mbps]	freqs[48]	69	1			T39	1		T419	1		T221	2
auto[BaudRate1p5Mbps]	freqs[50]	39	1			T95	2		T449	2		T238	3
auto[BaudRate1p5Mbps]	freqs[100]	158	1			T101	2		T103	1		T135	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded