Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2117 1 T4 4 T7 1 T8 3
all_levels[1] 501 1 T12 1 T18 1 T14 3
all_levels[2] 364 1 T93 1 T15 1 T104 2
all_levels[3] 299 1 T19 1 T17 1 T15 1
all_levels[4] 378 1 T21 1 T14 49 T101 2
all_levels[5] 276 1 T25 3 T168 2 T133 2
all_levels[6] 470 1 T92 3 T23 9 T95 2
all_levels[7] 180 1 T13 1 T22 2 T30 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%