Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	135380	1			T3	8		T4	8		T7	8
all_pins[1]	135380	1			T3	8		T4	8		T7	8
all_pins[2]	135380	1			T3	8		T4	8		T7	8
all_pins[3]	135380	1			T3	8		T4	8		T7	8
all_pins[4]	135380	1			T3	8		T4	8		T7	8
all_pins[5]	135380	1			T3	8		T4	8		T7	8
all_pins[6]	135380	1			T3	8		T4	8		T7	8
all_pins[7]	135380	1			T3	8		T4	8		T7	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1074321	1			T3	53		T4	44		T7	54
values[0x1]	8719	1			T3	11		T4	20		T7	10
transitions[0x0=>0x1]	7842	1			T3	8		T4	12		T7	9
transitions[0x1=>0x0]	7860	1			T3	9		T4	12		T7	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	133057	1			T3	7		T4	7		T7	6
all_pins[0]	values[0x1]	2323	1			T3	1		T4	1		T7	2
all_pins[0]	transitions[0x0=>0x1]	2047	1			T3	1		T4	1		T7	1
all_pins[0]	transitions[0x1=>0x0]	1856	1			T4	2		T46	4		T57	1
all_pins[1]	values[0x0]	133248	1			T3	8		T4	6		T7	7
all_pins[1]	values[0x1]	2132	1			T4	2		T7	1		T46	4
all_pins[1]	transitions[0x0=>0x1]	1855	1			T4	2		T7	1		T46	3
all_pins[1]	transitions[0x1=>0x0]	1996	1			T3	2		T4	2		T7	3
all_pins[2]	values[0x0]	133107	1			T3	6		T4	6		T7	5
all_pins[2]	values[0x1]	2273	1			T3	2		T4	2		T7	3
all_pins[2]	transitions[0x0=>0x1]	2233	1			T3	1		T4	2		T7	3
all_pins[2]	transitions[0x1=>0x0]	167	1			T3	1		T4	1		T8	2
all_pins[3]	values[0x0]	135173	1			T3	6		T4	7		T7	8
all_pins[3]	values[0x1]	207	1			T3	2		T4	1		T8	2
all_pins[3]	transitions[0x0=>0x1]	151	1			T3	2		T8	2		T57	1
all_pins[3]	transitions[0x1=>0x0]	293	1			T4	2		T7	2		T45	2
all_pins[4]	values[0x0]	135031	1			T3	8		T4	5		T7	6
all_pins[4]	values[0x1]	349	1			T4	3		T7	2		T45	2
all_pins[4]	transitions[0x0=>0x1]	284	1			T4	1		T7	2		T45	1
all_pins[4]	transitions[0x1=>0x0]	173	1			T3	3		T4	2		T8	1
all_pins[5]	values[0x0]	135142	1			T3	5		T4	4		T7	8
all_pins[5]	values[0x1]	238	1			T3	3		T4	4		T8	1
all_pins[5]	transitions[0x0=>0x1]	192	1			T3	2		T4	1		T8	1
all_pins[5]	transitions[0x1=>0x0]	811	1			T3	1		T4	1		T7	1
all_pins[6]	values[0x0]	134523	1			T3	6		T4	4		T7	7
all_pins[6]	values[0x1]	857	1			T3	2		T4	4		T7	1
all_pins[6]	transitions[0x0=>0x1]	799	1			T3	2		T4	2		T7	1
all_pins[6]	transitions[0x1=>0x0]	282	1			T3	1		T4	1		T7	1
all_pins[7]	values[0x0]	135040	1			T3	7		T4	5		T7	7
all_pins[7]	values[0x1]	340	1			T3	1		T4	3		T7	1
all_pins[7]	transitions[0x0=>0x1]	281	1			T4	3		T7	1		T45	1
all_pins[7]	transitions[0x1=>0x0]	2282	1			T3	1		T4	1		T7	2