Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00


Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 7 0 7 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 0 7 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 1396 1 T3 1 T4 2 T7 6
all_levels[1] 598 1 T21 2 T14 4 T22 3
all_levels[2] 623 1 T19 1 T21 2 T14 3
all_levels[3] 649 1 T17 4 T21 1 T18 2
all_levels[4] 586 1 T19 2 T25 5 T30 1
all_levels[5] 501 1 T17 6 T14 1 T103 1
all_levels[6] 567 1 T13 1 T17 12 T21 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%