Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	704	1			T3	7		T4	7		T7	7
all_values[1]	704	1			T3	7		T4	7		T7	7
all_values[2]	704	1			T3	7		T4	7		T7	7
all_values[3]	704	1			T3	7		T4	7		T7	7
all_values[4]	704	1			T3	7		T4	7		T7	7
all_values[5]	704	1			T3	7		T4	7		T7	7
all_values[6]	704	1			T3	7		T4	7		T7	7
all_values[7]	704	1			T3	7		T4	7		T7	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2991

1

T3

30

T4

27

T7

38

auto[1]

2641

1

T3

26

T4

29

T7

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2139

1

T3

22

T4

20

T7

18

auto[1]

3493

1

T3

34

T4

36

T7

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3274

1

T3

34

T4

35

T7

31

auto[1]

2358

1

T3

22

T4

21

T7

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	157	1			T3	3		T4	4		T8	1
all_values[0]	auto[0]	auto[0]	auto[1]	66	1			T7	2		T46	1		T100	1
all_values[0]	auto[0]	auto[1]	auto[0]	135	1			T3	3		T4	1		T8	1
all_values[0]	auto[0]	auto[1]	auto[1]	67	1			T7	2		T45	1		T398	1
all_values[0]	auto[1]	auto[0]	auto[1]	151	1			T3	1		T4	1		T7	2
all_values[0]	auto[1]	auto[1]	auto[1]	128	1			T4	1		T7	1		T8	1
all_values[1]	auto[0]	auto[0]	auto[0]	160	1			T3	5		T4	1		T7	5
all_values[1]	auto[0]	auto[0]	auto[1]	67	1			T8	2		T45	1		T100	2
all_values[1]	auto[0]	auto[1]	auto[0]	126	1			T3	1		T4	2		T45	1
all_values[1]	auto[0]	auto[1]	auto[1]	65	1			T4	1		T7	1		T46	3
all_values[1]	auto[1]	auto[0]	auto[1]	156	1			T4	2		T7	1		T8	1
all_values[1]	auto[1]	auto[1]	auto[1]	130	1			T3	1		T4	1		T45	1
all_values[2]	auto[0]	auto[0]	auto[0]	129	1			T3	1		T4	1		T8	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T3	1		T4	2		T7	1
all_values[2]	auto[0]	auto[1]	auto[0]	119	1			T4	2		T45	1		T65	2
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T3	1		T4	1		T8	2
all_values[2]	auto[1]	auto[0]	auto[1]	166	1			T3	2		T7	1		T8	1
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T3	2		T4	1		T7	5
all_values[3]	auto[0]	auto[0]	auto[0]	157	1			T4	1		T7	4		T8	2
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T3	2		T4	2		T7	1
all_values[3]	auto[0]	auto[1]	auto[0]	99	1			T3	1		T7	1		T57	1
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T3	2		T8	1		T65	2
all_values[3]	auto[1]	auto[0]	auto[1]	173	1			T3	2		T4	4		T7	1
all_values[3]	auto[1]	auto[1]	auto[1]	127	1			T57	2		T65	2		T399	2
all_values[4]	auto[0]	auto[0]	auto[0]	151	1			T3	1		T7	2		T100	2
all_values[4]	auto[0]	auto[0]	auto[1]	67	1			T4	1		T7	1		T8	1
all_values[4]	auto[0]	auto[1]	auto[0]	126	1			T3	1		T4	2		T45	1
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T4	2		T7	1		T46	1
all_values[4]	auto[1]	auto[0]	auto[1]	146	1			T3	2		T4	2		T7	3
all_values[4]	auto[1]	auto[1]	auto[1]	144	1			T3	3		T45	3		T57	3
all_values[5]	auto[0]	auto[0]	auto[0]	131	1			T3	2		T46	1		T65	1
all_values[5]	auto[0]	auto[0]	auto[1]	64	1			T7	2		T8	2		T57	1
all_values[5]	auto[0]	auto[1]	auto[0]	133	1			T4	3		T45	2		T46	2
all_values[5]	auto[0]	auto[1]	auto[1]	90	1			T3	3		T4	1		T45	1
all_values[5]	auto[1]	auto[0]	auto[1]	159	1			T7	5		T8	2		T65	3
all_values[5]	auto[1]	auto[1]	auto[1]	127	1			T3	2		T4	3		T45	1
all_values[6]	auto[0]	auto[0]	auto[0]	140	1			T3	1		T4	2		T7	1
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T3	2		T4	1		T7	1
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T7	2		T8	1		T57	2
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T4	2		T46	1		T57	1
all_values[6]	auto[1]	auto[0]	auto[1]	146	1			T3	2		T8	1		T45	1
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T3	2		T4	2		T7	3
all_values[7]	auto[0]	auto[0]	auto[0]	142	1			T4	1		T7	3		T8	1
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T3	1		T8	1		T100	2
all_values[7]	auto[0]	auto[1]	auto[0]	106	1			T3	3		T57	1		T65	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T4	2		T7	1		T8	1
all_values[7]	auto[1]	auto[0]	auto[1]	176	1			T3	2		T4	2		T7	2
all_values[7]	auto[1]	auto[1]	auto[1]	133	1			T3	1		T4	2		T7	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal