Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.30 99.79 98.45 100.00 99.76 100.00 97.77


Total test records in report: 1293
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
T1253 /workspace/coverage/cover_reg_top/44.uart_intr_test.2143014640 Jan 21 12:24:14 PM PST 24 Jan 21 12:24:16 PM PST 24 51696436 ps
T1254 /workspace/coverage/cover_reg_top/16.uart_csr_rw.38901253 Jan 21 02:16:05 PM PST 24 Jan 21 02:16:08 PM PST 24 13798891 ps
T1255 /workspace/coverage/cover_reg_top/32.uart_intr_test.3786943293 Jan 21 12:45:55 PM PST 24 Jan 21 12:45:57 PM PST 24 33302984 ps
T1256 /workspace/coverage/cover_reg_top/14.uart_intr_test.957246643 Jan 21 02:32:49 PM PST 24 Jan 21 02:32:52 PM PST 24 198476887 ps
T1257 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3501304553 Jan 21 12:45:53 PM PST 24 Jan 21 12:45:56 PM PST 24 19092913 ps
T1258 /workspace/coverage/cover_reg_top/6.uart_intr_test.1271108227 Jan 21 01:33:04 PM PST 24 Jan 21 01:33:09 PM PST 24 18022895 ps
T1259 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3612714329 Jan 21 01:06:38 PM PST 24 Jan 21 01:06:39 PM PST 24 16053238 ps
T1260 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2086773332 Jan 21 01:08:52 PM PST 24 Jan 21 01:08:54 PM PST 24 79770687 ps
T1261 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2809923469 Jan 21 01:17:05 PM PST 24 Jan 21 01:17:09 PM PST 24 121743123 ps
T1262 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.730696128 Jan 21 12:54:48 PM PST 24 Jan 21 12:54:50 PM PST 24 53490174 ps
T1263 /workspace/coverage/cover_reg_top/2.uart_tl_errors.463478624 Jan 21 01:52:06 PM PST 24 Jan 21 01:52:09 PM PST 24 38593715 ps
T1264 /workspace/coverage/cover_reg_top/17.uart_csr_rw.52986086 Jan 21 12:23:45 PM PST 24 Jan 21 12:23:56 PM PST 24 30330259 ps
T86 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.774688658 Jan 21 01:00:29 PM PST 24 Jan 21 01:00:32 PM PST 24 165879077 ps
T1265 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2587114724 Jan 21 12:58:44 PM PST 24 Jan 21 12:58:46 PM PST 24 105196062 ps
T1266 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2023810658 Jan 21 12:23:46 PM PST 24 Jan 21 12:23:57 PM PST 24 89860147 ps
T84 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3302621167 Jan 21 12:24:56 PM PST 24 Jan 21 12:24:58 PM PST 24 48339026 ps
T1267 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3415026407 Jan 21 12:24:47 PM PST 24 Jan 21 12:24:49 PM PST 24 160363562 ps
T1268 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1257340337 Jan 21 12:23:19 PM PST 24 Jan 21 12:23:21 PM PST 24 130128132 ps
T1269 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.228599752 Jan 21 01:24:58 PM PST 24 Jan 21 01:25:01 PM PST 24 20771570 ps
T1270 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3347269615 Jan 21 01:29:07 PM PST 24 Jan 21 01:29:08 PM PST 24 43497871 ps
T1271 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4277429804 Jan 21 12:37:06 PM PST 24 Jan 21 12:37:08 PM PST 24 200090657 ps
T1272 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.831170434 Jan 21 12:45:35 PM PST 24 Jan 21 12:45:37 PM PST 24 122833857 ps
T1273 /workspace/coverage/cover_reg_top/21.uart_intr_test.284289523 Jan 21 12:23:48 PM PST 24 Jan 21 12:23:56 PM PST 24 16201582 ps
T1274 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.697675092 Jan 21 12:24:23 PM PST 24 Jan 21 12:24:28 PM PST 24 48829365 ps
T1275 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1572879695 Jan 21 12:22:25 PM PST 24 Jan 21 12:22:26 PM PST 24 17911572 ps
T1276 /workspace/coverage/cover_reg_top/24.uart_intr_test.1277269717 Jan 21 12:23:47 PM PST 24 Jan 21 12:23:56 PM PST 24 47254055 ps
T1277 /workspace/coverage/cover_reg_top/16.uart_intr_test.2904981463 Jan 21 12:40:01 PM PST 24 Jan 21 12:40:03 PM PST 24 18254929 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3040044324 Jan 21 12:40:27 PM PST 24 Jan 21 12:40:29 PM PST 24 184447843 ps
T1279 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1638160758 Jan 21 01:49:14 PM PST 24 Jan 21 01:49:15 PM PST 24 70138849 ps
T1280 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1922828824 Jan 21 12:24:49 PM PST 24 Jan 21 12:24:51 PM PST 24 82375859 ps
T1281 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.849090823 Jan 21 12:23:33 PM PST 24 Jan 21 12:23:35 PM PST 24 43043536 ps
T1282 /workspace/coverage/cover_reg_top/2.uart_intr_test.3484437445 Jan 21 01:13:00 PM PST 24 Jan 21 01:13:01 PM PST 24 37989449 ps
T1283 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3165450408 Jan 21 01:06:37 PM PST 24 Jan 21 01:06:38 PM PST 24 17184808 ps
T1284 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.323150772 Jan 21 12:24:50 PM PST 24 Jan 21 12:24:54 PM PST 24 115312423 ps
T1285 /workspace/coverage/cover_reg_top/15.uart_intr_test.3239363738 Jan 21 12:50:19 PM PST 24 Jan 21 12:50:21 PM PST 24 15607097 ps
T1286 /workspace/coverage/cover_reg_top/4.uart_intr_test.2607782186 Jan 21 12:53:55 PM PST 24 Jan 21 12:53:56 PM PST 24 25888702 ps
T1287 /workspace/coverage/cover_reg_top/13.uart_intr_test.1178843653 Jan 21 01:16:44 PM PST 24 Jan 21 01:16:46 PM PST 24 15604788 ps
T1288 /workspace/coverage/cover_reg_top/36.uart_intr_test.305103515 Jan 21 12:24:00 PM PST 24 Jan 21 12:24:03 PM PST 24 14584628 ps
T1289 /workspace/coverage/cover_reg_top/33.uart_intr_test.2893996988 Jan 21 12:24:06 PM PST 24 Jan 21 12:24:07 PM PST 24 27773588 ps
T1290 /workspace/coverage/cover_reg_top/46.uart_intr_test.968415924 Jan 21 12:42:44 PM PST 24 Jan 21 12:42:50 PM PST 24 49105012 ps
T1291 /workspace/coverage/cover_reg_top/19.uart_intr_test.1965669207 Jan 21 01:32:41 PM PST 24 Jan 21 01:32:44 PM PST 24 17174456 ps
T1292 /workspace/coverage/cover_reg_top/11.uart_csr_rw.943058865 Jan 21 12:22:25 PM PST 24 Jan 21 12:22:26 PM PST 24 51799286 ps
T1293 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3101436643 Jan 21 02:21:46 PM PST 24 Jan 21 02:21:47 PM PST 24 35705450 ps

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3514962660
Short name T5
Test name
Test status
Simulation time 22792602 ps
CPU time 0.97 seconds
Started Jan 21 12:24:43 PM PST 24
Finished Jan 21 12:24:45 PM PST 24
Peak memory 199496 kb
Host smart-d8d05399-3368-476f-8210-0130423587bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514962660 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3514962660
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all.1519214255
Short name T14
Test name
Test status
Simulation time 941533047876 ps
CPU time 344.73 seconds
Started Jan 21 01:28:02 PM PST 24
Finished Jan 21 01:33:48 PM PST 24
Peak memory 200004 kb
Host smart-aa6e4dd2-f6fc-40de-80c6-80115988c672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519214255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1519214255
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all.1508190871
Short name T15
Test name
Test status
Simulation time 508246874480 ps
CPU time 346.23 seconds
Started Jan 21 01:39:23 PM PST 24
Finished Jan 21 01:45:14 PM PST 24
Peak memory 199952 kb
Host smart-74268d30-9b95-45ee-8f00-ffec2f8df43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508190871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1508190871
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3257669835
Short name T4
Test name
Test status
Simulation time 14835749 ps
CPU time 0.61 seconds
Started Jan 21 01:07:35 PM PST 24
Finished Jan 21 01:07:42 PM PST 24
Peak memory 194176 kb
Host smart-686a49fc-7f60-42bb-a6a2-7188f43d1204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257669835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3257669835
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.882126755
Short name T342
Test name
Test status
Simulation time 323138166511 ps
CPU time 1399.83 seconds
Started Jan 21 02:41:23 PM PST 24
Finished Jan 21 03:04:45 PM PST 24
Peak memory 227036 kb
Host smart-e2eb997c-6053-4278-ba0f-2218917a972a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882126755 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.882126755
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2735760573
Short name T35
Test name
Test status
Simulation time 277211218 ps
CPU time 1.35 seconds
Started Jan 21 12:48:07 PM PST 24
Finished Jan 21 12:48:13 PM PST 24
Peak memory 198832 kb
Host smart-711a2dba-bcf0-4520-9652-5439ed40ba2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735760573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2735760573
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/26.uart_stress_all.52476504
Short name T111
Test name
Test status
Simulation time 624350645667 ps
CPU time 108.87 seconds
Started Jan 21 01:34:10 PM PST 24
Finished Jan 21 01:36:00 PM PST 24
Peak memory 208408 kb
Host smart-0470dea2-5e29-41cb-a7b3-7979db2e0cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52476504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.52476504
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all.756983220
Short name T28
Test name
Test status
Simulation time 955097825692 ps
CPU time 303.74 seconds
Started Jan 21 01:24:39 PM PST 24
Finished Jan 21 01:29:47 PM PST 24
Peak memory 199884 kb
Host smart-62c0cee8-2393-44ea-a6ab-f9000552c937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756983220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.756983220
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3547298611
Short name T431
Test name
Test status
Simulation time 113374594918 ps
CPU time 631.86 seconds
Started Jan 21 02:34:44 PM PST 24
Finished Jan 21 02:45:29 PM PST 24
Peak memory 200056 kb
Host smart-715b1ac5-4e9e-487b-a77d-315d3660a6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547298611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3547298611
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1199313492
Short name T10
Test name
Test status
Simulation time 37528037 ps
CPU time 0.62 seconds
Started Jan 21 12:24:28 PM PST 24
Finished Jan 21 12:24:32 PM PST 24
Peak memory 194300 kb
Host smart-76088fd0-fbff-43c7-b53d-f0621b024b07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199313492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1199313492
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2491881335
Short name T13
Test name
Test status
Simulation time 63301132418 ps
CPU time 25.38 seconds
Started Jan 21 01:43:00 PM PST 24
Finished Jan 21 01:43:26 PM PST 24
Peak memory 199672 kb
Host smart-c2bd91d3-9e1a-4d3e-b1a1-ec598e25b052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491881335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2491881335
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4045718115
Short name T132
Test name
Test status
Simulation time 425390047113 ps
CPU time 530.9 seconds
Started Jan 21 01:33:33 PM PST 24
Finished Jan 21 01:42:30 PM PST 24
Peak memory 224740 kb
Host smart-174bd7ef-e06d-4e6e-b002-150a5f1ed542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045718115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4045718115
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.1506354671
Short name T108
Test name
Test status
Simulation time 88774672066 ps
CPU time 543.98 seconds
Started Jan 21 01:33:14 PM PST 24
Finished Jan 21 01:42:20 PM PST 24
Peak memory 200008 kb
Host smart-abd44b93-e6b6-4c20-a64f-8d6c5e8ee054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506354671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1506354671
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.911423234
Short name T319
Test name
Test status
Simulation time 180213164504 ps
CPU time 809.11 seconds
Started Jan 21 02:35:08 PM PST 24
Finished Jan 21 02:48:38 PM PST 24
Peak memory 224924 kb
Host smart-51546df8-bd07-44e0-9262-f5f8d320b735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911423234 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.911423234
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3994900705
Short name T99
Test name
Test status
Simulation time 206286478 ps
CPU time 1.81 seconds
Started Jan 21 12:24:43 PM PST 24
Finished Jan 21 12:24:45 PM PST 24
Peak memory 199660 kb
Host smart-4962b557-f5ca-4acf-a6dc-b361d5934c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994900705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3994900705
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/default/21.uart_stress_all.2062655904
Short name T137
Test name
Test status
Simulation time 93420605654 ps
CPU time 1253.94 seconds
Started Jan 21 01:32:53 PM PST 24
Finished Jan 21 01:53:55 PM PST 24
Peak memory 199980 kb
Host smart-2f96c1db-c5da-4770-b143-ee5714bfff31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062655904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2062655904
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_intr.1215828264
Short name T167
Test name
Test status
Simulation time 1851833779839 ps
CPU time 955 seconds
Started Jan 21 01:30:24 PM PST 24
Finished Jan 21 01:46:20 PM PST 24
Peak memory 200028 kb
Host smart-7dc98e1b-e97c-4663-b264-2513d4262772
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215828264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1215828264
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2220263465
Short name T144
Test name
Test status
Simulation time 48921484447 ps
CPU time 70.96 seconds
Started Jan 21 01:31:52 PM PST 24
Finished Jan 21 01:33:05 PM PST 24
Peak memory 200044 kb
Host smart-ceea748b-a210-4938-970f-fdb274cf583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220263465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2220263465
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2465282285
Short name T79
Test name
Test status
Simulation time 113094904 ps
CPU time 0.81 seconds
Started Jan 21 01:25:53 PM PST 24
Finished Jan 21 01:25:55 PM PST 24
Peak memory 217224 kb
Host smart-bdbc79a9-961a-480f-b1a3-b8ae00ca4087
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465282285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2465282285
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.77390901
Short name T310
Test name
Test status
Simulation time 200020261509 ps
CPU time 87.99 seconds
Started Jan 21 02:29:19 PM PST 24
Finished Jan 21 02:30:48 PM PST 24
Peak memory 199848 kb
Host smart-c7cfd175-b73f-44a5-b14f-a72ab21a4628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77390901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.77390901
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_stress_all.528800754
Short name T159
Test name
Test status
Simulation time 233576790908 ps
CPU time 119.57 seconds
Started Jan 21 01:40:42 PM PST 24
Finished Jan 21 01:42:42 PM PST 24
Peak memory 199964 kb
Host smart-5bbd0769-8cfd-40b1-b3b9-27717a55ec10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528800754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.528800754
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2149506001
Short name T21
Test name
Test status
Simulation time 268143484093 ps
CPU time 377.62 seconds
Started Jan 21 01:42:40 PM PST 24
Finished Jan 21 01:48:58 PM PST 24
Peak memory 216680 kb
Host smart-40c0e093-8fd4-4cca-918e-765d2a1e0ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149506001 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2149506001
Directory /workspace/99.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1136986058
Short name T38
Test name
Test status
Simulation time 83453854 ps
CPU time 1.23 seconds
Started Jan 21 12:23:46 PM PST 24
Finished Jan 21 12:23:57 PM PST 24
Peak memory 198724 kb
Host smart-6b973eb8-33f3-4917-8c54-3b212f61e288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136986058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1136986058
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3138020761
Short name T92
Test name
Test status
Simulation time 35708787766 ps
CPU time 53.33 seconds
Started Jan 21 01:34:41 PM PST 24
Finished Jan 21 01:35:35 PM PST 24
Peak memory 199944 kb
Host smart-2a17c618-483c-4739-9d3e-a07e01e63591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138020761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3138020761
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2685097865
Short name T47
Test name
Test status
Simulation time 53378372 ps
CPU time 0.54 seconds
Started Jan 21 12:25:00 PM PST 24
Finished Jan 21 12:25:02 PM PST 24
Peak memory 195144 kb
Host smart-9bda971f-4564-433f-99d7-cc9b33a7da88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685097865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2685097865
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.750482221
Short name T106
Test name
Test status
Simulation time 170943261604 ps
CPU time 28.46 seconds
Started Jan 21 01:41:37 PM PST 24
Finished Jan 21 01:42:13 PM PST 24
Peak memory 199964 kb
Host smart-079d1e19-ab34-4350-9a8c-9b68762525e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750482221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.750482221
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1307647100
Short name T100
Test name
Test status
Simulation time 31008540 ps
CPU time 0.57 seconds
Started Jan 21 12:41:48 PM PST 24
Finished Jan 21 12:41:49 PM PST 24
Peak memory 194100 kb
Host smart-d2d1f41b-69bb-499c-9051-7f1b103e419d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307647100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1307647100
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3263574581
Short name T61
Test name
Test status
Simulation time 161092325912 ps
CPU time 620.64 seconds
Started Jan 21 01:41:39 PM PST 24
Finished Jan 21 01:52:05 PM PST 24
Peak memory 216368 kb
Host smart-54086289-52e0-449b-9b67-f8a3c50aae67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263574581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3263574581
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3105348234
Short name T247
Test name
Test status
Simulation time 169401846630 ps
CPU time 746.68 seconds
Started Jan 21 01:28:02 PM PST 24
Finished Jan 21 01:40:30 PM PST 24
Peak memory 216548 kb
Host smart-7d0fc075-b634-4f65-bf6a-249963a30cb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105348234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3105348234
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_alert_test.248803275
Short name T507
Test name
Test status
Simulation time 50100729 ps
CPU time 0.54 seconds
Started Jan 21 01:24:46 PM PST 24
Finished Jan 21 01:24:48 PM PST 24
Peak memory 195600 kb
Host smart-02eaf567-b404-4cf1-827a-d1d899013eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248803275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.248803275
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1261207617
Short name T198
Test name
Test status
Simulation time 44900645990 ps
CPU time 18.83 seconds
Started Jan 21 01:24:58 PM PST 24
Finished Jan 21 01:25:20 PM PST 24
Peak memory 199952 kb
Host smart-8aebc8d4-358c-46c9-a9a4-963251014455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261207617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1261207617
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1249033668
Short name T200
Test name
Test status
Simulation time 289364864446 ps
CPU time 435.24 seconds
Started Jan 21 01:28:56 PM PST 24
Finished Jan 21 01:36:12 PM PST 24
Peak memory 200048 kb
Host smart-738b5c4d-203d-476e-9a69-7b5faf51cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249033668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1249033668
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1452038711
Short name T151
Test name
Test status
Simulation time 202688476452 ps
CPU time 138 seconds
Started Jan 21 01:45:33 PM PST 24
Finished Jan 21 01:47:52 PM PST 24
Peak memory 199824 kb
Host smart-79d46faa-32ec-496a-8e5a-38381d3eb625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452038711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1452038711
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.4123521974
Short name T289
Test name
Test status
Simulation time 273548278757 ps
CPU time 842.92 seconds
Started Jan 21 01:41:48 PM PST 24
Finished Jan 21 01:55:56 PM PST 24
Peak memory 223856 kb
Host smart-77c04089-d15d-426d-9f5d-21859bbd7d9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123521974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.4123521974
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all.1615654188
Short name T269
Test name
Test status
Simulation time 300997893923 ps
CPU time 1476.19 seconds
Started Jan 21 01:35:44 PM PST 24
Finished Jan 21 02:00:21 PM PST 24
Peak memory 208436 kb
Host smart-78eb7ed6-2bd5-4463-a28c-5e0e0bbaac05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615654188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1615654188
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1302299177
Short name T304
Test name
Test status
Simulation time 27160364408 ps
CPU time 56.84 seconds
Started Jan 21 01:41:29 PM PST 24
Finished Jan 21 01:42:26 PM PST 24
Peak memory 199980 kb
Host smart-b4d0ffe9-b04e-4a98-8382-382c10592e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302299177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1302299177
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.8321844
Short name T142
Test name
Test status
Simulation time 225760220448 ps
CPU time 82.48 seconds
Started Jan 21 01:43:04 PM PST 24
Finished Jan 21 01:44:27 PM PST 24
Peak memory 199976 kb
Host smart-821aa1fb-e45c-4b51-946f-f03015c9fea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8321844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.8321844
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.734254106
Short name T116
Test name
Test status
Simulation time 120579253049 ps
CPU time 96.3 seconds
Started Jan 21 01:43:08 PM PST 24
Finished Jan 21 01:44:45 PM PST 24
Peak memory 200032 kb
Host smart-cd8b98ba-3262-482d-a0f0-177e2523b6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734254106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.734254106
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3240219800
Short name T473
Test name
Test status
Simulation time 1243536587 ps
CPU time 1.87 seconds
Started Jan 21 12:24:50 PM PST 24
Finished Jan 21 12:24:53 PM PST 24
Peak memory 199520 kb
Host smart-2195002e-2bc6-4fb4-80c0-3c3b9807c107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240219800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3240219800
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.662315970
Short name T356
Test name
Test status
Simulation time 64975350499 ps
CPU time 25.43 seconds
Started Jan 21 01:24:29 PM PST 24
Finished Jan 21 01:24:55 PM PST 24
Peak memory 200024 kb
Host smart-bc2415f6-6559-4777-bb66-bc965f59de71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662315970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.662315970
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2646364115
Short name T344
Test name
Test status
Simulation time 13568125918 ps
CPU time 7.5 seconds
Started Jan 21 01:43:20 PM PST 24
Finished Jan 21 01:43:28 PM PST 24
Peak memory 199944 kb
Host smart-4aca92bd-e713-4a21-8783-dbf14182b93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646364115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2646364115
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.455083271
Short name T123
Test name
Test status
Simulation time 28416915311 ps
CPU time 53.09 seconds
Started Jan 21 01:43:25 PM PST 24
Finished Jan 21 01:44:19 PM PST 24
Peak memory 199960 kb
Host smart-5e81e99e-0e40-40f5-af59-c9d47c4321a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455083271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.455083271
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4067299215
Short name T323
Test name
Test status
Simulation time 115434328247 ps
CPU time 41.35 seconds
Started Jan 21 01:44:33 PM PST 24
Finished Jan 21 01:45:16 PM PST 24
Peak memory 199972 kb
Host smart-9971cdba-d060-413a-a7e0-d27b5af79dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067299215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4067299215
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2615805796
Short name T194
Test name
Test status
Simulation time 61688918332 ps
CPU time 28.64 seconds
Started Jan 21 01:41:25 PM PST 24
Finished Jan 21 01:41:54 PM PST 24
Peak memory 199964 kb
Host smart-f3d0d040-bc47-47ca-97d0-4eb4c29af558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615805796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2615805796
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.257630946
Short name T145
Test name
Test status
Simulation time 138491722724 ps
CPU time 32.9 seconds
Started Jan 21 01:41:53 PM PST 24
Finished Jan 21 01:42:29 PM PST 24
Peak memory 199740 kb
Host smart-73cab981-7e86-4c1e-a223-895af93e3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257630946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.257630946
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.272941257
Short name T301
Test name
Test status
Simulation time 53274287308 ps
CPU time 24.43 seconds
Started Jan 21 01:42:34 PM PST 24
Finished Jan 21 01:42:59 PM PST 24
Peak memory 200052 kb
Host smart-9c49b274-2445-415a-ad74-b69a1257f0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272941257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.272941257
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2905538787
Short name T216
Test name
Test status
Simulation time 58354396652 ps
CPU time 26.04 seconds
Started Jan 21 01:43:23 PM PST 24
Finished Jan 21 01:43:50 PM PST 24
Peak memory 199580 kb
Host smart-78dec367-7151-4667-a532-aacbf603397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905538787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2905538787
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3414573876
Short name T234
Test name
Test status
Simulation time 38227030391 ps
CPU time 16.12 seconds
Started Jan 21 02:32:34 PM PST 24
Finished Jan 21 02:32:51 PM PST 24
Peak memory 199916 kb
Host smart-ac57d36b-72de-4fc2-b661-61533a15fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414573876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3414573876
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3775740222
Short name T320
Test name
Test status
Simulation time 46048077082 ps
CPU time 45.6 seconds
Started Jan 21 01:43:33 PM PST 24
Finished Jan 21 01:44:20 PM PST 24
Peak memory 200040 kb
Host smart-c2718fae-bf33-4af5-86d4-394314dc3b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775740222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3775740222
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1620794230
Short name T358
Test name
Test status
Simulation time 52203435427 ps
CPU time 22.09 seconds
Started Jan 21 01:39:54 PM PST 24
Finished Jan 21 01:40:26 PM PST 24
Peak memory 199328 kb
Host smart-3f6d6ea7-083e-4b0e-ae05-a789004f9235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620794230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1620794230
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2229244941
Short name T274
Test name
Test status
Simulation time 22576211945 ps
CPU time 9.37 seconds
Started Jan 21 01:43:07 PM PST 24
Finished Jan 21 01:43:17 PM PST 24
Peak memory 198652 kb
Host smart-fcdb5bc8-6b54-4b86-8838-63293172cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229244941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2229244941
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.229228751
Short name T153
Test name
Test status
Simulation time 160877076784 ps
CPU time 254.04 seconds
Started Jan 21 01:31:49 PM PST 24
Finished Jan 21 01:36:05 PM PST 24
Peak memory 200032 kb
Host smart-24f95e37-68ce-4528-a6e3-6788e808cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229228751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.229228751
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2181381816
Short name T210
Test name
Test status
Simulation time 103375081994 ps
CPU time 26.89 seconds
Started Jan 21 01:44:33 PM PST 24
Finished Jan 21 01:45:01 PM PST 24
Peak memory 200000 kb
Host smart-6f881f89-bf32-46c0-a833-2ffd1e7c99d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181381816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2181381816
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3182236663
Short name T354
Test name
Test status
Simulation time 92666952717 ps
CPU time 23.93 seconds
Started Jan 21 02:21:15 PM PST 24
Finished Jan 21 02:21:40 PM PST 24
Peak memory 199932 kb
Host smart-ca1c37be-a8af-46bd-b7ac-39ba704bca6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182236663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3182236663
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.317306970
Short name T267
Test name
Test status
Simulation time 130253919800 ps
CPU time 37.88 seconds
Started Jan 21 01:45:29 PM PST 24
Finished Jan 21 01:46:07 PM PST 24
Peak memory 199776 kb
Host smart-74771e36-2fc6-4f62-8a96-a1b84f899e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317306970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.317306970
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.188332925
Short name T233
Test name
Test status
Simulation time 65522755913 ps
CPU time 62.65 seconds
Started Jan 21 02:27:00 PM PST 24
Finished Jan 21 02:28:04 PM PST 24
Peak memory 199368 kb
Host smart-ddcfecc7-fd7d-4d7e-8cd6-235b7871ac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188332925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.188332925
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2133609147
Short name T175
Test name
Test status
Simulation time 83456671404 ps
CPU time 31.52 seconds
Started Jan 21 01:45:52 PM PST 24
Finished Jan 21 01:46:25 PM PST 24
Peak memory 199928 kb
Host smart-3ae57245-cc5d-45e1-9068-289643dc0088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133609147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2133609147
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.972675001
Short name T392
Test name
Test status
Simulation time 478560287921 ps
CPU time 916.01 seconds
Started Jan 21 01:35:40 PM PST 24
Finished Jan 21 01:50:57 PM PST 24
Peak memory 216696 kb
Host smart-26f2e1f3-947b-4b42-b7fd-6bb5d663c638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972675001 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.972675001
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1701603971
Short name T383
Test name
Test status
Simulation time 49979883590 ps
CPU time 22.55 seconds
Started Jan 21 01:26:52 PM PST 24
Finished Jan 21 01:27:15 PM PST 24
Peak memory 199856 kb
Host smart-c431eb67-1c00-48b4-854e-e67e5434d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701603971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1701603971
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.430984433
Short name T333
Test name
Test status
Simulation time 110212646456 ps
CPU time 243.22 seconds
Started Jan 21 01:28:56 PM PST 24
Finished Jan 21 01:33:00 PM PST 24
Peak memory 199872 kb
Host smart-58a8e7f0-bae6-44d8-a42f-957bf406809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430984433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.430984433
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3412652596
Short name T363
Test name
Test status
Simulation time 124612819549 ps
CPU time 47.78 seconds
Started Jan 21 01:42:59 PM PST 24
Finished Jan 21 01:43:47 PM PST 24
Peak memory 199852 kb
Host smart-f490dd28-aa37-4a45-a3b6-3e06662b117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412652596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3412652596
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3176690961
Short name T293
Test name
Test status
Simulation time 26334823870 ps
CPU time 35.96 seconds
Started Jan 21 01:43:17 PM PST 24
Finished Jan 21 01:43:54 PM PST 24
Peak memory 199872 kb
Host smart-83e11f11-1052-425c-9a48-135452f8551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176690961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3176690961
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1085147722
Short name T570
Test name
Test status
Simulation time 76560449028 ps
CPU time 36.47 seconds
Started Jan 21 01:30:25 PM PST 24
Finished Jan 21 01:31:02 PM PST 24
Peak memory 199232 kb
Host smart-8ac9d91f-729b-468d-9fcb-e9a839068b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085147722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1085147722
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2386540339
Short name T147
Test name
Test status
Simulation time 77775969363 ps
CPU time 69.54 seconds
Started Jan 21 02:08:36 PM PST 24
Finished Jan 21 02:09:47 PM PST 24
Peak memory 200240 kb
Host smart-271f51d4-7570-4cc7-b2d1-06607831c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386540339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2386540339
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2915569079
Short name T375
Test name
Test status
Simulation time 71876325846 ps
CPU time 61.82 seconds
Started Jan 21 01:30:43 PM PST 24
Finished Jan 21 01:31:46 PM PST 24
Peak memory 199200 kb
Host smart-664da2d9-a6c3-4503-88fe-424375b292c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915569079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2915569079
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1466462963
Short name T384
Test name
Test status
Simulation time 37650366219 ps
CPU time 63.01 seconds
Started Jan 21 01:44:01 PM PST 24
Finished Jan 21 01:45:05 PM PST 24
Peak memory 199796 kb
Host smart-d07e9c9c-b518-48ba-a2f9-76c90c7e44a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466462963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1466462963
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1073703250
Short name T311
Test name
Test status
Simulation time 37077291499 ps
CPU time 27.55 seconds
Started Jan 21 01:44:09 PM PST 24
Finished Jan 21 01:44:39 PM PST 24
Peak memory 199528 kb
Host smart-e7d310a1-347d-486d-a65a-f0a1e539e133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073703250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1073703250
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.580147151
Short name T141
Test name
Test status
Simulation time 50210664844 ps
CPU time 524.09 seconds
Started Jan 21 01:25:55 PM PST 24
Finished Jan 21 01:34:40 PM PST 24
Peak memory 215796 kb
Host smart-47d0fdfc-fa6a-4929-a377-955f469a291f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580147151 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.580147151
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3700854480
Short name T184
Test name
Test status
Simulation time 68580397292 ps
CPU time 43.81 seconds
Started Jan 21 02:31:18 PM PST 24
Finished Jan 21 02:32:02 PM PST 24
Peak memory 199320 kb
Host smart-bdbdc51e-8d08-498d-a048-fe190b6468a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700854480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3700854480
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3439168823
Short name T1170
Test name
Test status
Simulation time 79490781241 ps
CPU time 162.38 seconds
Started Jan 21 01:45:16 PM PST 24
Finished Jan 21 01:47:59 PM PST 24
Peak memory 200000 kb
Host smart-c981e06e-0ed8-4d3f-9097-ef230af39fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439168823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3439168823
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.809876486
Short name T1104
Test name
Test status
Simulation time 94711194624 ps
CPU time 43.09 seconds
Started Jan 21 02:26:03 PM PST 24
Finished Jan 21 02:26:47 PM PST 24
Peak memory 199912 kb
Host smart-8b27b65a-303c-4e11-8649-a0385e19e133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809876486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.809876486
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3626489489
Short name T332
Test name
Test status
Simulation time 78567957649 ps
CPU time 26.11 seconds
Started Jan 21 01:45:33 PM PST 24
Finished Jan 21 01:46:00 PM PST 24
Peak memory 199920 kb
Host smart-06531a51-7e2d-449e-8f06-9874755427d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626489489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3626489489
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.2142002354
Short name T179
Test name
Test status
Simulation time 127562916923 ps
CPU time 248.82 seconds
Started Jan 21 01:41:38 PM PST 24
Finished Jan 21 01:45:53 PM PST 24
Peak memory 199972 kb
Host smart-f1943ad3-8ebc-4268-af97-bc5877656570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142002354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2142002354
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2453986207
Short name T285
Test name
Test status
Simulation time 196535652555 ps
CPU time 79.09 seconds
Started Jan 21 01:36:56 PM PST 24
Finished Jan 21 01:38:17 PM PST 24
Peak memory 199968 kb
Host smart-70cfa376-d4fe-4e44-b8b5-fb9aa20b615a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453986207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2453986207
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1017419252
Short name T226
Test name
Test status
Simulation time 19880454346 ps
CPU time 34.16 seconds
Started Jan 21 01:40:53 PM PST 24
Finished Jan 21 01:41:28 PM PST 24
Peak memory 200012 kb
Host smart-0b3b05f1-e615-48bf-ab46-0bdbb3aee9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017419252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1017419252
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.821954345
Short name T321
Test name
Test status
Simulation time 29093613824 ps
CPU time 49.89 seconds
Started Jan 21 01:41:38 PM PST 24
Finished Jan 21 01:42:34 PM PST 24
Peak memory 200056 kb
Host smart-493d8523-b497-4a9d-a081-fd477700530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821954345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.821954345
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3150555603
Short name T371
Test name
Test status
Simulation time 107723087298 ps
CPU time 32.56 seconds
Started Jan 21 01:42:17 PM PST 24
Finished Jan 21 01:42:54 PM PST 24
Peak memory 200008 kb
Host smart-37c8bdb0-3cd2-4906-b1fa-702dc27036da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150555603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3150555603
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3382986654
Short name T491
Test name
Test status
Simulation time 36510678 ps
CPU time 0.56 seconds
Started Jan 21 12:42:11 PM PST 24
Finished Jan 21 12:42:12 PM PST 24
Peak memory 194044 kb
Host smart-09d3c91f-fd2a-4e7f-af3b-9fabc87f5881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382986654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3382986654
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2563849359
Short name T85
Test name
Test status
Simulation time 152046523 ps
CPU time 1.28 seconds
Started Jan 21 12:24:26 PM PST 24
Finished Jan 21 12:24:29 PM PST 24
Peak memory 197668 kb
Host smart-53fb8009-4011-48df-b1c9-70f033bf0068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563849359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2563849359
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1435703768
Short name T365
Test name
Test status
Simulation time 42670192438 ps
CPU time 41.68 seconds
Started Jan 21 01:29:12 PM PST 24
Finished Jan 21 01:29:55 PM PST 24
Peak memory 199920 kb
Host smart-90ce4167-e009-49db-aecd-b5b014c7c113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435703768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1435703768
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3713937011
Short name T374
Test name
Test status
Simulation time 298513351573 ps
CPU time 33.69 seconds
Started Jan 21 01:29:23 PM PST 24
Finished Jan 21 01:29:58 PM PST 24
Peak memory 199460 kb
Host smart-71bce12f-8968-42c9-8019-01f93f6710b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713937011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3713937011
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2029232279
Short name T260
Test name
Test status
Simulation time 220826061026 ps
CPU time 696.36 seconds
Started Jan 21 01:29:31 PM PST 24
Finished Jan 21 01:41:08 PM PST 24
Peak memory 227488 kb
Host smart-09092a51-a0dd-4a1b-94c2-2f21cef80517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029232279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2029232279
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1280557814
Short name T266
Test name
Test status
Simulation time 23104733386 ps
CPU time 9.04 seconds
Started Jan 21 03:20:55 PM PST 24
Finished Jan 21 03:21:16 PM PST 24
Peak memory 199196 kb
Host smart-afb9ce45-c0e3-4263-a69c-3d09f57ff606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280557814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1280557814
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.883450740
Short name T120
Test name
Test status
Simulation time 117492734152 ps
CPU time 11.96 seconds
Started Jan 21 01:43:16 PM PST 24
Finished Jan 21 01:43:28 PM PST 24
Peak memory 199960 kb
Host smart-a09cfaaf-b3e7-4d4c-a23c-ea29fd25ffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883450740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.883450740
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.766224224
Short name T227
Test name
Test status
Simulation time 129769632239 ps
CPU time 48.69 seconds
Started Jan 21 01:30:50 PM PST 24
Finished Jan 21 01:31:40 PM PST 24
Peak memory 199972 kb
Host smart-2007dcd6-419b-451b-bb93-773a30de53a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766224224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.766224224
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.444698023
Short name T212
Test name
Test status
Simulation time 13508963860 ps
CPU time 19.71 seconds
Started Jan 21 01:43:44 PM PST 24
Finished Jan 21 01:44:04 PM PST 24
Peak memory 199136 kb
Host smart-96b1ff2d-a9c6-45e6-aef9-f8257fc8fc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444698023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.444698023
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3951695842
Short name T215
Test name
Test status
Simulation time 138343964783 ps
CPU time 94.73 seconds
Started Jan 21 01:43:56 PM PST 24
Finished Jan 21 01:45:32 PM PST 24
Peak memory 200032 kb
Host smart-f0367cf0-b3a5-4722-98b8-8e385a6057cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951695842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3951695842
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.599783111
Short name T190
Test name
Test status
Simulation time 66272353776 ps
CPU time 33.49 seconds
Started Jan 21 01:43:51 PM PST 24
Finished Jan 21 01:44:25 PM PST 24
Peak memory 199852 kb
Host smart-5e5f96c1-34ed-47e9-8e94-937522cf1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599783111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.599783111
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.624636905
Short name T282
Test name
Test status
Simulation time 22975053802 ps
CPU time 20.92 seconds
Started Jan 21 01:43:53 PM PST 24
Finished Jan 21 01:44:14 PM PST 24
Peak memory 199960 kb
Host smart-7fa989bb-6bda-4a09-8f0b-059e2a95519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624636905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.624636905
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3085304640
Short name T318
Test name
Test status
Simulation time 177462144442 ps
CPU time 75.36 seconds
Started Jan 21 01:44:01 PM PST 24
Finished Jan 21 01:45:17 PM PST 24
Peak memory 200032 kb
Host smart-8ffe2aad-fe8c-4338-a262-5bb1cdb7038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085304640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3085304640
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.103258005
Short name T324
Test name
Test status
Simulation time 117507147226 ps
CPU time 146.06 seconds
Started Jan 21 01:44:02 PM PST 24
Finished Jan 21 01:46:28 PM PST 24
Peak memory 200024 kb
Host smart-2e77eac6-8dfd-4024-a9ce-3cb3ea3ddeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103258005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.103258005
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_perf.4193306311
Short name T283
Test name
Test status
Simulation time 15604138205 ps
CPU time 201.07 seconds
Started Jan 21 01:31:41 PM PST 24
Finished Jan 21 01:35:03 PM PST 24
Peak memory 199944 kb
Host smart-04d6469f-6532-4abe-aed6-4a1d555b6893
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193306311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4193306311
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1686772910
Short name T280
Test name
Test status
Simulation time 20974362683 ps
CPU time 32.6 seconds
Started Jan 21 01:31:51 PM PST 24
Finished Jan 21 01:32:25 PM PST 24
Peak memory 199084 kb
Host smart-3caff1db-5745-4492-9aa6-5a40e80cbb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686772910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1686772910
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3335102759
Short name T547
Test name
Test status
Simulation time 166559726595 ps
CPU time 68.66 seconds
Started Jan 21 01:31:52 PM PST 24
Finished Jan 21 01:33:02 PM PST 24
Peak memory 199948 kb
Host smart-8f6baa76-edc0-4462-b251-ef9f2ec40267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335102759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3335102759
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2649930671
Short name T360
Test name
Test status
Simulation time 55635838089 ps
CPU time 23.82 seconds
Started Jan 21 01:44:21 PM PST 24
Finished Jan 21 01:44:48 PM PST 24
Peak memory 200048 kb
Host smart-6ec58354-f0d7-4718-8eaa-90b9668230a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649930671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2649930671
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3366267470
Short name T391
Test name
Test status
Simulation time 63726201124 ps
CPU time 54.42 seconds
Started Jan 21 01:32:00 PM PST 24
Finished Jan 21 01:32:56 PM PST 24
Peak memory 199860 kb
Host smart-1bb34bc9-4d5e-4caf-a17f-a9eeca112e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366267470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3366267470
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.615601918
Short name T393
Test name
Test status
Simulation time 67609774890 ps
CPU time 34.3 seconds
Started Jan 21 01:32:08 PM PST 24
Finished Jan 21 01:32:44 PM PST 24
Peak memory 199912 kb
Host smart-b32a06cb-a067-41a1-9a19-c1fafb6b23d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615601918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.615601918
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2814799007
Short name T1210
Test name
Test status
Simulation time 88365754387 ps
CPU time 152.52 seconds
Started Jan 21 02:27:03 PM PST 24
Finished Jan 21 02:29:36 PM PST 24
Peak memory 199888 kb
Host smart-7f7125a2-e7e4-4619-b178-a10f4112cfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814799007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2814799007
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2705394293
Short name T150
Test name
Test status
Simulation time 173698066868 ps
CPU time 44.57 seconds
Started Jan 21 01:44:33 PM PST 24
Finished Jan 21 01:45:19 PM PST 24
Peak memory 199964 kb
Host smart-baf6d06a-ba84-4ff4-bd60-0825419c39f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705394293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2705394293
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1887095225
Short name T394
Test name
Test status
Simulation time 102597717777 ps
CPU time 146.4 seconds
Started Jan 21 01:32:36 PM PST 24
Finished Jan 21 01:35:03 PM PST 24
Peak memory 199712 kb
Host smart-1fcffd5b-269b-4627-a16e-a982b0c8e66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887095225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1887095225
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2847946025
Short name T338
Test name
Test status
Simulation time 80708310702 ps
CPU time 36.99 seconds
Started Jan 21 01:44:49 PM PST 24
Finished Jan 21 01:45:27 PM PST 24
Peak memory 199480 kb
Host smart-bfb71f32-8b31-4535-a383-ce3c25021a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847946025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2847946025
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.497365957
Short name T258
Test name
Test status
Simulation time 153512343058 ps
CPU time 56.56 seconds
Started Jan 21 02:30:41 PM PST 24
Finished Jan 21 02:31:38 PM PST 24
Peak memory 199708 kb
Host smart-91187e33-b5c3-44ff-ad07-c8849481853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497365957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.497365957
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1491339411
Short name T330
Test name
Test status
Simulation time 54081111575 ps
CPU time 21.84 seconds
Started Jan 21 02:24:38 PM PST 24
Finished Jan 21 02:25:00 PM PST 24
Peak memory 199972 kb
Host smart-31dcb193-8de1-43f1-91aa-4c892f7f2bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491339411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1491339411
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1846967666
Short name T335
Test name
Test status
Simulation time 56929539065 ps
CPU time 45.55 seconds
Started Jan 21 01:45:07 PM PST 24
Finished Jan 21 01:45:54 PM PST 24
Peak memory 199468 kb
Host smart-712fc9c4-816d-48bb-881b-da8f3db02fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846967666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1846967666
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1528407463
Short name T95
Test name
Test status
Simulation time 183903353648 ps
CPU time 146.91 seconds
Started Jan 21 01:45:06 PM PST 24
Finished Jan 21 01:47:33 PM PST 24
Peak memory 199976 kb
Host smart-951c186a-c480-4672-962b-92df3553f5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528407463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1528407463
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3672575477
Short name T178
Test name
Test status
Simulation time 37659239166 ps
CPU time 61.24 seconds
Started Jan 21 01:56:31 PM PST 24
Finished Jan 21 01:57:33 PM PST 24
Peak memory 199496 kb
Host smart-2599ec35-b3b6-468b-b59c-5db4d039eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672575477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3672575477
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.474163378
Short name T340
Test name
Test status
Simulation time 35838693546 ps
CPU time 29.72 seconds
Started Jan 21 01:45:29 PM PST 24
Finished Jan 21 01:45:59 PM PST 24
Peak memory 199976 kb
Host smart-e9cd11cc-a30a-4941-a9bb-ba4b1ce1d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474163378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.474163378
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2089897435
Short name T236
Test name
Test status
Simulation time 54753369945 ps
CPU time 37.96 seconds
Started Jan 21 01:45:33 PM PST 24
Finished Jan 21 01:46:12 PM PST 24
Peak memory 200028 kb
Host smart-fcd72343-13b8-48d8-b127-2a0c9eb6fbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089897435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2089897435
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3281777841
Short name T228
Test name
Test status
Simulation time 124856152731 ps
CPU time 97.53 seconds
Started Jan 21 02:07:49 PM PST 24
Finished Jan 21 02:09:29 PM PST 24
Peak memory 199932 kb
Host smart-1f716395-5681-44a2-9137-8271018f4fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281777841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3281777841
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.625527508
Short name T278
Test name
Test status
Simulation time 66692047038 ps
CPU time 134.84 seconds
Started Jan 21 01:45:44 PM PST 24
Finished Jan 21 01:48:00 PM PST 24
Peak memory 199916 kb
Host smart-ac3a7b85-5651-4a45-b314-2c8b3613e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625527508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.625527508
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.732174682
Short name T126
Test name
Test status
Simulation time 91717118184 ps
CPU time 25.2 seconds
Started Jan 21 01:45:47 PM PST 24
Finished Jan 21 01:46:13 PM PST 24
Peak memory 199936 kb
Host smart-64b640d5-9fc2-4050-8bf8-e183f9e86876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732174682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.732174682
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.471499978
Short name T172
Test name
Test status
Simulation time 17863587994 ps
CPU time 30.79 seconds
Started Jan 21 01:46:00 PM PST 24
Finished Jan 21 01:46:32 PM PST 24
Peak memory 200004 kb
Host smart-99549079-fefd-4e85-bf16-93aacf83ddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471499978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.471499978
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1169090580
Short name T386
Test name
Test status
Simulation time 171317435511 ps
CPU time 63.81 seconds
Started Jan 21 01:35:45 PM PST 24
Finished Jan 21 01:36:50 PM PST 24
Peak memory 200064 kb
Host smart-f04de5c1-7251-4902-9662-134e3396fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169090580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1169090580
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1262191634
Short name T288
Test name
Test status
Simulation time 20989501004 ps
CPU time 26.38 seconds
Started Jan 21 01:36:13 PM PST 24
Finished Jan 21 01:36:52 PM PST 24
Peak memory 198812 kb
Host smart-63b44220-dc6f-434a-b95c-042a7bff849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262191634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1262191634
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.938799302
Short name T389
Test name
Test status
Simulation time 73282368277 ps
CPU time 28.5 seconds
Started Jan 21 01:36:15 PM PST 24
Finished Jan 21 01:36:54 PM PST 24
Peak memory 199516 kb
Host smart-a921f216-26c7-409b-8535-6b6a39896667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938799302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.938799302
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_stress_all.447952564
Short name T152
Test name
Test status
Simulation time 388040578460 ps
CPU time 123.23 seconds
Started Jan 21 01:37:03 PM PST 24
Finished Jan 21 01:39:08 PM PST 24
Peak memory 208380 kb
Host smart-714e9955-fd0c-4f6a-bf33-c1dabae46a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447952564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.447952564
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1702069232
Short name T347
Test name
Test status
Simulation time 50192941789 ps
CPU time 13.58 seconds
Started Jan 21 01:38:12 PM PST 24
Finished Jan 21 01:38:27 PM PST 24
Peak memory 198888 kb
Host smart-b0136270-5250-4346-a868-b6b649b612c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702069232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1702069232
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3739306103
Short name T72
Test name
Test status
Simulation time 58610352244 ps
CPU time 529.94 seconds
Started Jan 21 01:38:29 PM PST 24
Finished Jan 21 01:47:20 PM PST 24
Peak memory 216436 kb
Host smart-2d1419bf-99d2-40da-b034-b80b90de2060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739306103 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3739306103
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2241863444
Short name T348
Test name
Test status
Simulation time 18599918603 ps
CPU time 7.78 seconds
Started Jan 21 01:38:48 PM PST 24
Finished Jan 21 01:38:56 PM PST 24
Peak memory 199416 kb
Host smart-cf9ba3da-ccc5-4c5a-8d0e-400711a314e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241863444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2241863444
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_perf.2133459450
Short name T277
Test name
Test status
Simulation time 24966110239 ps
CPU time 1496.83 seconds
Started Jan 21 01:39:23 PM PST 24
Finished Jan 21 02:04:25 PM PST 24
Peak memory 199940 kb
Host smart-5ef978b6-e325-4baa-a12b-4da531ba8282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133459450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2133459450
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1262722036
Short name T279
Test name
Test status
Simulation time 154674012453 ps
CPU time 323.83 seconds
Started Jan 21 01:41:07 PM PST 24
Finished Jan 21 01:46:32 PM PST 24
Peak memory 225352 kb
Host smart-0924b4f6-36c2-47ef-9ae4-7ebe9e2dc2f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262722036 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1262722036
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1589142638
Short name T244
Test name
Test status
Simulation time 109673798748 ps
CPU time 95 seconds
Started Jan 21 01:41:29 PM PST 24
Finished Jan 21 01:43:04 PM PST 24
Peak memory 200084 kb
Host smart-4c234aca-8878-4fa7-98ee-274b823c5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589142638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1589142638
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1617190850
Short name T224
Test name
Test status
Simulation time 96176070323 ps
CPU time 329.61 seconds
Started Jan 21 01:41:54 PM PST 24
Finished Jan 21 01:47:26 PM PST 24
Peak memory 216516 kb
Host smart-bc3d6dee-8126-432e-83af-196b0e175a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617190850 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1617190850
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1515109657
Short name T140
Test name
Test status
Simulation time 211116247714 ps
CPU time 91.88 seconds
Started Jan 21 01:41:56 PM PST 24
Finished Jan 21 01:43:28 PM PST 24
Peak memory 199940 kb
Host smart-af95898e-a232-4448-aaf0-bf2097bc1bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515109657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1515109657
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3749446569
Short name T378
Test name
Test status
Simulation time 48906008521 ps
CPU time 70.68 seconds
Started Jan 21 01:54:09 PM PST 24
Finished Jan 21 01:55:20 PM PST 24
Peak memory 199984 kb
Host smart-839cde9d-39e3-4a0d-9882-e7d0c3e6a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749446569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3749446569
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3479225304
Short name T281
Test name
Test status
Simulation time 97659601153 ps
CPU time 36.73 seconds
Started Jan 21 01:28:36 PM PST 24
Finished Jan 21 01:29:14 PM PST 24
Peak memory 199064 kb
Host smart-bdc7ca88-d6b4-43c3-b0eb-dd3cc5f71395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479225304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3479225304
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.13935782
Short name T174
Test name
Test status
Simulation time 83997939508 ps
CPU time 28.84 seconds
Started Jan 21 02:38:19 PM PST 24
Finished Jan 21 02:38:52 PM PST 24
Peak memory 200024 kb
Host smart-baf225c4-1e68-460f-90ed-f6dead9b1fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13935782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.13935782
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2918364161
Short name T76
Test name
Test status
Simulation time 19472854 ps
CPU time 0.68 seconds
Started Jan 21 12:24:50 PM PST 24
Finished Jan 21 12:24:52 PM PST 24
Peak memory 195012 kb
Host smart-61034906-d70a-4833-a5ac-7beab1c9afe3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918364161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2918364161
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4003571396
Short name T68
Test name
Test status
Simulation time 205857042 ps
CPU time 2.26 seconds
Started Jan 21 12:34:03 PM PST 24
Finished Jan 21 12:34:06 PM PST 24
Peak memory 197056 kb
Host smart-4bc401f9-eda5-4749-842d-a2a8a7093efa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003571396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4003571396
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1451530859
Short name T37
Test name
Test status
Simulation time 26242026 ps
CPU time 0.66 seconds
Started Jan 21 12:24:33 PM PST 24
Finished Jan 21 12:24:35 PM PST 24
Peak memory 193336 kb
Host smart-9cf1e173-7c22-4b75-90c7-e7c1d5b2ee47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451530859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1451530859
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1148990211
Short name T43
Test name
Test status
Simulation time 78711801 ps
CPU time 1.31 seconds
Started Jan 21 01:45:10 PM PST 24
Finished Jan 21 01:45:12 PM PST 24
Peak memory 199652 kb
Host smart-9f8296a9-7caa-473e-88bc-c2ecf6736965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148990211 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1148990211
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.655659288
Short name T73
Test name
Test status
Simulation time 54243522 ps
CPU time 0.69 seconds
Started Jan 21 12:24:33 PM PST 24
Finished Jan 21 12:24:35 PM PST 24
Peak memory 193384 kb
Host smart-4130d29b-fc59-4e10-b2ec-f055790a34a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655659288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.655659288
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1182943452
Short name T1246
Test name
Test status
Simulation time 35160768 ps
CPU time 0.58 seconds
Started Jan 21 01:22:59 PM PST 24
Finished Jan 21 01:23:01 PM PST 24
Peak memory 184860 kb
Host smart-65f156a1-3ccf-4f73-ad8f-e2f77342c58f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182943452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1182943452
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2910527427
Short name T50
Test name
Test status
Simulation time 31530444 ps
CPU time 0.61 seconds
Started Jan 21 12:46:43 PM PST 24
Finished Jan 21 12:46:44 PM PST 24
Peak memory 194372 kb
Host smart-72dc75c0-b489-48e1-8448-9bfc071fea70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910527427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2910527427
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2385852692
Short name T487
Test name
Test status
Simulation time 86198958 ps
CPU time 1.5 seconds
Started Jan 21 01:41:32 PM PST 24
Finished Jan 21 01:41:35 PM PST 24
Peak memory 198920 kb
Host smart-aabb0aef-e460-438a-abec-3e59ed3f2826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385852692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2385852692
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2748231101
Short name T477
Test name
Test status
Simulation time 125549730 ps
CPU time 0.7 seconds
Started Jan 21 01:52:03 PM PST 24
Finished Jan 21 01:52:05 PM PST 24
Peak memory 195228 kb
Host smart-f7f9d8c7-328e-4771-a913-3856804fe8b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748231101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2748231101
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.323150772
Short name T1284
Test name
Test status
Simulation time 115312423 ps
CPU time 2.16 seconds
Started Jan 21 12:24:50 PM PST 24
Finished Jan 21 12:24:54 PM PST 24
Peak memory 197336 kb
Host smart-f23672ca-a9bb-4f31-a780-1abd7e8a0d79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323150772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.323150772
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.267342093
Short name T36
Test name
Test status
Simulation time 1031579335 ps
CPU time 2.16 seconds
Started Jan 21 12:24:50 PM PST 24
Finished Jan 21 12:24:54 PM PST 24
Peak memory 195124 kb
Host smart-22d9b9b3-7acd-4c6d-93df-c1806a79b1fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267342093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.267342093
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2888920411
Short name T456
Test name
Test status
Simulation time 56629838 ps
CPU time 0.85 seconds
Started Jan 21 12:51:24 PM PST 24
Finished Jan 21 12:51:28 PM PST 24
Peak memory 199512 kb
Host smart-7a3c8368-3925-4402-9e36-680f59e1f88f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888920411 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2888920411
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3469403974
Short name T1245
Test name
Test status
Simulation time 49801312 ps
CPU time 0.68 seconds
Started Jan 21 12:24:24 PM PST 24
Finished Jan 21 12:24:27 PM PST 24
Peak memory 194436 kb
Host smart-ac97108a-156d-4aeb-8a9e-26830cd1c430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469403974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3469403974
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.455459415
Short name T1238
Test name
Test status
Simulation time 13940722 ps
CPU time 0.57 seconds
Started Jan 21 12:20:03 PM PST 24
Finished Jan 21 12:20:04 PM PST 24
Peak memory 184912 kb
Host smart-6721878a-46a1-4641-b3c6-5d28c571f9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455459415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.455459415
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.279212075
Short name T485
Test name
Test status
Simulation time 24105692 ps
CPU time 0.67 seconds
Started Jan 21 12:47:56 PM PST 24
Finished Jan 21 12:47:58 PM PST 24
Peak memory 195684 kb
Host smart-0e3ca0d4-484c-4837-a42f-ceffa35746c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279212075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.279212075
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.774688658
Short name T86
Test name
Test status
Simulation time 165879077 ps
CPU time 1.29 seconds
Started Jan 21 01:00:29 PM PST 24
Finished Jan 21 01:00:32 PM PST 24
Peak memory 198724 kb
Host smart-c86517d1-eb3d-487e-ad3e-eb9829416a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774688658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.774688658
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.730696128
Short name T1262
Test name
Test status
Simulation time 53490174 ps
CPU time 0.65 seconds
Started Jan 21 12:54:48 PM PST 24
Finished Jan 21 12:54:50 PM PST 24
Peak memory 196264 kb
Host smart-7a6da21e-5299-47ed-adae-a8fe315231b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730696128 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.730696128
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4003264918
Short name T67
Test name
Test status
Simulation time 51612412 ps
CPU time 0.6 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:37 PM PST 24
Peak memory 193760 kb
Host smart-2da046f4-40a5-467b-b172-8056ea595569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003264918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4003264918
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.4016508760
Short name T45
Test name
Test status
Simulation time 15364043 ps
CPU time 0.54 seconds
Started Jan 21 01:31:02 PM PST 24
Finished Jan 21 01:31:03 PM PST 24
Peak memory 184812 kb
Host smart-6dbaab27-70bc-40f7-85c6-3beaab7e75fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016508760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.4016508760
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.831170434
Short name T1272
Test name
Test status
Simulation time 122833857 ps
CPU time 0.74 seconds
Started Jan 21 12:45:35 PM PST 24
Finished Jan 21 12:45:37 PM PST 24
Peak memory 196512 kb
Host smart-d71266ca-9eca-4312-8e16-648d3c3ac84a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831170434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.831170434
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.4026974934
Short name T42
Test name
Test status
Simulation time 179326548 ps
CPU time 1.66 seconds
Started Jan 21 01:06:40 PM PST 24
Finished Jan 21 01:06:42 PM PST 24
Peak memory 199692 kb
Host smart-e696c949-758d-4aee-ac24-ac5a8c4bc5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026974934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4026974934
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.710982124
Short name T459
Test name
Test status
Simulation time 56178253 ps
CPU time 0.65 seconds
Started Jan 21 01:01:32 PM PST 24
Finished Jan 21 01:01:33 PM PST 24
Peak memory 197284 kb
Host smart-03d44fee-2aed-4baf-808d-51d335d256c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710982124 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.710982124
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.943058865
Short name T1292
Test name
Test status
Simulation time 51799286 ps
CPU time 0.6 seconds
Started Jan 21 12:22:25 PM PST 24
Finished Jan 21 12:22:26 PM PST 24
Peak memory 195100 kb
Host smart-8721c2cb-8feb-4855-9901-467002f63382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943058865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.943058865
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1572879695
Short name T1275
Test name
Test status
Simulation time 17911572 ps
CPU time 0.64 seconds
Started Jan 21 12:22:25 PM PST 24
Finished Jan 21 12:22:26 PM PST 24
Peak memory 195232 kb
Host smart-5dcc6788-bbb6-4b45-bd4d-b5b53171a2f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572879695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1572879695
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.93214905
Short name T475
Test name
Test status
Simulation time 151188355 ps
CPU time 1.12 seconds
Started Jan 21 12:56:34 PM PST 24
Finished Jan 21 12:56:39 PM PST 24
Peak memory 199468 kb
Host smart-56ba0e64-7a7a-4825-87cf-7d8af7639cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93214905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.93214905
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2086773332
Short name T1260
Test name
Test status
Simulation time 79770687 ps
CPU time 1 seconds
Started Jan 21 01:08:52 PM PST 24
Finished Jan 21 01:08:54 PM PST 24
Peak memory 198696 kb
Host smart-ea8c41ed-f98c-4449-afec-e356d44af4db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086773332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2086773332
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3118332240
Short name T482
Test name
Test status
Simulation time 33479946 ps
CPU time 0.69 seconds
Started Jan 21 12:25:02 PM PST 24
Finished Jan 21 12:25:05 PM PST 24
Peak memory 196736 kb
Host smart-6e739f51-4cca-4686-9108-c0946588b05b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118332240 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3118332240
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.715439784
Short name T1244
Test name
Test status
Simulation time 14004408 ps
CPU time 0.57 seconds
Started Jan 21 01:04:54 PM PST 24
Finished Jan 21 01:04:56 PM PST 24
Peak memory 194132 kb
Host smart-fdd01e1f-e66c-468a-ba35-ef5742af2acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715439784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.715439784
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2984927353
Short name T469
Test name
Test status
Simulation time 97679515 ps
CPU time 0.78 seconds
Started Jan 21 12:25:08 PM PST 24
Finished Jan 21 12:25:09 PM PST 24
Peak memory 196236 kb
Host smart-17596484-bf0a-476a-9490-87c76c0dd95d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984927353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2984927353
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3086552696
Short name T33
Test name
Test status
Simulation time 224674095 ps
CPU time 1.44 seconds
Started Jan 21 12:25:08 PM PST 24
Finished Jan 21 12:25:10 PM PST 24
Peak memory 199500 kb
Host smart-467c81e0-cb68-4970-b48e-ed635ff9d086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086552696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3086552696
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1638160758
Short name T1279
Test name
Test status
Simulation time 70138849 ps
CPU time 0.96 seconds
Started Jan 21 01:49:14 PM PST 24
Finished Jan 21 01:49:15 PM PST 24
Peak memory 198696 kb
Host smart-f6722be1-d3a8-4085-b77c-93ac878e3979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638160758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1638160758
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3114832892
Short name T98
Test name
Test status
Simulation time 35161827 ps
CPU time 0.69 seconds
Started Jan 21 12:24:47 PM PST 24
Finished Jan 21 12:24:49 PM PST 24
Peak memory 196552 kb
Host smart-ad07f5f6-0b78-47bc-a962-4337cb2c6e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114832892 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3114832892
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2031543460
Short name T1
Test name
Test status
Simulation time 11842241 ps
CPU time 0.59 seconds
Started Jan 21 12:51:23 PM PST 24
Finished Jan 21 12:51:28 PM PST 24
Peak memory 195200 kb
Host smart-5668e8ef-d831-4594-aea9-a155b04074db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031543460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2031543460
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1178843653
Short name T1287
Test name
Test status
Simulation time 15604788 ps
CPU time 0.55 seconds
Started Jan 21 01:16:44 PM PST 24
Finished Jan 21 01:16:46 PM PST 24
Peak memory 184860 kb
Host smart-3af8f3c2-e1da-431f-a886-71c9210a42f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178843653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1178843653
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1552232478
Short name T476
Test name
Test status
Simulation time 17793614 ps
CPU time 0.74 seconds
Started Jan 21 12:53:31 PM PST 24
Finished Jan 21 12:53:33 PM PST 24
Peak memory 196644 kb
Host smart-3f3e69da-92f1-4c43-989e-f2c900350580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552232478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1552232478
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2809923469
Short name T1261
Test name
Test status
Simulation time 121743123 ps
CPU time 1.39 seconds
Started Jan 21 01:17:05 PM PST 24
Finished Jan 21 01:17:09 PM PST 24
Peak memory 199652 kb
Host smart-1f580b51-5b6d-48c2-ae8d-1957ed4b95e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809923469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2809923469
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1967296763
Short name T83
Test name
Test status
Simulation time 144780245 ps
CPU time 1.29 seconds
Started Jan 21 12:37:15 PM PST 24
Finished Jan 21 12:37:17 PM PST 24
Peak memory 198768 kb
Host smart-45e60ff0-d131-4423-9cf3-51d93f0e8dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967296763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1967296763
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2152820655
Short name T486
Test name
Test status
Simulation time 53116538 ps
CPU time 1.34 seconds
Started Jan 21 01:40:09 PM PST 24
Finished Jan 21 01:40:11 PM PST 24
Peak memory 199820 kb
Host smart-47772423-be29-4a93-8210-846ac58d538c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152820655 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2152820655
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3165450408
Short name T1283
Test name
Test status
Simulation time 17184808 ps
CPU time 0.63 seconds
Started Jan 21 01:06:37 PM PST 24
Finished Jan 21 01:06:38 PM PST 24
Peak memory 195316 kb
Host smart-83a45681-39a4-4d70-bde2-a070a0e71a18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165450408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3165450408
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.957246643
Short name T1256
Test name
Test status
Simulation time 198476887 ps
CPU time 0.56 seconds
Started Jan 21 02:32:49 PM PST 24
Finished Jan 21 02:32:52 PM PST 24
Peak memory 184888 kb
Host smart-483918f6-da46-4a8c-b614-b6a3a68c37f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957246643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.957246643
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1922828824
Short name T1280
Test name
Test status
Simulation time 82375859 ps
CPU time 0.62 seconds
Started Jan 21 12:24:49 PM PST 24
Finished Jan 21 12:24:51 PM PST 24
Peak memory 195320 kb
Host smart-8626e53c-e9d2-42a1-a9fa-42d68b7addc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922828824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1922828824
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.4165917982
Short name T41
Test name
Test status
Simulation time 812669318 ps
CPU time 1.75 seconds
Started Jan 21 12:54:46 PM PST 24
Finished Jan 21 12:54:49 PM PST 24
Peak memory 199704 kb
Host smart-8483f7f6-90ea-4bae-adaa-6870ded5c33f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165917982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.4165917982
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3415026407
Short name T1267
Test name
Test status
Simulation time 160363562 ps
CPU time 0.94 seconds
Started Jan 21 12:24:47 PM PST 24
Finished Jan 21 12:24:49 PM PST 24
Peak memory 198636 kb
Host smart-f840c7ee-acfc-48c8-b777-f8d7ecea3c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415026407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3415026407
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3478830416
Short name T9
Test name
Test status
Simulation time 30474759 ps
CPU time 1.45 seconds
Started Jan 21 12:49:02 PM PST 24
Finished Jan 21 12:49:04 PM PST 24
Peak memory 199708 kb
Host smart-dcfd023f-e778-4828-beb1-837147301489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478830416 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3478830416
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.417148067
Short name T58
Test name
Test status
Simulation time 38569591 ps
CPU time 0.55 seconds
Started Jan 21 12:23:14 PM PST 24
Finished Jan 21 12:23:15 PM PST 24
Peak memory 195220 kb
Host smart-507bb4ca-8b57-4b8d-a504-e77c122dc135
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417148067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.417148067
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3239363738
Short name T1285
Test name
Test status
Simulation time 15607097 ps
CPU time 0.6 seconds
Started Jan 21 12:50:19 PM PST 24
Finished Jan 21 12:50:21 PM PST 24
Peak memory 184852 kb
Host smart-7b503d52-6009-4a40-b557-6402b53a01b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239363738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3239363738
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.187644649
Short name T74
Test name
Test status
Simulation time 37332264 ps
CPU time 0.75 seconds
Started Jan 21 12:51:24 PM PST 24
Finished Jan 21 12:51:28 PM PST 24
Peak memory 196580 kb
Host smart-151c4a6d-7503-4793-9811-8e894da3b38b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187644649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.187644649
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2815534917
Short name T1249
Test name
Test status
Simulation time 44522290 ps
CPU time 2.08 seconds
Started Jan 21 01:02:37 PM PST 24
Finished Jan 21 01:02:40 PM PST 24
Peak memory 199792 kb
Host smart-424e26dc-b13b-4b60-aa6c-f2f766dcc524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815534917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2815534917
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1294140434
Short name T1234
Test name
Test status
Simulation time 19206527 ps
CPU time 0.7 seconds
Started Jan 21 12:23:22 PM PST 24
Finished Jan 21 12:23:23 PM PST 24
Peak memory 197868 kb
Host smart-2f82a1af-c668-44c8-8e33-13664b1cdf74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294140434 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1294140434
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.38901253
Short name T1254
Test name
Test status
Simulation time 13798891 ps
CPU time 0.57 seconds
Started Jan 21 02:16:05 PM PST 24
Finished Jan 21 02:16:08 PM PST 24
Peak memory 195328 kb
Host smart-4512ede1-afad-4668-a648-7f1a4e34d3aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38901253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.38901253
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2904981463
Short name T1277
Test name
Test status
Simulation time 18254929 ps
CPU time 0.59 seconds
Started Jan 21 12:40:01 PM PST 24
Finished Jan 21 12:40:03 PM PST 24
Peak memory 184820 kb
Host smart-369407bc-9a52-4747-9857-133012db786b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904981463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2904981463
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3361666308
Short name T6
Test name
Test status
Simulation time 55984488 ps
CPU time 0.64 seconds
Started Jan 21 12:23:23 PM PST 24
Finished Jan 21 12:23:25 PM PST 24
Peak memory 195212 kb
Host smart-411a8b25-c7a6-4e50-8cc2-6f7d37378213
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361666308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3361666308
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4228118720
Short name T471
Test name
Test status
Simulation time 501483552 ps
CPU time 1.63 seconds
Started Jan 21 12:23:24 PM PST 24
Finished Jan 21 12:23:26 PM PST 24
Peak memory 199560 kb
Host smart-e706087c-32a6-491c-9797-24d8384a6a19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228118720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4228118720
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.640139580
Short name T397
Test name
Test status
Simulation time 44388589 ps
CPU time 0.89 seconds
Started Jan 21 12:23:22 PM PST 24
Finished Jan 21 12:23:23 PM PST 24
Peak memory 198328 kb
Host smart-13ed3cca-45bd-4ea2-81b5-a0efe927bbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640139580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.640139580
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.849090823
Short name T1281
Test name
Test status
Simulation time 43043536 ps
CPU time 0.76 seconds
Started Jan 21 12:23:33 PM PST 24
Finished Jan 21 12:23:35 PM PST 24
Peak memory 199116 kb
Host smart-fbb8ab72-1c7b-4b79-99ea-b505a2702a66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849090823 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.849090823
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.52986086
Short name T1264
Test name
Test status
Simulation time 30330259 ps
CPU time 0.59 seconds
Started Jan 21 12:23:45 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 194840 kb
Host smart-4e11b691-28a7-43dd-8394-fa96b33ac8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52986086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.52986086
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4282321014
Short name T8
Test name
Test status
Simulation time 38959760 ps
CPU time 0.57 seconds
Started Jan 21 12:23:18 PM PST 24
Finished Jan 21 12:23:19 PM PST 24
Peak memory 185176 kb
Host smart-6b11a551-5fb6-4d80-96ab-fbe5f8bbb756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282321014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4282321014
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2587114724
Short name T1265
Test name
Test status
Simulation time 105196062 ps
CPU time 0.73 seconds
Started Jan 21 12:58:44 PM PST 24
Finished Jan 21 12:58:46 PM PST 24
Peak memory 195488 kb
Host smart-ad0a2016-da93-431f-9032-7c3094cfe3da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587114724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2587114724
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.614623339
Short name T464
Test name
Test status
Simulation time 46431601 ps
CPU time 1.32 seconds
Started Jan 21 01:05:38 PM PST 24
Finished Jan 21 01:05:41 PM PST 24
Peak memory 199712 kb
Host smart-cd0ba320-2194-4785-80d9-0eacd7d07458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614623339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.614623339
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1257340337
Short name T1268
Test name
Test status
Simulation time 130128132 ps
CPU time 1.27 seconds
Started Jan 21 12:23:19 PM PST 24
Finished Jan 21 12:23:21 PM PST 24
Peak memory 198752 kb
Host smart-876272f2-8da2-417a-a791-52fcea2576ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257340337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1257340337
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1918454219
Short name T474
Test name
Test status
Simulation time 82318650 ps
CPU time 1.3 seconds
Started Jan 21 12:23:41 PM PST 24
Finished Jan 21 12:23:44 PM PST 24
Peak memory 200060 kb
Host smart-a9c8e981-4299-4da4-9aa4-c1f791f86080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918454219 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1918454219
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1990416920
Short name T1252
Test name
Test status
Simulation time 111278057 ps
CPU time 0.57 seconds
Started Jan 21 12:23:45 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 194920 kb
Host smart-db60a1d9-88bd-46cc-a624-cbf23d64cee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990416920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1990416920
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2904077686
Short name T1230
Test name
Test status
Simulation time 32179498 ps
CPU time 0.54 seconds
Started Jan 21 12:46:00 PM PST 24
Finished Jan 21 12:46:02 PM PST 24
Peak memory 184836 kb
Host smart-a6d73a87-4960-4042-a4e9-60793856fc73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904077686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2904077686
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.218068507
Short name T54
Test name
Test status
Simulation time 39515467 ps
CPU time 0.76 seconds
Started Jan 21 12:23:46 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 196380 kb
Host smart-3901666f-1f34-4a7f-97f5-64f25920df9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218068507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.218068507
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2023810658
Short name T1266
Test name
Test status
Simulation time 89860147 ps
CPU time 1.89 seconds
Started Jan 21 12:23:46 PM PST 24
Finished Jan 21 12:23:57 PM PST 24
Peak memory 199476 kb
Host smart-18d2a571-d58e-4e5d-bb67-219caca9e4f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023810658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2023810658
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1595410283
Short name T82
Test name
Test status
Simulation time 418734743 ps
CPU time 1.21 seconds
Started Jan 21 12:40:59 PM PST 24
Finished Jan 21 12:41:03 PM PST 24
Peak memory 198760 kb
Host smart-5d721567-df2c-43b3-b523-efb86cbc3cce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595410283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1595410283
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2387071059
Short name T96
Test name
Test status
Simulation time 15247686 ps
CPU time 0.65 seconds
Started Jan 21 12:23:47 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 196596 kb
Host smart-43be0467-38f0-46e3-bf5b-91511fecb5bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387071059 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2387071059
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3074558535
Short name T51
Test name
Test status
Simulation time 18414990 ps
CPU time 0.64 seconds
Started Jan 21 01:42:11 PM PST 24
Finished Jan 21 01:42:13 PM PST 24
Peak memory 195236 kb
Host smart-e5ed6c30-e028-43d1-a5e4-6e0ddfef90f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074558535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3074558535
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1965669207
Short name T1291
Test name
Test status
Simulation time 17174456 ps
CPU time 0.55 seconds
Started Jan 21 01:32:41 PM PST 24
Finished Jan 21 01:32:44 PM PST 24
Peak memory 194160 kb
Host smart-8b78f285-18dd-4b06-bb3d-66e097d75a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965669207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1965669207
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3101436643
Short name T1293
Test name
Test status
Simulation time 35705450 ps
CPU time 0.75 seconds
Started Jan 21 02:21:46 PM PST 24
Finished Jan 21 02:21:47 PM PST 24
Peak memory 196688 kb
Host smart-d49fa0eb-00a1-457b-9ff6-a0b06123cb47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101436643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3101436643
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3187901965
Short name T472
Test name
Test status
Simulation time 71299564 ps
CPU time 0.92 seconds
Started Jan 21 12:23:39 PM PST 24
Finished Jan 21 12:23:41 PM PST 24
Peak memory 199492 kb
Host smart-de843d72-d81e-4014-9fde-38b93d153a44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187901965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3187901965
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1084026497
Short name T49
Test name
Test status
Simulation time 39397451 ps
CPU time 0.65 seconds
Started Jan 21 12:45:14 PM PST 24
Finished Jan 21 12:45:16 PM PST 24
Peak memory 194444 kb
Host smart-f1e30b6b-2ade-423c-baf3-aa72582ac3b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084026497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1084026497
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3467706188
Short name T1229
Test name
Test status
Simulation time 445197103 ps
CPU time 2.26 seconds
Started Jan 21 12:25:08 PM PST 24
Finished Jan 21 12:25:11 PM PST 24
Peak memory 196772 kb
Host smart-0ba8d12e-82fe-47f5-b673-d02dabbb8fcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467706188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3467706188
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3081631511
Short name T468
Test name
Test status
Simulation time 28539265 ps
CPU time 0.58 seconds
Started Jan 21 12:41:23 PM PST 24
Finished Jan 21 12:41:24 PM PST 24
Peak memory 195168 kb
Host smart-e3a6a484-4e6c-4b4a-bc4e-6e91042ac104
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081631511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3081631511
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1192412336
Short name T461
Test name
Test status
Simulation time 26016390 ps
CPU time 0.84 seconds
Started Jan 21 12:55:01 PM PST 24
Finished Jan 21 12:55:03 PM PST 24
Peak memory 199624 kb
Host smart-cfab8453-063c-49cc-8ee5-f36273b94ba2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192412336 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1192412336
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2014564608
Short name T1233
Test name
Test status
Simulation time 12790746 ps
CPU time 0.59 seconds
Started Jan 21 12:25:01 PM PST 24
Finished Jan 21 12:25:04 PM PST 24
Peak memory 195036 kb
Host smart-2194f94a-758e-47f9-ae2c-17e59bfa98c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014564608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2014564608
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3484437445
Short name T1282
Test name
Test status
Simulation time 37989449 ps
CPU time 0.55 seconds
Started Jan 21 01:13:00 PM PST 24
Finished Jan 21 01:13:01 PM PST 24
Peak memory 184812 kb
Host smart-6f987197-4433-4539-a035-1f4f905f59d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484437445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3484437445
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3621198262
Short name T56
Test name
Test status
Simulation time 75636068 ps
CPU time 0.64 seconds
Started Jan 21 01:15:53 PM PST 24
Finished Jan 21 01:15:54 PM PST 24
Peak memory 195532 kb
Host smart-a5a0f33a-2a5e-4f9b-815e-95ca0d1075b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621198262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3621198262
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.463478624
Short name T1263
Test name
Test status
Simulation time 38593715 ps
CPU time 1.98 seconds
Started Jan 21 01:52:06 PM PST 24
Finished Jan 21 01:52:09 PM PST 24
Peak memory 199712 kb
Host smart-7bb60c0a-deb0-4381-89f0-faf7b16a1ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463478624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.463478624
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.781833219
Short name T34
Test name
Test status
Simulation time 51913086 ps
CPU time 0.97 seconds
Started Jan 21 12:53:34 PM PST 24
Finished Jan 21 12:53:38 PM PST 24
Peak memory 198940 kb
Host smart-a19362f8-8343-490b-aa64-fb6d3f21a138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781833219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.781833219
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3807462493
Short name T57
Test name
Test status
Simulation time 15520836 ps
CPU time 0.57 seconds
Started Jan 21 12:23:43 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 184804 kb
Host smart-f69f6dfb-0823-4b73-9a9c-08b3a26e5a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807462493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3807462493
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.284289523
Short name T1273
Test name
Test status
Simulation time 16201582 ps
CPU time 0.6 seconds
Started Jan 21 12:23:48 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 194392 kb
Host smart-b4028f91-9966-4524-89c2-119cbcea3cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284289523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.284289523
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.4084902829
Short name T463
Test name
Test status
Simulation time 41052991 ps
CPU time 0.61 seconds
Started Jan 21 12:44:32 PM PST 24
Finished Jan 21 12:44:34 PM PST 24
Peak memory 194008 kb
Host smart-334833a0-0312-4413-8e11-ead99d8180f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084902829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.4084902829
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1672196101
Short name T66
Test name
Test status
Simulation time 14287195 ps
CPU time 0.6 seconds
Started Jan 21 12:23:48 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 185176 kb
Host smart-1466c1bb-35b3-49a0-b965-c9f6fef492a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672196101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1672196101
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1277269717
Short name T1276
Test name
Test status
Simulation time 47254055 ps
CPU time 0.54 seconds
Started Jan 21 12:23:47 PM PST 24
Finished Jan 21 12:23:56 PM PST 24
Peak memory 185176 kb
Host smart-29a2405e-f610-40c3-9d7b-0c8637ee4786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277269717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1277269717
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2886618939
Short name T460
Test name
Test status
Simulation time 11148768 ps
CPU time 0.53 seconds
Started Jan 21 01:15:53 PM PST 24
Finished Jan 21 01:15:55 PM PST 24
Peak memory 184860 kb
Host smart-b9990d18-74f0-4a7c-911b-f14e34bad2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886618939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2886618939
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.898941742
Short name T1241
Test name
Test status
Simulation time 16653535 ps
CPU time 0.55 seconds
Started Jan 21 12:23:51 PM PST 24
Finished Jan 21 12:24:00 PM PST 24
Peak memory 184784 kb
Host smart-9745db0c-0262-45ba-914b-faab5a10e9fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898941742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.898941742
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1243019691
Short name T1231
Test name
Test status
Simulation time 39638836 ps
CPU time 0.61 seconds
Started Jan 21 12:38:27 PM PST 24
Finished Jan 21 12:38:30 PM PST 24
Peak memory 194044 kb
Host smart-d054d87a-7181-4a83-8f5a-67e23867d0cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243019691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1243019691
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1817045890
Short name T1242
Test name
Test status
Simulation time 19489815 ps
CPU time 0.55 seconds
Started Jan 21 12:23:53 PM PST 24
Finished Jan 21 12:24:00 PM PST 24
Peak memory 184932 kb
Host smart-b303f609-55d9-47fb-85de-5c9f3f390ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817045890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1817045890
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2438371775
Short name T77
Test name
Test status
Simulation time 97634705 ps
CPU time 0.7 seconds
Started Jan 21 12:25:08 PM PST 24
Finished Jan 21 12:25:09 PM PST 24
Peak memory 194692 kb
Host smart-9585dbb8-65c6-49f5-adac-15611e2e183b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438371775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2438371775
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4279251477
Short name T466
Test name
Test status
Simulation time 175628524 ps
CPU time 2.46 seconds
Started Jan 21 01:18:45 PM PST 24
Finished Jan 21 01:18:48 PM PST 24
Peak memory 197440 kb
Host smart-2c731540-101a-4ccc-b87b-96507424cc4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279251477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4279251477
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2387773300
Short name T2
Test name
Test status
Simulation time 30988313 ps
CPU time 0.58 seconds
Started Jan 21 12:54:17 PM PST 24
Finished Jan 21 12:54:19 PM PST 24
Peak memory 195168 kb
Host smart-4e0c4830-998a-4b1b-9ba3-f578bed2fa93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387773300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2387773300
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2189760126
Short name T484
Test name
Test status
Simulation time 18303296 ps
CPU time 0.86 seconds
Started Jan 21 12:54:59 PM PST 24
Finished Jan 21 12:55:01 PM PST 24
Peak memory 199580 kb
Host smart-dfa7bd88-379e-4ac9-a073-1075f17db426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189760126 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2189760126
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3347269615
Short name T1270
Test name
Test status
Simulation time 43497871 ps
CPU time 0.58 seconds
Started Jan 21 01:29:07 PM PST 24
Finished Jan 21 01:29:08 PM PST 24
Peak memory 195308 kb
Host smart-23a7f008-15e6-4619-8a6d-ae8712eaeae7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347269615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3347269615
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2823512139
Short name T65
Test name
Test status
Simulation time 15615142 ps
CPU time 0.58 seconds
Started Jan 21 12:43:07 PM PST 24
Finished Jan 21 12:43:09 PM PST 24
Peak memory 194064 kb
Host smart-82c2a5ff-be93-4309-95e3-dec3a7107f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823512139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2823512139
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.228599752
Short name T1269
Test name
Test status
Simulation time 20771570 ps
CPU time 0.66 seconds
Started Jan 21 01:24:58 PM PST 24
Finished Jan 21 01:25:01 PM PST 24
Peak memory 195632 kb
Host smart-2b13a621-f772-4ab2-bef8-7683742ff1bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228599752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.228599752
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3040044324
Short name T1278
Test name
Test status
Simulation time 184447843 ps
CPU time 1.16 seconds
Started Jan 21 12:40:27 PM PST 24
Finished Jan 21 12:40:29 PM PST 24
Peak memory 199704 kb
Host smart-07446bf6-d883-47f8-9df4-f623a459b256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040044324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3040044324
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3490090060
Short name T1237
Test name
Test status
Simulation time 52003245 ps
CPU time 0.95 seconds
Started Jan 21 12:19:29 PM PST 24
Finished Jan 21 12:19:31 PM PST 24
Peak memory 198596 kb
Host smart-af8db73e-a6c0-46da-b273-c5c4fe268628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490090060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3490090060
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3849811146
Short name T458
Test name
Test status
Simulation time 45094997 ps
CPU time 0.55 seconds
Started Jan 21 12:23:54 PM PST 24
Finished Jan 21 12:24:00 PM PST 24
Peak memory 184900 kb
Host smart-88351704-3b0a-4fb7-b498-e2f88c0b2a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849811146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3849811146
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3574619715
Short name T455
Test name
Test status
Simulation time 15472381 ps
CPU time 0.58 seconds
Started Jan 21 12:58:01 PM PST 24
Finished Jan 21 12:58:02 PM PST 24
Peak memory 184916 kb
Host smart-9141611a-e703-4bab-b5be-174982352ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574619715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3574619715
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3786943293
Short name T1255
Test name
Test status
Simulation time 33302984 ps
CPU time 0.54 seconds
Started Jan 21 12:45:55 PM PST 24
Finished Jan 21 12:45:57 PM PST 24
Peak memory 184832 kb
Host smart-22c18778-9652-4b49-8110-3d6a43e1f998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786943293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3786943293
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2893996988
Short name T1289
Test name
Test status
Simulation time 27773588 ps
CPU time 0.56 seconds
Started Jan 21 12:24:06 PM PST 24
Finished Jan 21 12:24:07 PM PST 24
Peak memory 184784 kb
Host smart-ae396dda-1850-4b69-a65c-5ec557815a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893996988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2893996988
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1397207602
Short name T399
Test name
Test status
Simulation time 36010136 ps
CPU time 0.54 seconds
Started Jan 21 12:24:01 PM PST 24
Finished Jan 21 12:24:03 PM PST 24
Peak memory 184824 kb
Host smart-59e72e1c-e796-44a3-ae02-12882a83d877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397207602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1397207602
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.305103515
Short name T1288
Test name
Test status
Simulation time 14584628 ps
CPU time 0.55 seconds
Started Jan 21 12:24:00 PM PST 24
Finished Jan 21 12:24:03 PM PST 24
Peak memory 184932 kb
Host smart-42f1c53a-95dc-4a7b-88b0-c8c446070bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305103515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.305103515
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.150432552
Short name T3
Test name
Test status
Simulation time 53762989 ps
CPU time 0.59 seconds
Started Jan 21 12:24:07 PM PST 24
Finished Jan 21 12:24:08 PM PST 24
Peak memory 185168 kb
Host smart-2ee3d226-e69c-494a-a7f1-b5873f4fc32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150432552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.150432552
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1984106019
Short name T465
Test name
Test status
Simulation time 47632173 ps
CPU time 0.6 seconds
Started Jan 21 12:24:00 PM PST 24
Finished Jan 21 12:24:03 PM PST 24
Peak memory 194028 kb
Host smart-4f9422f4-e9c5-4b1b-81d0-9892d3aef88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984106019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1984106019
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2640486475
Short name T400
Test name
Test status
Simulation time 14748470 ps
CPU time 0.56 seconds
Started Jan 21 02:28:21 PM PST 24
Finished Jan 21 02:28:22 PM PST 24
Peak memory 184932 kb
Host smart-20a6d469-248e-408b-badc-5f50884771f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640486475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2640486475
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3277059167
Short name T1236
Test name
Test status
Simulation time 18609681 ps
CPU time 0.64 seconds
Started Jan 21 12:24:43 PM PST 24
Finished Jan 21 12:24:44 PM PST 24
Peak memory 194300 kb
Host smart-a075b57f-eaf0-4dc1-a976-1c93325f3650
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277059167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3277059167
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.731526014
Short name T479
Test name
Test status
Simulation time 175267827 ps
CPU time 1.47 seconds
Started Jan 21 12:24:59 PM PST 24
Finished Jan 21 12:25:02 PM PST 24
Peak memory 197304 kb
Host smart-ca46541a-ba34-42ab-85e3-7a7ea3f5d03a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731526014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.731526014
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3817351520
Short name T52
Test name
Test status
Simulation time 16649304 ps
CPU time 0.56 seconds
Started Jan 21 12:31:34 PM PST 24
Finished Jan 21 12:31:36 PM PST 24
Peak memory 195172 kb
Host smart-33e83852-173b-43b7-809f-fd812276ca6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817351520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3817351520
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4030736285
Short name T483
Test name
Test status
Simulation time 15008101 ps
CPU time 0.65 seconds
Started Jan 21 01:31:11 PM PST 24
Finished Jan 21 01:31:13 PM PST 24
Peak memory 197172 kb
Host smart-be9ad331-1f3e-4972-8810-773a74617743
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030736285 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4030736285
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.760868560
Short name T1235
Test name
Test status
Simulation time 26019457 ps
CPU time 0.56 seconds
Started Jan 21 12:25:00 PM PST 24
Finished Jan 21 12:25:02 PM PST 24
Peak memory 195040 kb
Host smart-fb97ce5d-4784-4c00-8767-9c1940db2f48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760868560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.760868560
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2607782186
Short name T1286
Test name
Test status
Simulation time 25888702 ps
CPU time 0.56 seconds
Started Jan 21 12:53:55 PM PST 24
Finished Jan 21 12:53:56 PM PST 24
Peak memory 184724 kb
Host smart-28c70f83-bb51-4ab6-99de-a6d9170dfcec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607782186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2607782186
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2902654095
Short name T55
Test name
Test status
Simulation time 28356648 ps
CPU time 0.66 seconds
Started Jan 21 12:24:17 PM PST 24
Finished Jan 21 12:24:19 PM PST 24
Peak memory 194312 kb
Host smart-912407b6-93e9-40c8-b7bb-076ea7207439
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902654095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2902654095
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2151519504
Short name T81
Test name
Test status
Simulation time 83792361 ps
CPU time 1.65 seconds
Started Jan 21 12:25:00 PM PST 24
Finished Jan 21 12:25:04 PM PST 24
Peak memory 199664 kb
Host smart-02ef4066-92a4-4791-ab8e-d0a92aab3240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151519504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2151519504
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3302621167
Short name T84
Test name
Test status
Simulation time 48339026 ps
CPU time 0.98 seconds
Started Jan 21 12:24:56 PM PST 24
Finished Jan 21 12:24:58 PM PST 24
Peak memory 198336 kb
Host smart-f82d83ab-e979-4c9b-ad10-f4547774b26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302621167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3302621167
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.664609061
Short name T7
Test name
Test status
Simulation time 11664810 ps
CPU time 0.56 seconds
Started Jan 21 12:49:04 PM PST 24
Finished Jan 21 12:49:06 PM PST 24
Peak memory 184888 kb
Host smart-60a884df-ca57-4390-a773-5a2f27b6f381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664609061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.664609061
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2881733931
Short name T488
Test name
Test status
Simulation time 11774086 ps
CPU time 0.56 seconds
Started Jan 21 01:01:34 PM PST 24
Finished Jan 21 01:01:35 PM PST 24
Peak memory 184920 kb
Host smart-a963c359-3b4c-44ac-9956-6be42793d3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881733931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2881733931
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2652904503
Short name T454
Test name
Test status
Simulation time 27072139 ps
CPU time 0.55 seconds
Started Jan 21 12:40:10 PM PST 24
Finished Jan 21 12:40:16 PM PST 24
Peak memory 184820 kb
Host smart-c7109e6d-3451-4e76-9b2c-c86c819ba6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652904503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2652904503
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2331830411
Short name T398
Test name
Test status
Simulation time 15497513 ps
CPU time 0.53 seconds
Started Jan 21 12:49:17 PM PST 24
Finished Jan 21 12:49:18 PM PST 24
Peak memory 194028 kb
Host smart-f04d5778-ed98-4640-8162-acfaa6b980aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331830411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2331830411
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2143014640
Short name T1253
Test name
Test status
Simulation time 51696436 ps
CPU time 0.58 seconds
Started Jan 21 12:24:14 PM PST 24
Finished Jan 21 12:24:16 PM PST 24
Peak memory 194028 kb
Host smart-0a6220ac-8491-4b9a-ae9a-1795a5e5ed69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143014640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2143014640
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2442328847
Short name T490
Test name
Test status
Simulation time 131914225 ps
CPU time 0.58 seconds
Started Jan 21 12:24:15 PM PST 24
Finished Jan 21 12:24:17 PM PST 24
Peak memory 194028 kb
Host smart-a33b4b21-17b5-4a19-a81d-7232513c3d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442328847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2442328847
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.968415924
Short name T1290
Test name
Test status
Simulation time 49105012 ps
CPU time 0.55 seconds
Started Jan 21 12:42:44 PM PST 24
Finished Jan 21 12:42:50 PM PST 24
Peak memory 184932 kb
Host smart-19b77434-30bc-4a2d-a53e-0297f2c03d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968415924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.968415924
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1501328005
Short name T470
Test name
Test status
Simulation time 34513866 ps
CPU time 0.63 seconds
Started Jan 21 12:24:14 PM PST 24
Finished Jan 21 12:24:16 PM PST 24
Peak memory 194400 kb
Host smart-cc92ff29-d2b5-4017-bddf-b6774e5ebcb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501328005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1501328005
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2198153396
Short name T1239
Test name
Test status
Simulation time 87205659 ps
CPU time 0.55 seconds
Started Jan 21 12:24:26 PM PST 24
Finished Jan 21 12:24:28 PM PST 24
Peak memory 194400 kb
Host smart-e862d07f-398e-4a55-9493-7a863dbad996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198153396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2198153396
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2788823294
Short name T46
Test name
Test status
Simulation time 68878046 ps
CPU time 0.55 seconds
Started Jan 21 12:24:32 PM PST 24
Finished Jan 21 12:24:34 PM PST 24
Peak memory 194400 kb
Host smart-5a2b2f11-8346-4b0c-bd54-489c839ba8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788823294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2788823294
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2597353834
Short name T1240
Test name
Test status
Simulation time 19404330 ps
CPU time 0.55 seconds
Started Jan 21 01:56:14 PM PST 24
Finished Jan 21 01:56:15 PM PST 24
Peak memory 184944 kb
Host smart-5195a716-e117-4958-8393-2b89cedffbce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597353834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2597353834
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1402980978
Short name T1232
Test name
Test status
Simulation time 94087296 ps
CPU time 0.73 seconds
Started Jan 21 12:21:07 PM PST 24
Finished Jan 21 12:21:09 PM PST 24
Peak memory 197052 kb
Host smart-ce91932e-2ba8-4bbc-959f-3abb3747cc76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402980978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1402980978
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1793195723
Short name T481
Test name
Test status
Simulation time 60538330 ps
CPU time 1.34 seconds
Started Jan 21 12:22:25 PM PST 24
Finished Jan 21 12:22:27 PM PST 24
Peak memory 199556 kb
Host smart-fd5d974e-ed4a-434b-9a59-0aa83760d999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793195723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1793195723
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.697675092
Short name T1274
Test name
Test status
Simulation time 48829365 ps
CPU time 1.03 seconds
Started Jan 21 12:24:23 PM PST 24
Finished Jan 21 12:24:28 PM PST 24
Peak memory 197160 kb
Host smart-1c094814-78ba-44c2-84cf-40c3c232cdc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697675092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.697675092
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1401623196
Short name T1248
Test name
Test status
Simulation time 41192481 ps
CPU time 0.77 seconds
Started Jan 21 12:24:53 PM PST 24
Finished Jan 21 12:24:56 PM PST 24
Peak memory 198592 kb
Host smart-6761b369-0c35-40d0-9257-fb85049e4128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401623196 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1401623196
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3928191197
Short name T59
Test name
Test status
Simulation time 13434317 ps
CPU time 0.61 seconds
Started Jan 21 12:59:05 PM PST 24
Finished Jan 21 12:59:08 PM PST 24
Peak memory 195236 kb
Host smart-b7cee55a-d162-48f8-ad82-00fa85011948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928191197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3928191197
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1271108227
Short name T1258
Test name
Test status
Simulation time 18022895 ps
CPU time 0.59 seconds
Started Jan 21 01:33:04 PM PST 24
Finished Jan 21 01:33:09 PM PST 24
Peak memory 194040 kb
Host smart-40b9657a-98a5-4a7e-af99-2841e8e97d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271108227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1271108227
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.418997256
Short name T478
Test name
Test status
Simulation time 56015245 ps
CPU time 0.76 seconds
Started Jan 21 12:24:53 PM PST 24
Finished Jan 21 12:24:56 PM PST 24
Peak memory 196616 kb
Host smart-620e5e1f-8852-4c49-a7a6-3a09a03605c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418997256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.418997256
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.530601667
Short name T40
Test name
Test status
Simulation time 27592782 ps
CPU time 1.37 seconds
Started Jan 21 12:53:28 PM PST 24
Finished Jan 21 12:53:32 PM PST 24
Peak memory 199728 kb
Host smart-3f2f9d92-ba67-4caa-af0e-9628649f9aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530601667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.530601667
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.4277429804
Short name T1271
Test name
Test status
Simulation time 200090657 ps
CPU time 0.93 seconds
Started Jan 21 12:37:06 PM PST 24
Finished Jan 21 12:37:08 PM PST 24
Peak memory 198492 kb
Host smart-0600b097-011c-4de1-be53-b18f597fdc63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277429804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4277429804
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3501304553
Short name T1257
Test name
Test status
Simulation time 19092913 ps
CPU time 0.74 seconds
Started Jan 21 12:45:53 PM PST 24
Finished Jan 21 12:45:56 PM PST 24
Peak memory 197404 kb
Host smart-defe1868-7b59-4181-870c-a015ebf8cd62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501304553 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3501304553
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3612714329
Short name T1259
Test name
Test status
Simulation time 16053238 ps
CPU time 0.6 seconds
Started Jan 21 01:06:38 PM PST 24
Finished Jan 21 01:06:39 PM PST 24
Peak memory 195260 kb
Host smart-5b3d1871-6fa7-4175-a62b-6f36f3ef1db8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612714329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3612714329
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2784887214
Short name T1251
Test name
Test status
Simulation time 38765766 ps
CPU time 0.59 seconds
Started Jan 21 01:01:35 PM PST 24
Finished Jan 21 01:01:37 PM PST 24
Peak memory 194144 kb
Host smart-26d53179-f822-498c-8ebe-f1670825f19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784887214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2784887214
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.967946638
Short name T1243
Test name
Test status
Simulation time 66152137 ps
CPU time 0.84 seconds
Started Jan 21 12:58:06 PM PST 24
Finished Jan 21 12:58:08 PM PST 24
Peak memory 196532 kb
Host smart-8e9ef90e-6a7d-4adc-a1bd-4439d1d8c4f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967946638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.967946638
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1739963426
Short name T48
Test name
Test status
Simulation time 52333505 ps
CPU time 1.32 seconds
Started Jan 21 01:20:36 PM PST 24
Finished Jan 21 01:20:39 PM PST 24
Peak memory 199708 kb
Host smart-f0668d82-0b70-44f7-8478-f9a27c9a0cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739963426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1739963426
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.508974134
Short name T395
Test name
Test status
Simulation time 137586788 ps
CPU time 0.92 seconds
Started Jan 21 12:29:40 PM PST 24
Finished Jan 21 12:29:46 PM PST 24
Peak memory 198388 kb
Host smart-98e5e4ac-387a-4ddc-9644-5cdfdd04dafb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508974134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.508974134
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.951972603
Short name T489
Test name
Test status
Simulation time 24534640 ps
CPU time 0.73 seconds
Started Jan 21 01:34:41 PM PST 24
Finished Jan 21 01:34:43 PM PST 24
Peak memory 197612 kb
Host smart-e0678074-dd9a-411b-a5ce-72b8bf50c00c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951972603 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.951972603
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3088680358
Short name T75
Test name
Test status
Simulation time 46462445 ps
CPU time 0.65 seconds
Started Jan 21 12:22:43 PM PST 24
Finished Jan 21 12:22:44 PM PST 24
Peak memory 195228 kb
Host smart-50e51789-521a-4a9f-bfdc-70d71e341c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088680358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3088680358
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1830542883
Short name T462
Test name
Test status
Simulation time 39687423 ps
CPU time 0.53 seconds
Started Jan 21 12:25:01 PM PST 24
Finished Jan 21 12:25:03 PM PST 24
Peak memory 193872 kb
Host smart-1685a2cf-3478-4280-b078-6582d2a7564a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830542883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1830542883
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1893419526
Short name T1247
Test name
Test status
Simulation time 26959120 ps
CPU time 0.73 seconds
Started Jan 21 12:28:50 PM PST 24
Finished Jan 21 12:28:52 PM PST 24
Peak memory 196540 kb
Host smart-2d4c6560-9d4d-4bf5-aacf-5bcc7e3c1043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893419526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1893419526
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3463413729
Short name T457
Test name
Test status
Simulation time 40397374 ps
CPU time 2.06 seconds
Started Jan 21 12:54:51 PM PST 24
Finished Jan 21 12:54:54 PM PST 24
Peak memory 199552 kb
Host smart-c13ad76f-8f1e-4175-bf3e-ea78ba4c08fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463413729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3463413729
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4185995206
Short name T44
Test name
Test status
Simulation time 159290336 ps
CPU time 1.26 seconds
Started Jan 21 12:24:50 PM PST 24
Finished Jan 21 12:24:53 PM PST 24
Peak memory 198744 kb
Host smart-5b982dc3-c233-45b1-9ffe-7c97f959ecc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185995206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4185995206
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2806027573
Short name T97
Test name
Test status
Simulation time 20257980 ps
CPU time 0.74 seconds
Started Jan 21 01:30:21 PM PST 24
Finished Jan 21 01:30:22 PM PST 24
Peak memory 197432 kb
Host smart-ac9581b7-7267-4d64-8ccd-a2116122649e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806027573 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2806027573
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3795298084
Short name T53
Test name
Test status
Simulation time 35690174 ps
CPU time 0.62 seconds
Started Jan 21 12:40:26 PM PST 24
Finished Jan 21 12:40:27 PM PST 24
Peak memory 195164 kb
Host smart-8820bb78-4a75-4235-a0ef-d9a09ccc95bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795298084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3795298084
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1148721723
Short name T1250
Test name
Test status
Simulation time 32813538 ps
CPU time 0.58 seconds
Started Jan 21 01:10:08 PM PST 24
Finished Jan 21 01:10:10 PM PST 24
Peak memory 184960 kb
Host smart-7c60dbeb-3e9b-4438-abc8-e5c611766183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148721723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1148721723
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1701818861
Short name T467
Test name
Test status
Simulation time 16159548 ps
CPU time 0.7 seconds
Started Jan 21 02:00:56 PM PST 24
Finished Jan 21 02:00:58 PM PST 24
Peak memory 196732 kb
Host smart-743ac764-edc9-4953-8692-2a41bce8e1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701818861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1701818861
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3522005401
Short name T480
Test name
Test status
Simulation time 415737251 ps
CPU time 2.13 seconds
Started Jan 21 12:24:35 PM PST 24
Finished Jan 21 12:24:39 PM PST 24
Peak memory 198336 kb
Host smart-35771b20-0266-4a63-b748-0c00333ddfea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522005401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3522005401
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.677573067
Short name T396
Test name
Test status
Simulation time 102028959 ps
CPU time 1.34 seconds
Started Jan 21 12:47:47 PM PST 24
Finished Jan 21 12:47:50 PM PST 24
Peak memory 198772 kb
Host smart-cac921a3-232c-4d3c-8b7b-25bdfadc187c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677573067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.677573067
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3607567296
Short name T1026
Test name
Test status
Simulation time 54856095556 ps
CPU time 88.83 seconds
Started Jan 21 01:24:29 PM PST 24
Finished Jan 21 01:25:59 PM PST 24
Peak memory 199924 kb
Host smart-a3683b98-635e-4a5e-82d3-d3a45ea2e6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607567296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3607567296
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2876126183
Short name T966
Test name
Test status
Simulation time 44033073351 ps
CPU time 70.52 seconds
Started Jan 21 01:24:41 PM PST 24
Finished Jan 21 01:25:54 PM PST 24
Peak memory 199984 kb
Host smart-749b9528-a223-44d9-97ed-c2ffdf76b799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876126183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2876126183
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.71173017
Short name T27
Test name
Test status
Simulation time 231584615961 ps
CPU time 110.96 seconds
Started Jan 21 01:24:40 PM PST 24
Finished Jan 21 01:26:35 PM PST 24
Peak memory 199844 kb
Host smart-a8058636-8445-44fc-96a8-eb5aca5bb141
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71173017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.71173017
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3224014903
Short name T621
Test name
Test status
Simulation time 117675458391 ps
CPU time 102.81 seconds
Started Jan 21 01:24:40 PM PST 24
Finished Jan 21 01:26:27 PM PST 24
Peak memory 200044 kb
Host smart-a2a0c3c3-1234-41cb-88f4-5226decbf812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224014903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3224014903
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1061965205
Short name T30
Test name
Test status
Simulation time 10716528439 ps
CPU time 22.85 seconds
Started Jan 21 01:24:41 PM PST 24
Finished Jan 21 01:25:07 PM PST 24
Peak memory 198568 kb
Host smart-c89e8d09-4f2d-4549-957c-90930f35b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061965205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1061965205
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4049402260
Short name T780
Test name
Test status
Simulation time 178858780726 ps
CPU time 53.3 seconds
Started Jan 21 01:24:40 PM PST 24
Finished Jan 21 01:25:37 PM PST 24
Peak memory 208360 kb
Host smart-d6411972-2244-4a24-a9cc-1fa016fb0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049402260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4049402260
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1155230738
Short name T963
Test name
Test status
Simulation time 10899393523 ps
CPU time 295.05 seconds
Started Jan 21 01:24:41 PM PST 24
Finished Jan 21 01:29:39 PM PST 24
Peak memory 199900 kb
Host smart-7dd3690b-c263-4d08-ab1c-b6ca4fbf5e6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1155230738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1155230738
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3237713700
Short name T575
Test name
Test status
Simulation time 174340890722 ps
CPU time 61.48 seconds
Started Jan 21 01:24:40 PM PST 24
Finished Jan 21 01:25:45 PM PST 24
Peak memory 200016 kb
Host smart-37486cd5-16c7-4a6e-8581-e34dae1cceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237713700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3237713700
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1806652566
Short name T659
Test name
Test status
Simulation time 52343351232 ps
CPU time 22.13 seconds
Started Jan 21 01:24:40 PM PST 24
Finished Jan 21 01:25:06 PM PST 24
Peak memory 195544 kb
Host smart-3c60ef3b-5daa-490e-a36c-a3d4cfa30be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806652566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1806652566
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1641380600
Short name T90
Test name
Test status
Simulation time 64962475 ps
CPU time 0.84 seconds
Started Jan 21 01:24:40 PM PST 24
Finished Jan 21 01:24:45 PM PST 24
Peak memory 217164 kb
Host smart-dec5fc44-d0a1-4eb0-abc8-da27aabcd4ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641380600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1641380600
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2141790636
Short name T691
Test name
Test status
Simulation time 667655243 ps
CPU time 2.99 seconds
Started Jan 21 01:24:28 PM PST 24
Finished Jan 21 01:24:32 PM PST 24
Peak memory 198796 kb
Host smart-9dd74253-e140-4a47-ae01-e4c11a50b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141790636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2141790636
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4018166451
Short name T69
Test name
Test status
Simulation time 46032479440 ps
CPU time 417.52 seconds
Started Jan 21 01:24:40 PM PST 24
Finished Jan 21 01:31:41 PM PST 24
Peak memory 222580 kb
Host smart-9b00705a-8157-4fe1-8676-61c947df8899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018166451 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4018166451
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1036619888
Short name T964
Test name
Test status
Simulation time 9727749826 ps
CPU time 6.49 seconds
Started Jan 21 01:24:39 PM PST 24
Finished Jan 21 01:24:50 PM PST 24
Peak memory 199288 kb
Host smart-2b427f65-75c4-4110-815e-dbacc53ab7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036619888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1036619888
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3268040078
Short name T692
Test name
Test status
Simulation time 42763485388 ps
CPU time 76.24 seconds
Started Jan 21 01:24:29 PM PST 24
Finished Jan 21 01:25:46 PM PST 24
Peak memory 199940 kb
Host smart-04cbd3d9-65e2-4746-a3bd-68722390fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268040078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3268040078
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3594566941
Short name T535
Test name
Test status
Simulation time 13631821 ps
CPU time 0.55 seconds
Started Jan 21 01:25:34 PM PST 24
Finished Jan 21 01:25:35 PM PST 24
Peak memory 194632 kb
Host smart-ab35e7ca-0145-44ef-abc6-9ba2234a9819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594566941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3594566941
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1356086080
Short name T572
Test name
Test status
Simulation time 139637327941 ps
CPU time 110.88 seconds
Started Jan 21 01:24:59 PM PST 24
Finished Jan 21 01:26:52 PM PST 24
Peak memory 199928 kb
Host smart-23670c93-b3ee-4e19-947b-7abc403ac800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356086080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1356086080
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1904850900
Short name T634
Test name
Test status
Simulation time 51951575510 ps
CPU time 23.55 seconds
Started Jan 21 01:24:57 PM PST 24
Finished Jan 21 01:25:24 PM PST 24
Peak memory 197952 kb
Host smart-6a0d65e5-a8a3-4a47-829d-e09bc1199517
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904850900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1904850900
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1806775876
Short name T606
Test name
Test status
Simulation time 88744997274 ps
CPU time 484.96 seconds
Started Jan 21 01:50:02 PM PST 24
Finished Jan 21 01:58:08 PM PST 24
Peak memory 199956 kb
Host smart-165c28e2-2a02-4b15-a88c-52fcbd9ce98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1806775876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1806775876
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2655729367
Short name T532
Test name
Test status
Simulation time 7259288333 ps
CPU time 2.87 seconds
Started Jan 21 01:25:19 PM PST 24
Finished Jan 21 01:25:23 PM PST 24
Peak memory 198548 kb
Host smart-7debccba-d0c8-42d9-be91-b89c54aaae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655729367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2655729367
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2782205010
Short name T430
Test name
Test status
Simulation time 40728955818 ps
CPU time 66.6 seconds
Started Jan 21 01:24:57 PM PST 24
Finished Jan 21 01:26:07 PM PST 24
Peak memory 200288 kb
Host smart-5e860133-3182-43a9-8720-6e9d01390567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782205010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2782205010
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2354374720
Short name T664
Test name
Test status
Simulation time 9420254835 ps
CPU time 226.27 seconds
Started Jan 21 01:42:23 PM PST 24
Finished Jan 21 01:46:11 PM PST 24
Peak memory 199948 kb
Host smart-b3c0bf7c-34e5-4d43-946a-41cb4de1cdea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354374720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2354374720
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.825726172
Short name T806
Test name
Test status
Simulation time 1608943002 ps
CPU time 5.65 seconds
Started Jan 21 01:24:57 PM PST 24
Finished Jan 21 01:25:06 PM PST 24
Peak memory 198108 kb
Host smart-17ad3ffa-06c7-4051-8e8e-2b55a708335e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825726172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.825726172
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4153696924
Short name T368
Test name
Test status
Simulation time 128237886020 ps
CPU time 26.6 seconds
Started Jan 21 01:25:06 PM PST 24
Finished Jan 21 01:25:38 PM PST 24
Peak memory 200032 kb
Host smart-88663943-9a7b-474b-a96a-f80605d9dd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153696924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4153696924
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.927368731
Short name T1172
Test name
Test status
Simulation time 6054055882 ps
CPU time 3.03 seconds
Started Jan 21 01:25:04 PM PST 24
Finished Jan 21 01:25:08 PM PST 24
Peak memory 195436 kb
Host smart-83a46308-3513-47db-ab38-c123c14bfdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927368731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.927368731
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1405997316
Short name T80
Test name
Test status
Simulation time 107217185 ps
CPU time 0.77 seconds
Started Jan 21 01:25:34 PM PST 24
Finished Jan 21 01:25:35 PM PST 24
Peak memory 217112 kb
Host smart-88aa0bad-6215-45a4-83b1-8bb692646d1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405997316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1405997316
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4032484216
Short name T905
Test name
Test status
Simulation time 5562043414 ps
CPU time 7.15 seconds
Started Jan 21 01:24:50 PM PST 24
Finished Jan 21 01:24:58 PM PST 24
Peak memory 199324 kb
Host smart-fa1fc2fa-aab9-43ec-bd27-1f954d8fae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032484216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4032484216
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2584568219
Short name T24
Test name
Test status
Simulation time 721386588388 ps
CPU time 457.34 seconds
Started Jan 21 01:32:47 PM PST 24
Finished Jan 21 01:40:29 PM PST 24
Peak memory 200000 kb
Host smart-09c331f3-4491-4fab-ac98-e1b22537c638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584568219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2584568219
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3420912710
Short name T1201
Test name
Test status
Simulation time 32479703312 ps
CPU time 396.56 seconds
Started Jan 21 01:50:58 PM PST 24
Finished Jan 21 01:57:36 PM PST 24
Peak memory 215820 kb
Host smart-e7560e11-a4aa-415b-8796-6ec646dcf69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420912710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3420912710
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2764108575
Short name T1137
Test name
Test status
Simulation time 8576125323 ps
CPU time 9.41 seconds
Started Jan 21 02:18:26 PM PST 24
Finished Jan 21 02:18:37 PM PST 24
Peak memory 199980 kb
Host smart-fe7dd233-df69-4af1-ba75-5750fa318460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764108575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2764108575
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2069521281
Short name T1203
Test name
Test status
Simulation time 111963102427 ps
CPU time 117.96 seconds
Started Jan 21 01:24:49 PM PST 24
Finished Jan 21 01:26:48 PM PST 24
Peak memory 200020 kb
Host smart-85f605f6-5b04-49d1-9126-2caf3bc3b3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069521281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2069521281
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.649362902
Short name T531
Test name
Test status
Simulation time 36410206 ps
CPU time 0.55 seconds
Started Jan 21 01:29:14 PM PST 24
Finished Jan 21 01:29:15 PM PST 24
Peak memory 195612 kb
Host smart-387285c0-cf35-4414-81e9-06d4f08111bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649362902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.649362902
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.761230820
Short name T414
Test name
Test status
Simulation time 123427198379 ps
CPU time 203.22 seconds
Started Jan 21 01:29:02 PM PST 24
Finished Jan 21 01:32:27 PM PST 24
Peak memory 199948 kb
Host smart-da205d76-1ebc-48ae-9970-489e7f3e342a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761230820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.761230820
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_intr.1944171520
Short name T580
Test name
Test status
Simulation time 187544374915 ps
CPU time 136.23 seconds
Started Jan 21 01:29:02 PM PST 24
Finished Jan 21 01:31:20 PM PST 24
Peak memory 199296 kb
Host smart-66e91218-9776-496f-aa54-1d9d36fac089
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944171520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1944171520
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2990748321
Short name T623
Test name
Test status
Simulation time 90050513542 ps
CPU time 200.71 seconds
Started Jan 21 01:29:13 PM PST 24
Finished Jan 21 01:32:35 PM PST 24
Peak memory 199924 kb
Host smart-8b0acc77-d240-4a86-8f92-3b3f8cb22a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990748321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2990748321
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1188944769
Short name T1071
Test name
Test status
Simulation time 10102175418 ps
CPU time 6.75 seconds
Started Jan 21 01:29:13 PM PST 24
Finished Jan 21 01:29:21 PM PST 24
Peak memory 199916 kb
Host smart-bfb50489-c122-4ba6-ae77-32630b2f90da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188944769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1188944769
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3990586221
Short name T513
Test name
Test status
Simulation time 47925900138 ps
CPU time 27.95 seconds
Started Jan 21 01:29:03 PM PST 24
Finished Jan 21 01:29:32 PM PST 24
Peak memory 198672 kb
Host smart-6f2d812e-2c13-45b0-81a5-41e23d750e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990586221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3990586221
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.901618838
Short name T1128
Test name
Test status
Simulation time 16158157656 ps
CPU time 761.19 seconds
Started Jan 21 01:29:11 PM PST 24
Finished Jan 21 01:41:53 PM PST 24
Peak memory 199928 kb
Host smart-0b5a8cbb-c0b4-4109-8ffd-8c3c24af444d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901618838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.901618838
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1879614505
Short name T492
Test name
Test status
Simulation time 159908372 ps
CPU time 1.04 seconds
Started Jan 21 01:28:56 PM PST 24
Finished Jan 21 01:28:58 PM PST 24
Peak memory 197720 kb
Host smart-ff2361de-d4c1-4420-ac68-61a996791c74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879614505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1879614505
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3410582613
Short name T520
Test name
Test status
Simulation time 4206286436 ps
CPU time 1.46 seconds
Started Jan 21 02:09:42 PM PST 24
Finished Jan 21 02:09:48 PM PST 24
Peak memory 195580 kb
Host smart-19682be4-299f-4308-ab6b-56197fac7b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410582613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3410582613
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3899574888
Short name T435
Test name
Test status
Simulation time 6255813885 ps
CPU time 8.7 seconds
Started Jan 21 01:28:58 PM PST 24
Finished Jan 21 01:29:07 PM PST 24
Peak memory 199296 kb
Host smart-a92c865f-2fe3-4a67-b282-9ae28a1c1cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899574888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3899574888
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2961214597
Short name T579
Test name
Test status
Simulation time 1598791544558 ps
CPU time 415.47 seconds
Started Jan 21 01:29:14 PM PST 24
Finished Jan 21 01:36:10 PM PST 24
Peak memory 199956 kb
Host smart-18b4b727-e300-4239-90a6-43b6b5f3528b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961214597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2961214597
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1585513921
Short name T825
Test name
Test status
Simulation time 53342593731 ps
CPU time 120.18 seconds
Started Jan 21 01:29:14 PM PST 24
Finished Jan 21 01:31:15 PM PST 24
Peak memory 209568 kb
Host smart-cf638442-2b1d-4620-93ff-a1512bb11a88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585513921 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1585513921
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.497307598
Short name T840
Test name
Test status
Simulation time 841413572 ps
CPU time 3.89 seconds
Started Jan 21 01:29:15 PM PST 24
Finished Jan 21 01:29:19 PM PST 24
Peak memory 198844 kb
Host smart-4a969810-dad5-476d-9c51-e5010b27541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497307598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.497307598
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.562152545
Short name T1117
Test name
Test status
Simulation time 23622931546 ps
CPU time 36.82 seconds
Started Jan 21 01:28:55 PM PST 24
Finished Jan 21 01:29:33 PM PST 24
Peak memory 199808 kb
Host smart-69e07e79-c6d8-443f-a9fb-cb7befd13c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562152545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.562152545
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.136700689
Short name T299
Test name
Test status
Simulation time 123749928847 ps
CPU time 46.87 seconds
Started Jan 21 01:42:40 PM PST 24
Finished Jan 21 01:43:28 PM PST 24
Peak memory 199960 kb
Host smart-4a5255cb-7753-46dc-89e9-2018998f98b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136700689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.136700689
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1363958651
Short name T112
Test name
Test status
Simulation time 153218294779 ps
CPU time 94.62 seconds
Started Jan 21 01:42:40 PM PST 24
Finished Jan 21 01:44:15 PM PST 24
Peak memory 199912 kb
Host smart-44409252-88b8-4048-b3d0-b3a86981f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363958651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1363958651
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2970733077
Short name T334
Test name
Test status
Simulation time 26148626484 ps
CPU time 11.39 seconds
Started Jan 21 01:42:51 PM PST 24
Finished Jan 21 01:43:03 PM PST 24
Peak memory 200032 kb
Host smart-6b52519e-254b-463e-a59d-ef25becef05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970733077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2970733077
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1734235337
Short name T380
Test name
Test status
Simulation time 66130990996 ps
CPU time 65.38 seconds
Started Jan 21 01:42:49 PM PST 24
Finished Jan 21 01:43:55 PM PST 24
Peak memory 199864 kb
Host smart-60fed9c9-9a15-4d17-a3e0-86de410c1133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734235337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1734235337
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3130030341
Short name T662
Test name
Test status
Simulation time 16669180446 ps
CPU time 14.91 seconds
Started Jan 21 02:12:20 PM PST 24
Finished Jan 21 02:12:36 PM PST 24
Peak memory 199620 kb
Host smart-85813328-0511-4676-96e4-fae611ed2056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130030341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3130030341
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.107216761
Short name T645
Test name
Test status
Simulation time 63421481199 ps
CPU time 112.21 seconds
Started Jan 21 01:43:01 PM PST 24
Finished Jan 21 01:44:54 PM PST 24
Peak memory 199984 kb
Host smart-9749fa3e-32df-4cd9-a8f9-87d2ff9eea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107216761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.107216761
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2291822575
Short name T1225
Test name
Test status
Simulation time 114135488274 ps
CPU time 258.07 seconds
Started Jan 21 01:42:59 PM PST 24
Finished Jan 21 01:47:18 PM PST 24
Peak memory 199752 kb
Host smart-744ccd12-afe8-45b5-b389-a41069ffc02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291822575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2291822575
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1015787915
Short name T861
Test name
Test status
Simulation time 90936162482 ps
CPU time 34.74 seconds
Started Jan 21 01:43:02 PM PST 24
Finished Jan 21 01:43:37 PM PST 24
Peak memory 199996 kb
Host smart-a2f7ae9c-b78e-4bab-be5e-67a87aba69f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015787915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1015787915
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2953942173
Short name T522
Test name
Test status
Simulation time 30928308 ps
CPU time 0.55 seconds
Started Jan 21 01:29:32 PM PST 24
Finished Jan 21 01:29:33 PM PST 24
Peak memory 195644 kb
Host smart-b34d648e-4f99-4441-b287-f7cea7accaed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953942173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2953942173
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1713991024
Short name T856
Test name
Test status
Simulation time 107895073489 ps
CPU time 79.29 seconds
Started Jan 21 01:29:21 PM PST 24
Finished Jan 21 01:30:41 PM PST 24
Peak memory 199924 kb
Host smart-6bf5d388-f499-4894-a1f2-37cd9575ae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713991024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1713991024
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3403960340
Short name T1164
Test name
Test status
Simulation time 114757145667 ps
CPU time 169.27 seconds
Started Jan 21 01:29:23 PM PST 24
Finished Jan 21 01:32:13 PM PST 24
Peak memory 199412 kb
Host smart-c57f3e53-c1f8-4f2f-966a-806d947acf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403960340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3403960340
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2734715492
Short name T766
Test name
Test status
Simulation time 16028433297 ps
CPU time 27.78 seconds
Started Jan 21 01:29:24 PM PST 24
Finished Jan 21 01:29:53 PM PST 24
Peak memory 199444 kb
Host smart-55973c50-82e0-4375-a58f-b5d09bae6013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734715492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2734715492
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2361978435
Short name T434
Test name
Test status
Simulation time 1741510826771 ps
CPU time 2682.67 seconds
Started Jan 21 01:29:24 PM PST 24
Finished Jan 21 02:14:07 PM PST 24
Peak memory 199996 kb
Host smart-9112752f-a4f4-4d00-939a-69d105ac4abb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361978435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2361978435
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4234213378
Short name T592
Test name
Test status
Simulation time 49087800597 ps
CPU time 247.5 seconds
Started Jan 21 01:29:36 PM PST 24
Finished Jan 21 01:33:44 PM PST 24
Peak memory 199992 kb
Host smart-ea02ee3f-1775-4816-8007-b06801ffe9a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234213378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4234213378
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1926554501
Short name T1221
Test name
Test status
Simulation time 554674832 ps
CPU time 1.44 seconds
Started Jan 21 01:29:22 PM PST 24
Finished Jan 21 01:29:24 PM PST 24
Peak memory 195432 kb
Host smart-bea96e0d-e00e-4a61-bdb5-2728db8f29e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926554501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1926554501
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3456065709
Short name T822
Test name
Test status
Simulation time 6614336022 ps
CPU time 3.24 seconds
Started Jan 21 01:29:23 PM PST 24
Finished Jan 21 01:29:27 PM PST 24
Peak memory 193700 kb
Host smart-0a6f78e6-48bf-4bb0-861f-cb32d97cc561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456065709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3456065709
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1906478066
Short name T401
Test name
Test status
Simulation time 28764715877 ps
CPU time 149.45 seconds
Started Jan 21 01:29:33 PM PST 24
Finished Jan 21 01:32:03 PM PST 24
Peak memory 199996 kb
Host smart-eef850db-7c17-4eca-83cf-d6dfd5b967d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906478066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1906478066
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4040119025
Short name T555
Test name
Test status
Simulation time 132814929 ps
CPU time 0.77 seconds
Started Jan 21 01:29:21 PM PST 24
Finished Jan 21 01:29:23 PM PST 24
Peak memory 195404 kb
Host smart-b031d3b2-d866-4837-b669-2582b23f1321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040119025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4040119025
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4063275989
Short name T410
Test name
Test status
Simulation time 4686142591 ps
CPU time 8.72 seconds
Started Jan 21 01:29:22 PM PST 24
Finished Jan 21 01:29:31 PM PST 24
Peak memory 195784 kb
Host smart-e579dcd4-0f14-4166-9a45-01c1d4aad4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063275989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4063275989
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.65118297
Short name T851
Test name
Test status
Simulation time 282811726 ps
CPU time 1.69 seconds
Started Jan 21 01:29:13 PM PST 24
Finished Jan 21 01:29:16 PM PST 24
Peak memory 198348 kb
Host smart-4ec9a419-3129-46ab-9d6c-f1661fff77a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65118297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.65118297
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2136599435
Short name T272
Test name
Test status
Simulation time 315221616101 ps
CPU time 70.09 seconds
Started Jan 21 01:29:32 PM PST 24
Finished Jan 21 01:30:43 PM PST 24
Peak memory 199916 kb
Host smart-246809f3-e6c5-4314-be81-bc9ccfae826d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136599435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2136599435
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2249312032
Short name T983
Test name
Test status
Simulation time 1719595248 ps
CPU time 3.02 seconds
Started Jan 21 01:29:21 PM PST 24
Finished Jan 21 01:29:25 PM PST 24
Peak memory 198528 kb
Host smart-400647a6-864e-4ab6-87dd-60c2cf63772c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249312032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2249312032
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.400223198
Short name T737
Test name
Test status
Simulation time 140411930075 ps
CPU time 34.62 seconds
Started Jan 21 01:41:16 PM PST 24
Finished Jan 21 01:41:51 PM PST 24
Peak memory 199916 kb
Host smart-5d07f721-d4c3-4002-bbe3-8ec7360b903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400223198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.400223198
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1332595129
Short name T303
Test name
Test status
Simulation time 86358071741 ps
CPU time 132.25 seconds
Started Jan 21 01:42:59 PM PST 24
Finished Jan 21 01:45:12 PM PST 24
Peak memory 199984 kb
Host smart-b1b83e92-a8f9-44cb-94b5-fab7cad1aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332595129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1332595129
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2265471509
Short name T658
Test name
Test status
Simulation time 83639606820 ps
CPU time 34.15 seconds
Started Jan 21 01:43:05 PM PST 24
Finished Jan 21 01:43:39 PM PST 24
Peak memory 199992 kb
Host smart-984d3d55-b74d-46ea-af4b-9b4e08fcbe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265471509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2265471509
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1704618121
Short name T127
Test name
Test status
Simulation time 121457552119 ps
CPU time 195.12 seconds
Started Jan 21 01:43:08 PM PST 24
Finished Jan 21 01:46:24 PM PST 24
Peak memory 199916 kb
Host smart-5a7b6b09-ac0d-49b5-a0fc-e93bd66f1c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704618121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1704618121
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.4097033717
Short name T249
Test name
Test status
Simulation time 42595849954 ps
CPU time 99.46 seconds
Started Jan 21 01:43:07 PM PST 24
Finished Jan 21 01:44:47 PM PST 24
Peak memory 199892 kb
Host smart-5b0bc358-2c85-4be4-a60f-d448215aba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097033717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.4097033717
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2234658214
Short name T345
Test name
Test status
Simulation time 176166016477 ps
CPU time 72.95 seconds
Started Jan 21 01:43:10 PM PST 24
Finished Jan 21 01:44:24 PM PST 24
Peak memory 199984 kb
Host smart-f17c504e-a121-44fd-8cdc-b761b55e646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234658214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2234658214
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.157626482
Short name T573
Test name
Test status
Simulation time 6209936932 ps
CPU time 10.24 seconds
Started Jan 21 01:43:17 PM PST 24
Finished Jan 21 01:43:27 PM PST 24
Peak memory 198120 kb
Host smart-94ce0662-5577-400e-bfc3-68a51b1d0c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157626482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.157626482
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3406284996
Short name T1095
Test name
Test status
Simulation time 30913246386 ps
CPU time 51.97 seconds
Started Jan 21 03:48:40 PM PST 24
Finished Jan 21 03:49:32 PM PST 24
Peak memory 199960 kb
Host smart-101eb060-cb7a-41a8-a90b-6d653b12694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406284996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3406284996
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3563461883
Short name T751
Test name
Test status
Simulation time 44899681 ps
CPU time 0.56 seconds
Started Jan 21 01:29:53 PM PST 24
Finished Jan 21 01:29:56 PM PST 24
Peak memory 195644 kb
Host smart-f9d28024-00e1-4dbb-9be8-ab223e1aa1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563461883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3563461883
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2168640773
Short name T887
Test name
Test status
Simulation time 58856804788 ps
CPU time 25.49 seconds
Started Jan 21 01:29:32 PM PST 24
Finished Jan 21 01:29:58 PM PST 24
Peak memory 200000 kb
Host smart-d39d58c2-2c8a-47fc-bd0b-53c2ff8b2c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168640773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2168640773
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.806665078
Short name T948
Test name
Test status
Simulation time 22506824310 ps
CPU time 35.01 seconds
Started Jan 21 01:29:46 PM PST 24
Finished Jan 21 01:30:26 PM PST 24
Peak memory 199900 kb
Host smart-d533759c-9025-4258-967a-b26603240046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806665078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.806665078
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.183629780
Short name T1013
Test name
Test status
Simulation time 104793883910 ps
CPU time 83.8 seconds
Started Jan 21 01:29:44 PM PST 24
Finished Jan 21 01:31:09 PM PST 24
Peak memory 199980 kb
Host smart-c2310d95-3183-4a0c-9b93-532a96ef9ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183629780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.183629780
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1625826493
Short name T916
Test name
Test status
Simulation time 220809008683 ps
CPU time 216.94 seconds
Started Jan 21 01:29:45 PM PST 24
Finished Jan 21 01:33:27 PM PST 24
Peak memory 198804 kb
Host smart-6b730f11-ceb0-45c0-8625-8e0090a61501
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625826493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1625826493
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2171640136
Short name T418
Test name
Test status
Simulation time 107906483679 ps
CPU time 702.83 seconds
Started Jan 21 01:29:54 PM PST 24
Finished Jan 21 01:41:38 PM PST 24
Peak memory 200032 kb
Host smart-47f8031d-c853-47e4-89bc-f381819821cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171640136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2171640136
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2512363879
Short name T500
Test name
Test status
Simulation time 106829546 ps
CPU time 0.57 seconds
Started Jan 21 01:29:45 PM PST 24
Finished Jan 21 01:29:51 PM PST 24
Peak memory 195364 kb
Host smart-97fb34d1-60a8-43bc-b619-9453da920806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512363879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2512363879
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.4208316999
Short name T109
Test name
Test status
Simulation time 158008204628 ps
CPU time 71.04 seconds
Started Jan 21 01:29:43 PM PST 24
Finished Jan 21 01:30:56 PM PST 24
Peak memory 200076 kb
Host smart-a3e5e989-bb66-4d42-ab49-5ec3b04c0f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208316999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.4208316999
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3618831429
Short name T1046
Test name
Test status
Simulation time 25595665460 ps
CPU time 1246.44 seconds
Started Jan 21 01:52:35 PM PST 24
Finished Jan 21 02:13:32 PM PST 24
Peak memory 200048 kb
Host smart-0b77f82d-0d71-44e1-8310-2a1b2b70ab86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618831429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3618831429
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4136781915
Short name T715
Test name
Test status
Simulation time 1616563028 ps
CPU time 1.85 seconds
Started Jan 21 01:29:48 PM PST 24
Finished Jan 21 01:29:53 PM PST 24
Peak memory 197876 kb
Host smart-9d0068ac-99bc-4626-8181-1ea7a8921e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136781915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4136781915
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2439506845
Short name T727
Test name
Test status
Simulation time 258576071488 ps
CPU time 27.58 seconds
Started Jan 21 01:29:45 PM PST 24
Finished Jan 21 01:30:18 PM PST 24
Peak memory 199936 kb
Host smart-b61e1c19-c092-404a-ba62-28ea8a5059bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439506845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2439506845
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1318516039
Short name T982
Test name
Test status
Simulation time 4607508927 ps
CPU time 8.75 seconds
Started Jan 21 02:25:18 PM PST 24
Finished Jan 21 02:25:28 PM PST 24
Peak memory 195580 kb
Host smart-36d20a36-f680-47c6-8edb-edaf6a4fceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318516039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1318516039
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3222802184
Short name T821
Test name
Test status
Simulation time 486128960 ps
CPU time 2.19 seconds
Started Jan 21 01:29:33 PM PST 24
Finished Jan 21 01:29:36 PM PST 24
Peak memory 197764 kb
Host smart-d9055ebd-eb33-4283-b680-834aebc6830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222802184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3222802184
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1492082491
Short name T1103
Test name
Test status
Simulation time 108057037192 ps
CPU time 1355.77 seconds
Started Jan 21 01:29:53 PM PST 24
Finished Jan 21 01:52:31 PM PST 24
Peak memory 200240 kb
Host smart-93cf240c-f095-40ff-8869-0964b7e81ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492082491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1492082491
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1613581003
Short name T702
Test name
Test status
Simulation time 69725211183 ps
CPU time 222.71 seconds
Started Jan 21 01:29:53 PM PST 24
Finished Jan 21 01:33:38 PM PST 24
Peak memory 208392 kb
Host smart-9658753e-c008-459a-8314-9222b7ccc644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613581003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1613581003
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.984888264
Short name T1055
Test name
Test status
Simulation time 1199020508 ps
CPU time 3.42 seconds
Started Jan 21 02:19:50 PM PST 24
Finished Jan 21 02:19:54 PM PST 24
Peak memory 199024 kb
Host smart-668d42d6-3143-4a83-9ba8-e5bf68d02529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984888264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.984888264
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.552592138
Short name T802
Test name
Test status
Simulation time 74364721871 ps
CPU time 127.83 seconds
Started Jan 21 01:29:33 PM PST 24
Finished Jan 21 01:31:41 PM PST 24
Peak memory 200052 kb
Host smart-18710007-b455-4238-a71a-6a50f45e2bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552592138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.552592138
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3659950820
Short name T1072
Test name
Test status
Simulation time 134300318170 ps
CPU time 77.17 seconds
Started Jan 21 01:43:17 PM PST 24
Finished Jan 21 01:44:35 PM PST 24
Peak memory 199932 kb
Host smart-01e54d31-2297-4702-b576-9b87cf666104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659950820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3659950820
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3216106464
Short name T923
Test name
Test status
Simulation time 15180855182 ps
CPU time 23.39 seconds
Started Jan 21 02:04:15 PM PST 24
Finished Jan 21 02:04:41 PM PST 24
Peak memory 199288 kb
Host smart-2daa21ba-a3b9-499d-b8af-1713df644b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216106464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3216106464
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1437320379
Short name T681
Test name
Test status
Simulation time 15409640523 ps
CPU time 15.34 seconds
Started Jan 21 02:21:14 PM PST 24
Finished Jan 21 02:21:31 PM PST 24
Peak memory 199992 kb
Host smart-6fbc540a-5fe4-4b58-96e6-0af27e866aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437320379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1437320379
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2440358328
Short name T257
Test name
Test status
Simulation time 5302919794 ps
CPU time 9.95 seconds
Started Jan 21 01:43:19 PM PST 24
Finished Jan 21 01:43:29 PM PST 24
Peak memory 199996 kb
Host smart-860c94a0-cf61-4b1b-a74a-96b4a38dea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440358328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2440358328
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1021976541
Short name T1115
Test name
Test status
Simulation time 12470665716 ps
CPU time 14.5 seconds
Started Jan 21 02:20:31 PM PST 24
Finished Jan 21 02:20:46 PM PST 24
Peak memory 198784 kb
Host smart-6cc21a34-ab6e-4e7d-bef9-fb2dcdd6343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021976541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1021976541
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2976771640
Short name T314
Test name
Test status
Simulation time 238891600636 ps
CPU time 103.47 seconds
Started Jan 21 01:43:18 PM PST 24
Finished Jan 21 01:45:02 PM PST 24
Peak memory 199960 kb
Host smart-aefc80a2-5832-4d4b-a033-0677ab94d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976771640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2976771640
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3753079313
Short name T336
Test name
Test status
Simulation time 89778679630 ps
CPU time 32.32 seconds
Started Jan 21 02:23:29 PM PST 24
Finished Jan 21 02:24:05 PM PST 24
Peak memory 199948 kb
Host smart-c580490a-aac4-4627-a2a2-39084e8cca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753079313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3753079313
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1095241520
Short name T170
Test name
Test status
Simulation time 27130765211 ps
CPU time 38.77 seconds
Started Jan 21 01:58:40 PM PST 24
Finished Jan 21 01:59:20 PM PST 24
Peak memory 199796 kb
Host smart-29fba387-0cb4-40fe-b305-d3df67f7da09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095241520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1095241520
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.4026141231
Short name T835
Test name
Test status
Simulation time 109753164573 ps
CPU time 13.52 seconds
Started Jan 21 01:43:21 PM PST 24
Finished Jan 21 01:43:35 PM PST 24
Peak memory 199756 kb
Host smart-9c24ca5a-a05e-4435-bef4-d53f91bfb8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026141231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.4026141231
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.112967525
Short name T510
Test name
Test status
Simulation time 14264659 ps
CPU time 0.61 seconds
Started Jan 21 02:29:03 PM PST 24
Finished Jan 21 02:29:06 PM PST 24
Peak memory 195876 kb
Host smart-5de8f850-7b99-463b-9872-74380b6eb845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112967525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.112967525
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1880280583
Short name T129
Test name
Test status
Simulation time 19848164884 ps
CPU time 33.57 seconds
Started Jan 21 02:14:31 PM PST 24
Finished Jan 21 02:15:05 PM PST 24
Peak memory 199960 kb
Host smart-a84b92f7-e445-44f7-bb19-3ff6ffc486e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880280583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1880280583
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1012971681
Short name T955
Test name
Test status
Simulation time 27965878500 ps
CPU time 46.6 seconds
Started Jan 21 02:54:37 PM PST 24
Finished Jan 21 02:55:25 PM PST 24
Peak memory 200016 kb
Host smart-e010595c-d235-447d-9767-a402b4436047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012971681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1012971681
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2461996038
Short name T949
Test name
Test status
Simulation time 75878918841 ps
CPU time 68.26 seconds
Started Jan 21 01:30:05 PM PST 24
Finished Jan 21 01:31:17 PM PST 24
Peak memory 199892 kb
Host smart-d68063ba-e375-4b57-991a-5b9974030ec9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461996038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2461996038
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.231812815
Short name T872
Test name
Test status
Simulation time 124169903968 ps
CPU time 814.68 seconds
Started Jan 21 01:30:14 PM PST 24
Finished Jan 21 01:43:50 PM PST 24
Peak memory 199888 kb
Host smart-724c53e7-c2b5-4c48-995e-406a8249f9f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231812815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.231812815
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1671916857
Short name T1067
Test name
Test status
Simulation time 11113711488 ps
CPU time 4.54 seconds
Started Jan 21 02:12:14 PM PST 24
Finished Jan 21 02:12:20 PM PST 24
Peak memory 199508 kb
Host smart-857e5271-0333-44dd-97ab-4d726eee417e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671916857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1671916857
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.863888368
Short name T412
Test name
Test status
Simulation time 117511259828 ps
CPU time 52.6 seconds
Started Jan 21 01:30:06 PM PST 24
Finished Jan 21 01:31:01 PM PST 24
Peak memory 200076 kb
Host smart-09b02be8-3b3b-4c61-98dd-6285c4deb9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863888368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.863888368
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.1000202960
Short name T1082
Test name
Test status
Simulation time 12701144382 ps
CPU time 194.03 seconds
Started Jan 21 01:30:09 PM PST 24
Finished Jan 21 01:33:26 PM PST 24
Peak memory 199848 kb
Host smart-64742c5a-ce63-4332-8d7c-342e8f406902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000202960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1000202960
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3338977152
Short name T496
Test name
Test status
Simulation time 2435456143 ps
CPU time 17.66 seconds
Started Jan 21 01:30:06 PM PST 24
Finished Jan 21 01:30:26 PM PST 24
Peak memory 198388 kb
Host smart-3586ad83-5b93-4b4b-8f46-a6705c784aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3338977152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3338977152
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3417968459
Short name T382
Test name
Test status
Simulation time 34330515979 ps
CPU time 54.39 seconds
Started Jan 21 01:30:04 PM PST 24
Finished Jan 21 01:31:03 PM PST 24
Peak memory 199976 kb
Host smart-b677480c-12ae-4b6e-a03e-5c50467ee2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417968459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3417968459
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3941082236
Short name T567
Test name
Test status
Simulation time 1615865736 ps
CPU time 1.36 seconds
Started Jan 21 02:04:30 PM PST 24
Finished Jan 21 02:04:38 PM PST 24
Peak memory 195388 kb
Host smart-ce09921e-9b30-427f-819d-a03bcc2c5a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941082236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3941082236
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2577652619
Short name T884
Test name
Test status
Simulation time 119423828 ps
CPU time 0.72 seconds
Started Jan 21 01:43:19 PM PST 24
Finished Jan 21 01:43:21 PM PST 24
Peak memory 196732 kb
Host smart-1b05c237-5129-48de-8e2c-1d158f62fade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577652619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2577652619
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3225360341
Short name T1176
Test name
Test status
Simulation time 82402816133 ps
CPU time 449.86 seconds
Started Jan 21 01:30:15 PM PST 24
Finished Jan 21 01:37:46 PM PST 24
Peak memory 210172 kb
Host smart-690eea49-51ea-43d9-b9c9-55d384aa8a7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225360341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3225360341
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2152193956
Short name T1090
Test name
Test status
Simulation time 5089912409 ps
CPU time 1.23 seconds
Started Jan 21 01:30:06 PM PST 24
Finished Jan 21 01:30:10 PM PST 24
Peak memory 197856 kb
Host smart-d59ca3d9-d008-4957-90ec-0bc19443b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152193956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2152193956
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3868281639
Short name T219
Test name
Test status
Simulation time 104746025156 ps
CPU time 105.39 seconds
Started Jan 21 02:26:55 PM PST 24
Finished Jan 21 02:28:41 PM PST 24
Peak memory 199924 kb
Host smart-f4a42be2-87db-4e55-8f99-48ce8f69339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868281639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3868281639
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4217138787
Short name T1120
Test name
Test status
Simulation time 25152366870 ps
CPU time 43.39 seconds
Started Jan 21 01:43:21 PM PST 24
Finished Jan 21 01:44:05 PM PST 24
Peak memory 199976 kb
Host smart-42cbfd0c-6a3e-481b-880c-0c27cfa5ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217138787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4217138787
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1794100755
Short name T271
Test name
Test status
Simulation time 106879619653 ps
CPU time 139.52 seconds
Started Jan 21 01:43:18 PM PST 24
Finished Jan 21 01:45:38 PM PST 24
Peak memory 199992 kb
Host smart-a9d10b60-309c-4f73-b1bc-77b26ab0b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794100755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1794100755
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3890946452
Short name T993
Test name
Test status
Simulation time 17135394301 ps
CPU time 36.18 seconds
Started Jan 21 02:27:37 PM PST 24
Finished Jan 21 02:28:14 PM PST 24
Peak memory 200072 kb
Host smart-9a07d624-48a0-49a3-b55d-ff971e21253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890946452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3890946452
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3161190530
Short name T627
Test name
Test status
Simulation time 116866923429 ps
CPU time 180.03 seconds
Started Jan 21 01:43:24 PM PST 24
Finished Jan 21 01:46:25 PM PST 24
Peak memory 199940 kb
Host smart-f512b024-9189-4127-9a66-741c59f5f334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161190530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3161190530
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1745605699
Short name T105
Test name
Test status
Simulation time 46086240301 ps
CPU time 76.9 seconds
Started Jan 21 01:43:26 PM PST 24
Finished Jan 21 01:44:43 PM PST 24
Peak memory 199924 kb
Host smart-c811c3e5-6cb2-481a-be7f-bfafa9cfbb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745605699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1745605699
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1065674753
Short name T728
Test name
Test status
Simulation time 8131811672 ps
CPU time 13.31 seconds
Started Jan 21 01:43:24 PM PST 24
Finished Jan 21 01:43:38 PM PST 24
Peak memory 198796 kb
Host smart-58710726-afe1-4c9c-9956-fe4b5a5f4250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065674753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1065674753
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.4114192868
Short name T797
Test name
Test status
Simulation time 58310116 ps
CPU time 0.6 seconds
Started Jan 21 02:05:05 PM PST 24
Finished Jan 21 02:05:06 PM PST 24
Peak memory 195544 kb
Host smart-7f033157-2389-4652-a18e-737b72f46a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114192868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4114192868
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3435314148
Short name T1141
Test name
Test status
Simulation time 54052026884 ps
CPU time 83.82 seconds
Started Jan 21 01:44:52 PM PST 24
Finished Jan 21 01:46:19 PM PST 24
Peak memory 199992 kb
Host smart-fc7b6de3-5880-4959-a0f1-e0a93797b16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435314148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3435314148
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.4100484760
Short name T369
Test name
Test status
Simulation time 54510084601 ps
CPU time 46.25 seconds
Started Jan 21 01:30:23 PM PST 24
Finished Jan 21 01:31:10 PM PST 24
Peak memory 200028 kb
Host smart-f9e94fa7-edf8-4a8f-966e-52c1d37d0102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100484760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.4100484760
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3581059859
Short name T337
Test name
Test status
Simulation time 44434456922 ps
CPU time 37.18 seconds
Started Jan 21 01:30:24 PM PST 24
Finished Jan 21 01:31:02 PM PST 24
Peak memory 200016 kb
Host smart-c8c7eea6-c8a5-45f4-aa3b-18e557ea0bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581059859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3581059859
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1954855208
Short name T1204
Test name
Test status
Simulation time 49139078248 ps
CPU time 346.05 seconds
Started Jan 21 01:30:34 PM PST 24
Finished Jan 21 01:36:22 PM PST 24
Peak memory 199924 kb
Host smart-02a4b652-3fc9-4cec-9250-a71e00704707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954855208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1954855208
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3212961909
Short name T976
Test name
Test status
Simulation time 5024843207 ps
CPU time 4.83 seconds
Started Jan 21 01:30:33 PM PST 24
Finished Jan 21 01:30:40 PM PST 24
Peak memory 195532 kb
Host smart-f233246e-6214-4a92-b1ff-7c13dd81dd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212961909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3212961909
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.3021616837
Short name T1051
Test name
Test status
Simulation time 21737579071 ps
CPU time 1090.88 seconds
Started Jan 21 01:30:35 PM PST 24
Finished Jan 21 01:48:50 PM PST 24
Peak memory 199872 kb
Host smart-fe6b2c93-d2d2-48c2-9bd5-357322632eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021616837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3021616837
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.819283037
Short name T541
Test name
Test status
Simulation time 2053682161 ps
CPU time 5.44 seconds
Started Jan 21 01:30:24 PM PST 24
Finished Jan 21 01:30:30 PM PST 24
Peak memory 198032 kb
Host smart-82b42365-bbd9-49ff-ad5c-ed0b5f0d003e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819283037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.819283037
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.905155362
Short name T958
Test name
Test status
Simulation time 70553737867 ps
CPU time 64.5 seconds
Started Jan 21 01:30:25 PM PST 24
Finished Jan 21 01:31:30 PM PST 24
Peak memory 199860 kb
Host smart-1d4b5f69-d99d-4ca4-96d1-84b228efc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905155362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.905155362
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3970214133
Short name T1177
Test name
Test status
Simulation time 5408509325 ps
CPU time 2.73 seconds
Started Jan 21 01:30:24 PM PST 24
Finished Jan 21 01:30:28 PM PST 24
Peak memory 195864 kb
Host smart-bbd4efdd-fba8-4f89-9875-785baa204d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970214133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3970214133
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2455773342
Short name T854
Test name
Test status
Simulation time 290785810 ps
CPU time 1.01 seconds
Started Jan 21 01:30:13 PM PST 24
Finished Jan 21 01:30:15 PM PST 24
Peak memory 198024 kb
Host smart-e9b2f8b5-e7a3-4ef5-9693-cff7f94813f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455773342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2455773342
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2776731720
Short name T217
Test name
Test status
Simulation time 1011246055084 ps
CPU time 373.82 seconds
Started Jan 21 01:30:32 PM PST 24
Finished Jan 21 01:36:49 PM PST 24
Peak memory 199892 kb
Host smart-e493b42c-d29a-4cd6-837a-c227cc42b86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776731720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2776731720
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1787152384
Short name T776
Test name
Test status
Simulation time 36893608547 ps
CPU time 632.36 seconds
Started Jan 21 01:30:33 PM PST 24
Finished Jan 21 01:41:08 PM PST 24
Peak memory 210676 kb
Host smart-43fb924b-5fe0-4e75-8e98-cc7b466d5997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787152384 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1787152384
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.4240882924
Short name T981
Test name
Test status
Simulation time 315798466 ps
CPU time 1.68 seconds
Started Jan 21 01:30:23 PM PST 24
Finished Jan 21 01:30:26 PM PST 24
Peak memory 198112 kb
Host smart-8853d950-82a5-424d-8186-9bcfa64c7e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240882924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.4240882924
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1612948945
Short name T985
Test name
Test status
Simulation time 118937174791 ps
CPU time 43.02 seconds
Started Jan 21 01:30:14 PM PST 24
Finished Jan 21 01:30:58 PM PST 24
Peak memory 199996 kb
Host smart-8c9fcf68-e08c-490d-a303-22dfb97fe950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612948945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1612948945
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1491810741
Short name T697
Test name
Test status
Simulation time 28646857355 ps
CPU time 22.49 seconds
Started Jan 21 01:43:24 PM PST 24
Finished Jan 21 01:43:47 PM PST 24
Peak memory 199976 kb
Host smart-ff8d448d-e3ec-44a6-b90e-91fcb27847c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491810741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1491810741
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1236180867
Short name T146
Test name
Test status
Simulation time 38987658040 ps
CPU time 26.79 seconds
Started Jan 21 02:13:44 PM PST 24
Finished Jan 21 02:14:11 PM PST 24
Peak memory 199348 kb
Host smart-7576e7fc-a029-4b94-bf07-80246c965bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236180867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1236180867
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1788414989
Short name T820
Test name
Test status
Simulation time 163671047982 ps
CPU time 26.34 seconds
Started Jan 21 01:43:35 PM PST 24
Finished Jan 21 01:44:02 PM PST 24
Peak memory 199964 kb
Host smart-7b3062ac-bd02-4932-92cf-2a8cf434d142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788414989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1788414989
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2242675948
Short name T125
Test name
Test status
Simulation time 11435354145 ps
CPU time 27.62 seconds
Started Jan 21 01:43:33 PM PST 24
Finished Jan 21 01:44:01 PM PST 24
Peak memory 199884 kb
Host smart-85d98cbf-6cc8-4041-b934-ea87b1edcf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242675948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2242675948
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.455716616
Short name T988
Test name
Test status
Simulation time 48313004450 ps
CPU time 19.9 seconds
Started Jan 21 02:37:33 PM PST 24
Finished Jan 21 02:37:53 PM PST 24
Peak memory 199652 kb
Host smart-0650f7ad-c7a7-4dcb-8f26-4f23a48e6d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455716616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.455716616
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.474091525
Short name T1078
Test name
Test status
Simulation time 41840560878 ps
CPU time 79.53 seconds
Started Jan 21 01:43:36 PM PST 24
Finished Jan 21 01:44:56 PM PST 24
Peak memory 200004 kb
Host smart-189a2cd6-42af-47ba-ba4e-a8f95d7aa62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474091525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.474091525
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1341844076
Short name T437
Test name
Test status
Simulation time 95649364114 ps
CPU time 148.19 seconds
Started Jan 21 01:43:43 PM PST 24
Finished Jan 21 01:46:11 PM PST 24
Peak memory 199924 kb
Host smart-eae47fcd-748e-402f-ae3d-0069b560b1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341844076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1341844076
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2468977506
Short name T1182
Test name
Test status
Simulation time 13976468 ps
CPU time 0.56 seconds
Started Jan 21 01:30:52 PM PST 24
Finished Jan 21 01:30:54 PM PST 24
Peak memory 195480 kb
Host smart-706dd645-872d-41ad-b9b1-7e864d50e683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468977506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2468977506
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3219685123
Short name T757
Test name
Test status
Simulation time 146651435905 ps
CPU time 197.7 seconds
Started Jan 21 01:30:44 PM PST 24
Finished Jan 21 01:34:03 PM PST 24
Peak memory 199968 kb
Host smart-36234672-c820-4a6d-8c37-c0c72573196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219685123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3219685123
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3611529508
Short name T379
Test name
Test status
Simulation time 30258649265 ps
CPU time 12.91 seconds
Started Jan 21 02:35:57 PM PST 24
Finished Jan 21 02:36:11 PM PST 24
Peak memory 199864 kb
Host smart-1af2171d-fa74-4dc4-b542-73e9f3c6be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611529508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3611529508
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.2571522315
Short name T989
Test name
Test status
Simulation time 315496811821 ps
CPU time 1151.73 seconds
Started Jan 21 02:12:56 PM PST 24
Finished Jan 21 02:32:09 PM PST 24
Peak memory 199972 kb
Host smart-f90c34ef-2a5c-4ca7-aa14-6c876c4e1825
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571522315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2571522315
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1867879182
Short name T1166
Test name
Test status
Simulation time 60204272907 ps
CPU time 180.26 seconds
Started Jan 21 01:30:52 PM PST 24
Finished Jan 21 01:33:53 PM PST 24
Peak memory 200060 kb
Host smart-2603a35e-bf8e-4149-8124-3941b6d93f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867879182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1867879182
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.844480459
Short name T761
Test name
Test status
Simulation time 4008676241 ps
CPU time 1.85 seconds
Started Jan 21 01:30:48 PM PST 24
Finished Jan 21 01:30:51 PM PST 24
Peak memory 197156 kb
Host smart-639f100c-d723-40a5-9bc5-653a3de350f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844480459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.844480459
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.2851777600
Short name T449
Test name
Test status
Simulation time 124928002239 ps
CPU time 102.89 seconds
Started Jan 21 01:30:41 PM PST 24
Finished Jan 21 01:32:25 PM PST 24
Peak memory 208408 kb
Host smart-75f68a91-ceed-4cd0-9e2b-370e358d2c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851777600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2851777600
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.223335999
Short name T626
Test name
Test status
Simulation time 34218791701 ps
CPU time 894.62 seconds
Started Jan 21 01:30:42 PM PST 24
Finished Jan 21 01:45:38 PM PST 24
Peak memory 199960 kb
Host smart-09768a28-764f-4675-bcbe-47c345b4ec82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223335999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.223335999
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3911110462
Short name T511
Test name
Test status
Simulation time 157122124 ps
CPU time 0.69 seconds
Started Jan 21 01:30:45 PM PST 24
Finished Jan 21 01:30:46 PM PST 24
Peak memory 195472 kb
Host smart-fee51d29-fabf-4e80-b43f-d506e821081f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911110462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3911110462
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1044089661
Short name T735
Test name
Test status
Simulation time 230726265735 ps
CPU time 197.5 seconds
Started Jan 21 01:30:41 PM PST 24
Finished Jan 21 01:34:00 PM PST 24
Peak memory 199932 kb
Host smart-e881db35-02bd-4ece-a0e3-3f079c3a348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044089661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1044089661
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3360928462
Short name T583
Test name
Test status
Simulation time 1775481506 ps
CPU time 3.19 seconds
Started Jan 21 03:36:54 PM PST 24
Finished Jan 21 03:37:01 PM PST 24
Peak memory 195456 kb
Host smart-0355a2fa-38c9-469c-b843-c144689a4c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360928462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3360928462
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2886588590
Short name T20
Test name
Test status
Simulation time 662520132 ps
CPU time 1.8 seconds
Started Jan 21 01:47:52 PM PST 24
Finished Jan 21 01:47:55 PM PST 24
Peak memory 197648 kb
Host smart-c3b519b1-7264-4841-94ec-1e6a097713a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886588590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2886588590
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.929260126
Short name T700
Test name
Test status
Simulation time 24432549457 ps
CPU time 286.42 seconds
Started Jan 21 02:01:35 PM PST 24
Finished Jan 21 02:06:23 PM PST 24
Peak memory 213812 kb
Host smart-b418d74f-b6c1-4466-a0f3-bf9faf3e95c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929260126 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.929260126
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3518098430
Short name T852
Test name
Test status
Simulation time 12817630008 ps
CPU time 27.33 seconds
Started Jan 21 02:35:44 PM PST 24
Finished Jan 21 02:36:12 PM PST 24
Peak memory 198896 kb
Host smart-691f595b-f817-4736-8f8f-dcee0312477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518098430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3518098430
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.4000671675
Short name T961
Test name
Test status
Simulation time 48550684953 ps
CPU time 108.49 seconds
Started Jan 21 01:30:45 PM PST 24
Finished Jan 21 01:32:34 PM PST 24
Peak memory 200012 kb
Host smart-72b71dee-211d-4923-938b-f68b087dc8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000671675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4000671675
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2550865319
Short name T242
Test name
Test status
Simulation time 153153122209 ps
CPU time 51.77 seconds
Started Jan 21 01:43:44 PM PST 24
Finished Jan 21 01:44:37 PM PST 24
Peak memory 199976 kb
Host smart-6fdc7a54-2fde-436d-b7b2-bed3da3992ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550865319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2550865319
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1650783266
Short name T121
Test name
Test status
Simulation time 15806502704 ps
CPU time 26.64 seconds
Started Jan 21 01:43:42 PM PST 24
Finished Jan 21 01:44:09 PM PST 24
Peak memory 199852 kb
Host smart-dd4421ab-9d64-4dea-924d-7d1437502b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650783266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1650783266
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1932047474
Short name T855
Test name
Test status
Simulation time 30037946285 ps
CPU time 42.56 seconds
Started Jan 21 01:43:52 PM PST 24
Finished Jan 21 01:44:35 PM PST 24
Peak memory 199976 kb
Host smart-e904cd32-8487-4778-8081-c25eef0ffd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932047474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1932047474
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2072963312
Short name T847
Test name
Test status
Simulation time 14796286756 ps
CPU time 27.43 seconds
Started Jan 21 01:43:53 PM PST 24
Finished Jan 21 01:44:21 PM PST 24
Peak memory 199780 kb
Host smart-9a0519af-a23c-483a-9c74-803f7fe453a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072963312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2072963312
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2403982419
Short name T1222
Test name
Test status
Simulation time 47199842453 ps
CPU time 68.48 seconds
Started Jan 21 01:43:50 PM PST 24
Finished Jan 21 01:44:59 PM PST 24
Peak memory 199952 kb
Host smart-c2294340-aa07-4a51-ad49-5dc0bef1be47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403982419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2403982419
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.110763812
Short name T115
Test name
Test status
Simulation time 16911461955 ps
CPU time 23.23 seconds
Started Jan 21 01:43:51 PM PST 24
Finished Jan 21 01:44:15 PM PST 24
Peak memory 199912 kb
Host smart-afb8eaf6-8b39-4848-a94b-2baf08a4fa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110763812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.110763812
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1942060083
Short name T716
Test name
Test status
Simulation time 61951780 ps
CPU time 0.54 seconds
Started Jan 21 01:31:14 PM PST 24
Finished Jan 21 01:31:16 PM PST 24
Peak memory 195620 kb
Host smart-83c52760-f727-4459-a12d-acfd69cc27a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942060083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1942060083
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3310903564
Short name T924
Test name
Test status
Simulation time 108691016628 ps
CPU time 204.1 seconds
Started Jan 21 01:31:03 PM PST 24
Finished Jan 21 01:34:29 PM PST 24
Peak memory 199952 kb
Host smart-58fa5e6a-1b03-4fb4-be0a-bc1a92a759f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310903564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3310903564
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1296746434
Short name T939
Test name
Test status
Simulation time 58801894507 ps
CPU time 75.35 seconds
Started Jan 21 01:31:03 PM PST 24
Finished Jan 21 01:32:20 PM PST 24
Peak memory 199588 kb
Host smart-e1a4cb60-9807-4835-b3f6-5bc6544e35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296746434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1296746434
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3243871675
Short name T718
Test name
Test status
Simulation time 71406642811 ps
CPU time 71.92 seconds
Started Jan 21 01:31:03 PM PST 24
Finished Jan 21 01:32:15 PM PST 24
Peak memory 200012 kb
Host smart-3107e684-fb67-44ca-9b68-e669145f9ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243871675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3243871675
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.4125418711
Short name T451
Test name
Test status
Simulation time 803419685141 ps
CPU time 648.78 seconds
Started Jan 21 01:31:13 PM PST 24
Finished Jan 21 01:42:03 PM PST 24
Peak memory 199988 kb
Host smart-9b03b92f-bab2-478d-8f63-bf1bc8e5f494
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125418711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.4125418711
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2645278152
Short name T978
Test name
Test status
Simulation time 69210390816 ps
CPU time 322.88 seconds
Started Jan 21 01:31:14 PM PST 24
Finished Jan 21 01:36:38 PM PST 24
Peak memory 200000 kb
Host smart-68bed3d2-a2b3-431e-88f5-9498f8836e8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645278152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2645278152
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3581755021
Short name T1215
Test name
Test status
Simulation time 8693483934 ps
CPU time 7.97 seconds
Started Jan 21 01:31:13 PM PST 24
Finished Jan 21 01:31:23 PM PST 24
Peak memory 199400 kb
Host smart-41498f24-7bea-4f5c-9cd9-f6008afb8ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581755021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3581755021
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2171397111
Short name T695
Test name
Test status
Simulation time 187161376895 ps
CPU time 64.47 seconds
Started Jan 21 01:31:19 PM PST 24
Finished Jan 21 01:32:24 PM PST 24
Peak memory 199964 kb
Host smart-55a9e3d3-e414-43d4-8cd5-a266d1f4d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171397111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2171397111
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2022162959
Short name T617
Test name
Test status
Simulation time 29620264619 ps
CPU time 387.26 seconds
Started Jan 21 02:05:34 PM PST 24
Finished Jan 21 02:12:02 PM PST 24
Peak memory 199848 kb
Host smart-9eeb37e8-13d4-4852-a8e9-1e44a786ab33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022162959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2022162959
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.103159477
Short name T790
Test name
Test status
Simulation time 179144441366 ps
CPU time 24.33 seconds
Started Jan 21 01:31:12 PM PST 24
Finished Jan 21 01:31:37 PM PST 24
Peak memory 198128 kb
Host smart-4fac190c-e381-4c6f-b4ba-ba1a0f697fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103159477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.103159477
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3836177280
Short name T827
Test name
Test status
Simulation time 2214159457 ps
CPU time 4.01 seconds
Started Jan 21 01:31:12 PM PST 24
Finished Jan 21 01:31:17 PM PST 24
Peak memory 195496 kb
Host smart-a3719ea1-eb23-434c-b3d8-8f7d22f2cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836177280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3836177280
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1304310311
Short name T970
Test name
Test status
Simulation time 644893473 ps
CPU time 1.84 seconds
Started Jan 21 01:31:04 PM PST 24
Finished Jan 21 01:31:07 PM PST 24
Peak memory 199148 kb
Host smart-ead8bca0-8dde-4b82-baa6-7c991e491658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304310311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1304310311
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2281093754
Short name T831
Test name
Test status
Simulation time 299969966467 ps
CPU time 768.54 seconds
Started Jan 21 01:45:40 PM PST 24
Finished Jan 21 01:58:29 PM PST 24
Peak memory 216196 kb
Host smart-3a4dad3c-cbd4-4389-862c-9e997a28700d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281093754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2281093754
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3749767333
Short name T683
Test name
Test status
Simulation time 30837097140 ps
CPU time 401.79 seconds
Started Jan 21 02:10:42 PM PST 24
Finished Jan 21 02:17:27 PM PST 24
Peak memory 215220 kb
Host smart-624a8aa7-b067-4608-bf75-7dc3ebca7fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749767333 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3749767333
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1840296434
Short name T1193
Test name
Test status
Simulation time 617430190 ps
CPU time 2.79 seconds
Started Jan 21 01:31:19 PM PST 24
Finished Jan 21 01:31:22 PM PST 24
Peak memory 199128 kb
Host smart-fe8b0dbf-1aec-4849-8413-265617903ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840296434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1840296434
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1109883226
Short name T891
Test name
Test status
Simulation time 78042273933 ps
CPU time 293.64 seconds
Started Jan 21 01:31:04 PM PST 24
Finished Jan 21 01:35:59 PM PST 24
Peak memory 199808 kb
Host smart-c13cdbf7-2810-4a25-8022-c4f7342459a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109883226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1109883226
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1109816770
Short name T1169
Test name
Test status
Simulation time 14476238838 ps
CPU time 23.22 seconds
Started Jan 21 01:43:53 PM PST 24
Finished Jan 21 01:44:16 PM PST 24
Peak memory 199864 kb
Host smart-6b68b280-bab6-48a7-a42f-f6390bdcc54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109816770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1109816770
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2421350810
Short name T734
Test name
Test status
Simulation time 116370291416 ps
CPU time 178.67 seconds
Started Jan 21 01:43:53 PM PST 24
Finished Jan 21 01:46:52 PM PST 24
Peak memory 199980 kb
Host smart-10d5f371-6b5d-4a01-8df5-01dea84fe73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421350810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2421350810
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3533510222
Short name T107
Test name
Test status
Simulation time 31560680462 ps
CPU time 18.2 seconds
Started Jan 21 01:43:56 PM PST 24
Finished Jan 21 01:44:15 PM PST 24
Peak memory 199876 kb
Host smart-d5a2e0c0-f66e-406b-959e-cf1a421b6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533510222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3533510222
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3222314086
Short name T211
Test name
Test status
Simulation time 50873891937 ps
CPU time 60.4 seconds
Started Jan 21 01:43:50 PM PST 24
Finished Jan 21 01:44:51 PM PST 24
Peak memory 199660 kb
Host smart-40b32d24-ff9f-4a7d-befd-72e9a3ceb904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222314086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3222314086
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3778918858
Short name T795
Test name
Test status
Simulation time 18753485092 ps
CPU time 23.17 seconds
Started Jan 21 01:44:02 PM PST 24
Finished Jan 21 01:44:26 PM PST 24
Peak memory 199360 kb
Host smart-6b1963a6-bd08-4ea6-b2f5-235a9cb8e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778918858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3778918858
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1536438993
Short name T651
Test name
Test status
Simulation time 11489389300 ps
CPU time 11.98 seconds
Started Jan 21 01:44:01 PM PST 24
Finished Jan 21 01:44:14 PM PST 24
Peak memory 199952 kb
Host smart-af30ede3-1675-43fe-8ef6-e0b5de1c5fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536438993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1536438993
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1322076293
Short name T548
Test name
Test status
Simulation time 114812311259 ps
CPU time 90.37 seconds
Started Jan 21 01:44:01 PM PST 24
Finished Jan 21 01:45:32 PM PST 24
Peak memory 199956 kb
Host smart-5f560a87-f4c2-46d5-9193-0b39038ec922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322076293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1322076293
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4111956129
Short name T1105
Test name
Test status
Simulation time 43153406 ps
CPU time 0.57 seconds
Started Jan 21 01:31:40 PM PST 24
Finished Jan 21 01:31:41 PM PST 24
Peak memory 195468 kb
Host smart-d79bbf06-07f3-42d1-9efc-944f48de8e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111956129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4111956129
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.4271536122
Short name T290
Test name
Test status
Simulation time 37277389996 ps
CPU time 56.41 seconds
Started Jan 21 02:21:15 PM PST 24
Finished Jan 21 02:22:12 PM PST 24
Peak memory 199728 kb
Host smart-185d315e-4c86-466c-b9c3-a0078d1fe711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271536122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.4271536122
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.106880968
Short name T1163
Test name
Test status
Simulation time 128593927291 ps
CPU time 50.34 seconds
Started Jan 21 01:31:26 PM PST 24
Finished Jan 21 01:32:19 PM PST 24
Peak memory 200020 kb
Host smart-810806c0-b125-4714-bd49-729082103fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106880968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.106880968
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.841267075
Short name T292
Test name
Test status
Simulation time 187872775793 ps
CPU time 161.2 seconds
Started Jan 21 02:12:21 PM PST 24
Finished Jan 21 02:15:03 PM PST 24
Peak memory 199780 kb
Host smart-a3754c67-df0d-481c-aa4e-59e107f76dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841267075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.841267075
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2435138732
Short name T1110
Test name
Test status
Simulation time 62371964066 ps
CPU time 22.43 seconds
Started Jan 21 01:31:29 PM PST 24
Finished Jan 21 01:31:53 PM PST 24
Peak memory 198248 kb
Host smart-608c61ae-5064-418d-ba7e-d2ffa9681200
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435138732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2435138732
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2432088556
Short name T584
Test name
Test status
Simulation time 164940046509 ps
CPU time 1288.04 seconds
Started Jan 21 01:47:37 PM PST 24
Finished Jan 21 02:09:07 PM PST 24
Peak memory 200072 kb
Host smart-d468e47c-e255-412a-83eb-086799a53377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432088556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2432088556
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1510024498
Short name T758
Test name
Test status
Simulation time 112598476 ps
CPU time 0.77 seconds
Started Jan 21 01:31:40 PM PST 24
Finished Jan 21 01:31:41 PM PST 24
Peak memory 195396 kb
Host smart-0f244b0a-54d0-4919-8d73-cd71a691ec2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510024498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1510024498
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1623410548
Short name T423
Test name
Test status
Simulation time 152735205013 ps
CPU time 52.62 seconds
Started Jan 21 01:31:30 PM PST 24
Finished Jan 21 01:32:24 PM PST 24
Peak memory 199896 kb
Host smart-8c469140-5dff-48e3-b197-710722a2fd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623410548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1623410548
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2979876338
Short name T1014
Test name
Test status
Simulation time 77870814180 ps
CPU time 160.84 seconds
Started Jan 21 01:31:29 PM PST 24
Finished Jan 21 01:34:10 PM PST 24
Peak memory 199768 kb
Host smart-96a06f72-245d-431c-95b9-d5327f7239f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979876338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2979876338
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4264911974
Short name T408
Test name
Test status
Simulation time 782906206 ps
CPU time 0.97 seconds
Started Jan 21 01:31:29 PM PST 24
Finished Jan 21 01:31:31 PM PST 24
Peak memory 195428 kb
Host smart-71430117-366f-4e53-a8e3-83e648c457a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264911974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4264911974
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3602143836
Short name T534
Test name
Test status
Simulation time 5821185872 ps
CPU time 6.83 seconds
Started Jan 21 02:31:15 PM PST 24
Finished Jan 21 02:31:24 PM PST 24
Peak memory 198776 kb
Host smart-fc822997-8277-4fa2-8cae-3d8137bf0c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602143836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3602143836
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3229257266
Short name T372
Test name
Test status
Simulation time 1246902111443 ps
CPU time 398.93 seconds
Started Jan 21 01:31:41 PM PST 24
Finished Jan 21 01:38:21 PM PST 24
Peak memory 199948 kb
Host smart-4c492cce-a152-40d2-90e8-4b26cf202f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229257266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3229257266
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2194795721
Short name T181
Test name
Test status
Simulation time 56628249538 ps
CPU time 226.53 seconds
Started Jan 21 01:31:39 PM PST 24
Finished Jan 21 01:35:27 PM PST 24
Peak memory 213660 kb
Host smart-15528cc2-996e-4dad-b5fc-d01cc17dd051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194795721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2194795721
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1013693191
Short name T1131
Test name
Test status
Simulation time 1448055132 ps
CPU time 3 seconds
Started Jan 21 01:31:41 PM PST 24
Finished Jan 21 01:31:45 PM PST 24
Peak memory 198276 kb
Host smart-1497dec4-9b07-42e2-a6dc-94d0c2f6131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013693191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1013693191
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3525797736
Short name T787
Test name
Test status
Simulation time 14510873544 ps
CPU time 23.48 seconds
Started Jan 21 01:58:36 PM PST 24
Finished Jan 21 01:59:00 PM PST 24
Peak memory 199876 kb
Host smart-77ee3fb8-987b-4af8-a1e8-847207b1181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525797736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3525797736
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1165385027
Short name T192
Test name
Test status
Simulation time 59335390849 ps
CPU time 97.11 seconds
Started Jan 21 01:59:06 PM PST 24
Finished Jan 21 02:00:43 PM PST 24
Peak memory 199972 kb
Host smart-ecd6a137-66a2-4b2c-a5bb-82564467e868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165385027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1165385027
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.274657533
Short name T222
Test name
Test status
Simulation time 21605156880 ps
CPU time 37.51 seconds
Started Jan 21 01:44:10 PM PST 24
Finished Jan 21 01:44:53 PM PST 24
Peak memory 199896 kb
Host smart-e8150a9c-9e30-4110-8ebf-137b55fd99c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274657533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.274657533
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3593570165
Short name T1023
Test name
Test status
Simulation time 56846420570 ps
CPU time 142.99 seconds
Started Jan 21 01:44:10 PM PST 24
Finished Jan 21 01:46:38 PM PST 24
Peak memory 199968 kb
Host smart-8cdd64b6-9b37-4987-a7e8-edf0cb329db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593570165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3593570165
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.707969528
Short name T577
Test name
Test status
Simulation time 27308557856 ps
CPU time 39.61 seconds
Started Jan 21 01:44:10 PM PST 24
Finished Jan 21 01:44:55 PM PST 24
Peak memory 199420 kb
Host smart-2d522e24-7d54-4a0e-ab32-02681dca7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707969528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.707969528
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1869872542
Short name T1061
Test name
Test status
Simulation time 194617741137 ps
CPU time 48.01 seconds
Started Jan 21 01:44:13 PM PST 24
Finished Jan 21 01:45:09 PM PST 24
Peak memory 199560 kb
Host smart-0b36a765-c837-414c-bd32-589829824dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869872542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1869872542
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1701074770
Short name T114
Test name
Test status
Simulation time 23162658028 ps
CPU time 31.51 seconds
Started Jan 21 01:44:11 PM PST 24
Finished Jan 21 01:44:48 PM PST 24
Peak memory 199836 kb
Host smart-d924af66-5f00-4bed-8daf-dcfc1e1170d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701074770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1701074770
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.488060988
Short name T300
Test name
Test status
Simulation time 55786589877 ps
CPU time 44.77 seconds
Started Jan 21 01:44:10 PM PST 24
Finished Jan 21 01:45:00 PM PST 24
Peak memory 199976 kb
Host smart-f1a00138-8603-4476-81db-0c8f6d3220b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488060988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.488060988
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2099983149
Short name T801
Test name
Test status
Simulation time 50272820743 ps
CPU time 20.58 seconds
Started Jan 21 01:44:09 PM PST 24
Finished Jan 21 01:44:32 PM PST 24
Peak memory 199544 kb
Host smart-39355479-e0d0-4402-a75d-c5edcc2e55f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099983149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2099983149
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2325320666
Short name T251
Test name
Test status
Simulation time 48109056008 ps
CPU time 74.07 seconds
Started Jan 21 01:44:10 PM PST 24
Finished Jan 21 01:45:29 PM PST 24
Peak memory 199996 kb
Host smart-7b25c1fa-7c53-42b3-baea-50a6a0ee9303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325320666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2325320666
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1143823917
Short name T495
Test name
Test status
Simulation time 13958918 ps
CPU time 0.59 seconds
Started Jan 21 01:32:00 PM PST 24
Finished Jan 21 01:32:02 PM PST 24
Peak memory 194696 kb
Host smart-c9858969-bda7-4f64-b797-a4ce73eb0a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143823917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1143823917
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1157724071
Short name T381
Test name
Test status
Simulation time 167677183289 ps
CPU time 44.36 seconds
Started Jan 21 01:31:49 PM PST 24
Finished Jan 21 01:32:34 PM PST 24
Peak memory 199972 kb
Host smart-e244d77c-6b52-4419-9640-16f71dde89dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157724071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1157724071
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.2065159855
Short name T677
Test name
Test status
Simulation time 415909473059 ps
CPU time 122.08 seconds
Started Jan 21 01:31:59 PM PST 24
Finished Jan 21 01:34:02 PM PST 24
Peak memory 199008 kb
Host smart-cc984b08-6fd9-45b7-9771-436a097c07ff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065159855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2065159855
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2323150760
Short name T1167
Test name
Test status
Simulation time 131783086176 ps
CPU time 1118.53 seconds
Started Jan 21 01:31:58 PM PST 24
Finished Jan 21 01:50:37 PM PST 24
Peak memory 199916 kb
Host smart-3a6732f7-c87e-40ef-90a7-ab4b08bd31d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323150760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2323150760
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.17747811
Short name T1195
Test name
Test status
Simulation time 3011580303 ps
CPU time 6.28 seconds
Started Jan 21 01:31:59 PM PST 24
Finished Jan 21 01:32:06 PM PST 24
Peak memory 198280 kb
Host smart-e35ca42c-0d4f-45a4-9fa0-9527d9a30eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17747811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.17747811
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2976998814
Short name T93
Test name
Test status
Simulation time 98221576885 ps
CPU time 211.58 seconds
Started Jan 21 01:31:53 PM PST 24
Finished Jan 21 01:35:26 PM PST 24
Peak memory 208176 kb
Host smart-d34037d4-c40a-4bad-b4a3-b3436a1fc5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976998814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2976998814
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3627898566
Short name T641
Test name
Test status
Simulation time 16259241744 ps
CPU time 478.36 seconds
Started Jan 21 01:31:54 PM PST 24
Finished Jan 21 01:39:54 PM PST 24
Peak memory 199400 kb
Host smart-1f18c5fc-8dfe-43ea-9544-389a4214a9bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627898566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3627898566
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3426955158
Short name T1129
Test name
Test status
Simulation time 113717072 ps
CPU time 0.73 seconds
Started Jan 21 01:31:51 PM PST 24
Finished Jan 21 01:31:52 PM PST 24
Peak memory 195508 kb
Host smart-0190aa92-422e-4dc5-90fa-40a984d70de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426955158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3426955158
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1647430193
Short name T1114
Test name
Test status
Simulation time 52930457484 ps
CPU time 11.34 seconds
Started Jan 21 01:31:51 PM PST 24
Finished Jan 21 01:32:02 PM PST 24
Peak memory 195800 kb
Host smart-428077dd-acd0-440c-bac1-98dca9a96af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647430193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1647430193
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2277643663
Short name T838
Test name
Test status
Simulation time 5867316803 ps
CPU time 18.02 seconds
Started Jan 21 01:32:00 PM PST 24
Finished Jan 21 01:32:19 PM PST 24
Peak memory 199540 kb
Host smart-5dbce97a-f2d4-4018-b879-aea2b9a1e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277643663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2277643663
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.651799615
Short name T361
Test name
Test status
Simulation time 520191469338 ps
CPU time 299.99 seconds
Started Jan 21 01:31:58 PM PST 24
Finished Jan 21 01:36:59 PM PST 24
Peak memory 200080 kb
Host smart-91f65b97-a98f-45d2-bde2-8edf6ebb7906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651799615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.651799615
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2020635500
Short name T1136
Test name
Test status
Simulation time 14683339589 ps
CPU time 73.25 seconds
Started Jan 21 01:32:00 PM PST 24
Finished Jan 21 01:33:15 PM PST 24
Peak memory 208572 kb
Host smart-2e9c85fa-347e-40c9-ae0b-54ea86fa68d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020635500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2020635500
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1098844070
Short name T549
Test name
Test status
Simulation time 1302720623 ps
CPU time 4.01 seconds
Started Jan 21 01:32:00 PM PST 24
Finished Jan 21 01:32:05 PM PST 24
Peak memory 198408 kb
Host smart-8720c1c0-16b1-4dd2-a787-e6e455e0b72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098844070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1098844070
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.404661174
Short name T1219
Test name
Test status
Simulation time 118194738326 ps
CPU time 189.64 seconds
Started Jan 21 01:44:19 PM PST 24
Finished Jan 21 01:47:33 PM PST 24
Peak memory 199760 kb
Host smart-97e3976c-cfc4-4170-b498-a1cd65f71bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404661174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.404661174
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3387311917
Short name T341
Test name
Test status
Simulation time 59436592669 ps
CPU time 11.95 seconds
Started Jan 21 01:44:20 PM PST 24
Finished Jan 21 01:44:36 PM PST 24
Peak memory 199928 kb
Host smart-db2fb473-a51a-4bf3-b458-94f4ddc69fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387311917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3387311917
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2765879270
Short name T39
Test name
Test status
Simulation time 75513942169 ps
CPU time 63.38 seconds
Started Jan 21 03:01:35 PM PST 24
Finished Jan 21 03:02:40 PM PST 24
Peak memory 199912 kb
Host smart-32fcaa5d-0406-4b01-9223-b87b6f0b8d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765879270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2765879270
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2998389457
Short name T296
Test name
Test status
Simulation time 64844217572 ps
CPU time 121.38 seconds
Started Jan 21 01:44:19 PM PST 24
Finished Jan 21 01:46:25 PM PST 24
Peak memory 200000 kb
Host smart-37cabbfa-d01c-4d0f-98c7-264581814e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998389457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2998389457
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1042875200
Short name T816
Test name
Test status
Simulation time 45808204938 ps
CPU time 24.15 seconds
Started Jan 21 01:44:21 PM PST 24
Finished Jan 21 01:44:49 PM PST 24
Peak memory 199960 kb
Host smart-b8f9264d-54a0-40fa-aaeb-4eafead7cc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042875200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1042875200
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2730781570
Short name T298
Test name
Test status
Simulation time 107699240821 ps
CPU time 152.59 seconds
Started Jan 21 01:44:22 PM PST 24
Finished Jan 21 01:46:58 PM PST 24
Peak memory 199944 kb
Host smart-68054677-ed45-49d2-aff4-ac57a7d36cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730781570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2730781570
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2337864369
Short name T931
Test name
Test status
Simulation time 46407053138 ps
CPU time 10.64 seconds
Started Jan 21 02:35:42 PM PST 24
Finished Jan 21 02:35:53 PM PST 24
Peak memory 199712 kb
Host smart-96394f0d-b3b9-44ea-92f0-0e088cac85a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337864369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2337864369
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1201589937
Short name T912
Test name
Test status
Simulation time 8621330860 ps
CPU time 17.66 seconds
Started Jan 21 02:42:07 PM PST 24
Finished Jan 21 02:42:25 PM PST 24
Peak memory 200056 kb
Host smart-52e884a5-69af-4ad0-8f24-1167276d735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201589937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1201589937
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4242471646
Short name T313
Test name
Test status
Simulation time 102544380796 ps
CPU time 57.49 seconds
Started Jan 21 01:44:19 PM PST 24
Finished Jan 21 01:45:21 PM PST 24
Peak memory 199964 kb
Host smart-e31992da-e515-4963-9f1d-8c1e986f97e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242471646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4242471646
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3328598151
Short name T781
Test name
Test status
Simulation time 11517607 ps
CPU time 0.57 seconds
Started Jan 21 01:32:15 PM PST 24
Finished Jan 21 01:32:16 PM PST 24
Peak memory 195560 kb
Host smart-0a4e7778-1033-424c-9aba-cb91af852ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328598151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3328598151
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.985814263
Short name T221
Test name
Test status
Simulation time 137127013113 ps
CPU time 108.81 seconds
Started Jan 21 01:32:07 PM PST 24
Finished Jan 21 01:33:57 PM PST 24
Peak memory 199452 kb
Host smart-7e0944b7-b7a6-4acf-af67-8aeb98743f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985814263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.985814263
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1354878460
Short name T812
Test name
Test status
Simulation time 3439103028 ps
CPU time 1.97 seconds
Started Jan 21 01:32:09 PM PST 24
Finished Jan 21 01:32:12 PM PST 24
Peak memory 195856 kb
Host smart-26cfb98c-df26-430c-8b74-ffabbfa9fb88
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354878460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1354878460
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.787500201
Short name T779
Test name
Test status
Simulation time 168665940337 ps
CPU time 708.24 seconds
Started Jan 21 01:32:07 PM PST 24
Finished Jan 21 01:43:56 PM PST 24
Peak memory 199932 kb
Host smart-542bf83d-6d54-44c4-89fc-69078494f5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787500201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.787500201
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.979703682
Short name T527
Test name
Test status
Simulation time 2484259025 ps
CPU time 1.03 seconds
Started Jan 21 01:32:08 PM PST 24
Finished Jan 21 01:32:10 PM PST 24
Peak memory 195720 kb
Host smart-fe33a066-a35d-44bc-9dee-c77ddb2134a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979703682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.979703682
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.53440886
Short name T22
Test name
Test status
Simulation time 21362471688 ps
CPU time 50.33 seconds
Started Jan 21 01:32:06 PM PST 24
Finished Jan 21 01:32:58 PM PST 24
Peak memory 199048 kb
Host smart-30ddc830-4045-4d39-adf5-9bcca9262732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53440886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.53440886
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.362521156
Short name T569
Test name
Test status
Simulation time 33157875704 ps
CPU time 1660.79 seconds
Started Jan 21 01:32:07 PM PST 24
Finished Jan 21 01:59:49 PM PST 24
Peak memory 200020 kb
Host smart-afac7ea6-c378-48f0-a20d-e7d94c55b604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362521156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.362521156
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2729028976
Short name T1216
Test name
Test status
Simulation time 36349480607 ps
CPU time 17.39 seconds
Started Jan 21 01:32:07 PM PST 24
Finished Jan 21 01:32:26 PM PST 24
Peak memory 199916 kb
Host smart-95b48064-03a6-4052-abed-c16cc04181d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729028976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2729028976
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.21136823
Short name T601
Test name
Test status
Simulation time 3653774060 ps
CPU time 2.29 seconds
Started Jan 21 01:32:07 PM PST 24
Finished Jan 21 01:32:11 PM PST 24
Peak memory 195544 kb
Host smart-4ae77116-de44-427b-afb1-e2d4720b4ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21136823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.21136823
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1401099882
Short name T876
Test name
Test status
Simulation time 698897095 ps
CPU time 1.57 seconds
Started Jan 21 02:08:21 PM PST 24
Finished Jan 21 02:08:24 PM PST 24
Peak memory 197792 kb
Host smart-c3fb71d1-96c8-4396-b2e7-e9183657a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401099882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1401099882
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.523472887
Short name T373
Test name
Test status
Simulation time 230869978558 ps
CPU time 255.77 seconds
Started Jan 21 01:32:14 PM PST 24
Finished Jan 21 01:36:30 PM PST 24
Peak memory 199888 kb
Host smart-ae924f77-6db8-4761-91bd-8357d71520b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523472887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.523472887
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4031388580
Short name T729
Test name
Test status
Simulation time 301707736959 ps
CPU time 1257.24 seconds
Started Jan 21 02:22:40 PM PST 24
Finished Jan 21 02:43:37 PM PST 24
Peak memory 220680 kb
Host smart-656c67f1-cf61-494a-a6b3-21137baba741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031388580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4031388580
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1700458702
Short name T977
Test name
Test status
Simulation time 417676782 ps
CPU time 1.53 seconds
Started Jan 21 01:32:08 PM PST 24
Finished Jan 21 01:32:10 PM PST 24
Peak memory 197552 kb
Host smart-ee553fc8-7400-4f91-ab33-fe114ea78ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700458702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1700458702
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2078684854
Short name T585
Test name
Test status
Simulation time 945094256 ps
CPU time 0.92 seconds
Started Jan 21 01:31:58 PM PST 24
Finished Jan 21 01:32:00 PM PST 24
Peak memory 195668 kb
Host smart-ff023a8a-db0b-4951-bce3-1c81597a0a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078684854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2078684854
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.495432305
Short name T241
Test name
Test status
Simulation time 152270984891 ps
CPU time 233.94 seconds
Started Jan 21 01:44:32 PM PST 24
Finished Jan 21 01:48:27 PM PST 24
Peak memory 199884 kb
Host smart-ec59b4ad-e01d-4030-a77c-f93065fb2f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495432305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.495432305
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4127054533
Short name T346
Test name
Test status
Simulation time 183881631033 ps
CPU time 266.46 seconds
Started Jan 21 01:44:30 PM PST 24
Finished Jan 21 01:48:58 PM PST 24
Peak memory 199388 kb
Host smart-be25e8ee-a235-48eb-9189-608290c41019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127054533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4127054533
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3215906362
Short name T670
Test name
Test status
Simulation time 177772197717 ps
CPU time 67.2 seconds
Started Jan 21 01:44:35 PM PST 24
Finished Jan 21 01:45:43 PM PST 24
Peak memory 200004 kb
Host smart-e6efb5ff-a416-4c05-88e8-c6d7c930204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215906362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3215906362
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2277861494
Short name T223
Test name
Test status
Simulation time 110664171986 ps
CPU time 80.1 seconds
Started Jan 21 01:44:35 PM PST 24
Finished Jan 21 01:45:56 PM PST 24
Peak memory 199988 kb
Host smart-06d871b7-2835-400d-959c-44c0c145684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277861494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2277861494
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.853866299
Short name T742
Test name
Test status
Simulation time 77947866604 ps
CPU time 31.18 seconds
Started Jan 21 02:31:37 PM PST 24
Finished Jan 21 02:32:13 PM PST 24
Peak memory 199508 kb
Host smart-a734cc62-0bf6-4b03-8d5d-13515e4fc113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853866299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.853866299
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2963160579
Short name T1083
Test name
Test status
Simulation time 199542792871 ps
CPU time 18.84 seconds
Started Jan 21 01:44:32 PM PST 24
Finished Jan 21 01:44:51 PM PST 24
Peak memory 200032 kb
Host smart-4b2ba88f-ebf2-46a8-abab-b2668b2df986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963160579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2963160579
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.737979117
Short name T830
Test name
Test status
Simulation time 22400226014 ps
CPU time 39.75 seconds
Started Jan 21 01:44:36 PM PST 24
Finished Jan 21 01:45:17 PM PST 24
Peak memory 200012 kb
Host smart-50f2eec1-ce19-4193-8114-c16a246cf9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737979117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.737979117
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3944205899
Short name T811
Test name
Test status
Simulation time 27784536334 ps
CPU time 43.11 seconds
Started Jan 21 01:44:32 PM PST 24
Finished Jan 21 01:45:15 PM PST 24
Peak memory 198600 kb
Host smart-d588149f-000d-458c-8d69-2479b820016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944205899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3944205899
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1917135986
Short name T1208
Test name
Test status
Simulation time 88943145533 ps
CPU time 142.23 seconds
Started Jan 21 01:44:30 PM PST 24
Finished Jan 21 01:46:52 PM PST 24
Peak memory 199960 kb
Host smart-e0a3b27d-9f77-4e73-9de4-e26d87cd3976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917135986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1917135986
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3405639547
Short name T1038
Test name
Test status
Simulation time 34359716 ps
CPU time 0.57 seconds
Started Jan 21 01:26:00 PM PST 24
Finished Jan 21 01:26:01 PM PST 24
Peak memory 195600 kb
Host smart-48fbc557-55fc-4163-8126-2d82db85fcad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405639547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3405639547
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3546336409
Short name T195
Test name
Test status
Simulation time 260965719581 ps
CPU time 98.58 seconds
Started Jan 21 01:25:33 PM PST 24
Finished Jan 21 01:27:13 PM PST 24
Peak memory 200004 kb
Host smart-5eddd8cb-4059-4468-a3a7-39caa2b57c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546336409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3546336409
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1113894397
Short name T218
Test name
Test status
Simulation time 78524634820 ps
CPU time 29.59 seconds
Started Jan 21 01:25:33 PM PST 24
Finished Jan 21 01:26:03 PM PST 24
Peak memory 199344 kb
Host smart-b44bc3fc-80a3-4957-b8ec-b70e631424cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113894397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1113894397
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3558039349
Short name T642
Test name
Test status
Simulation time 477528833757 ps
CPU time 826.72 seconds
Started Jan 21 01:41:20 PM PST 24
Finished Jan 21 01:55:07 PM PST 24
Peak memory 199816 kb
Host smart-1a8e59cd-167a-49ae-a953-50072b55bfed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558039349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3558039349
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1787883867
Short name T504
Test name
Test status
Simulation time 131083234198 ps
CPU time 472.36 seconds
Started Jan 21 01:25:51 PM PST 24
Finished Jan 21 01:33:45 PM PST 24
Peak memory 199972 kb
Host smart-b8d186ca-8b95-4e1f-8143-e2e8577686b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787883867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1787883867
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.4104458308
Short name T566
Test name
Test status
Simulation time 9588580161 ps
CPU time 6.43 seconds
Started Jan 21 01:25:53 PM PST 24
Finished Jan 21 01:26:00 PM PST 24
Peak memory 199496 kb
Host smart-9e45468a-fe25-4c7a-8f81-d735f609af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104458308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.4104458308
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.4174348393
Short name T946
Test name
Test status
Simulation time 91818727770 ps
CPU time 181.93 seconds
Started Jan 21 01:25:41 PM PST 24
Finished Jan 21 01:28:44 PM PST 24
Peak memory 199824 kb
Host smart-056bc64d-c8c7-467c-9649-a0c7a842103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174348393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.4174348393
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2506685062
Short name T836
Test name
Test status
Simulation time 22166343396 ps
CPU time 278.36 seconds
Started Jan 21 01:25:50 PM PST 24
Finished Jan 21 01:30:29 PM PST 24
Peak memory 200004 kb
Host smart-14a53dce-dab1-4087-bb6e-cc12ddd5224c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506685062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2506685062
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.205121392
Short name T550
Test name
Test status
Simulation time 1512209214 ps
CPU time 5.26 seconds
Started Jan 21 02:42:38 PM PST 24
Finished Jan 21 02:42:43 PM PST 24
Peak memory 197892 kb
Host smart-3f279931-ef89-4030-a8a9-ddbe95a52093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205121392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.205121392
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4240377584
Short name T984
Test name
Test status
Simulation time 240029382020 ps
CPU time 492.03 seconds
Started Jan 21 01:25:40 PM PST 24
Finished Jan 21 01:33:53 PM PST 24
Peak memory 199996 kb
Host smart-7d62595f-ff41-4186-906d-0f303a9a47d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240377584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4240377584
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.357697312
Short name T1089
Test name
Test status
Simulation time 5750244909 ps
CPU time 10.87 seconds
Started Jan 21 01:25:41 PM PST 24
Finished Jan 21 01:25:53 PM PST 24
Peak memory 195560 kb
Host smart-8ed1b9c9-7861-479f-a53f-7b3b9b17dc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357697312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.357697312
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.4020565374
Short name T524
Test name
Test status
Simulation time 578730983 ps
CPU time 1.73 seconds
Started Jan 21 01:25:32 PM PST 24
Finished Jan 21 01:25:35 PM PST 24
Peak memory 199112 kb
Host smart-824329d0-19e4-42ce-9e23-f10ac4c21925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020565374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4020565374
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1556928271
Short name T425
Test name
Test status
Simulation time 233208966491 ps
CPU time 467.09 seconds
Started Jan 21 01:25:52 PM PST 24
Finished Jan 21 01:33:40 PM PST 24
Peak memory 199972 kb
Host smart-1288caf2-022f-45b9-955c-450dde38338b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556928271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1556928271
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3957612186
Short name T858
Test name
Test status
Simulation time 1675711755 ps
CPU time 1.95 seconds
Started Jan 21 01:30:37 PM PST 24
Finished Jan 21 01:30:41 PM PST 24
Peak memory 199256 kb
Host smart-5a3a953b-9268-4117-859b-704eb8c83532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957612186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3957612186
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2109324150
Short name T436
Test name
Test status
Simulation time 55348185790 ps
CPU time 94.85 seconds
Started Jan 21 01:25:34 PM PST 24
Finished Jan 21 01:27:09 PM PST 24
Peak memory 199880 kb
Host smart-49933002-296b-419b-8809-f1b292aab834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109324150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2109324150
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2241574448
Short name T493
Test name
Test status
Simulation time 73524198 ps
CPU time 0.57 seconds
Started Jan 21 01:32:39 PM PST 24
Finished Jan 21 01:32:44 PM PST 24
Peak memory 195480 kb
Host smart-1b3f2485-1a47-4656-8c05-1476f914c552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241574448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2241574448
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1795357532
Short name T769
Test name
Test status
Simulation time 47894011115 ps
CPU time 37.79 seconds
Started Jan 21 01:32:19 PM PST 24
Finished Jan 21 01:32:59 PM PST 24
Peak memory 198552 kb
Host smart-8c1fdd10-9e53-4a75-979b-e00ef1b74c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795357532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1795357532
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3819117990
Short name T1143
Test name
Test status
Simulation time 140577484715 ps
CPU time 137.21 seconds
Started Jan 21 02:02:13 PM PST 24
Finished Jan 21 02:04:31 PM PST 24
Peak memory 199948 kb
Host smart-16b2b207-614e-4b4f-98b9-5c2973f98661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819117990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3819117990
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2752611145
Short name T143
Test name
Test status
Simulation time 47166709452 ps
CPU time 25 seconds
Started Jan 21 01:32:19 PM PST 24
Finished Jan 21 01:32:46 PM PST 24
Peak memory 199980 kb
Host smart-390ffbaf-928d-4a7e-a79a-99686df215e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752611145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2752611145
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.142960238
Short name T1039
Test name
Test status
Simulation time 10634334157 ps
CPU time 2.36 seconds
Started Jan 21 01:32:19 PM PST 24
Finished Jan 21 01:32:24 PM PST 24
Peak memory 195544 kb
Host smart-bdb5ad8b-179c-4710-b0f5-e7c442dfb3f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142960238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.142960238
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4263858236
Short name T16
Test name
Test status
Simulation time 160425194180 ps
CPU time 143.5 seconds
Started Jan 21 01:32:34 PM PST 24
Finished Jan 21 01:35:00 PM PST 24
Peak memory 199960 kb
Host smart-cb4bf7c4-88c1-4c57-bd22-ad52db8a3c7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263858236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4263858236
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3364665209
Short name T505
Test name
Test status
Simulation time 6490976233 ps
CPU time 6.29 seconds
Started Jan 21 01:32:29 PM PST 24
Finished Jan 21 01:32:36 PM PST 24
Peak memory 198136 kb
Host smart-e75c77e8-ac6d-4a27-8f6f-9becbbc5c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364665209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3364665209
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.661291403
Short name T833
Test name
Test status
Simulation time 24254148998 ps
CPU time 39.95 seconds
Started Jan 21 01:32:28 PM PST 24
Finished Jan 21 01:33:09 PM PST 24
Peak memory 198368 kb
Host smart-fa81277c-9754-4140-a83c-10e1100693ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661291403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.661291403
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.461206460
Short name T263
Test name
Test status
Simulation time 11074213900 ps
CPU time 131.44 seconds
Started Jan 21 01:32:27 PM PST 24
Finished Jan 21 01:34:40 PM PST 24
Peak memory 199840 kb
Host smart-f43903a9-5824-41f6-b261-86838706f683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461206460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.461206460
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2983003111
Short name T694
Test name
Test status
Simulation time 3140499795 ps
CPU time 3.2 seconds
Started Jan 21 02:02:17 PM PST 24
Finished Jan 21 02:02:21 PM PST 24
Peak memory 198312 kb
Host smart-60ddecff-ef56-4dfe-92bf-69d137c2fcc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983003111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2983003111
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1896154067
Short name T764
Test name
Test status
Simulation time 113898863851 ps
CPU time 55.17 seconds
Started Jan 21 01:32:30 PM PST 24
Finished Jan 21 01:33:26 PM PST 24
Peak memory 199424 kb
Host smart-c690fd21-91dd-415a-b475-94cf3f7d8837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896154067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1896154067
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2937887849
Short name T693
Test name
Test status
Simulation time 1886145873 ps
CPU time 3.84 seconds
Started Jan 21 01:32:27 PM PST 24
Finished Jan 21 01:32:31 PM PST 24
Peak memory 195444 kb
Host smart-016d8092-1fad-4729-b39e-a815dcc68a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937887849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2937887849
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3026149415
Short name T450
Test name
Test status
Simulation time 295603232 ps
CPU time 1.26 seconds
Started Jan 21 01:32:19 PM PST 24
Finished Jan 21 01:32:23 PM PST 24
Peak memory 197156 kb
Host smart-673443d8-3155-43b7-b073-7c7897bad472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026149415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3026149415
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.194733854
Short name T376
Test name
Test status
Simulation time 54927403161 ps
CPU time 46.28 seconds
Started Jan 21 02:00:44 PM PST 24
Finished Jan 21 02:01:31 PM PST 24
Peak memory 199840 kb
Host smart-0321cc6e-a25a-4c6f-a4bf-b4bf884bb5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194733854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.194733854
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.444351911
Short name T877
Test name
Test status
Simulation time 1911222339 ps
CPU time 1.49 seconds
Started Jan 21 01:32:31 PM PST 24
Finished Jan 21 01:32:33 PM PST 24
Peak memory 196412 kb
Host smart-ff743036-b8e2-452b-9e4b-b846e6338c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444351911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.444351911
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1773008692
Short name T650
Test name
Test status
Simulation time 125512083423 ps
CPU time 161.71 seconds
Started Jan 21 01:32:19 PM PST 24
Finished Jan 21 01:35:03 PM PST 24
Peak memory 199888 kb
Host smart-5af94fd9-119d-449f-b4d8-5969406c76f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773008692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1773008692
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3918005981
Short name T302
Test name
Test status
Simulation time 141666286450 ps
CPU time 29.11 seconds
Started Jan 21 02:09:15 PM PST 24
Finished Jan 21 02:09:45 PM PST 24
Peak memory 199908 kb
Host smart-706bfc84-faaa-4f2b-8c03-0c7ad9ddf61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918005981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3918005981
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3418097695
Short name T564
Test name
Test status
Simulation time 37587814728 ps
CPU time 52.76 seconds
Started Jan 21 01:44:38 PM PST 24
Finished Jan 21 01:45:31 PM PST 24
Peak memory 199864 kb
Host smart-f7ba7ea6-24db-41c1-bb39-176afdb36e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418097695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3418097695
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.554062298
Short name T786
Test name
Test status
Simulation time 54723040488 ps
CPU time 16.34 seconds
Started Jan 21 02:45:13 PM PST 24
Finished Jan 21 02:45:30 PM PST 24
Peak memory 199972 kb
Host smart-c2697314-41de-428a-9557-f3148f88e14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554062298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.554062298
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.687649200
Short name T207
Test name
Test status
Simulation time 201849235113 ps
CPU time 279.17 seconds
Started Jan 21 01:44:36 PM PST 24
Finished Jan 21 01:49:16 PM PST 24
Peak memory 199864 kb
Host smart-7b7c5583-073b-48a4-be46-770ded87a267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687649200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.687649200
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1316239744
Short name T387
Test name
Test status
Simulation time 18936973932 ps
CPU time 26.61 seconds
Started Jan 21 01:44:38 PM PST 24
Finished Jan 21 01:45:06 PM PST 24
Peak memory 199940 kb
Host smart-f069d167-e803-45b7-950a-a0d517fc67c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316239744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1316239744
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2015465396
Short name T1135
Test name
Test status
Simulation time 28321343168 ps
CPU time 82.78 seconds
Started Jan 21 01:44:39 PM PST 24
Finished Jan 21 01:46:03 PM PST 24
Peak memory 199888 kb
Host smart-0ba30fab-824a-4dd5-812f-0fe666d65f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015465396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2015465396
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.122473869
Short name T980
Test name
Test status
Simulation time 154286830839 ps
CPU time 125 seconds
Started Jan 21 02:10:43 PM PST 24
Finished Jan 21 02:12:51 PM PST 24
Peak memory 199884 kb
Host smart-d9c55f76-1153-4c0e-9e95-7d8ba90b158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122473869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.122473869
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2202962464
Short name T1211
Test name
Test status
Simulation time 224680531571 ps
CPU time 87.08 seconds
Started Jan 21 03:01:11 PM PST 24
Finished Jan 21 03:02:44 PM PST 24
Peak memory 199988 kb
Host smart-ecad72b9-59c5-49a6-adb2-23faf6085ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202962464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2202962464
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3886675929
Short name T943
Test name
Test status
Simulation time 10958158 ps
CPU time 0.54 seconds
Started Jan 21 01:32:54 PM PST 24
Finished Jan 21 01:33:01 PM PST 24
Peak memory 194608 kb
Host smart-366d1814-c132-4451-ac27-d800a909de34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886675929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3886675929
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1990565159
Short name T1025
Test name
Test status
Simulation time 142012484716 ps
CPU time 52.61 seconds
Started Jan 21 01:32:38 PM PST 24
Finished Jan 21 01:33:36 PM PST 24
Peak memory 199728 kb
Host smart-31eaab89-bfd3-4c8d-9937-77b4be193abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990565159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1990565159
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2743053159
Short name T101
Test name
Test status
Simulation time 44222692556 ps
CPU time 59.86 seconds
Started Jan 21 01:32:37 PM PST 24
Finished Jan 21 01:33:42 PM PST 24
Peak memory 199684 kb
Host smart-1f79dfe5-fece-4ef7-a376-c806fdcad540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743053159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2743053159
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.665595166
Short name T674
Test name
Test status
Simulation time 285907793831 ps
CPU time 554.86 seconds
Started Jan 21 01:32:37 PM PST 24
Finished Jan 21 01:41:58 PM PST 24
Peak memory 199980 kb
Host smart-1f5cd1f1-24cc-48aa-a738-61dbedc1f1d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665595166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.665595166
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.89977931
Short name T698
Test name
Test status
Simulation time 93537296079 ps
CPU time 599.72 seconds
Started Jan 21 01:32:44 PM PST 24
Finished Jan 21 01:42:49 PM PST 24
Peak memory 200008 kb
Host smart-4e43cd6d-f1bf-4669-b123-49947db0e72a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89977931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.89977931
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3793499348
Short name T765
Test name
Test status
Simulation time 862213397 ps
CPU time 1.85 seconds
Started Jan 21 01:32:45 PM PST 24
Finished Jan 21 01:32:52 PM PST 24
Peak memory 195484 kb
Host smart-acbbb0e4-009b-4d6f-9d36-7ee52c9f3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793499348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3793499348
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1368086300
Short name T750
Test name
Test status
Simulation time 351475592211 ps
CPU time 52.63 seconds
Started Jan 21 01:32:46 PM PST 24
Finished Jan 21 01:33:44 PM PST 24
Peak memory 199880 kb
Host smart-36301b2d-ccca-444f-9986-b64c62a41b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368086300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1368086300
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2398818793
Short name T406
Test name
Test status
Simulation time 27326294697 ps
CPU time 758.15 seconds
Started Jan 21 01:32:44 PM PST 24
Finished Jan 21 01:45:28 PM PST 24
Peak memory 200024 kb
Host smart-59328410-57a5-4ef1-a569-5aa552cd134d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398818793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2398818793
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2466501693
Short name T785
Test name
Test status
Simulation time 3757872794 ps
CPU time 38.79 seconds
Started Jan 21 01:32:37 PM PST 24
Finished Jan 21 01:33:22 PM PST 24
Peak memory 198668 kb
Host smart-af0f982b-7957-4dae-af1b-fe118f4d1fcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466501693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2466501693
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1222599481
Short name T817
Test name
Test status
Simulation time 2743895275 ps
CPU time 4.85 seconds
Started Jan 21 02:25:02 PM PST 24
Finished Jan 21 02:25:08 PM PST 24
Peak memory 195496 kb
Host smart-9c08cece-914d-4055-acec-6e767aa9bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222599481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1222599481
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2432760132
Short name T1107
Test name
Test status
Simulation time 5975350918 ps
CPU time 29.47 seconds
Started Jan 21 01:32:43 PM PST 24
Finished Jan 21 01:33:16 PM PST 24
Peak memory 199128 kb
Host smart-f8d92de2-938b-4acd-8a2d-69d818fc475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432760132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2432760132
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.356777160
Short name T957
Test name
Test status
Simulation time 130100447605 ps
CPU time 680.69 seconds
Started Jan 21 01:32:52 PM PST 24
Finished Jan 21 01:44:14 PM PST 24
Peak memory 222484 kb
Host smart-ed2a61f2-9da2-4911-8545-5a3de1dc86f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356777160 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.356777160
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3822185472
Short name T962
Test name
Test status
Simulation time 3796693197 ps
CPU time 1.76 seconds
Started Jan 21 01:32:46 PM PST 24
Finished Jan 21 01:32:53 PM PST 24
Peak memory 198236 kb
Host smart-3aae9360-8723-4fbc-9e7f-eedb82e63219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822185472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3822185472
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3137110477
Short name T784
Test name
Test status
Simulation time 92276103397 ps
CPU time 225.19 seconds
Started Jan 21 01:32:43 PM PST 24
Finished Jan 21 01:36:32 PM PST 24
Peak memory 199940 kb
Host smart-f6710f52-d181-4401-97de-95313a6b3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137110477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3137110477
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1940948484
Short name T1043
Test name
Test status
Simulation time 12657159635 ps
CPU time 11.54 seconds
Started Jan 21 01:44:51 PM PST 24
Finished Jan 21 01:45:07 PM PST 24
Peak memory 200064 kb
Host smart-a434e606-4402-4600-b41f-f3e343d34126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940948484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1940948484
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4166702427
Short name T1009
Test name
Test status
Simulation time 34962515463 ps
CPU time 56.3 seconds
Started Jan 21 01:44:53 PM PST 24
Finished Jan 21 01:45:51 PM PST 24
Peak memory 199940 kb
Host smart-835f9821-5932-472d-954e-41e3ef41da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166702427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4166702427
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2705487043
Short name T322
Test name
Test status
Simulation time 36037337194 ps
CPU time 10.27 seconds
Started Jan 21 01:45:01 PM PST 24
Finished Jan 21 01:45:12 PM PST 24
Peak memory 198304 kb
Host smart-67d23531-54d4-413e-ba69-7b83a1b53e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705487043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2705487043
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1791481279
Short name T252
Test name
Test status
Simulation time 219095789720 ps
CPU time 110.41 seconds
Started Jan 21 01:44:56 PM PST 24
Finished Jan 21 01:46:49 PM PST 24
Peak memory 199968 kb
Host smart-be08a8ae-5eb0-43b4-9b13-6905cacd95cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791481279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1791481279
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3928271284
Short name T875
Test name
Test status
Simulation time 11745322958 ps
CPU time 19.95 seconds
Started Jan 21 01:44:56 PM PST 24
Finished Jan 21 01:45:18 PM PST 24
Peak memory 199136 kb
Host smart-a61ccbab-732d-4ed5-a9b6-2525726c8ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928271284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3928271284
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1377579926
Short name T264
Test name
Test status
Simulation time 106263422813 ps
CPU time 50.32 seconds
Started Jan 21 01:44:57 PM PST 24
Finished Jan 21 01:45:49 PM PST 24
Peak memory 200008 kb
Host smart-c6c801c4-9d94-4b11-a64d-1a3efec07279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377579926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1377579926
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2112290194
Short name T853
Test name
Test status
Simulation time 40140509646 ps
CPU time 14.63 seconds
Started Jan 21 01:45:01 PM PST 24
Finished Jan 21 01:45:17 PM PST 24
Peak memory 200000 kb
Host smart-6443ccb0-ba64-4d31-adc7-ade66ebd0ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112290194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2112290194
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2017215646
Short name T743
Test name
Test status
Simulation time 106219045549 ps
CPU time 28.47 seconds
Started Jan 21 02:15:43 PM PST 24
Finished Jan 21 02:16:13 PM PST 24
Peak memory 199848 kb
Host smart-0ee35829-af80-4cca-abc1-e2de26cc66f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017215646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2017215646
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1002673632
Short name T919
Test name
Test status
Simulation time 20793974 ps
CPU time 0.56 seconds
Started Jan 21 02:51:13 PM PST 24
Finished Jan 21 02:51:14 PM PST 24
Peak memory 195524 kb
Host smart-6ae1f8f9-409f-435e-b728-38e997f327a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002673632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1002673632
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2314884956
Short name T803
Test name
Test status
Simulation time 58924860005 ps
CPU time 51.5 seconds
Started Jan 21 01:32:53 PM PST 24
Finished Jan 21 01:33:51 PM PST 24
Peak memory 199928 kb
Host smart-bbd853a2-9902-4fad-9b4d-c104453f3773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314884956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2314884956
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2479298956
Short name T972
Test name
Test status
Simulation time 64930119764 ps
CPU time 81.04 seconds
Started Jan 21 01:54:51 PM PST 24
Finished Jan 21 01:56:14 PM PST 24
Peak memory 199904 kb
Host smart-da48b97d-d800-4747-81a0-f412d58e2ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479298956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2479298956
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_intr.1759279332
Short name T1118
Test name
Test status
Simulation time 6783617877 ps
CPU time 2.96 seconds
Started Jan 21 01:32:51 PM PST 24
Finished Jan 21 01:32:56 PM PST 24
Peak memory 195884 kb
Host smart-5b2af653-7c27-46a0-9262-3d93d16f0ecf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759279332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1759279332
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2193056213
Short name T979
Test name
Test status
Simulation time 87618600558 ps
CPU time 431.16 seconds
Started Jan 21 01:33:04 PM PST 24
Finished Jan 21 01:40:19 PM PST 24
Peak memory 199960 kb
Host smart-532be7c1-5ff7-4bd8-8b02-66a635fddff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193056213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2193056213
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1335400147
Short name T1175
Test name
Test status
Simulation time 39699854075 ps
CPU time 16.19 seconds
Started Jan 21 02:46:56 PM PST 24
Finished Jan 21 02:47:12 PM PST 24
Peak memory 198216 kb
Host smart-af34765f-f194-4c0e-8b2d-a7143853387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335400147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1335400147
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1388818196
Short name T1123
Test name
Test status
Simulation time 11705511059 ps
CPU time 597.81 seconds
Started Jan 21 01:33:05 PM PST 24
Finished Jan 21 01:43:06 PM PST 24
Peak memory 199968 kb
Host smart-67c5c33a-e9de-4618-9040-578fde50c433
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388818196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1388818196
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.296580851
Short name T1077
Test name
Test status
Simulation time 3698810871 ps
CPU time 11.85 seconds
Started Jan 21 01:32:53 PM PST 24
Finished Jan 21 01:33:11 PM PST 24
Peak memory 198692 kb
Host smart-f805d5aa-e3fb-4edd-a4f1-b8036872b298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=296580851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.296580851
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1090432592
Short name T131
Test name
Test status
Simulation time 121958795314 ps
CPU time 174.93 seconds
Started Jan 21 01:33:01 PM PST 24
Finished Jan 21 01:36:00 PM PST 24
Peak memory 199992 kb
Host smart-26913411-a507-4030-9d1b-9079eba50154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090432592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1090432592
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2116678140
Short name T699
Test name
Test status
Simulation time 6179901555 ps
CPU time 10.66 seconds
Started Jan 21 01:33:01 PM PST 24
Finished Jan 21 01:33:16 PM PST 24
Peak memory 195544 kb
Host smart-c3211484-f4de-435f-831d-55dfb753b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116678140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2116678140
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1561895730
Short name T710
Test name
Test status
Simulation time 483486421 ps
CPU time 1.15 seconds
Started Jan 21 01:32:52 PM PST 24
Finished Jan 21 01:32:58 PM PST 24
Peak memory 197912 kb
Host smart-58ffdc98-6fdc-4d5a-85a7-f517d3c4add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561895730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1561895730
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.11573712
Short name T307
Test name
Test status
Simulation time 241721253155 ps
CPU time 227.15 seconds
Started Jan 21 01:33:02 PM PST 24
Finished Jan 21 01:36:54 PM PST 24
Peak memory 200008 kb
Host smart-05bb137a-7bee-438d-8404-5659729a11b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11573712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.11573712
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.4092035496
Short name T974
Test name
Test status
Simulation time 169122192716 ps
CPU time 633.79 seconds
Started Jan 21 01:33:01 PM PST 24
Finished Jan 21 01:43:37 PM PST 24
Peak memory 224900 kb
Host smart-eb07cf2d-d1eb-420a-997b-ee87fdd1d55b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092035496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4092035496
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4055727603
Short name T638
Test name
Test status
Simulation time 1112847234 ps
CPU time 3.08 seconds
Started Jan 21 01:33:02 PM PST 24
Finished Jan 21 01:33:10 PM PST 24
Peak memory 198196 kb
Host smart-d421421f-c846-41e3-971f-9361fa98b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055727603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4055727603
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3918334762
Short name T1150
Test name
Test status
Simulation time 7814988178 ps
CPU time 8.32 seconds
Started Jan 21 01:32:53 PM PST 24
Finished Jan 21 01:33:09 PM PST 24
Peak memory 199968 kb
Host smart-f3be39f2-d0d7-450e-873f-ffadbf98c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918334762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3918334762
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3669696238
Short name T1162
Test name
Test status
Simulation time 67801956977 ps
CPU time 106.82 seconds
Started Jan 21 01:44:57 PM PST 24
Finished Jan 21 01:46:46 PM PST 24
Peak memory 199972 kb
Host smart-552dc08a-c7ec-46dc-b618-a3dcadaf4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669696238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3669696238
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3660885164
Short name T245
Test name
Test status
Simulation time 37631828294 ps
CPU time 17.95 seconds
Started Jan 21 01:44:56 PM PST 24
Finished Jan 21 01:45:16 PM PST 24
Peak memory 199692 kb
Host smart-ec693177-162e-452f-b78b-0a6faf003e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660885164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3660885164
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3714349780
Short name T521
Test name
Test status
Simulation time 19934316780 ps
CPU time 33.47 seconds
Started Jan 21 01:45:06 PM PST 24
Finished Jan 21 01:45:41 PM PST 24
Peak memory 199964 kb
Host smart-fa4ac003-e94f-46b1-b422-e6816bfbc910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714349780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3714349780
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1232606191
Short name T248
Test name
Test status
Simulation time 149905902181 ps
CPU time 66.09 seconds
Started Jan 21 01:45:06 PM PST 24
Finished Jan 21 01:46:14 PM PST 24
Peak memory 199804 kb
Host smart-d21def0e-c78f-49de-9415-371c6dfb6bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232606191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1232606191
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3043577300
Short name T329
Test name
Test status
Simulation time 16959545138 ps
CPU time 14.04 seconds
Started Jan 21 01:45:05 PM PST 24
Finished Jan 21 01:45:20 PM PST 24
Peak memory 199244 kb
Host smart-3d366cf5-46be-4be2-a5d0-9da7bfcf2fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043577300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3043577300
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.418231558
Short name T240
Test name
Test status
Simulation time 26779662333 ps
CPU time 11.66 seconds
Started Jan 21 01:45:06 PM PST 24
Finished Jan 21 01:45:18 PM PST 24
Peak memory 199240 kb
Host smart-fcc489e9-34b1-497f-98f3-ada28e951770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418231558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.418231558
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3759356633
Short name T1027
Test name
Test status
Simulation time 35567839161 ps
CPU time 60.84 seconds
Started Jan 21 03:58:05 PM PST 24
Finished Jan 21 03:59:07 PM PST 24
Peak memory 199984 kb
Host smart-bbe7b61e-813b-4872-b967-a18b44f7e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759356633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3759356633
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1310503500
Short name T276
Test name
Test status
Simulation time 237466926732 ps
CPU time 217.28 seconds
Started Jan 21 01:45:07 PM PST 24
Finished Jan 21 01:48:45 PM PST 24
Peak memory 199916 kb
Host smart-9f764dee-d7b9-4492-ba00-68c4a8d0129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310503500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1310503500
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3597859050
Short name T809
Test name
Test status
Simulation time 143581861809 ps
CPU time 51.76 seconds
Started Jan 21 01:45:09 PM PST 24
Finished Jan 21 01:46:01 PM PST 24
Peak memory 199512 kb
Host smart-4b39a9b8-fddd-446e-86dc-33344432e85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597859050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3597859050
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.483838662
Short name T89
Test name
Test status
Simulation time 11233760 ps
CPU time 0.55 seconds
Started Jan 21 01:33:14 PM PST 24
Finished Jan 21 01:33:17 PM PST 24
Peak memory 194680 kb
Host smart-ffa7e897-f40f-439c-81dc-fba4be3cbd77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483838662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.483838662
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2878815054
Short name T1160
Test name
Test status
Simulation time 55586031287 ps
CPU time 91.9 seconds
Started Jan 21 01:33:01 PM PST 24
Finished Jan 21 01:34:37 PM PST 24
Peak memory 200032 kb
Host smart-7518878d-e638-4a7c-ba47-44e03ddbf6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878815054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2878815054
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1061359840
Short name T350
Test name
Test status
Simulation time 132470504257 ps
CPU time 211.88 seconds
Started Jan 21 01:33:04 PM PST 24
Finished Jan 21 01:36:40 PM PST 24
Peak memory 199924 kb
Host smart-cf227065-5017-4714-8c50-aa9de524b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061359840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1061359840
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2931478608
Short name T844
Test name
Test status
Simulation time 43638712927 ps
CPU time 47.69 seconds
Started Jan 21 01:33:01 PM PST 24
Finished Jan 21 01:33:51 PM PST 24
Peak memory 199928 kb
Host smart-55abb5b7-7976-46cb-8f6c-745b64ba84f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931478608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2931478608
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1758706478
Short name T605
Test name
Test status
Simulation time 135646173568 ps
CPU time 56.41 seconds
Started Jan 21 01:33:12 PM PST 24
Finished Jan 21 01:34:10 PM PST 24
Peak memory 199764 kb
Host smart-44d69368-9aec-4c7b-81fa-1e15af16f83a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758706478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1758706478
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.870888125
Short name T794
Test name
Test status
Simulation time 106618480776 ps
CPU time 175.34 seconds
Started Jan 21 01:33:16 PM PST 24
Finished Jan 21 01:36:13 PM PST 24
Peak memory 199976 kb
Host smart-405c7be3-9923-44df-9c0b-752943bd7fbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870888125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.870888125
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3809570144
Short name T1006
Test name
Test status
Simulation time 7014982667 ps
CPU time 8.07 seconds
Started Jan 21 02:15:50 PM PST 24
Finished Jan 21 02:15:59 PM PST 24
Peak memory 198672 kb
Host smart-d475a42b-017a-47a2-ae94-83c5d2767ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809570144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3809570144
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1810640999
Short name T1199
Test name
Test status
Simulation time 136966255447 ps
CPU time 67.14 seconds
Started Jan 21 01:54:12 PM PST 24
Finished Jan 21 01:55:20 PM PST 24
Peak memory 200164 kb
Host smart-e81cc998-6511-4097-b88c-dcdab28acbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810640999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1810640999
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3302708933
Short name T706
Test name
Test status
Simulation time 15753129368 ps
CPU time 878.06 seconds
Started Jan 21 01:33:16 PM PST 24
Finished Jan 21 01:47:56 PM PST 24
Peak memory 200004 kb
Host smart-e638da88-9927-439b-97ab-60056b06f355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302708933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3302708933
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4143147910
Short name T906
Test name
Test status
Simulation time 3622336211 ps
CPU time 27.04 seconds
Started Jan 21 02:29:42 PM PST 24
Finished Jan 21 02:30:10 PM PST 24
Peak memory 197696 kb
Host smart-225688e4-adc5-4d3c-aa15-f9979eeef059
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143147910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4143147910
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3602681138
Short name T865
Test name
Test status
Simulation time 228627815264 ps
CPU time 138.88 seconds
Started Jan 21 01:33:13 PM PST 24
Finished Jan 21 01:35:33 PM PST 24
Peak memory 199692 kb
Host smart-b6de652a-efef-4936-ac88-fa9e5a5b0ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602681138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3602681138
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2793373795
Short name T998
Test name
Test status
Simulation time 1820683792 ps
CPU time 1.86 seconds
Started Jan 21 01:33:16 PM PST 24
Finished Jan 21 01:33:19 PM PST 24
Peak memory 195480 kb
Host smart-da5d57e8-2f81-40a1-b130-e36fc9e11627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793373795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2793373795
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.109154336
Short name T11
Test name
Test status
Simulation time 564937443 ps
CPU time 1.65 seconds
Started Jan 21 01:33:02 PM PST 24
Finished Jan 21 01:33:08 PM PST 24
Peak memory 197740 kb
Host smart-9ce0deee-7d10-4f2e-af8f-5bc1985d68a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109154336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.109154336
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.505373579
Short name T647
Test name
Test status
Simulation time 34289063224 ps
CPU time 447.53 seconds
Started Jan 21 02:15:52 PM PST 24
Finished Jan 21 02:23:20 PM PST 24
Peak memory 208280 kb
Host smart-d664c39d-75ef-4bd5-b40f-2f47cc37422a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505373579 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.505373579
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3058500004
Short name T1024
Test name
Test status
Simulation time 1026221919 ps
CPU time 3.9 seconds
Started Jan 21 02:30:43 PM PST 24
Finished Jan 21 02:30:47 PM PST 24
Peak memory 198156 kb
Host smart-fa801047-2d4f-47bf-b8c2-9dd761d61302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058500004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3058500004
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1828433987
Short name T689
Test name
Test status
Simulation time 8840017129 ps
CPU time 13.77 seconds
Started Jan 21 01:33:02 PM PST 24
Finished Jan 21 01:33:21 PM PST 24
Peak memory 199884 kb
Host smart-73b97479-1f94-489a-9858-058aa9391303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828433987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1828433987
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1695303933
Short name T1030
Test name
Test status
Simulation time 32799300660 ps
CPU time 11.85 seconds
Started Jan 21 02:47:49 PM PST 24
Finished Jan 21 02:48:03 PM PST 24
Peak memory 199844 kb
Host smart-d17f6222-3e50-41c4-b1a9-f54bf2aeeed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695303933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1695303933
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1403033
Short name T1144
Test name
Test status
Simulation time 74612468776 ps
CPU time 29.44 seconds
Started Jan 21 01:45:08 PM PST 24
Finished Jan 21 01:45:39 PM PST 24
Peak memory 199952 kb
Host smart-419b808f-557c-4bdf-98ef-84befc462d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1403033
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2239642052
Short name T1223
Test name
Test status
Simulation time 148880857387 ps
CPU time 38.09 seconds
Started Jan 21 01:45:07 PM PST 24
Finished Jan 21 01:45:47 PM PST 24
Peak memory 199964 kb
Host smart-44cfc3ec-a602-4ef4-b64f-a64cb3834902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239642052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2239642052
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.72083818
Short name T936
Test name
Test status
Simulation time 48478391699 ps
CPU time 72.01 seconds
Started Jan 21 01:45:08 PM PST 24
Finished Jan 21 01:46:22 PM PST 24
Peak memory 199804 kb
Host smart-a02c6aea-2512-4637-b05f-397a7203a3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72083818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.72083818
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2683768010
Short name T231
Test name
Test status
Simulation time 21796137975 ps
CPU time 37.69 seconds
Started Jan 21 01:45:13 PM PST 24
Finished Jan 21 01:45:51 PM PST 24
Peak memory 200020 kb
Host smart-0ebfcc8b-cb12-4b87-a6ea-9d59e837788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683768010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2683768010
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.516922858
Short name T230
Test name
Test status
Simulation time 136518414389 ps
CPU time 228.95 seconds
Started Jan 21 02:13:09 PM PST 24
Finished Jan 21 02:16:59 PM PST 24
Peak memory 199964 kb
Host smart-1c375acc-929d-456a-a9da-c531d88df1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516922858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.516922858
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1187541273
Short name T197
Test name
Test status
Simulation time 156498355673 ps
CPU time 58.07 seconds
Started Jan 21 01:45:14 PM PST 24
Finished Jan 21 01:46:13 PM PST 24
Peak memory 199968 kb
Host smart-e7bc40a2-90f7-458a-9317-40cb13f69b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187541273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1187541273
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.324066836
Short name T377
Test name
Test status
Simulation time 194139561163 ps
CPU time 45.86 seconds
Started Jan 21 01:45:13 PM PST 24
Finished Jan 21 01:45:59 PM PST 24
Peak memory 199932 kb
Host smart-f307ed03-6cae-494f-9e82-c9d9a1b46824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324066836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.324066836
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1975313457
Short name T834
Test name
Test status
Simulation time 57645482 ps
CPU time 0.54 seconds
Started Jan 21 01:33:33 PM PST 24
Finished Jan 21 01:33:39 PM PST 24
Peak memory 195588 kb
Host smart-566ff8a3-29ca-4804-8ace-09648bdf9741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975313457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1975313457
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2616096794
Short name T660
Test name
Test status
Simulation time 143631279994 ps
CPU time 169.82 seconds
Started Jan 21 01:33:26 PM PST 24
Finished Jan 21 01:36:17 PM PST 24
Peak memory 199932 kb
Host smart-8a4e9180-b548-4a56-ae7f-33a85d320b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616096794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2616096794
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3940439707
Short name T1149
Test name
Test status
Simulation time 245282961635 ps
CPU time 752.04 seconds
Started Jan 21 02:13:37 PM PST 24
Finished Jan 21 02:26:12 PM PST 24
Peak memory 199676 kb
Host smart-08e866a4-c238-4301-958a-8a9065fe9e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940439707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3940439707
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.872346911
Short name T1056
Test name
Test status
Simulation time 35616166798 ps
CPU time 17.35 seconds
Started Jan 21 01:33:28 PM PST 24
Finished Jan 21 01:33:46 PM PST 24
Peak memory 199740 kb
Host smart-9dbbe47a-f38e-4e65-87c7-bf73f4037440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872346911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.872346911
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2072130878
Short name T892
Test name
Test status
Simulation time 95431647231 ps
CPU time 38.68 seconds
Started Jan 21 01:33:28 PM PST 24
Finished Jan 21 01:34:08 PM PST 24
Peak memory 199476 kb
Host smart-459c8847-9741-4c4d-b19c-7a30946d5376
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072130878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2072130878
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.999880000
Short name T545
Test name
Test status
Simulation time 94439758482 ps
CPU time 157.87 seconds
Started Jan 21 01:33:35 PM PST 24
Finished Jan 21 01:36:17 PM PST 24
Peak memory 199860 kb
Host smart-d2e8d971-433b-4186-b1ca-44eac8928511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999880000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.999880000
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2931891833
Short name T537
Test name
Test status
Simulation time 7040944608 ps
CPU time 13.8 seconds
Started Jan 21 01:33:35 PM PST 24
Finished Jan 21 01:33:53 PM PST 24
Peak memory 198740 kb
Host smart-1787166c-73d9-47e8-8eea-967048e6f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931891833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2931891833
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.324071461
Short name T1109
Test name
Test status
Simulation time 48546263222 ps
CPU time 21.92 seconds
Started Jan 21 02:42:11 PM PST 24
Finished Jan 21 02:42:34 PM PST 24
Peak memory 198500 kb
Host smart-291934e6-ff8f-4304-89b0-8393e0905a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324071461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.324071461
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2656114052
Short name T690
Test name
Test status
Simulation time 14077807012 ps
CPU time 373.57 seconds
Started Jan 21 01:33:33 PM PST 24
Finished Jan 21 01:39:53 PM PST 24
Peak memory 199980 kb
Host smart-16c9610d-35b8-4def-93fa-973c920606ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656114052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2656114052
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.157376019
Short name T1097
Test name
Test status
Simulation time 2232852683 ps
CPU time 13.45 seconds
Started Jan 21 01:33:26 PM PST 24
Finished Jan 21 01:33:41 PM PST 24
Peak memory 197688 kb
Host smart-f3c68cfd-f4db-4254-ba8c-9aeefd5a8158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157376019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.157376019
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3602180529
Short name T973
Test name
Test status
Simulation time 47255445757 ps
CPU time 18.66 seconds
Started Jan 21 03:24:49 PM PST 24
Finished Jan 21 03:25:11 PM PST 24
Peak memory 199940 kb
Host smart-39965d2d-9176-4686-b48d-a8592d1496c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602180529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3602180529
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1840020423
Short name T815
Test name
Test status
Simulation time 4006383961 ps
CPU time 6.55 seconds
Started Jan 21 01:33:26 PM PST 24
Finished Jan 21 01:33:34 PM PST 24
Peak memory 195748 kb
Host smart-4a9860c2-3a16-40c5-a7ab-f118fbc2c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840020423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1840020423
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2937125532
Short name T947
Test name
Test status
Simulation time 5628029949 ps
CPU time 15 seconds
Started Jan 21 01:57:22 PM PST 24
Finished Jan 21 01:57:38 PM PST 24
Peak memory 199828 kb
Host smart-c34856ce-c358-4deb-9e7e-6189f1e9e490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937125532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2937125532
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3105355160
Short name T232
Test name
Test status
Simulation time 337861004865 ps
CPU time 983.89 seconds
Started Jan 21 01:33:36 PM PST 24
Finished Jan 21 01:50:03 PM PST 24
Peak memory 216572 kb
Host smart-5121fa72-4a8e-4b01-8982-08b12efde7ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105355160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3105355160
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3492921862
Short name T614
Test name
Test status
Simulation time 1211695071 ps
CPU time 2.81 seconds
Started Jan 21 01:33:25 PM PST 24
Finished Jan 21 01:33:30 PM PST 24
Peak memory 198448 kb
Host smart-3dc7a2f7-1d18-41d5-a541-a4423665270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492921862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3492921862
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3442720407
Short name T1154
Test name
Test status
Simulation time 167613418098 ps
CPU time 79.72 seconds
Started Jan 21 01:33:17 PM PST 24
Finished Jan 21 01:34:38 PM PST 24
Peak memory 199924 kb
Host smart-51489e85-173a-46e8-92b6-df821e6bb4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442720407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3442720407
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4266510934
Short name T110
Test name
Test status
Simulation time 35438396764 ps
CPU time 52.23 seconds
Started Jan 21 02:21:55 PM PST 24
Finished Jan 21 02:22:48 PM PST 24
Peak memory 199972 kb
Host smart-2c655288-33fa-4d8c-b203-32a5abe8db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266510934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4266510934
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1633362096
Short name T214
Test name
Test status
Simulation time 28396695377 ps
CPU time 66.44 seconds
Started Jan 21 01:45:13 PM PST 24
Finished Jan 21 01:46:20 PM PST 24
Peak memory 199968 kb
Host smart-a5d644e4-fd53-4830-b574-a564a71dc1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633362096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1633362096
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1538629563
Short name T754
Test name
Test status
Simulation time 64132711528 ps
CPU time 58.76 seconds
Started Jan 21 01:45:22 PM PST 24
Finished Jan 21 01:46:22 PM PST 24
Peak memory 200060 kb
Host smart-a40263d0-abd4-4ef0-a2b4-caab9017e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538629563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1538629563
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3582651717
Short name T139
Test name
Test status
Simulation time 125008298403 ps
CPU time 25.73 seconds
Started Jan 21 01:45:29 PM PST 24
Finished Jan 21 01:45:56 PM PST 24
Peak memory 200004 kb
Host smart-12f56165-7abf-441f-912f-97d2d6c083ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582651717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3582651717
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.809365616
Short name T701
Test name
Test status
Simulation time 16943071401 ps
CPU time 15.31 seconds
Started Jan 21 01:45:28 PM PST 24
Finished Jan 21 01:45:44 PM PST 24
Peak memory 199360 kb
Host smart-9d6565ff-ceae-4d73-96d2-0be6fd8c8f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809365616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.809365616
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3089683869
Short name T881
Test name
Test status
Simulation time 30050007535 ps
CPU time 12.44 seconds
Started Jan 21 01:45:27 PM PST 24
Finished Jan 21 01:45:40 PM PST 24
Peak memory 199912 kb
Host smart-ecaf33b5-f9de-4122-95c8-399f7f29dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089683869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3089683869
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1816653367
Short name T1190
Test name
Test status
Simulation time 127147808976 ps
CPU time 51.82 seconds
Started Jan 21 01:45:23 PM PST 24
Finished Jan 21 01:46:16 PM PST 24
Peak memory 199896 kb
Host smart-521bf27f-d5e4-434f-9318-26b170cecedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816653367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1816653367
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1033224050
Short name T999
Test name
Test status
Simulation time 63793612771 ps
CPU time 45.39 seconds
Started Jan 21 01:45:29 PM PST 24
Finished Jan 21 01:46:15 PM PST 24
Peak memory 199956 kb
Host smart-f72b96e2-775d-4199-a641-43ea7203c20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033224050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1033224050
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1957822530
Short name T869
Test name
Test status
Simulation time 39807247 ps
CPU time 0.57 seconds
Started Jan 21 01:34:03 PM PST 24
Finished Jan 21 01:34:05 PM PST 24
Peak memory 193364 kb
Host smart-2e24fd0e-0a5e-4158-b4c1-c8307ca44d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957822530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1957822530
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.257602795
Short name T275
Test name
Test status
Simulation time 64959314547 ps
CPU time 28.52 seconds
Started Jan 21 01:33:42 PM PST 24
Finished Jan 21 01:34:13 PM PST 24
Peak memory 199868 kb
Host smart-63e235fe-db3d-4ef7-a3c1-985d28c76baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257602795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.257602795
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3009278115
Short name T668
Test name
Test status
Simulation time 107081308031 ps
CPU time 94.63 seconds
Started Jan 21 01:33:43 PM PST 24
Finished Jan 21 01:35:19 PM PST 24
Peak memory 199936 kb
Host smart-01d82974-3fa7-4593-8e7f-be6c69d36bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009278115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3009278115
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2843529877
Short name T602
Test name
Test status
Simulation time 23198187954 ps
CPU time 15.67 seconds
Started Jan 21 01:33:41 PM PST 24
Finished Jan 21 01:34:00 PM PST 24
Peak memory 198728 kb
Host smart-4d690699-aa69-4104-aeb2-4a90683ecc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843529877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2843529877
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3164138666
Short name T136
Test name
Test status
Simulation time 1446797763843 ps
CPU time 1983.65 seconds
Started Jan 21 01:33:53 PM PST 24
Finished Jan 21 02:06:58 PM PST 24
Peak memory 200008 kb
Host smart-5b971d46-c0c9-44ae-b099-ceae987a9853
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164138666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3164138666
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1144676908
Short name T740
Test name
Test status
Simulation time 139078040794 ps
CPU time 499.42 seconds
Started Jan 21 01:33:53 PM PST 24
Finished Jan 21 01:42:14 PM PST 24
Peak memory 200032 kb
Host smart-d7acdded-1009-45db-a40c-8ade1e3492e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144676908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1144676908
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.841984788
Short name T832
Test name
Test status
Simulation time 2872585231 ps
CPU time 2.09 seconds
Started Jan 21 01:33:49 PM PST 24
Finished Jan 21 01:33:52 PM PST 24
Peak memory 198016 kb
Host smart-c0818420-0830-45bf-b358-bbab46a8dd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841984788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.841984788
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3630931782
Short name T130
Test name
Test status
Simulation time 66136768162 ps
CPU time 13.29 seconds
Started Jan 21 01:33:49 PM PST 24
Finished Jan 21 01:34:04 PM PST 24
Peak memory 195344 kb
Host smart-5bfe1432-361e-4e3e-828f-681a87bbbaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630931782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3630931782
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2785149705
Short name T798
Test name
Test status
Simulation time 12723183593 ps
CPU time 294.8 seconds
Started Jan 21 01:33:50 PM PST 24
Finished Jan 21 01:38:46 PM PST 24
Peak memory 199992 kb
Host smart-c18fce9f-cec5-46b1-98eb-e8cc6af98523
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785149705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2785149705
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1763703399
Short name T607
Test name
Test status
Simulation time 2315110281 ps
CPU time 4.02 seconds
Started Jan 21 01:33:42 PM PST 24
Finished Jan 21 01:33:48 PM PST 24
Peak memory 198484 kb
Host smart-986a6463-a865-4e41-9ae0-f507aa12cd1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763703399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1763703399
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3316119159
Short name T746
Test name
Test status
Simulation time 84082713833 ps
CPU time 132.79 seconds
Started Jan 21 01:33:51 PM PST 24
Finished Jan 21 01:36:05 PM PST 24
Peak memory 199912 kb
Host smart-abf6a84f-9061-4c27-a0b4-963beb927b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316119159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3316119159
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.62195197
Short name T922
Test name
Test status
Simulation time 1980614943 ps
CPU time 1.45 seconds
Started Jan 21 01:33:51 PM PST 24
Finished Jan 21 01:33:55 PM PST 24
Peak memory 195408 kb
Host smart-3056ccbc-2a4f-45c6-9b7a-1afafa12d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62195197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.62195197
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.779675483
Short name T930
Test name
Test status
Simulation time 323549951 ps
CPU time 1.15 seconds
Started Jan 21 01:33:45 PM PST 24
Finished Jan 21 01:33:48 PM PST 24
Peak memory 198060 kb
Host smart-1296e562-00d0-4187-8d6f-3dc6c1c08937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779675483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.779675483
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3570923950
Short name T630
Test name
Test status
Simulation time 186170141945 ps
CPU time 192.36 seconds
Started Jan 21 01:34:02 PM PST 24
Finished Jan 21 01:37:16 PM PST 24
Peak memory 208372 kb
Host smart-d710e068-1f68-477c-8de9-b43c4f4993e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570923950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3570923950
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1643259434
Short name T1152
Test name
Test status
Simulation time 6874582921 ps
CPU time 11.75 seconds
Started Jan 21 01:33:56 PM PST 24
Finished Jan 21 01:34:09 PM PST 24
Peak memory 200028 kb
Host smart-b113649f-7df0-4db3-b0af-49996bfe9bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643259434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1643259434
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3856830796
Short name T156
Test name
Test status
Simulation time 46499708047 ps
CPU time 11.72 seconds
Started Jan 21 02:11:06 PM PST 24
Finished Jan 21 02:11:18 PM PST 24
Peak memory 198428 kb
Host smart-173051e2-7e9a-4d2d-adab-e81cd047d473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856830796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3856830796
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2763534212
Short name T1003
Test name
Test status
Simulation time 2415915387 ps
CPU time 4.13 seconds
Started Jan 21 01:45:32 PM PST 24
Finished Jan 21 01:45:36 PM PST 24
Peak memory 196936 kb
Host smart-fbef3c96-9907-40b5-8e14-54e7a0c7beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763534212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2763534212
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.98876094
Short name T343
Test name
Test status
Simulation time 192656121273 ps
CPU time 30.44 seconds
Started Jan 21 02:05:07 PM PST 24
Finished Jan 21 02:05:39 PM PST 24
Peak memory 199584 kb
Host smart-23fb220d-f22d-4151-b876-207652ed78c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98876094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.98876094
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.121366109
Short name T287
Test name
Test status
Simulation time 26349906568 ps
CPU time 44.63 seconds
Started Jan 21 01:45:36 PM PST 24
Finished Jan 21 01:46:21 PM PST 24
Peak memory 199636 kb
Host smart-a4b523d9-e76e-42bf-ad71-0484ffc4a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121366109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.121366109
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2829705850
Short name T498
Test name
Test status
Simulation time 33871984 ps
CPU time 0.56 seconds
Started Jan 21 01:34:10 PM PST 24
Finished Jan 21 01:34:11 PM PST 24
Peak memory 195464 kb
Host smart-56e9641d-276b-41e3-8b78-c25d3e24ec6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829705850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2829705850
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2518624466
Short name T628
Test name
Test status
Simulation time 150106650729 ps
CPU time 235.35 seconds
Started Jan 21 01:34:01 PM PST 24
Finished Jan 21 01:37:58 PM PST 24
Peak memory 199900 kb
Host smart-2dbfa167-1cf9-4f1c-a467-fd5cc34ef882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518624466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2518624466
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1267254809
Short name T331
Test name
Test status
Simulation time 19994842069 ps
CPU time 12.88 seconds
Started Jan 21 01:34:01 PM PST 24
Finished Jan 21 01:34:15 PM PST 24
Peak memory 198508 kb
Host smart-56f0a85a-80a6-4b27-a675-bc49e28bb418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267254809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1267254809
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3266087801
Short name T1106
Test name
Test status
Simulation time 54226979875 ps
CPU time 94.26 seconds
Started Jan 21 01:34:01 PM PST 24
Finished Jan 21 01:35:37 PM PST 24
Peak memory 199976 kb
Host smart-6262daf1-6d12-4e94-8dd7-4980c5bc73b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266087801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3266087801
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1287845932
Short name T886
Test name
Test status
Simulation time 212344848155 ps
CPU time 616.94 seconds
Started Jan 21 01:34:16 PM PST 24
Finished Jan 21 01:44:34 PM PST 24
Peak memory 200060 kb
Host smart-2ccb23b7-ebae-41b8-87fb-4f0d2fa52954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287845932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1287845932
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2463992130
Short name T954
Test name
Test status
Simulation time 5895193907 ps
CPU time 4.19 seconds
Started Jan 21 01:34:09 PM PST 24
Finished Jan 21 01:34:14 PM PST 24
Peak memory 198524 kb
Host smart-17faff96-090d-4c58-b873-fd849c333783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463992130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2463992130
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.306540683
Short name T755
Test name
Test status
Simulation time 66846413194 ps
CPU time 61.1 seconds
Started Jan 21 01:34:03 PM PST 24
Finished Jan 21 01:35:05 PM PST 24
Peak memory 198884 kb
Host smart-b310ae39-e001-463c-9047-3c7d432103ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306540683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.306540683
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.789380212
Short name T767
Test name
Test status
Simulation time 15884662857 ps
CPU time 803.86 seconds
Started Jan 21 01:34:12 PM PST 24
Finished Jan 21 01:47:37 PM PST 24
Peak memory 199912 kb
Host smart-56f80861-9292-47ed-b6ad-70c8f5a26f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789380212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.789380212
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.434318567
Short name T1142
Test name
Test status
Simulation time 109210263 ps
CPU time 0.73 seconds
Started Jan 21 01:34:03 PM PST 24
Finished Jan 21 01:34:05 PM PST 24
Peak memory 194184 kb
Host smart-f50930c9-84a0-4ff1-937d-e10252ea8d57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434318567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.434318567
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3983468199
Short name T168
Test name
Test status
Simulation time 117591308681 ps
CPU time 91.12 seconds
Started Jan 21 01:34:15 PM PST 24
Finished Jan 21 01:35:48 PM PST 24
Peak memory 200012 kb
Host smart-8c404b04-6151-41e6-909a-5ad2ae4b9fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983468199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3983468199
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2791931743
Short name T933
Test name
Test status
Simulation time 40205067435 ps
CPU time 29.23 seconds
Started Jan 21 01:34:03 PM PST 24
Finished Jan 21 01:34:33 PM PST 24
Peak memory 195544 kb
Host smart-6b58683d-bab1-498f-a9f4-5715cb135a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791931743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2791931743
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4157689518
Short name T514
Test name
Test status
Simulation time 5534042650 ps
CPU time 12 seconds
Started Jan 21 01:34:03 PM PST 24
Finished Jan 21 01:34:16 PM PST 24
Peak memory 199360 kb
Host smart-bf880fa5-8183-41f8-baf7-7570cce6715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157689518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4157689518
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.445915528
Short name T986
Test name
Test status
Simulation time 167313747542 ps
CPU time 726.03 seconds
Started Jan 21 01:34:15 PM PST 24
Finished Jan 21 01:46:23 PM PST 24
Peak memory 216748 kb
Host smart-2542970c-8ae3-4110-a349-194999764f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445915528 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.445915528
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3323560033
Short name T857
Test name
Test status
Simulation time 1184812533 ps
CPU time 4.99 seconds
Started Jan 21 01:34:15 PM PST 24
Finished Jan 21 01:34:22 PM PST 24
Peak memory 198452 kb
Host smart-c605c188-56f9-4886-97c2-2d00f68ef989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323560033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3323560033
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1701029701
Short name T618
Test name
Test status
Simulation time 76035504037 ps
CPU time 34.65 seconds
Started Jan 21 01:34:01 PM PST 24
Finished Jan 21 01:34:38 PM PST 24
Peak memory 200072 kb
Host smart-0566811d-8b02-4d9c-8fd6-42a01fc8139c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701029701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1701029701
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2468967169
Short name T157
Test name
Test status
Simulation time 137393376558 ps
CPU time 61.13 seconds
Started Jan 21 01:52:22 PM PST 24
Finished Jan 21 01:53:25 PM PST 24
Peak memory 199832 kb
Host smart-bd7bec0b-421a-4422-b26f-70869ae238d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468967169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2468967169
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1735991817
Short name T176
Test name
Test status
Simulation time 8775754955 ps
CPU time 13.97 seconds
Started Jan 21 01:45:45 PM PST 24
Finished Jan 21 01:46:00 PM PST 24
Peak memory 199476 kb
Host smart-807f1765-cfe8-4fcc-8c9b-a05bb72c3f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735991817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1735991817
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3214645071
Short name T640
Test name
Test status
Simulation time 24238840319 ps
CPU time 12.43 seconds
Started Jan 21 01:45:45 PM PST 24
Finished Jan 21 01:45:58 PM PST 24
Peak memory 199660 kb
Host smart-313f5708-d2c4-4c85-9e7b-c7b128eee1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214645071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3214645071
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1107364165
Short name T1016
Test name
Test status
Simulation time 88244082807 ps
CPU time 68.1 seconds
Started Jan 21 01:45:48 PM PST 24
Finished Jan 21 01:46:57 PM PST 24
Peak memory 199956 kb
Host smart-a4f404f1-0f3b-4b5c-aa82-6b303fb13bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107364165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1107364165
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3640835921
Short name T259
Test name
Test status
Simulation time 31918375651 ps
CPU time 16.24 seconds
Started Jan 21 01:45:42 PM PST 24
Finished Jan 21 01:45:59 PM PST 24
Peak memory 198756 kb
Host smart-756787d7-0f50-49b2-8378-3331eb9adb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640835921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3640835921
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1013729079
Short name T305
Test name
Test status
Simulation time 75970568700 ps
CPU time 23.26 seconds
Started Jan 21 01:45:49 PM PST 24
Finished Jan 21 01:46:13 PM PST 24
Peak memory 200028 kb
Host smart-43ec7ae2-a387-4a10-b4d4-428e137c28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013729079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1013729079
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3112275973
Short name T1064
Test name
Test status
Simulation time 70768637667 ps
CPU time 51.02 seconds
Started Jan 21 01:45:43 PM PST 24
Finished Jan 21 01:46:34 PM PST 24
Peak memory 199300 kb
Host smart-0d96408c-c170-45c6-85a1-f989660b1576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112275973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3112275973
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3271274885
Short name T262
Test name
Test status
Simulation time 74895991546 ps
CPU time 246.87 seconds
Started Jan 21 01:45:43 PM PST 24
Finished Jan 21 01:49:51 PM PST 24
Peak memory 200008 kb
Host smart-3c95d925-26cd-432b-8b48-48c3ed74c0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271274885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3271274885
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2061782045
Short name T620
Test name
Test status
Simulation time 31727900 ps
CPU time 0.54 seconds
Started Jan 21 01:34:38 PM PST 24
Finished Jan 21 01:34:39 PM PST 24
Peak memory 195636 kb
Host smart-972ce51d-fb2e-4cef-8d99-6bd98eec909b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061782045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2061782045
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2914194917
Short name T1033
Test name
Test status
Simulation time 19998207751 ps
CPU time 29.98 seconds
Started Jan 21 01:34:21 PM PST 24
Finished Jan 21 01:34:51 PM PST 24
Peak memory 199900 kb
Host smart-d63eb923-c529-462e-ad87-7c99cfabc728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914194917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2914194917
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1296615578
Short name T590
Test name
Test status
Simulation time 365076305221 ps
CPU time 123.55 seconds
Started Jan 21 01:34:23 PM PST 24
Finished Jan 21 01:36:28 PM PST 24
Peak memory 199628 kb
Host smart-22c8d0d9-ec4c-498e-a39c-ee7289210e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296615578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1296615578
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3567163466
Short name T593
Test name
Test status
Simulation time 133503127651 ps
CPU time 100.88 seconds
Started Jan 21 01:34:21 PM PST 24
Finished Jan 21 01:36:03 PM PST 24
Peak memory 199988 kb
Host smart-5ebbd4f6-550d-43e1-8df9-45969f89a0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567163466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3567163466
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1902170667
Short name T440
Test name
Test status
Simulation time 212293582340 ps
CPU time 82.85 seconds
Started Jan 21 01:34:20 PM PST 24
Finished Jan 21 01:35:43 PM PST 24
Peak memory 197632 kb
Host smart-6d3ff189-ce49-4974-ac13-d414d68ac4fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902170667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1902170667
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1314413180
Short name T503
Test name
Test status
Simulation time 60292378603 ps
CPU time 300.72 seconds
Started Jan 21 01:34:31 PM PST 24
Finished Jan 21 01:39:32 PM PST 24
Peak memory 199916 kb
Host smart-8b19e6a4-3532-444d-a053-f2379bd257d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314413180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1314413180
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.4155167455
Short name T1155
Test name
Test status
Simulation time 6735482883 ps
CPU time 10.27 seconds
Started Jan 21 01:34:28 PM PST 24
Finished Jan 21 01:34:39 PM PST 24
Peak memory 198544 kb
Host smart-07fac809-6ab6-4038-b8a4-3ddbe9d64c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155167455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.4155167455
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.478292285
Short name T903
Test name
Test status
Simulation time 93314416778 ps
CPU time 44.07 seconds
Started Jan 21 01:34:30 PM PST 24
Finished Jan 21 01:35:16 PM PST 24
Peak memory 198672 kb
Host smart-fc44611f-14d0-4ea8-9c3a-d0576f163ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478292285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.478292285
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2842691539
Short name T1074
Test name
Test status
Simulation time 26347566925 ps
CPU time 516.28 seconds
Started Jan 21 01:44:46 PM PST 24
Finished Jan 21 01:53:23 PM PST 24
Peak memory 199824 kb
Host smart-d642b4fa-186a-48e3-bba4-61ea67b750a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842691539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2842691539
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.19413920
Short name T910
Test name
Test status
Simulation time 1709080402 ps
CPU time 2.68 seconds
Started Jan 21 01:34:21 PM PST 24
Finished Jan 21 01:34:24 PM PST 24
Peak memory 197656 kb
Host smart-72b0981d-50e3-451f-bff6-cb59223e3dbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19413920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.19413920
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.794211440
Short name T306
Test name
Test status
Simulation time 86671477390 ps
CPU time 58.09 seconds
Started Jan 21 01:34:29 PM PST 24
Finished Jan 21 01:35:28 PM PST 24
Peak memory 199460 kb
Host smart-f3d600c1-fb35-45df-a5b7-b7331aa1e881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794211440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.794211440
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3479534659
Short name T783
Test name
Test status
Simulation time 4421957081 ps
CPU time 7.43 seconds
Started Jan 21 01:34:29 PM PST 24
Finished Jan 21 01:34:37 PM PST 24
Peak memory 195568 kb
Host smart-c0c4e432-bc7d-4921-ae7a-4d26e7f01850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479534659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3479534659
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.490087922
Short name T1054
Test name
Test status
Simulation time 455353118 ps
CPU time 1.3 seconds
Started Jan 21 01:34:20 PM PST 24
Finished Jan 21 01:34:22 PM PST 24
Peak memory 198084 kb
Host smart-4f0b2d9f-e3e5-4f9e-ae53-80816b479cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490087922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.490087922
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.629095780
Short name T270
Test name
Test status
Simulation time 89640424933 ps
CPU time 2133.58 seconds
Started Jan 21 01:34:28 PM PST 24
Finished Jan 21 02:10:03 PM PST 24
Peak memory 208428 kb
Host smart-981cab27-88aa-4b51-8415-d8f803dd0b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629095780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.629095780
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3561977710
Short name T1099
Test name
Test status
Simulation time 1293938783 ps
CPU time 2.29 seconds
Started Jan 21 01:34:29 PM PST 24
Finished Jan 21 01:34:32 PM PST 24
Peak memory 197740 kb
Host smart-c221045e-695e-419d-a223-500e6572533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561977710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3561977710
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2247040605
Short name T135
Test name
Test status
Simulation time 4579025022 ps
CPU time 8.57 seconds
Started Jan 21 01:34:23 PM PST 24
Finished Jan 21 01:34:32 PM PST 24
Peak memory 199952 kb
Host smart-1eb4cf80-eda9-4560-b923-4d54d92d749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247040605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2247040605
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.4206090139
Short name T117
Test name
Test status
Simulation time 67967618199 ps
CPU time 317.37 seconds
Started Jan 21 01:45:47 PM PST 24
Finished Jan 21 01:51:06 PM PST 24
Peak memory 199852 kb
Host smart-eb986b68-a331-4e50-b12c-6764cd0a0ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206090139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.4206090139
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.896785406
Short name T726
Test name
Test status
Simulation time 21675337548 ps
CPU time 8.59 seconds
Started Jan 21 01:45:44 PM PST 24
Finished Jan 21 01:45:53 PM PST 24
Peak memory 198148 kb
Host smart-b55d8118-858b-4366-a29b-9deda8b87a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896785406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.896785406
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.691710892
Short name T171
Test name
Test status
Simulation time 38063806329 ps
CPU time 15.63 seconds
Started Jan 21 01:45:47 PM PST 24
Finished Jan 21 01:46:03 PM PST 24
Peak memory 200004 kb
Host smart-778ec954-23bd-4990-96fa-038363e4b1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691710892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.691710892
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2221651937
Short name T685
Test name
Test status
Simulation time 8861137813 ps
CPU time 16.89 seconds
Started Jan 21 01:45:47 PM PST 24
Finished Jan 21 01:46:05 PM PST 24
Peak memory 200056 kb
Host smart-8470d020-a018-45a6-94e2-092026a28593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221651937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2221651937
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1213867411
Short name T1212
Test name
Test status
Simulation time 114166630581 ps
CPU time 12.9 seconds
Started Jan 21 01:45:48 PM PST 24
Finished Jan 21 01:46:02 PM PST 24
Peak memory 199972 kb
Host smart-89c4ff49-7803-4dac-be5b-c6f0024e8984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213867411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1213867411
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.744431629
Short name T353
Test name
Test status
Simulation time 9415228829 ps
CPU time 16.79 seconds
Started Jan 21 01:45:56 PM PST 24
Finished Jan 21 01:46:14 PM PST 24
Peak memory 199560 kb
Host smart-7388b9e6-6200-40ac-b6b3-e8324d6e713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744431629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.744431629
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.177386695
Short name T206
Test name
Test status
Simulation time 224325205647 ps
CPU time 25.19 seconds
Started Jan 21 01:45:55 PM PST 24
Finished Jan 21 01:46:22 PM PST 24
Peak memory 199996 kb
Host smart-3e565300-1fb8-419d-b8e2-42675e0fe3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177386695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.177386695
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.471063280
Short name T951
Test name
Test status
Simulation time 35454056449 ps
CPU time 13.59 seconds
Started Jan 21 02:00:45 PM PST 24
Finished Jan 21 02:01:00 PM PST 24
Peak memory 199308 kb
Host smart-178ac35e-090e-497b-8360-aee738749019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471063280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.471063280
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3250614497
Short name T890
Test name
Test status
Simulation time 13616253486 ps
CPU time 21.74 seconds
Started Jan 21 01:45:55 PM PST 24
Finished Jan 21 01:46:17 PM PST 24
Peak memory 199848 kb
Host smart-54dc0de7-804a-4552-8b61-e16c4a28d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250614497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3250614497
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1595371505
Short name T867
Test name
Test status
Simulation time 36902719 ps
CPU time 0.58 seconds
Started Jan 21 01:34:52 PM PST 24
Finished Jan 21 01:34:53 PM PST 24
Peak memory 195588 kb
Host smart-0ae3af77-3da0-43cb-bbd3-c19acc733b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595371505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1595371505
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4102520144
Short name T533
Test name
Test status
Simulation time 121358570545 ps
CPU time 178.25 seconds
Started Jan 21 01:34:38 PM PST 24
Finished Jan 21 01:37:37 PM PST 24
Peak memory 200048 kb
Host smart-aa33daaf-02a4-4966-8369-0163a2105e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102520144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4102520144
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.832294814
Short name T894
Test name
Test status
Simulation time 130180082653 ps
CPU time 105.02 seconds
Started Jan 21 01:34:41 PM PST 24
Finished Jan 21 01:36:27 PM PST 24
Peak memory 199032 kb
Host smart-508b93c7-e65c-40e0-96f8-f3b286ea7d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832294814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.832294814
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.1482652142
Short name T950
Test name
Test status
Simulation time 364241550124 ps
CPU time 152.38 seconds
Started Jan 21 01:34:37 PM PST 24
Finished Jan 21 01:37:11 PM PST 24
Peak memory 199952 kb
Host smart-0dd113ee-3e10-4751-9d7b-098b1a995a2b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482652142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1482652142
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2525390420
Short name T403
Test name
Test status
Simulation time 90001746598 ps
CPU time 654.26 seconds
Started Jan 21 02:53:18 PM PST 24
Finished Jan 21 03:04:14 PM PST 24
Peak memory 199984 kb
Host smart-4bc3cfcc-fb38-404c-8e9d-fe10b0d9ef26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525390420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2525390420
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3289880957
Short name T525
Test name
Test status
Simulation time 9893869908 ps
CPU time 11.54 seconds
Started Jan 21 01:34:39 PM PST 24
Finished Jan 21 01:34:52 PM PST 24
Peak memory 198308 kb
Host smart-26989135-58dc-46cf-a3ef-aa2a4e3ed759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289880957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3289880957
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2101892816
Short name T133
Test name
Test status
Simulation time 120900413799 ps
CPU time 56.22 seconds
Started Jan 21 01:34:40 PM PST 24
Finished Jan 21 01:35:37 PM PST 24
Peak memory 199132 kb
Host smart-1e857804-c55a-4f22-8a39-2dc69b174131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101892816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2101892816
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.614411520
Short name T896
Test name
Test status
Simulation time 30145501316 ps
CPU time 386.11 seconds
Started Jan 21 01:34:53 PM PST 24
Finished Jan 21 01:41:20 PM PST 24
Peak memory 199916 kb
Host smart-663ea61c-1ff8-4040-9fcf-d758f57620e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614411520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.614411520
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2630650277
Short name T971
Test name
Test status
Simulation time 1521541185 ps
CPU time 3.32 seconds
Started Jan 21 01:34:39 PM PST 24
Finished Jan 21 01:34:43 PM PST 24
Peak memory 198016 kb
Host smart-b00b6bca-af35-4640-8815-60a724904a19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2630650277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2630650277
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.938121436
Short name T317
Test name
Test status
Simulation time 150282935545 ps
CPU time 39.23 seconds
Started Jan 21 01:34:38 PM PST 24
Finished Jan 21 01:35:18 PM PST 24
Peak memory 200004 kb
Host smart-4d810dae-ed81-4e9f-84a3-1b54d9556e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938121436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.938121436
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3054791487
Short name T704
Test name
Test status
Simulation time 48097143450 ps
CPU time 36.17 seconds
Started Jan 21 01:34:39 PM PST 24
Finished Jan 21 01:35:15 PM PST 24
Peak memory 195472 kb
Host smart-b525466a-e1c1-4a34-8fcf-a644b8ddf278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054791487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3054791487
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3256177195
Short name T819
Test name
Test status
Simulation time 521902251 ps
CPU time 1.62 seconds
Started Jan 21 01:56:22 PM PST 24
Finished Jan 21 01:56:25 PM PST 24
Peak memory 197892 kb
Host smart-31e6e781-ce89-4284-9eb8-42ceaa3b6c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256177195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3256177195
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.239215189
Short name T656
Test name
Test status
Simulation time 174769461117 ps
CPU time 72.12 seconds
Started Jan 21 01:34:52 PM PST 24
Finished Jan 21 01:36:05 PM PST 24
Peak memory 200216 kb
Host smart-ea1dd573-50aa-4316-b8c3-2953060352ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239215189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.239215189
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2383100136
Short name T31
Test name
Test status
Simulation time 55368320841 ps
CPU time 452 seconds
Started Jan 21 02:30:34 PM PST 24
Finished Jan 21 02:38:07 PM PST 24
Peak memory 215868 kb
Host smart-cdbcf2ed-48ce-49b2-a979-0571ebfb8a84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383100136 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2383100136
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1595990098
Short name T1008
Test name
Test status
Simulation time 1007213784 ps
CPU time 1.49 seconds
Started Jan 21 01:34:42 PM PST 24
Finished Jan 21 01:34:44 PM PST 24
Peak memory 198216 kb
Host smart-21330647-f285-4537-bfdc-963544752b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595990098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1595990098
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1183325501
Short name T608
Test name
Test status
Simulation time 26868922135 ps
CPU time 13.04 seconds
Started Jan 21 01:34:39 PM PST 24
Finished Jan 21 01:34:53 PM PST 24
Peak memory 196780 kb
Host smart-836ba18b-0c91-4538-8c0c-59bd6023dae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183325501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1183325501
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3674534823
Short name T235
Test name
Test status
Simulation time 102218850580 ps
CPU time 15.2 seconds
Started Jan 21 01:45:52 PM PST 24
Finished Jan 21 01:46:08 PM PST 24
Peak memory 199540 kb
Host smart-9b67fd9f-0272-423f-ae37-fa4dbcec2905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674534823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3674534823
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4181605734
Short name T149
Test name
Test status
Simulation time 123239110535 ps
CPU time 190.05 seconds
Started Jan 21 02:12:56 PM PST 24
Finished Jan 21 02:16:06 PM PST 24
Peak memory 199992 kb
Host smart-1776b65a-5738-46e7-977a-af0d64a5cbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181605734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4181605734
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3237939349
Short name T1158
Test name
Test status
Simulation time 179449993409 ps
CPU time 140.05 seconds
Started Jan 21 01:45:51 PM PST 24
Finished Jan 21 01:48:12 PM PST 24
Peak memory 200000 kb
Host smart-b0290738-39e1-4618-9770-da5a93d459b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237939349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3237939349
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3975446057
Short name T1205
Test name
Test status
Simulation time 12128548051 ps
CPU time 17.55 seconds
Started Jan 21 02:19:13 PM PST 24
Finished Jan 21 02:19:32 PM PST 24
Peak memory 199348 kb
Host smart-f63cd215-ecdf-481f-b5e1-072b083f34c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975446057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3975446057
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2562922541
Short name T134
Test name
Test status
Simulation time 27261810476 ps
CPU time 50.11 seconds
Started Jan 21 01:45:59 PM PST 24
Finished Jan 21 01:46:50 PM PST 24
Peak memory 199788 kb
Host smart-56ab727e-b995-4d02-b1a6-e7d1f6c37542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562922541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2562922541
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3576091300
Short name T1036
Test name
Test status
Simulation time 46020561581 ps
CPU time 110.66 seconds
Started Jan 21 01:46:01 PM PST 24
Finished Jan 21 01:47:53 PM PST 24
Peak memory 200032 kb
Host smart-6f66b2b1-64c1-43da-a927-41e86273f115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576091300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3576091300
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1322274532
Short name T1068
Test name
Test status
Simulation time 9485573927 ps
CPU time 9.29 seconds
Started Jan 21 01:46:03 PM PST 24
Finished Jan 21 01:46:13 PM PST 24
Peak memory 199964 kb
Host smart-0402fbdd-b12c-4fa5-9a30-769c20a77955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322274532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1322274532
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2089158707
Short name T201
Test name
Test status
Simulation time 150097476507 ps
CPU time 269.09 seconds
Started Jan 21 01:46:05 PM PST 24
Finished Jan 21 01:50:35 PM PST 24
Peak memory 200032 kb
Host smart-cda68c49-50e0-4112-8b91-7a272ca4adaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089158707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2089158707
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3392904050
Short name T1220
Test name
Test status
Simulation time 116399892 ps
CPU time 0.57 seconds
Started Jan 21 01:35:09 PM PST 24
Finished Jan 21 01:35:10 PM PST 24
Peak memory 195552 kb
Host smart-170b9abe-101f-4116-a072-2ca1ec06b579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392904050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3392904050
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2013811938
Short name T1079
Test name
Test status
Simulation time 74065329100 ps
CPU time 29.42 seconds
Started Jan 21 01:35:01 PM PST 24
Finished Jan 21 01:35:32 PM PST 24
Peak memory 200024 kb
Host smart-99a8d05a-926c-432e-866b-d794abdf0ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013811938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2013811938
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3337350596
Short name T828
Test name
Test status
Simulation time 64658816578 ps
CPU time 46.4 seconds
Started Jan 21 01:35:01 PM PST 24
Finished Jan 21 01:35:49 PM PST 24
Peak memory 199872 kb
Host smart-0b226e4d-afed-4ba5-b65b-1cce8889cd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337350596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3337350596
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3777808628
Short name T1156
Test name
Test status
Simulation time 50607406983 ps
CPU time 42.91 seconds
Started Jan 21 02:09:24 PM PST 24
Finished Jan 21 02:10:09 PM PST 24
Peak memory 199944 kb
Host smart-9885c918-696c-4b24-b360-b2be6a6d19ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777808628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3777808628
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3460447396
Short name T546
Test name
Test status
Simulation time 1096660231137 ps
CPU time 1758.27 seconds
Started Jan 21 01:34:59 PM PST 24
Finished Jan 21 02:04:18 PM PST 24
Peak memory 198212 kb
Host smart-b271f281-6506-4ca0-8c14-a0a4916a349d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460447396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3460447396
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1431989517
Short name T882
Test name
Test status
Simulation time 105100079661 ps
CPU time 326.17 seconds
Started Jan 21 01:52:53 PM PST 24
Finished Jan 21 01:58:20 PM PST 24
Peak memory 199852 kb
Host smart-31cf3d04-2cdb-468a-ac61-ecc6772a69b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1431989517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1431989517
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4108288503
Short name T494
Test name
Test status
Simulation time 3945314835 ps
CPU time 7.27 seconds
Started Jan 21 01:35:00 PM PST 24
Finished Jan 21 01:35:08 PM PST 24
Peak memory 197324 kb
Host smart-9768c376-f734-47ca-88b4-fc61626178c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108288503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4108288503
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.723593292
Short name T1042
Test name
Test status
Simulation time 40008554329 ps
CPU time 27.4 seconds
Started Jan 21 01:34:58 PM PST 24
Finished Jan 21 01:35:26 PM PST 24
Peak memory 198412 kb
Host smart-1335797c-5df0-43b5-9600-56438727cb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723593292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.723593292
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3528624290
Short name T539
Test name
Test status
Simulation time 14124647671 ps
CPU time 407.21 seconds
Started Jan 21 01:34:59 PM PST 24
Finished Jan 21 01:41:47 PM PST 24
Peak memory 199996 kb
Host smart-730df83b-5a01-4e50-800b-567975f7fc69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528624290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3528624290
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3184571134
Short name T273
Test name
Test status
Simulation time 150381084307 ps
CPU time 30.96 seconds
Started Jan 21 01:34:58 PM PST 24
Finished Jan 21 01:35:30 PM PST 24
Peak memory 199144 kb
Host smart-ffaca897-fdcb-42be-915f-b6898a1bb6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184571134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3184571134
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.657132350
Short name T1140
Test name
Test status
Simulation time 3092912123 ps
CPU time 2.15 seconds
Started Jan 21 01:35:00 PM PST 24
Finished Jan 21 01:35:04 PM PST 24
Peak memory 195760 kb
Host smart-a5ad6dfe-f564-4f4c-8c0d-e1a456c4c6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657132350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.657132350
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.299754985
Short name T965
Test name
Test status
Simulation time 498186855 ps
CPU time 1.83 seconds
Started Jan 21 01:34:54 PM PST 24
Finished Jan 21 01:34:57 PM PST 24
Peak memory 198020 kb
Host smart-8a722f2d-67bd-4180-8acb-7d2321892264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299754985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.299754985
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3868775172
Short name T424
Test name
Test status
Simulation time 196670026755 ps
CPU time 66.48 seconds
Started Jan 21 01:42:44 PM PST 24
Finished Jan 21 01:43:51 PM PST 24
Peak memory 199932 kb
Host smart-717c1187-9d59-49e5-95c6-18f369556638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868775172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3868775172
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.800569784
Short name T589
Test name
Test status
Simulation time 94336737152 ps
CPU time 266.46 seconds
Started Jan 21 01:35:09 PM PST 24
Finished Jan 21 01:39:37 PM PST 24
Peak memory 214376 kb
Host smart-ca6bcecc-bfcb-4dac-b94b-578124cf030c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800569784 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.800569784
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3733099791
Short name T918
Test name
Test status
Simulation time 1158176775 ps
CPU time 2.56 seconds
Started Jan 21 02:29:17 PM PST 24
Finished Jan 21 02:29:20 PM PST 24
Peak memory 199188 kb
Host smart-e1d8913f-96c3-43a4-8378-a52ea7552bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733099791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3733099791
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1967403709
Short name T416
Test name
Test status
Simulation time 155701842022 ps
CPU time 49.57 seconds
Started Jan 21 01:35:00 PM PST 24
Finished Jan 21 01:35:50 PM PST 24
Peak memory 199972 kb
Host smart-2829c6fb-9728-4fc4-840e-5612a3897982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967403709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1967403709
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.955478973
Short name T113
Test name
Test status
Simulation time 307222416763 ps
CPU time 46.05 seconds
Started Jan 21 01:46:01 PM PST 24
Finished Jan 21 01:46:48 PM PST 24
Peak memory 199780 kb
Host smart-1dc08b96-93f8-4718-bddf-5542c69cded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955478973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.955478973
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2339035245
Short name T909
Test name
Test status
Simulation time 35606573579 ps
CPU time 63.27 seconds
Started Jan 21 01:46:01 PM PST 24
Finished Jan 21 01:47:05 PM PST 24
Peak memory 199852 kb
Host smart-8f3b725b-a9db-48cd-af51-277f466d48c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339035245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2339035245
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2389565330
Short name T160
Test name
Test status
Simulation time 157093688056 ps
CPU time 16.57 seconds
Started Jan 21 01:45:59 PM PST 24
Finished Jan 21 01:46:17 PM PST 24
Peak memory 200012 kb
Host smart-7b3f13ff-d51b-4545-b721-5460338534a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389565330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2389565330
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1335819619
Short name T777
Test name
Test status
Simulation time 160376577147 ps
CPU time 17.8 seconds
Started Jan 21 01:46:04 PM PST 24
Finished Jan 21 01:46:23 PM PST 24
Peak memory 199472 kb
Host smart-f0e4a250-1f41-4bab-8732-3bf018028441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335819619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1335819619
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2935765988
Short name T705
Test name
Test status
Simulation time 115224555017 ps
CPU time 24.8 seconds
Started Jan 21 01:46:03 PM PST 24
Finished Jan 21 01:46:29 PM PST 24
Peak memory 199128 kb
Host smart-98d66a00-062b-4731-95dd-09cf17d99f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935765988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2935765988
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1948489002
Short name T928
Test name
Test status
Simulation time 41287416993 ps
CPU time 18.95 seconds
Started Jan 21 01:46:02 PM PST 24
Finished Jan 21 01:46:22 PM PST 24
Peak memory 198920 kb
Host smart-8ae81e83-590c-466a-a2cd-a34b7dd36dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948489002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1948489002
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.843136180
Short name T261
Test name
Test status
Simulation time 6048614340 ps
CPU time 9.86 seconds
Started Jan 21 01:46:04 PM PST 24
Finished Jan 21 01:46:15 PM PST 24
Peak memory 198112 kb
Host smart-01c16729-9420-4c94-8b17-1e7cbc726bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843136180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.843136180
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.137147238
Short name T203
Test name
Test status
Simulation time 126375563954 ps
CPU time 61.73 seconds
Started Jan 21 01:46:04 PM PST 24
Finished Jan 21 01:47:07 PM PST 24
Peak memory 199956 kb
Host smart-f3b4f378-99ad-41f4-868a-538a5947299c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137147238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.137147238
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3603346794
Short name T119
Test name
Test status
Simulation time 10760827063 ps
CPU time 11.97 seconds
Started Jan 21 01:46:01 PM PST 24
Finished Jan 21 01:46:14 PM PST 24
Peak memory 199116 kb
Host smart-4ff66bf7-e0d3-4c95-b8a8-025b1c431953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603346794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3603346794
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.519652975
Short name T128
Test name
Test status
Simulation time 133895232191 ps
CPU time 247.58 seconds
Started Jan 21 01:46:12 PM PST 24
Finished Jan 21 01:50:20 PM PST 24
Peak memory 199956 kb
Host smart-91404982-ed8e-4931-b0ff-a8def0a06335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519652975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.519652975
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2462748243
Short name T629
Test name
Test status
Simulation time 59350783 ps
CPU time 0.55 seconds
Started Jan 21 01:26:19 PM PST 24
Finished Jan 21 01:26:21 PM PST 24
Peak memory 194640 kb
Host smart-49983933-1d1a-4be2-b308-945b8f495935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462748243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2462748243
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2520262230
Short name T637
Test name
Test status
Simulation time 121001467969 ps
CPU time 42.96 seconds
Started Jan 21 02:39:06 PM PST 24
Finished Jan 21 02:39:53 PM PST 24
Peak memory 199928 kb
Host smart-d0e56ec6-8c99-43bf-9fda-8a82b183ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520262230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2520262230
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3983385975
Short name T848
Test name
Test status
Simulation time 12681512053 ps
CPU time 10.31 seconds
Started Jan 21 01:26:00 PM PST 24
Finished Jan 21 01:26:11 PM PST 24
Peak memory 197872 kb
Host smart-4366ebef-e2b6-4cd4-bd0a-a282ea5ca5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983385975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3983385975
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.910275036
Short name T239
Test name
Test status
Simulation time 51072359502 ps
CPU time 16.99 seconds
Started Jan 21 01:44:46 PM PST 24
Finished Jan 21 01:45:03 PM PST 24
Peak memory 200020 kb
Host smart-c8be3af8-cb7d-4278-b821-d631fbb8c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910275036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.910275036
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2047681234
Short name T565
Test name
Test status
Simulation time 89147498276 ps
CPU time 155.77 seconds
Started Jan 21 01:26:10 PM PST 24
Finished Jan 21 01:28:46 PM PST 24
Peak memory 198060 kb
Host smart-e0c0ac47-70bb-4559-9050-0b72f41c3dc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047681234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2047681234
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3585960590
Short name T968
Test name
Test status
Simulation time 53154543313 ps
CPU time 455.34 seconds
Started Jan 21 01:33:06 PM PST 24
Finished Jan 21 01:40:45 PM PST 24
Peak memory 199904 kb
Host smart-f9cb17ae-d489-4cd4-93e1-ffd09b630473
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585960590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3585960590
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1596496237
Short name T788
Test name
Test status
Simulation time 4001345274 ps
CPU time 7.74 seconds
Started Jan 21 01:26:10 PM PST 24
Finished Jan 21 01:26:18 PM PST 24
Peak memory 197840 kb
Host smart-3e099177-49bf-4783-96ce-dae701d16f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596496237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1596496237
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3685761009
Short name T1101
Test name
Test status
Simulation time 29150234848 ps
CPU time 52.14 seconds
Started Jan 21 01:37:28 PM PST 24
Finished Jan 21 01:38:21 PM PST 24
Peak memory 199060 kb
Host smart-940383c1-7dcc-4a7c-b980-b1395ae6cb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685761009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3685761009
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2424547490
Short name T1015
Test name
Test status
Simulation time 3702535859 ps
CPU time 49.67 seconds
Started Jan 21 01:46:57 PM PST 24
Finished Jan 21 01:47:48 PM PST 24
Peak memory 199844 kb
Host smart-c35e2bae-9de6-487e-9d2b-d7b06360c727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424547490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2424547490
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3803895361
Short name T29
Test name
Test status
Simulation time 1838647397 ps
CPU time 9.77 seconds
Started Jan 21 01:47:54 PM PST 24
Finished Jan 21 01:48:05 PM PST 24
Peak memory 197500 kb
Host smart-fbe5d54a-9c6d-41bd-994b-ed05dbeb0f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803895361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3803895361
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.673790292
Short name T724
Test name
Test status
Simulation time 36976113387 ps
CPU time 60.38 seconds
Started Jan 21 01:26:07 PM PST 24
Finished Jan 21 01:27:08 PM PST 24
Peak memory 199200 kb
Host smart-9c39b024-e80a-4423-9fe5-89d230290d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673790292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.673790292
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2676882097
Short name T419
Test name
Test status
Simulation time 43775552666 ps
CPU time 30.42 seconds
Started Jan 21 01:53:33 PM PST 24
Finished Jan 21 01:54:04 PM PST 24
Peak memory 195468 kb
Host smart-3efc0b37-9d2f-4aaf-b698-29663a955f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676882097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2676882097
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3771927779
Short name T91
Test name
Test status
Simulation time 123339141 ps
CPU time 0.77 seconds
Started Jan 21 01:26:19 PM PST 24
Finished Jan 21 01:26:20 PM PST 24
Peak memory 217148 kb
Host smart-c1aa4e89-f868-4d5f-89d5-53ed02914efa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771927779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3771927779
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.905871295
Short name T551
Test name
Test status
Simulation time 474353078 ps
CPU time 1.27 seconds
Started Jan 21 01:33:16 PM PST 24
Finished Jan 21 01:33:18 PM PST 24
Peak memory 198100 kb
Host smart-50bbdcd5-73a4-4d00-ba2f-aeefa6bb1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905871295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.905871295
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2204209202
Short name T940
Test name
Test status
Simulation time 114025943609 ps
CPU time 906.66 seconds
Started Jan 21 01:26:19 PM PST 24
Finished Jan 21 01:41:27 PM PST 24
Peak memory 216420 kb
Host smart-d74a8837-eccc-49c7-9df6-96cb7265c2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204209202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2204209202
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1299999894
Short name T731
Test name
Test status
Simulation time 43062357014 ps
CPU time 526.41 seconds
Started Jan 21 01:26:19 PM PST 24
Finished Jan 21 01:35:07 PM PST 24
Peak memory 216660 kb
Host smart-d1a09724-b2c1-41c4-8801-ca72d83c8862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299999894 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1299999894
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4167865209
Short name T1224
Test name
Test status
Simulation time 1266867965 ps
CPU time 4.58 seconds
Started Jan 21 01:46:29 PM PST 24
Finished Jan 21 01:46:34 PM PST 24
Peak memory 200116 kb
Host smart-1c940c09-566b-44d3-b86c-e2418405d539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167865209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4167865209
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3225015793
Short name T509
Test name
Test status
Simulation time 13863890047 ps
CPU time 16.27 seconds
Started Jan 21 02:24:55 PM PST 24
Finished Jan 21 02:25:12 PM PST 24
Peak memory 199628 kb
Host smart-11d88c0d-afc8-4fb2-9e11-67ce9d852559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225015793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3225015793
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3026287457
Short name T501
Test name
Test status
Simulation time 49758000 ps
CPU time 0.57 seconds
Started Jan 21 01:35:33 PM PST 24
Finished Jan 21 01:35:36 PM PST 24
Peak memory 195648 kb
Host smart-9d81cd63-f5f2-4ed2-af62-6a2fe3ba95b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026287457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3026287457
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1514616270
Short name T1037
Test name
Test status
Simulation time 88961150910 ps
CPU time 43.82 seconds
Started Jan 21 02:07:02 PM PST 24
Finished Jan 21 02:07:58 PM PST 24
Peak memory 199868 kb
Host smart-22c97c1b-85a3-45d8-9b24-82f463c72c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514616270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1514616270
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1585700123
Short name T744
Test name
Test status
Simulation time 98642203241 ps
CPU time 44.41 seconds
Started Jan 21 01:35:09 PM PST 24
Finished Jan 21 01:35:55 PM PST 24
Peak memory 199412 kb
Host smart-1c3cd620-dcf4-4e4b-b7f8-3dd47c5746a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585700123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1585700123
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2150949328
Short name T1127
Test name
Test status
Simulation time 147823666968 ps
CPU time 45.29 seconds
Started Jan 21 01:54:09 PM PST 24
Finished Jan 21 01:54:55 PM PST 24
Peak memory 199924 kb
Host smart-fa9ebcd6-8a21-4501-a104-378ea4b551be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150949328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2150949328
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.768610457
Short name T680
Test name
Test status
Simulation time 1066202494726 ps
CPU time 801.22 seconds
Started Jan 21 01:35:17 PM PST 24
Finished Jan 21 01:48:39 PM PST 24
Peak memory 199508 kb
Host smart-b99d32f1-a9c5-493e-9459-f38c9144d59a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768610457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.768610457
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.4116891548
Short name T1001
Test name
Test status
Simulation time 53189606580 ps
CPU time 486.56 seconds
Started Jan 21 01:35:18 PM PST 24
Finished Jan 21 01:43:25 PM PST 24
Peak memory 199976 kb
Host smart-935b5901-46aa-414c-a29a-70553d5ace55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116891548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.4116891548
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.650890662
Short name T611
Test name
Test status
Simulation time 15647858170 ps
CPU time 24.72 seconds
Started Jan 21 01:35:17 PM PST 24
Finished Jan 21 01:35:43 PM PST 24
Peak memory 199092 kb
Host smart-dc3fd37b-1ec3-4e91-9eb9-83fb47b65057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650890662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.650890662
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1638545690
Short name T678
Test name
Test status
Simulation time 35590285504 ps
CPU time 30.07 seconds
Started Jan 21 01:35:19 PM PST 24
Finished Jan 21 01:35:50 PM PST 24
Peak memory 195740 kb
Host smart-22dd2833-d1fc-4776-83b6-b4d37e9c0f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638545690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1638545690
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2683613654
Short name T562
Test name
Test status
Simulation time 13049508524 ps
CPU time 80.87 seconds
Started Jan 21 01:35:17 PM PST 24
Finished Jan 21 01:36:39 PM PST 24
Peak memory 199976 kb
Host smart-70a2ca27-a699-45b4-a354-2943c3a93261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683613654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2683613654
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.695967309
Short name T578
Test name
Test status
Simulation time 4050761414 ps
CPU time 7.97 seconds
Started Jan 21 01:35:19 PM PST 24
Finished Jan 21 01:35:28 PM PST 24
Peak memory 198472 kb
Host smart-94c45bfd-7a22-440a-91e3-3e5f4bf172e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695967309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.695967309
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3095215306
Short name T359
Test name
Test status
Simulation time 76194801175 ps
CPU time 63.92 seconds
Started Jan 21 01:35:19 PM PST 24
Finished Jan 21 01:36:24 PM PST 24
Peak memory 200020 kb
Host smart-62ce3a96-9244-4f93-ae70-616b6679e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095215306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3095215306
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1779419627
Short name T502
Test name
Test status
Simulation time 2052764121 ps
CPU time 3.53 seconds
Started Jan 21 01:35:17 PM PST 24
Finished Jan 21 01:35:22 PM PST 24
Peak memory 195488 kb
Host smart-98032692-b5e7-4c8a-a1fd-b519a988bb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779419627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1779419627
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2772044010
Short name T773
Test name
Test status
Simulation time 5711121855 ps
CPU time 9.24 seconds
Started Jan 21 01:35:08 PM PST 24
Finished Jan 21 01:35:19 PM PST 24
Peak memory 199396 kb
Host smart-e002d465-1cc4-401b-8d3a-904eb4f473cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772044010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2772044010
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3410416986
Short name T571
Test name
Test status
Simulation time 46556093799 ps
CPU time 53.11 seconds
Started Jan 21 01:35:35 PM PST 24
Finished Jan 21 01:36:30 PM PST 24
Peak memory 199980 kb
Host smart-4959d6ef-d763-403f-be2e-cabc022a5c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410416986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3410416986
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3609924624
Short name T444
Test name
Test status
Simulation time 44036301727 ps
CPU time 481.87 seconds
Started Jan 21 02:29:14 PM PST 24
Finished Jan 21 02:37:16 PM PST 24
Peak memory 214040 kb
Host smart-1f24f5e9-e0cb-4d39-8286-fca44dae401a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609924624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3609924624
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2699866977
Short name T920
Test name
Test status
Simulation time 3183496310 ps
CPU time 2.31 seconds
Started Jan 21 02:40:42 PM PST 24
Finished Jan 21 02:40:49 PM PST 24
Peak memory 199232 kb
Host smart-60302d90-85ab-4b70-8224-2b73760fde53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699866977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2699866977
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1525591468
Short name T667
Test name
Test status
Simulation time 260301997702 ps
CPU time 121.27 seconds
Started Jan 21 01:35:08 PM PST 24
Finished Jan 21 01:37:10 PM PST 24
Peak memory 199992 kb
Host smart-2279df84-4fd0-426a-b42d-2af62ca5aa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525591468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1525591468
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1048383125
Short name T529
Test name
Test status
Simulation time 13969098 ps
CPU time 0.54 seconds
Started Jan 21 01:35:44 PM PST 24
Finished Jan 21 01:35:46 PM PST 24
Peak memory 195644 kb
Host smart-d06b1c80-2a7f-432f-9abb-5a3e65929d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048383125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1048383125
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1964608349
Short name T556
Test name
Test status
Simulation time 97459593030 ps
CPU time 67.08 seconds
Started Jan 21 01:35:37 PM PST 24
Finished Jan 21 01:36:45 PM PST 24
Peak memory 200024 kb
Host smart-c8dbe6c7-4316-47f4-8a53-c77b7ff22d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964608349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1964608349
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.4042274660
Short name T845
Test name
Test status
Simulation time 36113550692 ps
CPU time 14.66 seconds
Started Jan 21 01:35:31 PM PST 24
Finished Jan 21 01:35:49 PM PST 24
Peak memory 199004 kb
Host smart-93a4b20e-f9e7-4b8c-9346-dc1ec243faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042274660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4042274660
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2814779857
Short name T1022
Test name
Test status
Simulation time 35651330128 ps
CPU time 15.64 seconds
Started Jan 21 01:35:34 PM PST 24
Finished Jan 21 01:35:51 PM PST 24
Peak memory 199052 kb
Host smart-39c773c6-9ed6-4153-a186-52d6d8fb5636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814779857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2814779857
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2713928219
Short name T646
Test name
Test status
Simulation time 143636593377 ps
CPU time 256.15 seconds
Started Jan 21 01:35:32 PM PST 24
Finished Jan 21 01:39:51 PM PST 24
Peak memory 199948 kb
Host smart-5b71e1c2-3b10-4015-bf28-c59d07b74279
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713928219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2713928219
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3169234822
Short name T1194
Test name
Test status
Simulation time 360616043666 ps
CPU time 645.59 seconds
Started Jan 21 01:35:44 PM PST 24
Finished Jan 21 01:46:30 PM PST 24
Peak memory 200048 kb
Host smart-994cde17-2435-477e-9610-229dfb29f358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169234822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3169234822
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2046371014
Short name T687
Test name
Test status
Simulation time 4239348423 ps
CPU time 6.56 seconds
Started Jan 21 01:35:39 PM PST 24
Finished Jan 21 01:35:47 PM PST 24
Peak memory 198336 kb
Host smart-0d690b93-f9a5-4c0d-9d81-a54ce1181bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046371014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2046371014
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.671311477
Short name T568
Test name
Test status
Simulation time 61187847660 ps
CPU time 12.9 seconds
Started Jan 21 01:35:33 PM PST 24
Finished Jan 21 01:35:48 PM PST 24
Peak memory 195036 kb
Host smart-35d48b4d-e1b0-4d5f-9941-59897b5c6f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671311477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.671311477
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1600075364
Short name T829
Test name
Test status
Simulation time 32463731193 ps
CPU time 110.24 seconds
Started Jan 21 01:35:44 PM PST 24
Finished Jan 21 01:37:35 PM PST 24
Peak memory 199988 kb
Host smart-bbb94c96-938c-4664-a346-a420d60dc22c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600075364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1600075364
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3449365079
Short name T447
Test name
Test status
Simulation time 933148689 ps
CPU time 2.72 seconds
Started Jan 21 01:35:36 PM PST 24
Finished Jan 21 01:35:41 PM PST 24
Peak memory 197888 kb
Host smart-55b4d874-5053-432c-8c3a-e9c52ea09b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449365079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3449365079
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4037248291
Short name T871
Test name
Test status
Simulation time 2009219845 ps
CPU time 1.86 seconds
Started Jan 21 01:35:34 PM PST 24
Finished Jan 21 01:35:37 PM PST 24
Peak memory 195472 kb
Host smart-f57ba45d-87c3-4b50-abbf-d28b6e224a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037248291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4037248291
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3568708949
Short name T433
Test name
Test status
Simulation time 480371340 ps
CPU time 1.43 seconds
Started Jan 21 01:35:35 PM PST 24
Finished Jan 21 01:35:39 PM PST 24
Peak memory 198176 kb
Host smart-6f1fe1a4-02bd-47e9-a320-068bfca76b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568708949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3568708949
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.4067891343
Short name T530
Test name
Test status
Simulation time 7422860810 ps
CPU time 15.88 seconds
Started Jan 21 01:35:42 PM PST 24
Finished Jan 21 01:36:00 PM PST 24
Peak memory 199832 kb
Host smart-db19d18d-c671-42c1-af16-d5c82cca521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067891343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.4067891343
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3006625389
Short name T807
Test name
Test status
Simulation time 56382252100 ps
CPU time 107.71 seconds
Started Jan 21 01:35:31 PM PST 24
Finished Jan 21 01:37:23 PM PST 24
Peak memory 199916 kb
Host smart-4a6cccfe-890f-41f5-ac13-d9b48273454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006625389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3006625389
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2547433920
Short name T1041
Test name
Test status
Simulation time 15070499 ps
CPU time 0.56 seconds
Started Jan 21 01:36:06 PM PST 24
Finished Jan 21 01:36:17 PM PST 24
Peak memory 195576 kb
Host smart-80889690-38e0-46c8-93e7-a0f2c7629644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547433920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2547433920
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.631156703
Short name T390
Test name
Test status
Simulation time 95479960940 ps
CPU time 44.96 seconds
Started Jan 21 01:35:48 PM PST 24
Finished Jan 21 01:36:35 PM PST 24
Peak memory 199948 kb
Host smart-985496b2-8aea-44d7-9b7c-f8326acbd7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631156703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.631156703
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1820916397
Short name T870
Test name
Test status
Simulation time 20704270422 ps
CPU time 29.89 seconds
Started Jan 21 01:35:49 PM PST 24
Finished Jan 21 01:36:21 PM PST 24
Peak memory 199728 kb
Host smart-96b612ce-157f-4060-8486-42e610b9fa0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820916397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1820916397
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3063327871
Short name T213
Test name
Test status
Simulation time 64450686285 ps
CPU time 89.64 seconds
Started Jan 21 01:35:48 PM PST 24
Finished Jan 21 01:37:20 PM PST 24
Peak memory 199924 kb
Host smart-5395ac37-78e7-4c6e-85b6-262b4aa54d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063327871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3063327871
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2262641511
Short name T581
Test name
Test status
Simulation time 686928887161 ps
CPU time 492.12 seconds
Started Jan 21 01:35:49 PM PST 24
Finished Jan 21 01:44:04 PM PST 24
Peak memory 200020 kb
Host smart-455a07a5-2e60-4688-9c4c-8e22cba35254
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262641511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2262641511
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.147761031
Short name T405
Test name
Test status
Simulation time 171404264572 ps
CPU time 241.11 seconds
Started Jan 21 01:35:59 PM PST 24
Finished Jan 21 01:40:02 PM PST 24
Peak memory 199880 kb
Host smart-5c50d5c0-d459-4f55-8fe1-903ab2792200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147761031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.147761031
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3867432339
Short name T676
Test name
Test status
Simulation time 4921220876 ps
CPU time 4.02 seconds
Started Jan 21 01:35:59 PM PST 24
Finished Jan 21 01:36:04 PM PST 24
Peak memory 199024 kb
Host smart-1261e497-82a6-4675-91ac-ad82cf6529e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867432339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3867432339
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.307797630
Short name T1019
Test name
Test status
Simulation time 10926669528 ps
CPU time 13.1 seconds
Started Jan 21 01:35:51 PM PST 24
Finished Jan 21 01:36:05 PM PST 24
Peak memory 197292 kb
Host smart-21d09866-98ee-46bd-b61d-032322571b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307797630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.307797630
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.258223622
Short name T1185
Test name
Test status
Simulation time 16880845950 ps
CPU time 190.99 seconds
Started Jan 21 01:35:57 PM PST 24
Finished Jan 21 01:39:10 PM PST 24
Peak memory 199968 kb
Host smart-f0f3a83b-c47f-4492-aab0-3d1c9aa8c9ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258223622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.258223622
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2115024381
Short name T25
Test name
Test status
Simulation time 67143998961 ps
CPU time 111.43 seconds
Started Jan 21 01:35:57 PM PST 24
Finished Jan 21 01:37:50 PM PST 24
Peak memory 199780 kb
Host smart-b0c34fa9-c2b1-4969-881d-6f66e015e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115024381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2115024381
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1863153273
Short name T888
Test name
Test status
Simulation time 1754140525 ps
CPU time 2 seconds
Started Jan 21 01:35:48 PM PST 24
Finished Jan 21 01:35:53 PM PST 24
Peak memory 195432 kb
Host smart-7a872f7b-fe46-42ff-952a-429622567079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863153273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1863153273
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1533799609
Short name T880
Test name
Test status
Simulation time 279587632 ps
CPU time 2.49 seconds
Started Jan 21 01:35:45 PM PST 24
Finished Jan 21 01:35:49 PM PST 24
Peak memory 198396 kb
Host smart-5bbca637-7097-486c-ab1c-2a8b2cf4a5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533799609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1533799609
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1533160085
Short name T1197
Test name
Test status
Simulation time 49991368072 ps
CPU time 39.66 seconds
Started Jan 21 01:36:08 PM PST 24
Finished Jan 21 01:36:57 PM PST 24
Peak memory 198484 kb
Host smart-89305a58-6d1b-4d07-a525-3ed097f5a7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533160085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1533160085
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1112075491
Short name T738
Test name
Test status
Simulation time 277965473481 ps
CPU time 555.34 seconds
Started Jan 21 01:36:02 PM PST 24
Finished Jan 21 01:45:24 PM PST 24
Peak memory 216608 kb
Host smart-cc97b25e-e795-484b-bdde-3320b1b8eb5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112075491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1112075491
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3290970484
Short name T1228
Test name
Test status
Simulation time 2709890899 ps
CPU time 2.23 seconds
Started Jan 21 01:35:57 PM PST 24
Finished Jan 21 01:36:01 PM PST 24
Peak memory 197924 kb
Host smart-b5b0b100-4800-4c2b-bd9c-a4df189abe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290970484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3290970484
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2620238812
Short name T1057
Test name
Test status
Simulation time 78130806059 ps
CPU time 115.23 seconds
Started Jan 21 01:35:49 PM PST 24
Finished Jan 21 01:37:46 PM PST 24
Peak memory 199928 kb
Host smart-77908cb7-7b01-491f-bca6-2c7676127b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620238812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2620238812
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3845923218
Short name T1178
Test name
Test status
Simulation time 47696582 ps
CPU time 0.54 seconds
Started Jan 21 01:36:16 PM PST 24
Finished Jan 21 01:36:27 PM PST 24
Peak memory 195540 kb
Host smart-1c65f206-43bd-4c0f-8553-04eee50b088d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845923218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3845923218
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.243886008
Short name T1102
Test name
Test status
Simulation time 29721351688 ps
CPU time 45.11 seconds
Started Jan 21 01:36:13 PM PST 24
Finished Jan 21 01:37:10 PM PST 24
Peak memory 199984 kb
Host smart-4e138e2b-dbd5-4edb-b16d-e12850a31d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243886008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.243886008
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2968162156
Short name T161
Test name
Test status
Simulation time 158940251977 ps
CPU time 260.65 seconds
Started Jan 21 01:36:05 PM PST 24
Finished Jan 21 01:40:37 PM PST 24
Peak memory 199956 kb
Host smart-2bacf5b5-91b0-413b-bcff-0199b7a8343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968162156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2968162156
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3680357544
Short name T624
Test name
Test status
Simulation time 697011259234 ps
CPU time 156.6 seconds
Started Jan 21 01:36:17 PM PST 24
Finished Jan 21 01:39:04 PM PST 24
Peak memory 199512 kb
Host smart-31828da2-e7dc-47b9-b220-af11ef344447
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680357544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3680357544
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.193582211
Short name T883
Test name
Test status
Simulation time 163859367949 ps
CPU time 281.48 seconds
Started Jan 21 01:36:19 PM PST 24
Finished Jan 21 01:41:09 PM PST 24
Peak memory 199992 kb
Host smart-beafbf38-9054-4201-94ff-f42df7f55f58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193582211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.193582211
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2597178661
Short name T603
Test name
Test status
Simulation time 3510612743 ps
CPU time 6.64 seconds
Started Jan 21 01:36:17 PM PST 24
Finished Jan 21 01:36:34 PM PST 24
Peak memory 200000 kb
Host smart-3423aa26-d861-4df0-982c-6f878f90c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597178661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2597178661
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.440857308
Short name T1076
Test name
Test status
Simulation time 47289219598 ps
CPU time 75.16 seconds
Started Jan 21 01:36:16 PM PST 24
Finished Jan 21 01:37:42 PM PST 24
Peak memory 199144 kb
Host smart-de4400e5-9456-438a-a2ba-07fa3b6b6aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440857308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.440857308
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2647786148
Short name T415
Test name
Test status
Simulation time 17827622302 ps
CPU time 85.6 seconds
Started Jan 21 01:36:17 PM PST 24
Finished Jan 21 01:37:52 PM PST 24
Peak memory 200008 kb
Host smart-279a9e7f-efc9-4069-a49e-1295e3377bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647786148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2647786148
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.4049725382
Short name T428
Test name
Test status
Simulation time 53831772173 ps
CPU time 43.4 seconds
Started Jan 21 01:36:19 PM PST 24
Finished Jan 21 01:37:11 PM PST 24
Peak memory 195552 kb
Host smart-2d3f081e-6bf2-467e-8cf0-7ab7cb3318d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049725382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4049725382
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.4201443663
Short name T1047
Test name
Test status
Simulation time 690050675 ps
CPU time 3.21 seconds
Started Jan 21 01:36:10 PM PST 24
Finished Jan 21 01:36:21 PM PST 24
Peak memory 197740 kb
Host smart-bc0acf1b-1af7-4250-aa13-1e4560e7c280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201443663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.4201443663
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3034992269
Short name T709
Test name
Test status
Simulation time 155194541863 ps
CPU time 103.52 seconds
Started Jan 21 01:36:18 PM PST 24
Finished Jan 21 01:38:11 PM PST 24
Peak memory 208372 kb
Host smart-b79e542d-f3e8-4a42-a014-f29b6d1594f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034992269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3034992269
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.964098493
Short name T1000
Test name
Test status
Simulation time 49312791308 ps
CPU time 529.77 seconds
Started Jan 21 01:36:17 PM PST 24
Finished Jan 21 01:45:17 PM PST 24
Peak memory 209468 kb
Host smart-da005a21-c7fb-46b2-bb3c-027d7feaf281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964098493 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.964098493
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2346584911
Short name T771
Test name
Test status
Simulation time 7242531230 ps
CPU time 19.45 seconds
Started Jan 21 02:49:41 PM PST 24
Finished Jan 21 02:50:01 PM PST 24
Peak memory 199388 kb
Host smart-2d43414e-b878-47ea-b928-12f7e22a794f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346584911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2346584911
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1752693636
Short name T837
Test name
Test status
Simulation time 61470312345 ps
CPU time 169.27 seconds
Started Jan 21 01:36:10 PM PST 24
Finished Jan 21 01:39:07 PM PST 24
Peak memory 199972 kb
Host smart-054f706d-91e0-45a7-afa7-1af6b2e902a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752693636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1752693636
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3384285901
Short name T908
Test name
Test status
Simulation time 14579807 ps
CPU time 0.55 seconds
Started Jan 21 01:36:36 PM PST 24
Finished Jan 21 01:36:39 PM PST 24
Peak memory 195588 kb
Host smart-211e80b7-83fa-452a-b01e-a8a77d8cbccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384285901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3384285901
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3076341865
Short name T915
Test name
Test status
Simulation time 320195807153 ps
CPU time 421.22 seconds
Started Jan 21 01:36:28 PM PST 24
Finished Jan 21 01:43:33 PM PST 24
Peak memory 199948 kb
Host smart-a34bd811-c3b9-40cb-95dd-cd1c10de2fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076341865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3076341865
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2078246970
Short name T316
Test name
Test status
Simulation time 131973396584 ps
CPU time 223.2 seconds
Started Jan 21 01:36:26 PM PST 24
Finished Jan 21 01:40:14 PM PST 24
Peak memory 199664 kb
Host smart-57f395cd-b4f9-4657-8b22-9e3588f18845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078246970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2078246970
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3343234633
Short name T229
Test name
Test status
Simulation time 30287836097 ps
CPU time 24.14 seconds
Started Jan 21 02:13:09 PM PST 24
Finished Jan 21 02:13:35 PM PST 24
Peak memory 199908 kb
Host smart-fb13a560-2b54-4bd5-a017-8e81728887ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343234633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3343234633
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3695701689
Short name T934
Test name
Test status
Simulation time 99140479332 ps
CPU time 18.03 seconds
Started Jan 21 01:36:26 PM PST 24
Finished Jan 21 01:36:49 PM PST 24
Peak memory 198452 kb
Host smart-0ae8a8cd-2b26-4256-aaac-cb6783c257e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695701689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3695701689
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.405259988
Short name T841
Test name
Test status
Simulation time 42384320265 ps
CPU time 342.5 seconds
Started Jan 21 01:36:36 PM PST 24
Finished Jan 21 01:42:20 PM PST 24
Peak memory 199844 kb
Host smart-41f9935b-a58c-4fd6-bf11-37baf09b794a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405259988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.405259988
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3716677876
Short name T12
Test name
Test status
Simulation time 3701643669 ps
CPU time 5.47 seconds
Started Jan 21 01:36:42 PM PST 24
Finished Jan 21 01:36:53 PM PST 24
Peak memory 198724 kb
Host smart-945c6170-9612-4027-9c8a-75362aeca531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716677876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3716677876
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2005635686
Short name T759
Test name
Test status
Simulation time 49292415324 ps
CPU time 127.24 seconds
Started Jan 21 01:36:26 PM PST 24
Finished Jan 21 01:38:39 PM PST 24
Peak memory 200208 kb
Host smart-4f196613-6aec-400c-9825-c1a17ff0ddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005635686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2005635686
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3260125009
Short name T243
Test name
Test status
Simulation time 5970187593 ps
CPU time 340.68 seconds
Started Jan 21 01:36:41 PM PST 24
Finished Jan 21 01:42:28 PM PST 24
Peak memory 199988 kb
Host smart-018e89eb-497a-467f-b590-40f45582344e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260125009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3260125009
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.886904337
Short name T177
Test name
Test status
Simulation time 31853345681 ps
CPU time 10.48 seconds
Started Jan 21 01:36:29 PM PST 24
Finished Jan 21 01:36:43 PM PST 24
Peak memory 198424 kb
Host smart-80498632-37f4-4b9d-b43a-0f9bac666be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886904337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.886904337
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1666962684
Short name T597
Test name
Test status
Simulation time 788893573 ps
CPU time 0.9 seconds
Started Jan 21 01:36:30 PM PST 24
Finished Jan 21 01:36:33 PM PST 24
Peak memory 195488 kb
Host smart-f1224f33-f7b8-498f-940c-d62f6c3d3068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666962684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1666962684
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.4223092088
Short name T421
Test name
Test status
Simulation time 5726386169 ps
CPU time 9.27 seconds
Started Jan 21 01:36:17 PM PST 24
Finished Jan 21 01:36:36 PM PST 24
Peak memory 199820 kb
Host smart-90300e13-22e6-4864-a0f8-6037f9bc23db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223092088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.4223092088
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2698784719
Short name T443
Test name
Test status
Simulation time 39824815799 ps
CPU time 540.07 seconds
Started Jan 21 01:36:35 PM PST 24
Finished Jan 21 01:45:38 PM PST 24
Peak memory 211468 kb
Host smart-fcab8574-9257-4a6a-ab67-9de5da92eb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698784719 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2698784719
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.217341989
Short name T1002
Test name
Test status
Simulation time 1044198428 ps
CPU time 3.87 seconds
Started Jan 21 01:36:32 PM PST 24
Finished Jan 21 01:36:37 PM PST 24
Peak memory 198332 kb
Host smart-c1757a88-0d94-4235-aa8e-6c239d9b670b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217341989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.217341989
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3381901431
Short name T1021
Test name
Test status
Simulation time 43728764576 ps
CPU time 15 seconds
Started Jan 21 01:36:28 PM PST 24
Finished Jan 21 01:36:47 PM PST 24
Peak memory 198524 kb
Host smart-33ed8f59-39ef-49d8-9909-467e5c32f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381901431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3381901431
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3686526457
Short name T1032
Test name
Test status
Simulation time 51100093 ps
CPU time 0.55 seconds
Started Jan 21 01:36:46 PM PST 24
Finished Jan 21 01:36:50 PM PST 24
Peak memory 195464 kb
Host smart-18328828-17b5-49e9-9939-3cd8a845a6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686526457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3686526457
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1525694241
Short name T600
Test name
Test status
Simulation time 98401907689 ps
CPU time 79.29 seconds
Started Jan 21 01:36:37 PM PST 24
Finished Jan 21 01:37:57 PM PST 24
Peak memory 199964 kb
Host smart-97a028dc-f471-465e-a76b-c02ce4d2d6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525694241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1525694241
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3884721779
Short name T432
Test name
Test status
Simulation time 27162218958 ps
CPU time 21.79 seconds
Started Jan 21 02:20:33 PM PST 24
Finished Jan 21 02:20:56 PM PST 24
Peak memory 199408 kb
Host smart-ee4b189b-65cc-4c30-890d-65488c5c185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884721779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3884721779
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1096485849
Short name T163
Test name
Test status
Simulation time 157330552180 ps
CPU time 133.81 seconds
Started Jan 21 01:36:38 PM PST 24
Finished Jan 21 01:38:54 PM PST 24
Peak memory 199884 kb
Host smart-d8dcfb02-64a9-4cea-921f-5186f7d0e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096485849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1096485849
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.271082179
Short name T576
Test name
Test status
Simulation time 286577441889 ps
CPU time 439.63 seconds
Started Jan 21 01:36:46 PM PST 24
Finished Jan 21 01:44:09 PM PST 24
Peak memory 199052 kb
Host smart-e4e0e17f-aafc-405b-aa81-bf53839866c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271082179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.271082179
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2435371981
Short name T862
Test name
Test status
Simulation time 105069523326 ps
CPU time 803.17 seconds
Started Jan 21 01:36:44 PM PST 24
Finished Jan 21 01:50:12 PM PST 24
Peak memory 200032 kb
Host smart-ff3404f5-df48-4d0b-b395-0819759828db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435371981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2435371981
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2251824307
Short name T911
Test name
Test status
Simulation time 6039288371 ps
CPU time 30.14 seconds
Started Jan 21 01:36:45 PM PST 24
Finished Jan 21 01:37:19 PM PST 24
Peak memory 199836 kb
Host smart-f49ae58e-6b88-4880-9c2a-9a37fc7dd92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251824307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2251824307
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.413074214
Short name T103
Test name
Test status
Simulation time 132447441878 ps
CPU time 202.54 seconds
Started Jan 21 01:36:45 PM PST 24
Finished Jan 21 01:40:12 PM PST 24
Peak memory 200052 kb
Host smart-b494db9d-2324-41f4-aebb-e5167f12c58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413074214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.413074214
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3638342657
Short name T917
Test name
Test status
Simulation time 22231855772 ps
CPU time 1222.76 seconds
Started Jan 21 01:36:46 PM PST 24
Finished Jan 21 01:57:13 PM PST 24
Peak memory 199968 kb
Host smart-fd43ccf0-6d6a-49d8-a358-f5c2ab160769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638342657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3638342657
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1160448775
Short name T1183
Test name
Test status
Simulation time 2601365010 ps
CPU time 8.4 seconds
Started Jan 21 01:36:41 PM PST 24
Finished Jan 21 01:36:56 PM PST 24
Peak memory 198256 kb
Host smart-6bff7289-2052-4e6c-ae40-3f1b162e2f05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160448775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1160448775
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.552575253
Short name T284
Test name
Test status
Simulation time 181663772783 ps
CPU time 145.11 seconds
Started Jan 21 01:36:45 PM PST 24
Finished Jan 21 01:39:15 PM PST 24
Peak memory 199432 kb
Host smart-36e49885-9439-400d-a706-68480d7f1abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552575253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.552575253
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2565174785
Short name T791
Test name
Test status
Simulation time 33356313293 ps
CPU time 55.12 seconds
Started Jan 21 01:36:47 PM PST 24
Finished Jan 21 01:37:45 PM PST 24
Peak memory 195544 kb
Host smart-19e980e6-67a0-4e3b-92d7-c0686e968442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565174785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2565174785
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3446041454
Short name T512
Test name
Test status
Simulation time 845970342 ps
CPU time 2.86 seconds
Started Jan 21 01:36:36 PM PST 24
Finished Jan 21 01:36:41 PM PST 24
Peak memory 198980 kb
Host smart-992036a7-13d9-4716-895e-ea253341658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446041454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3446041454
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.357106350
Short name T254
Test name
Test status
Simulation time 392566984301 ps
CPU time 415.03 seconds
Started Jan 21 01:36:44 PM PST 24
Finished Jan 21 01:43:44 PM PST 24
Peak memory 215804 kb
Host smart-edd4efbf-c63c-4044-a8a4-0cacfb5783a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357106350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.357106350
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1722178472
Short name T1085
Test name
Test status
Simulation time 51313948589 ps
CPU time 296.09 seconds
Started Jan 21 01:36:45 PM PST 24
Finished Jan 21 01:41:45 PM PST 24
Peak memory 208388 kb
Host smart-b913e0ac-a605-4866-9551-a2ac3b78d7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722178472 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1722178472
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.919548940
Short name T655
Test name
Test status
Simulation time 6424968107 ps
CPU time 17.8 seconds
Started Jan 21 01:36:47 PM PST 24
Finished Jan 21 01:37:08 PM PST 24
Peak memory 199260 kb
Host smart-5ce55c6f-2597-4356-9d54-d91f0eb7546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919548940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.919548940
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3894342916
Short name T560
Test name
Test status
Simulation time 18816436082 ps
CPU time 8 seconds
Started Jan 21 01:36:37 PM PST 24
Finished Jan 21 01:36:47 PM PST 24
Peak memory 199840 kb
Host smart-22599dcd-df1a-412b-952b-bbeee9048886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894342916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3894342916
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1704890853
Short name T88
Test name
Test status
Simulation time 17153621 ps
CPU time 0.55 seconds
Started Jan 21 01:37:12 PM PST 24
Finished Jan 21 01:37:13 PM PST 24
Peak memory 194632 kb
Host smart-b8a7e58f-e797-4298-9383-92f49702565a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704890853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1704890853
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1012857659
Short name T721
Test name
Test status
Simulation time 61304217859 ps
CPU time 94.29 seconds
Started Jan 21 01:36:57 PM PST 24
Finished Jan 21 01:38:33 PM PST 24
Peak memory 200024 kb
Host smart-4bfaac8e-1186-4667-b3f2-86707a7fcff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012857659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1012857659
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3348317307
Short name T1020
Test name
Test status
Simulation time 103584602729 ps
CPU time 264.75 seconds
Started Jan 21 02:26:14 PM PST 24
Finished Jan 21 02:30:39 PM PST 24
Peak memory 199956 kb
Host smart-e4211020-f7b7-4981-bdd4-c16b73eafab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348317307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3348317307
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2656563244
Short name T707
Test name
Test status
Simulation time 158225719410 ps
CPU time 957.28 seconds
Started Jan 21 01:37:05 PM PST 24
Finished Jan 21 01:53:03 PM PST 24
Peak memory 199844 kb
Host smart-cada6d30-a6a6-44da-a4ef-5410796ac204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656563244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2656563244
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1360618332
Short name T897
Test name
Test status
Simulation time 3326405186 ps
CPU time 7.09 seconds
Started Jan 21 01:37:06 PM PST 24
Finished Jan 21 01:37:14 PM PST 24
Peak memory 199020 kb
Host smart-8b48e1ab-a1a3-4f21-b60d-322f5bf30a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360618332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1360618332
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2295591189
Short name T610
Test name
Test status
Simulation time 17866642205 ps
CPU time 28.55 seconds
Started Jan 21 01:37:05 PM PST 24
Finished Jan 21 01:37:34 PM PST 24
Peak memory 197764 kb
Host smart-5957654e-e02c-467c-a9e0-b86f3d652091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295591189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2295591189
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3518953377
Short name T684
Test name
Test status
Simulation time 29584320234 ps
CPU time 699.97 seconds
Started Jan 21 02:00:55 PM PST 24
Finished Jan 21 02:12:36 PM PST 24
Peak memory 200064 kb
Host smart-f9ab8f16-1924-4954-a1b0-d1c0177f8cc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518953377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3518953377
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.412469956
Short name T846
Test name
Test status
Simulation time 32253939781 ps
CPU time 53.44 seconds
Started Jan 21 01:37:06 PM PST 24
Finished Jan 21 01:38:00 PM PST 24
Peak memory 199516 kb
Host smart-3f6c9f9a-8e3d-43aa-abf0-476e7e373dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412469956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.412469956
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.572852119
Short name T519
Test name
Test status
Simulation time 2581975326 ps
CPU time 4.41 seconds
Started Jan 21 01:37:04 PM PST 24
Finished Jan 21 01:37:09 PM PST 24
Peak memory 195556 kb
Host smart-97941f39-f492-4af0-b2ae-8a6f97e86b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572852119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.572852119
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1459249304
Short name T420
Test name
Test status
Simulation time 5997284234 ps
CPU time 30.71 seconds
Started Jan 21 01:36:44 PM PST 24
Finished Jan 21 01:37:20 PM PST 24
Peak memory 199356 kb
Host smart-461c7eb8-1f19-4be5-9596-c4dd164e7872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459249304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1459249304
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2678665019
Short name T1050
Test name
Test status
Simulation time 26207782141 ps
CPU time 231.53 seconds
Started Jan 21 01:37:03 PM PST 24
Finished Jan 21 01:40:56 PM PST 24
Peak memory 208504 kb
Host smart-acb7294a-25fb-4607-9a19-852801520fd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678665019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2678665019
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3943673699
Short name T652
Test name
Test status
Simulation time 1213436706 ps
CPU time 2.66 seconds
Started Jan 21 01:37:05 PM PST 24
Finished Jan 21 01:37:09 PM PST 24
Peak memory 199008 kb
Host smart-184dfc22-3dc1-4a4a-b2c3-39dd4c42f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943673699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3943673699
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1365216732
Short name T596
Test name
Test status
Simulation time 25485289276 ps
CPU time 8.72 seconds
Started Jan 21 01:36:55 PM PST 24
Finished Jan 21 01:37:06 PM PST 24
Peak memory 198484 kb
Host smart-42e2eb21-9965-4a23-ac3b-a144d4fb6572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365216732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1365216732
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1060000075
Short name T941
Test name
Test status
Simulation time 16664772 ps
CPU time 0.59 seconds
Started Jan 21 01:37:20 PM PST 24
Finished Jan 21 01:37:22 PM PST 24
Peak memory 195540 kb
Host smart-050d0c7c-d16d-4882-8fae-777e590ee92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060000075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1060000075
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.952758552
Short name T1217
Test name
Test status
Simulation time 77514389302 ps
CPU time 23.01 seconds
Started Jan 21 01:37:15 PM PST 24
Finished Jan 21 01:37:39 PM PST 24
Peak memory 199968 kb
Host smart-5b6bc3cd-445e-4d13-b553-187f147cef62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952758552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.952758552
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3405049749
Short name T688
Test name
Test status
Simulation time 132910273529 ps
CPU time 228.88 seconds
Started Jan 21 01:37:13 PM PST 24
Finished Jan 21 01:41:03 PM PST 24
Peak memory 199908 kb
Host smart-3f4f26f3-9e98-4490-8f68-ba3eb8911fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405049749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3405049749
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1830702291
Short name T118
Test name
Test status
Simulation time 104905890626 ps
CPU time 164.92 seconds
Started Jan 21 01:37:11 PM PST 24
Finished Jan 21 01:39:57 PM PST 24
Peak memory 200012 kb
Host smart-6b63b406-f48c-4eb4-ac00-19faac90f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830702291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1830702291
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3552817776
Short name T453
Test name
Test status
Simulation time 469658070975 ps
CPU time 156.76 seconds
Started Jan 21 01:37:10 PM PST 24
Finished Jan 21 01:39:48 PM PST 24
Peak memory 200000 kb
Host smart-0e6b281f-8c2f-47b5-9b82-c8a80886af54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552817776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3552817776
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2266238675
Short name T554
Test name
Test status
Simulation time 134323922176 ps
CPU time 411.36 seconds
Started Jan 21 01:37:23 PM PST 24
Finished Jan 21 01:44:15 PM PST 24
Peak memory 199924 kb
Host smart-1bb31991-fc5d-42fc-b558-937c96c467bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266238675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2266238675
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2254830510
Short name T935
Test name
Test status
Simulation time 3503287170 ps
CPU time 14.53 seconds
Started Jan 21 01:37:20 PM PST 24
Finished Jan 21 01:37:36 PM PST 24
Peak memory 198724 kb
Host smart-99804f0e-fa38-4a72-b5f7-a327a614615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254830510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2254830510
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3360376273
Short name T1066
Test name
Test status
Simulation time 62770791119 ps
CPU time 85.62 seconds
Started Jan 21 01:37:12 PM PST 24
Finished Jan 21 01:38:38 PM PST 24
Peak memory 198864 kb
Host smart-dd3fa5ee-44f1-4683-962b-355f4d2327ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360376273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3360376273
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.4152239427
Short name T441
Test name
Test status
Simulation time 9387037906 ps
CPU time 271.76 seconds
Started Jan 21 01:37:19 PM PST 24
Finished Jan 21 01:41:52 PM PST 24
Peak memory 199916 kb
Host smart-b64fccc9-3779-43b5-810d-7e833a80e922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4152239427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.4152239427
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2930987884
Short name T357
Test name
Test status
Simulation time 92297705573 ps
CPU time 42.87 seconds
Started Jan 21 01:37:16 PM PST 24
Finished Jan 21 01:38:00 PM PST 24
Peak memory 200012 kb
Host smart-06900503-8071-4087-b0b6-27a1b53265f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930987884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2930987884
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.71874007
Short name T1044
Test name
Test status
Simulation time 1725291399 ps
CPU time 3.15 seconds
Started Jan 21 01:37:16 PM PST 24
Finished Jan 21 01:37:20 PM PST 24
Peak memory 195460 kb
Host smart-fad807db-d0a2-41ca-b25c-eacb050214cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71874007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.71874007
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1333648490
Short name T1028
Test name
Test status
Simulation time 289829171 ps
CPU time 1.05 seconds
Started Jan 21 01:37:12 PM PST 24
Finished Jan 21 01:37:14 PM PST 24
Peak memory 198848 kb
Host smart-c81db7d8-cfde-47cc-aa69-71a1b67744a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333648490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1333648490
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.860625885
Short name T312
Test name
Test status
Simulation time 269356415899 ps
CPU time 407.6 seconds
Started Jan 21 01:37:22 PM PST 24
Finished Jan 21 01:44:11 PM PST 24
Peak memory 215620 kb
Host smart-c502b1f5-852d-4a1a-93a5-f1f3c7e3ef41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860625885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.860625885
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.336856115
Short name T63
Test name
Test status
Simulation time 273834329275 ps
CPU time 786.38 seconds
Started Jan 21 01:37:21 PM PST 24
Finished Jan 21 01:50:29 PM PST 24
Peak memory 216632 kb
Host smart-6afdc61d-53a9-4eed-9ab7-4fe148517f5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336856115 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.336856115
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1104521112
Short name T598
Test name
Test status
Simulation time 1399260303 ps
CPU time 2.15 seconds
Started Jan 21 01:37:22 PM PST 24
Finished Jan 21 01:37:25 PM PST 24
Peak memory 197972 kb
Host smart-d0329b7e-94ee-4c35-9241-984aca33ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104521112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1104521112
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2618445509
Short name T720
Test name
Test status
Simulation time 27651563091 ps
CPU time 51.45 seconds
Started Jan 21 01:37:16 PM PST 24
Finished Jan 21 01:38:09 PM PST 24
Peak memory 199964 kb
Host smart-be6900a8-1284-4ca5-ae19-c5071927777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618445509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2618445509
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.305504225
Short name T1111
Test name
Test status
Simulation time 20932083 ps
CPU time 0.54 seconds
Started Jan 21 01:37:45 PM PST 24
Finished Jan 21 01:37:47 PM PST 24
Peak memory 195424 kb
Host smart-04686cc1-a01c-4608-867b-382ec837942d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305504225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.305504225
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3817189668
Short name T768
Test name
Test status
Simulation time 215656170061 ps
CPU time 87.25 seconds
Started Jan 21 01:37:32 PM PST 24
Finished Jan 21 01:39:01 PM PST 24
Peak memory 199972 kb
Host smart-f9fcfcc1-1073-407e-82ed-79cd012ac3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817189668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3817189668
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1572116117
Short name T523
Test name
Test status
Simulation time 41955636604 ps
CPU time 18.83 seconds
Started Jan 21 01:37:32 PM PST 24
Finished Jan 21 01:37:53 PM PST 24
Peak memory 198992 kb
Host smart-005ca08e-2637-4062-be71-8a9876f2e3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572116117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1572116117
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3751553559
Short name T122
Test name
Test status
Simulation time 27071687763 ps
CPU time 42.63 seconds
Started Jan 21 02:12:07 PM PST 24
Finished Jan 21 02:12:51 PM PST 24
Peak memory 199968 kb
Host smart-059c1d33-2357-4746-b8ac-25253f17ba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751553559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3751553559
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2498975584
Short name T166
Test name
Test status
Simulation time 1413056809746 ps
CPU time 569.87 seconds
Started Jan 21 01:37:31 PM PST 24
Finished Jan 21 01:47:01 PM PST 24
Peak memory 198528 kb
Host smart-7da04f00-1b25-4e3c-953f-43eb4c0f3dc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498975584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2498975584
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3052240798
Short name T402
Test name
Test status
Simulation time 58324465080 ps
CPU time 310.67 seconds
Started Jan 21 01:37:46 PM PST 24
Finished Jan 21 01:42:58 PM PST 24
Peak memory 200012 kb
Host smart-dbe9f66e-6a8f-4194-b932-b7dcf794287c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052240798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3052240798
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.244174141
Short name T937
Test name
Test status
Simulation time 7349592229 ps
CPU time 13.88 seconds
Started Jan 21 01:37:46 PM PST 24
Finished Jan 21 01:38:01 PM PST 24
Peak memory 199168 kb
Host smart-43c1094e-74fd-42a5-9708-6706eeb31a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244174141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.244174141
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3953433886
Short name T1086
Test name
Test status
Simulation time 17309990729 ps
CPU time 29.52 seconds
Started Jan 21 01:37:30 PM PST 24
Finished Jan 21 01:38:01 PM PST 24
Peak memory 196904 kb
Host smart-4655e2de-fabd-45f2-b348-696420431810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953433886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3953433886
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.4245887013
Short name T747
Test name
Test status
Simulation time 14890042315 ps
CPU time 186.53 seconds
Started Jan 21 01:37:42 PM PST 24
Finished Jan 21 01:40:50 PM PST 24
Peak memory 199920 kb
Host smart-3b04fe68-4aff-4049-8c14-9688900fa7b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245887013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4245887013
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.994703301
Short name T557
Test name
Test status
Simulation time 1489633190 ps
CPU time 6.04 seconds
Started Jan 21 02:21:50 PM PST 24
Finished Jan 21 02:21:57 PM PST 24
Peak memory 198052 kb
Host smart-4d290c7f-855a-4646-842d-2b96a4bca355
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994703301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.994703301
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4054534991
Short name T1168
Test name
Test status
Simulation time 120762705542 ps
CPU time 171.34 seconds
Started Jan 21 01:37:44 PM PST 24
Finished Jan 21 01:40:36 PM PST 24
Peak memory 200012 kb
Host smart-3168bb92-da26-45aa-a1b6-12b4cb300c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054534991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4054534991
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.844588430
Short name T762
Test name
Test status
Simulation time 5212404537 ps
CPU time 2.9 seconds
Started Jan 21 01:37:32 PM PST 24
Finished Jan 21 01:37:36 PM PST 24
Peak memory 195496 kb
Host smart-e87d60fc-0963-4b9b-85a9-3ed678440165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844588430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.844588430
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3966543095
Short name T613
Test name
Test status
Simulation time 873455051 ps
CPU time 2.65 seconds
Started Jan 21 01:37:20 PM PST 24
Finished Jan 21 01:37:24 PM PST 24
Peak memory 198372 kb
Host smart-986629e8-ff9f-4bb4-bbbc-6062d1303df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966543095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3966543095
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3106171901
Short name T987
Test name
Test status
Simulation time 130821312696 ps
CPU time 839.01 seconds
Started Jan 21 01:37:43 PM PST 24
Finished Jan 21 01:51:44 PM PST 24
Peak memory 200056 kb
Host smart-60f61729-1708-4e87-8b27-2f24447101ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106171901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3106171901
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1804877541
Short name T295
Test name
Test status
Simulation time 44601589206 ps
CPU time 585.27 seconds
Started Jan 21 01:37:40 PM PST 24
Finished Jan 21 01:47:26 PM PST 24
Peak memory 216732 kb
Host smart-a5df4464-6855-470d-915b-ff5f24323912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804877541 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1804877541
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.421102866
Short name T633
Test name
Test status
Simulation time 6903641141 ps
CPU time 11.76 seconds
Started Jan 21 01:37:46 PM PST 24
Finished Jan 21 01:37:59 PM PST 24
Peak memory 198792 kb
Host smart-8827dd93-bf07-4e74-846a-839c691f8e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421102866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.421102866
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.437237806
Short name T996
Test name
Test status
Simulation time 97379625514 ps
CPU time 15.85 seconds
Started Jan 21 01:37:30 PM PST 24
Finished Jan 21 01:37:47 PM PST 24
Peak memory 196700 kb
Host smart-629d171f-005e-4111-8347-7e1571844d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437237806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.437237806
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.436901122
Short name T1213
Test name
Test status
Simulation time 14255100 ps
CPU time 0.6 seconds
Started Jan 21 01:38:10 PM PST 24
Finished Jan 21 01:38:11 PM PST 24
Peak memory 195640 kb
Host smart-b2b54dc5-0d8e-43c4-8e46-414b6a956f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436901122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.436901122
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.989462803
Short name T388
Test name
Test status
Simulation time 29047549980 ps
CPU time 18.75 seconds
Started Jan 21 01:37:46 PM PST 24
Finished Jan 21 01:38:06 PM PST 24
Peak memory 199892 kb
Host smart-83ee8809-1339-43dd-adc6-bd0540eac186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989462803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.989462803
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2343497785
Short name T370
Test name
Test status
Simulation time 94082625272 ps
CPU time 42.9 seconds
Started Jan 21 01:37:42 PM PST 24
Finished Jan 21 01:38:25 PM PST 24
Peak memory 199948 kb
Host smart-161bae73-95bb-4be8-9a9a-6507ee670075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343497785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2343497785
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2789519489
Short name T995
Test name
Test status
Simulation time 23712045604 ps
CPU time 42.16 seconds
Started Jan 21 01:37:42 PM PST 24
Finished Jan 21 01:38:25 PM PST 24
Peak memory 199832 kb
Host smart-15827247-6d61-4c0b-a9d2-06a34824d832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789519489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2789519489
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3775482847
Short name T625
Test name
Test status
Simulation time 17370009316 ps
CPU time 4.1 seconds
Started Jan 21 01:37:42 PM PST 24
Finished Jan 21 01:37:47 PM PST 24
Peak memory 197532 kb
Host smart-ff2da01b-c92e-4f13-8511-a5534122ae68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775482847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3775482847
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3528609116
Short name T663
Test name
Test status
Simulation time 64531189098 ps
CPU time 398.22 seconds
Started Jan 21 02:40:03 PM PST 24
Finished Jan 21 02:46:42 PM PST 24
Peak memory 199900 kb
Host smart-84d68d96-000a-4a08-8c74-2dfb4068f2fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528609116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3528609116
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1741339616
Short name T675
Test name
Test status
Simulation time 11001918378 ps
CPU time 10.88 seconds
Started Jan 21 01:37:58 PM PST 24
Finished Jan 21 01:38:10 PM PST 24
Peak memory 198220 kb
Host smart-0a15908e-2f27-433d-a5ff-68f0bd610030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741339616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1741339616
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2656258022
Short name T1124
Test name
Test status
Simulation time 39010555058 ps
CPU time 88.85 seconds
Started Jan 21 01:37:42 PM PST 24
Finished Jan 21 01:39:12 PM PST 24
Peak memory 198264 kb
Host smart-7043deae-f06d-488a-8118-ba1ba43cee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656258022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2656258022
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3455379211
Short name T1069
Test name
Test status
Simulation time 31499557804 ps
CPU time 1595.78 seconds
Started Jan 21 02:13:43 PM PST 24
Finished Jan 21 02:40:20 PM PST 24
Peak memory 200012 kb
Host smart-297c672f-a048-47c7-ba85-a3f2d6eda8cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455379211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3455379211
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1558204545
Short name T599
Test name
Test status
Simulation time 121898665409 ps
CPU time 31.63 seconds
Started Jan 21 02:13:01 PM PST 24
Finished Jan 21 02:13:33 PM PST 24
Peak memory 199996 kb
Host smart-71f4d3d4-3ba3-418d-bac5-ac58f915163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558204545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1558204545
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.450150612
Short name T616
Test name
Test status
Simulation time 3376160168 ps
CPU time 2.05 seconds
Started Jan 21 01:37:45 PM PST 24
Finished Jan 21 01:37:48 PM PST 24
Peak memory 195408 kb
Host smart-d2dc5afa-ef0c-4da5-8012-e7e0839a75ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450150612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.450150612
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.4070072297
Short name T1073
Test name
Test status
Simulation time 265651798 ps
CPU time 1.29 seconds
Started Jan 21 01:37:44 PM PST 24
Finished Jan 21 01:37:47 PM PST 24
Peak memory 197568 kb
Host smart-9ab41e09-e460-43bc-ad36-72c56e1c6271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070072297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4070072297
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4263353978
Short name T956
Test name
Test status
Simulation time 210870830310 ps
CPU time 189.53 seconds
Started Jan 21 01:37:53 PM PST 24
Finished Jan 21 01:41:03 PM PST 24
Peak memory 216704 kb
Host smart-212235ba-1988-4b0f-8e4b-49caa3c5cafd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263353978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4263353978
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3409434909
Short name T1081
Test name
Test status
Simulation time 6529835127 ps
CPU time 7.34 seconds
Started Jan 21 01:53:25 PM PST 24
Finished Jan 21 01:53:33 PM PST 24
Peak memory 199280 kb
Host smart-784fc0d6-13da-4b96-a409-1f18dfa89d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409434909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3409434909
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3662144401
Short name T739
Test name
Test status
Simulation time 110858022617 ps
CPU time 43.3 seconds
Started Jan 21 01:37:42 PM PST 24
Finished Jan 21 01:38:25 PM PST 24
Peak memory 200256 kb
Host smart-a6a7d338-cd94-406b-8d99-153e3f170367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662144401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3662144401
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.949631271
Short name T544
Test name
Test status
Simulation time 13935007 ps
CPU time 0.6 seconds
Started Jan 21 01:48:30 PM PST 24
Finished Jan 21 01:48:31 PM PST 24
Peak memory 195572 kb
Host smart-f208e969-3a85-4a8e-83c6-62328d36b5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949631271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.949631271
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.316179891
Short name T385
Test name
Test status
Simulation time 86948397833 ps
CPU time 39.52 seconds
Started Jan 21 01:43:18 PM PST 24
Finished Jan 21 01:43:58 PM PST 24
Peak memory 199984 kb
Host smart-fcd91f3a-13b2-433d-8a64-5c475ec48617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316179891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.316179891
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3910531950
Short name T969
Test name
Test status
Simulation time 56041657621 ps
CPU time 23.18 seconds
Started Jan 21 01:26:28 PM PST 24
Finished Jan 21 01:26:51 PM PST 24
Peak memory 199216 kb
Host smart-8bd49541-9156-420d-bffc-c393f2389595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910531950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3910531950
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.963635070
Short name T19
Test name
Test status
Simulation time 7883844361 ps
CPU time 5.77 seconds
Started Jan 21 01:26:29 PM PST 24
Finished Jan 21 01:26:36 PM PST 24
Peak memory 200000 kb
Host smart-bb0a12b1-6d0d-4d1a-b324-c3f913a895dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963635070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.963635070
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3991134881
Short name T1184
Test name
Test status
Simulation time 589100515917 ps
CPU time 166.33 seconds
Started Jan 21 01:50:18 PM PST 24
Finished Jan 21 01:53:11 PM PST 24
Peak memory 199984 kb
Host smart-e24c9f76-2dc8-41b2-a4a1-2632e762e8d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991134881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3991134881
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3971303815
Short name T661
Test name
Test status
Simulation time 74267835041 ps
CPU time 270.25 seconds
Started Jan 21 01:26:39 PM PST 24
Finished Jan 21 01:31:10 PM PST 24
Peak memory 200080 kb
Host smart-8b28a68d-4b28-4447-92c4-4a1767f8c092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971303815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3971303815
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3487826752
Short name T508
Test name
Test status
Simulation time 881523402 ps
CPU time 2.15 seconds
Started Jan 21 01:51:56 PM PST 24
Finished Jan 21 01:51:59 PM PST 24
Peak memory 197436 kb
Host smart-f69c96ae-c33d-4ed1-ae5b-d8d18d259f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487826752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3487826752
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1664698759
Short name T1058
Test name
Test status
Simulation time 120594252675 ps
CPU time 66.67 seconds
Started Jan 21 01:26:28 PM PST 24
Finished Jan 21 01:27:35 PM PST 24
Peak memory 208060 kb
Host smart-41c8ad2d-9c14-40cd-9054-fd9a0a494581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664698759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1664698759
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.891114078
Short name T719
Test name
Test status
Simulation time 27308710649 ps
CPU time 112.54 seconds
Started Jan 21 01:26:41 PM PST 24
Finished Jan 21 01:28:35 PM PST 24
Peak memory 200052 kb
Host smart-4523b0e1-0ab8-4012-bc2c-bfc6b1866bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891114078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.891114078
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4032302707
Short name T499
Test name
Test status
Simulation time 1576918103 ps
CPU time 1.99 seconds
Started Jan 21 01:26:30 PM PST 24
Finished Jan 21 01:26:33 PM PST 24
Peak memory 197976 kb
Host smart-8b405b60-5345-4563-ba00-4cca2ed71ce1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032302707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4032302707
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.981173200
Short name T1206
Test name
Test status
Simulation time 132158105838 ps
CPU time 59.01 seconds
Started Jan 21 01:26:30 PM PST 24
Finished Jan 21 01:27:29 PM PST 24
Peak memory 199884 kb
Host smart-7bca4773-7d7a-4007-9450-38bb5e608b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981173200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.981173200
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2794199291
Short name T921
Test name
Test status
Simulation time 5138568450 ps
CPU time 2.75 seconds
Started Jan 21 01:26:30 PM PST 24
Finished Jan 21 01:26:33 PM PST 24
Peak memory 195592 kb
Host smart-ee5505dc-9c7f-4bfe-9acc-8776703dfc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794199291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2794199291
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2431423463
Short name T78
Test name
Test status
Simulation time 153177557 ps
CPU time 0.86 seconds
Started Jan 21 01:26:50 PM PST 24
Finished Jan 21 01:26:52 PM PST 24
Peak memory 217116 kb
Host smart-024c1e21-9697-47a8-84bb-e92752511dc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431423463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2431423463
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3272476750
Short name T722
Test name
Test status
Simulation time 465802291 ps
CPU time 1.78 seconds
Started Jan 21 01:26:20 PM PST 24
Finished Jan 21 01:26:22 PM PST 24
Peak memory 198408 kb
Host smart-dd4acb04-c994-4a2a-9492-293e65ef8188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272476750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3272476750
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.858571779
Short name T1087
Test name
Test status
Simulation time 21111893778 ps
CPU time 27.57 seconds
Started Jan 21 01:26:39 PM PST 24
Finished Jan 21 01:27:08 PM PST 24
Peak memory 199728 kb
Host smart-e4f354ea-8a65-45c4-9385-d0144d8dc280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858571779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.858571779
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1581971913
Short name T17
Test name
Test status
Simulation time 68554483145 ps
CPU time 315.55 seconds
Started Jan 21 01:26:41 PM PST 24
Finished Jan 21 01:31:57 PM PST 24
Peak memory 213188 kb
Host smart-2e2592a2-a22b-4e9f-94f6-68bf9a069475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581971913 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1581971913
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.4195717516
Short name T426
Test name
Test status
Simulation time 2399562372 ps
CPU time 2.61 seconds
Started Jan 21 01:26:30 PM PST 24
Finished Jan 21 01:26:33 PM PST 24
Peak memory 198404 kb
Host smart-72e831eb-b549-40a1-a821-e305dd1d6ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195717516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.4195717516
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.298974914
Short name T631
Test name
Test status
Simulation time 93284318756 ps
CPU time 93.54 seconds
Started Jan 21 01:26:31 PM PST 24
Finished Jan 21 01:28:05 PM PST 24
Peak memory 199904 kb
Host smart-c36168c5-1dfd-433d-ae35-61d8b8a50f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298974914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.298974914
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3531661782
Short name T913
Test name
Test status
Simulation time 99719342 ps
CPU time 0.55 seconds
Started Jan 21 02:12:08 PM PST 24
Finished Jan 21 02:12:09 PM PST 24
Peak memory 194664 kb
Host smart-e602cc7a-17a1-49fb-9eb3-f37020e2ecf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531661782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3531661782
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1865218221
Short name T749
Test name
Test status
Simulation time 210386019379 ps
CPU time 64.32 seconds
Started Jan 21 01:38:14 PM PST 24
Finished Jan 21 01:39:19 PM PST 24
Peak memory 199760 kb
Host smart-35ccbfa8-afa5-4640-9827-6646c296cd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865218221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1865218221
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2030261316
Short name T885
Test name
Test status
Simulation time 253595364279 ps
CPU time 47.95 seconds
Started Jan 21 01:38:04 PM PST 24
Finished Jan 21 01:38:53 PM PST 24
Peak memory 198708 kb
Host smart-e873d7b7-3bf8-4c79-972a-5819131ce6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030261316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2030261316
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.399503146
Short name T770
Test name
Test status
Simulation time 72491222904 ps
CPU time 154.44 seconds
Started Jan 21 01:38:10 PM PST 24
Finished Jan 21 01:40:45 PM PST 24
Peak memory 199972 kb
Host smart-1fb06479-2ca2-47de-9520-6d01619bd3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399503146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.399503146
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3600864456
Short name T666
Test name
Test status
Simulation time 241151725603 ps
CPU time 329.33 seconds
Started Jan 21 01:38:11 PM PST 24
Finished Jan 21 01:43:42 PM PST 24
Peak memory 198900 kb
Host smart-a4771232-221b-4001-bb70-76025569c257
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600864456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3600864456
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2029151206
Short name T553
Test name
Test status
Simulation time 56728946070 ps
CPU time 306.43 seconds
Started Jan 21 01:38:17 PM PST 24
Finished Jan 21 01:43:24 PM PST 24
Peak memory 199956 kb
Host smart-fa18e48a-d7c5-4135-98cd-720986f24301
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029151206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2029151206
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3652877731
Short name T559
Test name
Test status
Simulation time 9705294145 ps
CPU time 9.54 seconds
Started Jan 21 01:38:09 PM PST 24
Finished Jan 21 01:38:20 PM PST 24
Peak memory 199528 kb
Host smart-3f4c2a84-04ac-4d47-8c46-fbf67fb611ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652877731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3652877731
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.4015210475
Short name T1179
Test name
Test status
Simulation time 11395970365 ps
CPU time 19.97 seconds
Started Jan 21 02:11:55 PM PST 24
Finished Jan 21 02:12:15 PM PST 24
Peak memory 198300 kb
Host smart-24bab56f-d6ee-4ccc-9111-cdc6aa5a2f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015210475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.4015210475
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3832030038
Short name T895
Test name
Test status
Simulation time 28617938634 ps
CPU time 1591.28 seconds
Started Jan 21 01:38:06 PM PST 24
Finished Jan 21 02:04:39 PM PST 24
Peak memory 199816 kb
Host smart-ed1e3818-865d-4637-b45a-88092ef6ad31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832030038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3832030038
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.567970147
Short name T102
Test name
Test status
Simulation time 115197724739 ps
CPU time 235.44 seconds
Started Jan 21 01:38:13 PM PST 24
Finished Jan 21 01:42:10 PM PST 24
Peak memory 200048 kb
Host smart-a000dd28-ea2c-4146-b499-f8087418c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567970147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.567970147
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1994588393
Short name T772
Test name
Test status
Simulation time 33085910850 ps
CPU time 23.33 seconds
Started Jan 21 01:38:09 PM PST 24
Finished Jan 21 01:38:33 PM PST 24
Peak memory 195748 kb
Host smart-e29b2721-ac2b-41f7-8a6d-230fdd7e0d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994588393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1994588393
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.567267542
Short name T669
Test name
Test status
Simulation time 785059867 ps
CPU time 1.3 seconds
Started Jan 21 01:38:03 PM PST 24
Finished Jan 21 01:38:06 PM PST 24
Peak memory 198088 kb
Host smart-65969286-bb7b-4648-8606-6978b05130f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567267542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.567267542
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2122343808
Short name T1010
Test name
Test status
Simulation time 1351788219119 ps
CPU time 393.21 seconds
Started Jan 21 03:10:44 PM PST 24
Finished Jan 21 03:17:20 PM PST 24
Peak memory 208396 kb
Host smart-027165cf-a6a6-4d49-abfe-6d1fa61e4910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122343808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2122343808
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3372349980
Short name T1146
Test name
Test status
Simulation time 418218838021 ps
CPU time 584.03 seconds
Started Jan 21 01:38:12 PM PST 24
Finished Jan 21 01:47:57 PM PST 24
Peak memory 224952 kb
Host smart-fd6f40f9-74e7-4c6f-b4b9-11865066cab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372349980 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3372349980
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1117200981
Short name T805
Test name
Test status
Simulation time 6794505418 ps
CPU time 8.64 seconds
Started Jan 21 02:31:20 PM PST 24
Finished Jan 21 02:31:30 PM PST 24
Peak memory 198884 kb
Host smart-baf47de0-0774-4a32-98cc-6b87dbb2ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117200981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1117200981
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.458429625
Short name T1119
Test name
Test status
Simulation time 18947955108 ps
CPU time 29.07 seconds
Started Jan 21 01:38:03 PM PST 24
Finished Jan 21 01:38:33 PM PST 24
Peak memory 199980 kb
Host smart-b0c45460-8bab-4c13-97e0-ac434a9b8b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458429625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.458429625
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2381707652
Short name T595
Test name
Test status
Simulation time 21706771 ps
CPU time 0.56 seconds
Started Jan 21 01:38:30 PM PST 24
Finished Jan 21 01:38:31 PM PST 24
Peak memory 195672 kb
Host smart-ae63fc10-f9d7-4062-845a-ddd4cf275fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381707652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2381707652
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2151646658
Short name T1062
Test name
Test status
Simulation time 74150935996 ps
CPU time 54.68 seconds
Started Jan 21 01:38:13 PM PST 24
Finished Jan 21 01:39:09 PM PST 24
Peak memory 199924 kb
Host smart-3ffc29d8-9f43-4f4c-bb48-c2dfaa17847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151646658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2151646658
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3535979892
Short name T255
Test name
Test status
Simulation time 94095694040 ps
CPU time 32.63 seconds
Started Jan 21 01:38:19 PM PST 24
Finished Jan 21 01:38:53 PM PST 24
Peak memory 199964 kb
Host smart-f89407bc-74c2-45c2-8bae-9547ba834f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535979892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3535979892
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2632366908
Short name T1134
Test name
Test status
Simulation time 1233316626584 ps
CPU time 660.13 seconds
Started Jan 21 02:38:23 PM PST 24
Finished Jan 21 02:49:24 PM PST 24
Peak memory 200064 kb
Host smart-86c1253c-f1f5-48fe-8970-6e1f4d65618d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632366908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2632366908
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.985870419
Short name T850
Test name
Test status
Simulation time 71629573585 ps
CPU time 125.54 seconds
Started Jan 21 01:38:29 PM PST 24
Finished Jan 21 01:40:35 PM PST 24
Peak memory 199928 kb
Host smart-3e9e1be8-44fd-413e-955b-e6f3810eee0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985870419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.985870419
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3284530966
Short name T588
Test name
Test status
Simulation time 3872602465 ps
CPU time 4.02 seconds
Started Jan 21 01:38:31 PM PST 24
Finished Jan 21 01:38:35 PM PST 24
Peak memory 199888 kb
Host smart-113d61d2-8bdd-4ea7-89b4-3aad430e3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284530966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3284530966
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1726895320
Short name T732
Test name
Test status
Simulation time 47053840613 ps
CPU time 26.22 seconds
Started Jan 21 01:38:21 PM PST 24
Finished Jan 21 01:38:48 PM PST 24
Peak memory 198228 kb
Host smart-3381e22c-a37b-4a7b-a500-7d6e5cfd95b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726895320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1726895320
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3806762700
Short name T796
Test name
Test status
Simulation time 12890658120 ps
CPU time 699.78 seconds
Started Jan 21 01:38:29 PM PST 24
Finished Jan 21 01:50:10 PM PST 24
Peak memory 200004 kb
Host smart-d1bf3ec9-6acb-4168-bd35-2dbecb7d2fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806762700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3806762700
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2675434878
Short name T990
Test name
Test status
Simulation time 3091314977 ps
CPU time 21.32 seconds
Started Jan 21 02:05:51 PM PST 24
Finished Jan 21 02:06:13 PM PST 24
Peak memory 198108 kb
Host smart-e9683661-5559-44e8-8e3b-757db0521548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675434878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2675434878
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3413909167
Short name T182
Test name
Test status
Simulation time 21479350971 ps
CPU time 35.39 seconds
Started Jan 21 01:38:27 PM PST 24
Finished Jan 21 01:39:03 PM PST 24
Peak memory 199132 kb
Host smart-3b0d98c2-10da-4280-a4cc-8f07d4b2aaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413909167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3413909167
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2599745961
Short name T536
Test name
Test status
Simulation time 43649994453 ps
CPU time 18.36 seconds
Started Jan 21 01:38:19 PM PST 24
Finished Jan 21 01:38:39 PM PST 24
Peak memory 195620 kb
Host smart-9f8d3664-6d1e-4317-a04c-56e0a9d847e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599745961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2599745961
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.349286592
Short name T713
Test name
Test status
Simulation time 6306687150 ps
CPU time 6.46 seconds
Started Jan 21 01:38:12 PM PST 24
Finished Jan 21 01:38:20 PM PST 24
Peak memory 199272 kb
Host smart-d0aae99d-a6ff-474b-96b5-4245455cf7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349286592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.349286592
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3515604374
Short name T873
Test name
Test status
Simulation time 252368520530 ps
CPU time 117.12 seconds
Started Jan 21 01:38:31 PM PST 24
Finished Jan 21 01:40:28 PM PST 24
Peak memory 216320 kb
Host smart-88ceeded-03e2-4c0b-8116-ea097dbfca92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515604374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3515604374
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3271095690
Short name T561
Test name
Test status
Simulation time 2479022899 ps
CPU time 1.93 seconds
Started Jan 21 01:38:30 PM PST 24
Finished Jan 21 01:38:33 PM PST 24
Peak memory 198048 kb
Host smart-2d7a8373-d549-4539-86e1-bd4c5a97e33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271095690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3271095690
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2921212525
Short name T782
Test name
Test status
Simulation time 17705544655 ps
CPU time 34.57 seconds
Started Jan 21 02:17:50 PM PST 24
Finished Jan 21 02:18:25 PM PST 24
Peak memory 199968 kb
Host smart-f05d968e-3089-48f2-9f13-f8edd391addc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921212525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2921212525
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1226176996
Short name T506
Test name
Test status
Simulation time 31053185 ps
CPU time 0.54 seconds
Started Jan 21 01:38:47 PM PST 24
Finished Jan 21 01:38:49 PM PST 24
Peak memory 195480 kb
Host smart-51c425a8-03c5-4f20-9d0a-b9a6dcd15967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226176996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1226176996
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1902670150
Short name T711
Test name
Test status
Simulation time 51113865355 ps
CPU time 75.35 seconds
Started Jan 21 01:38:37 PM PST 24
Finished Jan 21 01:39:53 PM PST 24
Peak memory 199936 kb
Host smart-4ddf8f0a-1d16-4301-9d86-c240e10bfc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902670150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1902670150
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1293308421
Short name T294
Test name
Test status
Simulation time 113935751682 ps
CPU time 128.24 seconds
Started Jan 21 01:38:39 PM PST 24
Finished Jan 21 01:40:48 PM PST 24
Peak memory 199852 kb
Host smart-4cfce7aa-68ba-4458-bfda-1bbd48567647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293308421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1293308421
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3198745126
Short name T879
Test name
Test status
Simulation time 54110973108 ps
CPU time 32.13 seconds
Started Jan 21 01:38:46 PM PST 24
Finished Jan 21 01:39:19 PM PST 24
Peak memory 199620 kb
Host smart-dfc8407c-6ae1-403f-821d-2b80b5070a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198745126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3198745126
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.637498552
Short name T1075
Test name
Test status
Simulation time 46414626289 ps
CPU time 97.82 seconds
Started Jan 21 02:31:22 PM PST 24
Finished Jan 21 02:33:01 PM PST 24
Peak memory 199788 kb
Host smart-caa2d4ea-b18b-409b-9c94-2080fb9f2810
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637498552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.637498552
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2201206591
Short name T1045
Test name
Test status
Simulation time 172359867423 ps
CPU time 271.01 seconds
Started Jan 21 01:38:46 PM PST 24
Finished Jan 21 01:43:18 PM PST 24
Peak memory 200000 kb
Host smart-7581e874-e498-4dfc-877c-c6cf52a1f3ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201206591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2201206591
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_noise_filter.184771588
Short name T1226
Test name
Test status
Simulation time 155460731758 ps
CPU time 136.09 seconds
Started Jan 21 01:38:39 PM PST 24
Finished Jan 21 01:40:56 PM PST 24
Peak memory 199800 kb
Host smart-e209bae0-7e9b-49a1-b5af-cda42d5f7af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184771588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.184771588
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3675877505
Short name T901
Test name
Test status
Simulation time 8001702339 ps
CPU time 112.56 seconds
Started Jan 21 01:38:46 PM PST 24
Finished Jan 21 01:40:40 PM PST 24
Peak memory 199948 kb
Host smart-5107a11f-3b17-45fc-afb2-8724b48462fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675877505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3675877505
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3472041721
Short name T1070
Test name
Test status
Simulation time 800862570 ps
CPU time 5.25 seconds
Started Jan 21 01:38:38 PM PST 24
Finished Jan 21 01:38:44 PM PST 24
Peak memory 197768 kb
Host smart-aaba1f17-1a73-40fd-b86c-7279ecfe1c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472041721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3472041721
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2694808627
Short name T1112
Test name
Test status
Simulation time 53546730433 ps
CPU time 14.85 seconds
Started Jan 21 01:38:38 PM PST 24
Finished Jan 21 01:38:54 PM PST 24
Peak memory 199296 kb
Host smart-79409182-b887-43ee-acac-f31c8f47deda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694808627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2694808627
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1198638231
Short name T448
Test name
Test status
Simulation time 39444442302 ps
CPU time 33.21 seconds
Started Jan 21 01:38:46 PM PST 24
Finished Jan 21 01:39:20 PM PST 24
Peak memory 195584 kb
Host smart-a2cda979-77a4-46cd-89b7-17471bdb95b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198638231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1198638231
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3559178934
Short name T1200
Test name
Test status
Simulation time 717067553 ps
CPU time 1.8 seconds
Started Jan 21 01:38:39 PM PST 24
Finished Jan 21 01:38:42 PM PST 24
Peak memory 197764 kb
Host smart-d397cffa-6f20-4195-b4e2-da6597eb32ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559178934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3559178934
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2843481962
Short name T752
Test name
Test status
Simulation time 1061483108955 ps
CPU time 440.76 seconds
Started Jan 21 02:18:25 PM PST 24
Finished Jan 21 02:25:46 PM PST 24
Peak memory 199952 kb
Host smart-526a9e36-e1d4-4b8e-a8f7-81afa5a6cc31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843481962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2843481962
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3670980785
Short name T64
Test name
Test status
Simulation time 114878517319 ps
CPU time 1214.45 seconds
Started Jan 21 02:13:25 PM PST 24
Finished Jan 21 02:33:40 PM PST 24
Peak memory 229284 kb
Host smart-6fd5d5f7-0036-4979-b07e-124373fa788e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670980785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3670980785
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.4107699025
Short name T893
Test name
Test status
Simulation time 1239402519 ps
CPU time 1.36 seconds
Started Jan 21 02:46:57 PM PST 24
Finished Jan 21 02:47:00 PM PST 24
Peak memory 198744 kb
Host smart-6dedc6a9-2fc7-4bd9-9f7f-6420a1c9284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107699025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4107699025
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.4254266939
Short name T1011
Test name
Test status
Simulation time 40901695850 ps
CPU time 23.5 seconds
Started Jan 21 03:14:42 PM PST 24
Finished Jan 21 03:15:06 PM PST 24
Peak memory 199764 kb
Host smart-82c89f3c-c7d4-4ad9-b565-9d7872f138c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254266939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4254266939
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1087704887
Short name T1005
Test name
Test status
Simulation time 18073340 ps
CPU time 0.54 seconds
Started Jan 21 01:39:06 PM PST 24
Finished Jan 21 01:39:07 PM PST 24
Peak memory 195504 kb
Host smart-5678bf66-2fc6-40d6-bf40-1e6d3d9a6805
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087704887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1087704887
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2806718083
Short name T199
Test name
Test status
Simulation time 80908585077 ps
CPU time 13.23 seconds
Started Jan 21 02:22:39 PM PST 24
Finished Jan 21 02:22:53 PM PST 24
Peak memory 199376 kb
Host smart-10749670-ac00-4d45-bcea-02d373db0452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806718083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2806718083
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.4161323912
Short name T367
Test name
Test status
Simulation time 119487111572 ps
CPU time 101.14 seconds
Started Jan 21 01:38:46 PM PST 24
Finished Jan 21 01:40:28 PM PST 24
Peak memory 199968 kb
Host smart-94103059-4859-4db2-87d6-0d361eb5a246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161323912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.4161323912
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_intr.1244646788
Short name T540
Test name
Test status
Simulation time 89613728354 ps
CPU time 141.53 seconds
Started Jan 21 01:38:59 PM PST 24
Finished Jan 21 01:41:23 PM PST 24
Peak memory 197792 kb
Host smart-3914e669-0a14-4097-94c8-b708089d48ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244646788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1244646788
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.937472064
Short name T1088
Test name
Test status
Simulation time 216194728560 ps
CPU time 234.07 seconds
Started Jan 21 01:39:06 PM PST 24
Finished Jan 21 01:43:01 PM PST 24
Peak memory 200012 kb
Host smart-84cd809a-7ef2-4e4f-8a6b-c154e51faa1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937472064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.937472064
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.455912941
Short name T1048
Test name
Test status
Simulation time 2837544158 ps
CPU time 3.53 seconds
Started Jan 21 01:39:07 PM PST 24
Finished Jan 21 01:39:11 PM PST 24
Peak memory 198812 kb
Host smart-9cd4801c-d2fa-4a9c-b2b3-adc58ecd7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455912941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.455912941
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1510245891
Short name T1091
Test name
Test status
Simulation time 17151605158 ps
CPU time 30.51 seconds
Started Jan 21 01:38:55 PM PST 24
Finished Jan 21 01:39:26 PM PST 24
Peak memory 198644 kb
Host smart-f0377da7-6c8e-4777-9259-5a87da2d098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510245891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1510245891
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1393868510
Short name T1031
Test name
Test status
Simulation time 9942457834 ps
CPU time 133.16 seconds
Started Jan 21 01:39:05 PM PST 24
Finished Jan 21 01:41:19 PM PST 24
Peak memory 199824 kb
Host smart-861218d4-5912-4c38-90f2-b601daa50c8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393868510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1393868510
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2187651241
Short name T619
Test name
Test status
Simulation time 1141326829 ps
CPU time 12.78 seconds
Started Jan 21 01:38:56 PM PST 24
Finished Jan 21 01:39:14 PM PST 24
Peak memory 198084 kb
Host smart-169d6508-e0ac-4d8d-b793-7414a9688fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2187651241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2187651241
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.749946572
Short name T1147
Test name
Test status
Simulation time 26003383225 ps
CPU time 12.99 seconds
Started Jan 21 01:38:55 PM PST 24
Finished Jan 21 01:39:12 PM PST 24
Peak memory 199936 kb
Host smart-9ec2e665-7893-426e-baca-b1ffb4377c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749946572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.749946572
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4075876907
Short name T991
Test name
Test status
Simulation time 4975017768 ps
CPU time 4 seconds
Started Jan 21 01:38:56 PM PST 24
Finished Jan 21 01:39:06 PM PST 24
Peak memory 195624 kb
Host smart-9c90c0ed-2c5c-47b2-b81d-e3e2c84d98fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075876907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4075876907
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.779350027
Short name T1133
Test name
Test status
Simulation time 268261196 ps
CPU time 1.89 seconds
Started Jan 21 01:38:46 PM PST 24
Finished Jan 21 01:38:49 PM PST 24
Peak memory 198196 kb
Host smart-de0e2e3c-836d-4734-9bc8-4efd934a2270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779350027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.779350027
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2692687023
Short name T574
Test name
Test status
Simulation time 176444006899 ps
CPU time 31.06 seconds
Started Jan 21 02:26:28 PM PST 24
Finished Jan 21 02:26:59 PM PST 24
Peak memory 200016 kb
Host smart-5ec9cf63-3b9f-4168-82c9-dd6c08f95007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692687023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2692687023
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2266926571
Short name T1049
Test name
Test status
Simulation time 44137475982 ps
CPU time 420.35 seconds
Started Jan 21 01:39:07 PM PST 24
Finished Jan 21 01:46:08 PM PST 24
Peak memory 216324 kb
Host smart-0f8fcacb-927c-4a41-af17-50f6315943fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266926571 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2266926571
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.4253377229
Short name T907
Test name
Test status
Simulation time 1055381507 ps
CPU time 3.53 seconds
Started Jan 21 01:38:59 PM PST 24
Finished Jan 21 01:39:05 PM PST 24
Peak memory 197300 kb
Host smart-0a211947-f86e-4a51-af0d-71c9e1581fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253377229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4253377229
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1759826033
Short name T604
Test name
Test status
Simulation time 22390050917 ps
CPU time 39.17 seconds
Started Jan 21 01:38:45 PM PST 24
Finished Jan 21 01:39:26 PM PST 24
Peak memory 199972 kb
Host smart-ff3ce878-6809-42a6-8d2d-3fabac29344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759826033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1759826033
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.336153376
Short name T558
Test name
Test status
Simulation time 27863098 ps
CPU time 0.57 seconds
Started Jan 21 01:39:24 PM PST 24
Finished Jan 21 01:39:33 PM PST 24
Peak memory 195640 kb
Host smart-bdb3aa68-bc51-4df2-83b2-2195f25fe9fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336153376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.336153376
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3236552243
Short name T1012
Test name
Test status
Simulation time 97851183346 ps
CPU time 146.18 seconds
Started Jan 21 01:39:14 PM PST 24
Finished Jan 21 01:41:54 PM PST 24
Peak memory 199868 kb
Host smart-de950174-41b0-40c4-b442-5ed9cc4a2ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236552243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3236552243
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1729264571
Short name T427
Test name
Test status
Simulation time 381988091917 ps
CPU time 60.27 seconds
Started Jan 21 01:39:14 PM PST 24
Finished Jan 21 01:40:28 PM PST 24
Peak memory 199948 kb
Host smart-7f23ca5f-d36e-4e50-9b65-930ffb264b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729264571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1729264571
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2157861684
Short name T1202
Test name
Test status
Simulation time 34479663037 ps
CPU time 45.47 seconds
Started Jan 21 01:39:19 PM PST 24
Finished Jan 21 01:40:13 PM PST 24
Peak memory 198420 kb
Host smart-4304ffc3-f5ac-4c61-9765-fc0739a10a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157861684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2157861684
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.300381383
Short name T793
Test name
Test status
Simulation time 2467690884506 ps
CPU time 3308.26 seconds
Started Jan 21 02:30:30 PM PST 24
Finished Jan 21 03:25:43 PM PST 24
Peak memory 199368 kb
Host smart-803dc86f-6d98-4041-98ad-df73e2f829cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300381383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.300381383
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2056377268
Short name T291
Test name
Test status
Simulation time 39594422103 ps
CPU time 175.15 seconds
Started Jan 21 01:39:22 PM PST 24
Finished Jan 21 01:42:23 PM PST 24
Peak memory 200008 kb
Host smart-c4c9ce2e-74a3-418c-9327-c7822903b234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056377268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2056377268
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2679469298
Short name T1017
Test name
Test status
Simulation time 1324497657 ps
CPU time 1.38 seconds
Started Jan 21 02:07:41 PM PST 24
Finished Jan 21 02:07:43 PM PST 24
Peak memory 197052 kb
Host smart-023df3d0-0cdc-4e71-b2f8-459430e2c14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679469298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2679469298
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1739354439
Short name T800
Test name
Test status
Simulation time 28986077968 ps
CPU time 11.19 seconds
Started Jan 21 01:39:24 PM PST 24
Finished Jan 21 01:39:40 PM PST 24
Peak memory 195688 kb
Host smart-b4655b6c-ba6e-4c6a-9d24-df7fdce3b14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739354439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1739354439
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.674648560
Short name T994
Test name
Test status
Simulation time 4563478695 ps
CPU time 15.62 seconds
Started Jan 21 01:39:18 PM PST 24
Finished Jan 21 01:39:44 PM PST 24
Peak memory 198604 kb
Host smart-48dd87c6-36fc-4f6e-9555-3224e307b700
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674648560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.674648560
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.890572940
Short name T169
Test name
Test status
Simulation time 60387004162 ps
CPU time 17.46 seconds
Started Jan 21 02:51:18 PM PST 24
Finished Jan 21 02:51:36 PM PST 24
Peak memory 199736 kb
Host smart-1fb15a04-e9b0-4f10-a256-35613a52d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890572940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.890572940
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1675927635
Short name T703
Test name
Test status
Simulation time 4370729267 ps
CPU time 2.3 seconds
Started Jan 21 01:39:24 PM PST 24
Finished Jan 21 01:39:31 PM PST 24
Peak memory 195904 kb
Host smart-44887a9a-e2aa-46fe-a88e-59b29525d97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675927635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1675927635
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1592568641
Short name T609
Test name
Test status
Simulation time 6176470219 ps
CPU time 20.4 seconds
Started Jan 21 01:39:07 PM PST 24
Finished Jan 21 01:39:28 PM PST 24
Peak memory 199152 kb
Host smart-6fccecb1-475e-40fd-87ab-fe0e5b336880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592568641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1592568641
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3174545094
Short name T438
Test name
Test status
Simulation time 25934832747 ps
CPU time 404.81 seconds
Started Jan 21 01:39:23 PM PST 24
Finished Jan 21 01:46:13 PM PST 24
Peak memory 216724 kb
Host smart-71580712-247a-4002-8fc5-d9b6e45c510c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174545094 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3174545094
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3739830321
Short name T1165
Test name
Test status
Simulation time 1415200575 ps
CPU time 2.75 seconds
Started Jan 21 01:39:24 PM PST 24
Finished Jan 21 01:39:32 PM PST 24
Peak memory 198800 kb
Host smart-93998b75-19f6-4a63-a649-b78cecca2dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739830321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3739830321
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2633085574
Short name T563
Test name
Test status
Simulation time 35660659542 ps
CPU time 56.08 seconds
Started Jan 21 01:39:14 PM PST 24
Finished Jan 21 01:40:24 PM PST 24
Peak memory 200256 kb
Host smart-1105ccf7-f4b4-410f-a36c-c62c9faf832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633085574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2633085574
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2922039907
Short name T945
Test name
Test status
Simulation time 12447551 ps
CPU time 0.54 seconds
Started Jan 21 01:39:55 PM PST 24
Finished Jan 21 01:40:05 PM PST 24
Peak memory 194480 kb
Host smart-205f0010-e591-4637-b8e5-c8d79a827de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922039907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2922039907
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.119277442
Short name T413
Test name
Test status
Simulation time 184829778686 ps
CPU time 22.31 seconds
Started Jan 21 01:39:32 PM PST 24
Finished Jan 21 01:39:57 PM PST 24
Peak memory 199384 kb
Host smart-26fb9a26-fbd9-418a-9267-fff2ebfaf6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119277442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.119277442
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.791164947
Short name T237
Test name
Test status
Simulation time 225721358284 ps
CPU time 187.01 seconds
Started Jan 21 01:39:32 PM PST 24
Finished Jan 21 01:42:42 PM PST 24
Peak memory 199416 kb
Host smart-31ff7665-6f7b-4938-98c7-b06ad127dc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791164947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.791164947
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.423065506
Short name T124
Test name
Test status
Simulation time 59192173830 ps
CPU time 106.1 seconds
Started Jan 21 01:39:33 PM PST 24
Finished Jan 21 01:41:21 PM PST 24
Peak memory 199756 kb
Host smart-381f46d3-6c43-4509-9ce5-e9541113b665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423065506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.423065506
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2845527125
Short name T733
Test name
Test status
Simulation time 190522970310 ps
CPU time 201.65 seconds
Started Jan 21 01:39:43 PM PST 24
Finished Jan 21 01:43:17 PM PST 24
Peak memory 199888 kb
Host smart-aabf0d58-4eb3-4cff-b466-4cca2843f814
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845527125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2845527125
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3549900978
Short name T407
Test name
Test status
Simulation time 87219198608 ps
CPU time 305.92 seconds
Started Jan 21 01:39:55 PM PST 24
Finished Jan 21 01:45:11 PM PST 24
Peak memory 199844 kb
Host smart-4446ca5c-610f-4fdd-b5da-8a0c5c179e8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549900978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3549900978
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3181220642
Short name T1139
Test name
Test status
Simulation time 82063609287 ps
CPU time 128.89 seconds
Started Jan 21 01:39:43 PM PST 24
Finished Jan 21 01:42:04 PM PST 24
Peak memory 200000 kb
Host smart-6aae3569-9078-47a7-8baa-8fcf35ad0c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181220642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3181220642
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1801210561
Short name T250
Test name
Test status
Simulation time 10814144076 ps
CPU time 637.43 seconds
Started Jan 21 01:39:59 PM PST 24
Finished Jan 21 01:50:43 PM PST 24
Peak memory 200008 kb
Host smart-2ae0b9da-181a-4bb2-ba3b-93097f3f4c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801210561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1801210561
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.586713055
Short name T639
Test name
Test status
Simulation time 175174810 ps
CPU time 0.78 seconds
Started Jan 21 01:39:44 PM PST 24
Finished Jan 21 01:40:01 PM PST 24
Peak memory 196604 kb
Host smart-804123bc-190a-4a25-9c52-ec1473481590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586713055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.586713055
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3305069153
Short name T328
Test name
Test status
Simulation time 139823877565 ps
CPU time 238.88 seconds
Started Jan 21 01:39:42 PM PST 24
Finished Jan 21 01:43:54 PM PST 24
Peak memory 199972 kb
Host smart-74670481-da78-44a1-82eb-7e75847ad5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305069153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3305069153
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2478654825
Short name T1159
Test name
Test status
Simulation time 548998212 ps
CPU time 1.11 seconds
Started Jan 21 01:39:43 PM PST 24
Finished Jan 21 01:39:56 PM PST 24
Peak memory 195480 kb
Host smart-dd38933a-b4b0-4b50-b2d7-6e363d9ff0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478654825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2478654825
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3111789694
Short name T813
Test name
Test status
Simulation time 5554547158 ps
CPU time 17.57 seconds
Started Jan 21 01:39:23 PM PST 24
Finished Jan 21 01:39:46 PM PST 24
Peak memory 199212 kb
Host smart-e0a6864f-fe0b-4db4-93f3-cd8a8ab5e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111789694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3111789694
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4258353771
Short name T942
Test name
Test status
Simulation time 263235408419 ps
CPU time 374.88 seconds
Started Jan 21 01:39:55 PM PST 24
Finished Jan 21 01:46:20 PM PST 24
Peak memory 199952 kb
Host smart-0c9306a9-4d3c-46d4-9bc4-15668152be3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258353771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4258353771
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2653206763
Short name T1188
Test name
Test status
Simulation time 1149515409912 ps
CPU time 1636.22 seconds
Started Jan 21 01:39:56 PM PST 24
Finished Jan 21 02:07:22 PM PST 24
Peak memory 224952 kb
Host smart-0f23abd6-f3ea-4ba9-85ca-9b137660b5bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653206763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2653206763
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3868009739
Short name T1096
Test name
Test status
Simulation time 730710026 ps
CPU time 2.68 seconds
Started Jan 21 01:39:42 PM PST 24
Finished Jan 21 01:39:57 PM PST 24
Peak memory 197884 kb
Host smart-7e43f29e-ae77-47ec-b8b5-51dfdeab33d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868009739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3868009739
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1507031263
Short name T644
Test name
Test status
Simulation time 53358137554 ps
CPU time 28.48 seconds
Started Jan 21 01:39:33 PM PST 24
Finished Jan 21 01:40:04 PM PST 24
Peak memory 199992 kb
Host smart-07d6d359-7ea3-41db-be14-abe8411fbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507031263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1507031263
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.4036028119
Short name T859
Test name
Test status
Simulation time 13699296 ps
CPU time 0.56 seconds
Started Jan 21 01:40:12 PM PST 24
Finished Jan 21 01:40:14 PM PST 24
Peak memory 195636 kb
Host smart-a2788f7e-53c1-49d5-87ba-d312cc2be82e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036028119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.4036028119
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.199307724
Short name T104
Test name
Test status
Simulation time 63134041951 ps
CPU time 35.28 seconds
Started Jan 21 01:39:57 PM PST 24
Finished Jan 21 01:40:41 PM PST 24
Peak memory 199956 kb
Host smart-11e2e24a-d00c-4578-a5d0-7c6d283258d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199307724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.199307724
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3441239099
Short name T1186
Test name
Test status
Simulation time 22269772822 ps
CPU time 44.08 seconds
Started Jan 21 01:39:59 PM PST 24
Finished Jan 21 01:40:50 PM PST 24
Peak memory 199508 kb
Host smart-e96f7bbf-d718-414f-8144-0c93fdd1735f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441239099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3441239099
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1918473301
Short name T1063
Test name
Test status
Simulation time 12097237541 ps
CPU time 25.21 seconds
Started Jan 21 01:40:05 PM PST 24
Finished Jan 21 01:40:32 PM PST 24
Peak memory 199928 kb
Host smart-cf757fd6-ae07-4c6e-a376-fd43c3c169d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918473301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1918473301
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.464292144
Short name T23
Test name
Test status
Simulation time 74093193301 ps
CPU time 34.62 seconds
Started Jan 21 01:40:07 PM PST 24
Finished Jan 21 01:40:44 PM PST 24
Peak memory 198772 kb
Host smart-18338cb3-3b23-4651-9616-e26597b6b87b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464292144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.464292144
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3122821808
Short name T736
Test name
Test status
Simulation time 120952843078 ps
CPU time 237.56 seconds
Started Jan 21 02:11:07 PM PST 24
Finished Jan 21 02:15:05 PM PST 24
Peak memory 200284 kb
Host smart-5be049de-df5f-437c-a649-e0aceae709bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122821808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3122821808
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2043367666
Short name T914
Test name
Test status
Simulation time 3564992801 ps
CPU time 6.74 seconds
Started Jan 21 01:40:07 PM PST 24
Finished Jan 21 01:40:14 PM PST 24
Peak memory 195548 kb
Host smart-8da8bffe-4bec-4436-b1fd-97678c85a1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043367666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2043367666
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3248625927
Short name T185
Test name
Test status
Simulation time 107992674570 ps
CPU time 26.76 seconds
Started Jan 21 01:40:04 PM PST 24
Finished Jan 21 01:40:33 PM PST 24
Peak memory 208388 kb
Host smart-77164fd6-0d99-4479-9468-f5404afb7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248625927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3248625927
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2637902139
Short name T268
Test name
Test status
Simulation time 21737215892 ps
CPU time 275.61 seconds
Started Jan 21 02:21:53 PM PST 24
Finished Jan 21 02:26:29 PM PST 24
Peak memory 200208 kb
Host smart-0ec3c1cf-7653-481f-9980-7beab2e0d83c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637902139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2637902139
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1613958757
Short name T808
Test name
Test status
Simulation time 3450317624 ps
CPU time 10.36 seconds
Started Jan 21 01:40:07 PM PST 24
Finished Jan 21 01:40:18 PM PST 24
Peak memory 198420 kb
Host smart-249da338-6490-4ed8-b214-e62bb051ff81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613958757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1613958757
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2654812124
Short name T582
Test name
Test status
Simulation time 20645386586 ps
CPU time 27.88 seconds
Started Jan 21 01:40:07 PM PST 24
Finished Jan 21 01:40:36 PM PST 24
Peak memory 199972 kb
Host smart-3e0d75b9-94cb-460b-8a99-dd7d61bd438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654812124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2654812124
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3803571796
Short name T763
Test name
Test status
Simulation time 2113690804 ps
CPU time 2.37 seconds
Started Jan 21 01:40:05 PM PST 24
Finished Jan 21 01:40:09 PM PST 24
Peak memory 195444 kb
Host smart-bed97756-3de0-43e7-a36c-5e1177256030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803571796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3803571796
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4075615676
Short name T1113
Test name
Test status
Simulation time 5539451298 ps
CPU time 9.36 seconds
Started Jan 21 01:39:56 PM PST 24
Finished Jan 21 01:40:15 PM PST 24
Peak memory 199272 kb
Host smart-ebb6d78f-2fd1-49d0-b0d3-35ce78ec2caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075615676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4075615676
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2109073620
Short name T253
Test name
Test status
Simulation time 382884401726 ps
CPU time 184.4 seconds
Started Jan 21 01:40:13 PM PST 24
Finished Jan 21 01:43:19 PM PST 24
Peak memory 215908 kb
Host smart-9201ad2c-1f97-413c-9ace-1af9da5bd5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109073620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2109073620
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2228266789
Short name T422
Test name
Test status
Simulation time 34460373662 ps
CPU time 631.62 seconds
Started Jan 21 02:14:08 PM PST 24
Finished Jan 21 02:24:40 PM PST 24
Peak memory 209920 kb
Host smart-bbf9d850-8496-4f1e-8b77-9872efb6f7c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228266789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2228266789
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2218278164
Short name T799
Test name
Test status
Simulation time 1083528944 ps
CPU time 3.33 seconds
Started Jan 21 01:40:04 PM PST 24
Finished Jan 21 01:40:10 PM PST 24
Peak memory 198156 kb
Host smart-109b4194-dac5-4aa0-a4b3-17bb17dba4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218278164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2218278164
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2327275890
Short name T1065
Test name
Test status
Simulation time 61781454320 ps
CPU time 52.23 seconds
Started Jan 21 01:39:56 PM PST 24
Finished Jan 21 01:40:58 PM PST 24
Peak memory 199972 kb
Host smart-e775a848-9e11-4b29-933f-7c4e0a7671bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327275890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2327275890
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1897549224
Short name T543
Test name
Test status
Simulation time 13921949 ps
CPU time 0.58 seconds
Started Jan 21 01:40:43 PM PST 24
Finished Jan 21 01:40:44 PM PST 24
Peak memory 194552 kb
Host smart-f7755182-38dc-46e0-a97e-24f0d7d18774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897549224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1897549224
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1711928669
Short name T679
Test name
Test status
Simulation time 17440042033 ps
CPU time 27.61 seconds
Started Jan 21 01:40:13 PM PST 24
Finished Jan 21 01:40:42 PM PST 24
Peak memory 199976 kb
Host smart-42e1dc9c-c924-406c-b4c2-16bc5a9e8499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711928669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1711928669
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1510381008
Short name T1125
Test name
Test status
Simulation time 188755029138 ps
CPU time 320.26 seconds
Started Jan 21 02:41:36 PM PST 24
Finished Jan 21 02:46:57 PM PST 24
Peak memory 200100 kb
Host smart-fdf05d4a-f825-46a5-b28d-8698650fed07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510381008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1510381008
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1928903818
Short name T952
Test name
Test status
Simulation time 7524196501 ps
CPU time 6.46 seconds
Started Jan 21 01:40:22 PM PST 24
Finished Jan 21 01:40:30 PM PST 24
Peak memory 199888 kb
Host smart-d6d25057-1795-4e5a-b9b2-228b0771d081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928903818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1928903818
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2608229099
Short name T26
Test name
Test status
Simulation time 122223890254 ps
CPU time 52.24 seconds
Started Jan 21 01:40:22 PM PST 24
Finished Jan 21 01:41:16 PM PST 24
Peak memory 197748 kb
Host smart-ec0f2cd6-90ca-483f-b1ce-d7512947f4f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608229099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2608229099
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1388536640
Short name T586
Test name
Test status
Simulation time 164789727323 ps
CPU time 402.96 seconds
Started Jan 21 01:40:34 PM PST 24
Finished Jan 21 01:47:18 PM PST 24
Peak memory 199968 kb
Host smart-787fb73f-a97b-4443-9ba4-8bc9f6c16f5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388536640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1388536640
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2520889163
Short name T1218
Test name
Test status
Simulation time 9538356716 ps
CPU time 12.64 seconds
Started Jan 21 01:40:23 PM PST 24
Finished Jan 21 01:40:37 PM PST 24
Peak memory 198256 kb
Host smart-fa5183bd-13fc-4a4c-bf6c-b04b7db44051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520889163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2520889163
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.790116923
Short name T138
Test name
Test status
Simulation time 62979555003 ps
CPU time 45.38 seconds
Started Jan 21 01:40:23 PM PST 24
Finished Jan 21 01:41:10 PM PST 24
Peak memory 198660 kb
Host smart-1bcd46fc-3272-4f67-abc9-3ef24b343843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790116923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.790116923
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.518473566
Short name T900
Test name
Test status
Simulation time 16448387259 ps
CPU time 911.99 seconds
Started Jan 21 01:40:26 PM PST 24
Finished Jan 21 01:55:39 PM PST 24
Peak memory 199932 kb
Host smart-97a28488-1b88-4023-80ec-4fb1e1649b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518473566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.518473566
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.943591881
Short name T1122
Test name
Test status
Simulation time 2343309252 ps
CPU time 17.04 seconds
Started Jan 21 01:40:26 PM PST 24
Finished Jan 21 01:40:44 PM PST 24
Peak memory 198396 kb
Host smart-37080fe0-1447-415b-a949-ab23f8ffa517
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943591881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.943591881
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.1659002919
Short name T1094
Test name
Test status
Simulation time 52035395291 ps
CPU time 77.97 seconds
Started Jan 21 01:40:22 PM PST 24
Finished Jan 21 01:41:41 PM PST 24
Peak memory 199296 kb
Host smart-b3066b19-3ad4-4667-9718-a6278e17f353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659002919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1659002919
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.440793108
Short name T429
Test name
Test status
Simulation time 3909654463 ps
CPU time 1.66 seconds
Started Jan 21 01:40:25 PM PST 24
Finished Jan 21 01:40:28 PM PST 24
Peak memory 195888 kb
Host smart-33286cf6-b733-41bd-b615-39fe6b18e256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440793108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.440793108
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.463035094
Short name T1180
Test name
Test status
Simulation time 670714598 ps
CPU time 1.72 seconds
Started Jan 21 02:19:51 PM PST 24
Finished Jan 21 02:19:54 PM PST 24
Peak memory 198184 kb
Host smart-8b82eb51-7c2a-40e9-8438-3a6d3cd27d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463035094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.463035094
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2974229186
Short name T708
Test name
Test status
Simulation time 46200967739 ps
CPU time 522.81 seconds
Started Jan 21 01:40:35 PM PST 24
Finished Jan 21 01:49:19 PM PST 24
Peak memory 215548 kb
Host smart-b80a39fc-53f2-4ff8-baa3-5a1beb77c290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974229186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2974229186
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3786885857
Short name T1059
Test name
Test status
Simulation time 6274431236 ps
CPU time 12.58 seconds
Started Jan 21 01:40:21 PM PST 24
Finished Jan 21 01:40:34 PM PST 24
Peak memory 199328 kb
Host smart-eb8a0499-219a-4d80-befa-cdcba6194de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786885857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3786885857
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2207433605
Short name T594
Test name
Test status
Simulation time 121177378350 ps
CPU time 29.03 seconds
Started Jan 21 02:07:02 PM PST 24
Finished Jan 21 02:07:43 PM PST 24
Peak memory 199980 kb
Host smart-6ec57982-1ecd-4e7a-a617-e23e4fe0f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207433605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2207433605
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.707593047
Short name T653
Test name
Test status
Simulation time 13226990 ps
CPU time 0.56 seconds
Started Jan 21 01:40:52 PM PST 24
Finished Jan 21 01:40:53 PM PST 24
Peak memory 195648 kb
Host smart-f5c92453-4958-45dd-a9e6-bcb9eb5be26c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707593047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.707593047
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3059853921
Short name T186
Test name
Test status
Simulation time 203653525088 ps
CPU time 100.06 seconds
Started Jan 21 01:40:45 PM PST 24
Finished Jan 21 01:42:25 PM PST 24
Peak memory 199928 kb
Host smart-c44c36b4-a4c0-4ae2-b41a-2e97d4b1ae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059853921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3059853921
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1177559426
Short name T1029
Test name
Test status
Simulation time 94677099139 ps
CPU time 154.04 seconds
Started Jan 21 01:40:42 PM PST 24
Finished Jan 21 01:43:17 PM PST 24
Peak memory 199976 kb
Host smart-8600d664-1f56-4ab5-9f37-ece702a80987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177559426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1177559426
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3716100842
Short name T204
Test name
Test status
Simulation time 112071338384 ps
CPU time 59.17 seconds
Started Jan 21 01:40:41 PM PST 24
Finished Jan 21 01:41:41 PM PST 24
Peak memory 199988 kb
Host smart-f1084099-e7c2-4f4d-b3b0-b739bbac10d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716100842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3716100842
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2146039157
Short name T899
Test name
Test status
Simulation time 100883955484 ps
CPU time 49.95 seconds
Started Jan 21 01:40:40 PM PST 24
Finished Jan 21 01:41:31 PM PST 24
Peak memory 200052 kb
Host smart-4953c25e-31eb-4663-9a46-b7957efef510
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146039157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2146039157
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1698071213
Short name T818
Test name
Test status
Simulation time 61331856975 ps
CPU time 146.95 seconds
Started Jan 21 01:40:59 PM PST 24
Finished Jan 21 01:43:27 PM PST 24
Peak memory 199988 kb
Host smart-235f45a9-9123-4111-890a-7bae01983943
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698071213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1698071213
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3495318372
Short name T1007
Test name
Test status
Simulation time 7777503238 ps
CPU time 16.94 seconds
Started Jan 21 01:40:55 PM PST 24
Finished Jan 21 01:41:12 PM PST 24
Peak memory 198880 kb
Host smart-fbc8adfc-5377-4130-a256-650079137d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495318372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3495318372
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.585937674
Short name T1138
Test name
Test status
Simulation time 136350704001 ps
CPU time 53.21 seconds
Started Jan 21 01:40:45 PM PST 24
Finished Jan 21 01:41:39 PM PST 24
Peak memory 198768 kb
Host smart-b205386b-a6b6-4fe4-92c5-1c8903725ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585937674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.585937674
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1928527659
Short name T648
Test name
Test status
Simulation time 35141760637 ps
CPU time 780.48 seconds
Started Jan 21 01:40:54 PM PST 24
Finished Jan 21 01:53:55 PM PST 24
Peak memory 199980 kb
Host smart-05ae3c8d-016b-49ff-a7b5-ca7552b1923f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928527659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1928527659
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1711293170
Short name T538
Test name
Test status
Simulation time 4920739812 ps
CPU time 11.3 seconds
Started Jan 21 01:40:42 PM PST 24
Finished Jan 21 01:40:54 PM PST 24
Peak memory 198612 kb
Host smart-4701b2a1-91ac-4df9-922d-2a33822f5292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711293170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1711293170
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3158253374
Short name T654
Test name
Test status
Simulation time 25128387659 ps
CPU time 42 seconds
Started Jan 21 01:40:41 PM PST 24
Finished Jan 21 01:41:24 PM PST 24
Peak memory 198728 kb
Host smart-d3b726bd-24f2-4b50-beb0-d66ac63230cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158253374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3158253374
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1371798538
Short name T823
Test name
Test status
Simulation time 39815268478 ps
CPU time 51.98 seconds
Started Jan 21 01:40:40 PM PST 24
Finished Jan 21 01:41:33 PM PST 24
Peak memory 195460 kb
Host smart-0573f1a7-26ba-46dd-b55c-eaca6bfcd1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371798538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1371798538
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1809861657
Short name T615
Test name
Test status
Simulation time 140021544 ps
CPU time 0.78 seconds
Started Jan 21 01:40:41 PM PST 24
Finished Jan 21 01:40:43 PM PST 24
Peak memory 196472 kb
Host smart-c31419af-8309-4d40-9f78-d8d422209657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809861657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1809861657
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1300844705
Short name T1181
Test name
Test status
Simulation time 196030927878 ps
CPU time 1317.69 seconds
Started Jan 21 01:40:54 PM PST 24
Finished Jan 21 02:02:53 PM PST 24
Peak memory 199984 kb
Host smart-6097d44e-449a-4f4f-b986-d413e031c671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300844705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1300844705
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1371841744
Short name T997
Test name
Test status
Simulation time 18455586956 ps
CPU time 513.37 seconds
Started Jan 21 01:40:51 PM PST 24
Finished Jan 21 01:49:25 PM PST 24
Peak memory 209840 kb
Host smart-52ec3bfd-2c3e-4cb1-ada1-95f7aad8162d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371841744 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1371841744
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3705688628
Short name T1100
Test name
Test status
Simulation time 1212158802 ps
CPU time 2.87 seconds
Started Jan 21 01:40:59 PM PST 24
Finished Jan 21 01:41:03 PM PST 24
Peak memory 198012 kb
Host smart-70e4ec7e-fd36-4f28-8293-d5c54191531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705688628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3705688628
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2008273092
Short name T926
Test name
Test status
Simulation time 229822137269 ps
CPU time 102.23 seconds
Started Jan 21 01:40:40 PM PST 24
Finished Jan 21 01:42:24 PM PST 24
Peak memory 199928 kb
Host smart-956c85ed-8e63-40f9-9d81-3b2d633fe6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008273092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2008273092
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3317126714
Short name T622
Test name
Test status
Simulation time 48915944 ps
CPU time 0.55 seconds
Started Jan 21 01:41:07 PM PST 24
Finished Jan 21 01:41:08 PM PST 24
Peak memory 195648 kb
Host smart-83f51890-5c3c-44dc-9cd6-4ce1d29fa4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317126714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3317126714
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1404963295
Short name T863
Test name
Test status
Simulation time 138643847496 ps
CPU time 92.47 seconds
Started Jan 21 01:40:52 PM PST 24
Finished Jan 21 01:42:25 PM PST 24
Peak memory 199888 kb
Host smart-3f3644a0-e75a-4a2e-8280-43964c0e802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404963295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1404963295
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1357544449
Short name T148
Test name
Test status
Simulation time 28878621070 ps
CPU time 60.91 seconds
Started Jan 21 01:40:52 PM PST 24
Finished Jan 21 01:41:54 PM PST 24
Peak memory 199928 kb
Host smart-f9ccfa03-37c5-4f9a-b1db-9f253f0f5733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357544449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1357544449
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_intr.2086611083
Short name T860
Test name
Test status
Simulation time 6554342787 ps
CPU time 5.05 seconds
Started Jan 21 01:41:04 PM PST 24
Finished Jan 21 01:41:10 PM PST 24
Peak memory 195508 kb
Host smart-248996f9-faaa-4284-abca-a79c652392e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086611083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2086611083
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2262447041
Short name T1060
Test name
Test status
Simulation time 107442593399 ps
CPU time 1016.26 seconds
Started Jan 21 01:40:58 PM PST 24
Finished Jan 21 01:57:55 PM PST 24
Peak memory 200052 kb
Host smart-74cc5ea4-194a-4c5f-ab8a-13b1c96d0dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262447041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2262447041
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1023375560
Short name T849
Test name
Test status
Simulation time 6383135882 ps
CPU time 7.6 seconds
Started Jan 21 01:40:59 PM PST 24
Finished Jan 21 01:41:07 PM PST 24
Peak memory 199800 kb
Host smart-5fed5154-196c-410e-a09b-0569733a003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023375560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1023375560
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2373667370
Short name T552
Test name
Test status
Simulation time 96929806302 ps
CPU time 92.49 seconds
Started Jan 21 01:41:03 PM PST 24
Finished Jan 21 01:42:36 PM PST 24
Peak memory 208364 kb
Host smart-9ee6f8c8-e339-483e-9a32-aa6460faaab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373667370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2373667370
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1384492287
Short name T1173
Test name
Test status
Simulation time 17083072872 ps
CPU time 528.94 seconds
Started Jan 21 01:41:00 PM PST 24
Finished Jan 21 01:49:49 PM PST 24
Peak memory 199956 kb
Host smart-fccf1786-a5de-47a2-9f95-3c90465cb507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384492287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1384492287
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.358874935
Short name T714
Test name
Test status
Simulation time 1861582582 ps
CPU time 5.15 seconds
Started Jan 21 01:40:56 PM PST 24
Finished Jan 21 01:41:02 PM PST 24
Peak memory 198076 kb
Host smart-e0aff7f7-fddc-4c1c-b911-393d89149fce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358874935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.358874935
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.903067120
Short name T673
Test name
Test status
Simulation time 49498989766 ps
CPU time 38.5 seconds
Started Jan 21 01:40:59 PM PST 24
Finished Jan 21 01:41:38 PM PST 24
Peak memory 198796 kb
Host smart-a2589dab-9461-40b7-aa0c-3e157af18cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903067120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.903067120
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3382560194
Short name T925
Test name
Test status
Simulation time 2077792537 ps
CPU time 3.99 seconds
Started Jan 21 01:40:59 PM PST 24
Finished Jan 21 01:41:04 PM PST 24
Peak memory 195488 kb
Host smart-76d741b6-856f-46a3-80c2-6636347830be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382560194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3382560194
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2872416181
Short name T792
Test name
Test status
Simulation time 343300484 ps
CPU time 0.92 seconds
Started Jan 21 01:40:50 PM PST 24
Finished Jan 21 01:40:52 PM PST 24
Peak memory 198648 kb
Host smart-a3a589c3-16ea-4b77-b53e-784831c1753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872416181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2872416181
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2778637921
Short name T591
Test name
Test status
Simulation time 286962196150 ps
CPU time 629.06 seconds
Started Jan 21 01:41:06 PM PST 24
Finished Jan 21 01:51:36 PM PST 24
Peak memory 200240 kb
Host smart-4ca1f0f7-e46e-4421-8fc0-90465aa72df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778637921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2778637921
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.347404694
Short name T238
Test name
Test status
Simulation time 96204811176 ps
CPU time 577.28 seconds
Started Jan 21 01:41:03 PM PST 24
Finished Jan 21 01:50:41 PM PST 24
Peak memory 228748 kb
Host smart-9886f801-47ca-4890-8d1f-577e94471be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347404694 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.347404694
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.4022000690
Short name T516
Test name
Test status
Simulation time 1525097826 ps
CPU time 1.77 seconds
Started Jan 21 01:41:03 PM PST 24
Finished Jan 21 01:41:05 PM PST 24
Peak memory 199120 kb
Host smart-8a93b569-d399-4273-9028-5bc34c5f3189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022000690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.4022000690
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2845476026
Short name T587
Test name
Test status
Simulation time 13069425312 ps
CPU time 21.71 seconds
Started Jan 21 01:40:52 PM PST 24
Finished Jan 21 01:41:14 PM PST 24
Peak memory 199908 kb
Host smart-d1a0c8cd-577f-4310-ace7-567d95bef9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845476026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2845476026
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3613590100
Short name T1018
Test name
Test status
Simulation time 35059023 ps
CPU time 0.56 seconds
Started Jan 21 01:27:08 PM PST 24
Finished Jan 21 01:27:09 PM PST 24
Peak memory 195652 kb
Host smart-b318a2c3-6839-479b-b633-80f7c4026308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613590100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3613590100
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.190956169
Short name T826
Test name
Test status
Simulation time 20708411813 ps
CPU time 18.6 seconds
Started Jan 21 01:26:50 PM PST 24
Finished Jan 21 01:27:10 PM PST 24
Peak memory 198472 kb
Host smart-1455685e-3691-44a4-848a-f50de99e15e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190956169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.190956169
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1565302733
Short name T364
Test name
Test status
Simulation time 91956826543 ps
CPU time 27.65 seconds
Started Jan 21 01:26:50 PM PST 24
Finished Jan 21 01:27:18 PM PST 24
Peak memory 198820 kb
Host smart-6f10f868-21be-4f53-b7c0-ec3d770477c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565302733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1565302733
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.3118124026
Short name T938
Test name
Test status
Simulation time 294836337736 ps
CPU time 138.6 seconds
Started Jan 21 01:37:27 PM PST 24
Finished Jan 21 01:39:46 PM PST 24
Peak memory 199920 kb
Host smart-c47fc9ee-fcfa-4b9b-80dc-8d8ef947f914
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118124026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3118124026
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2656636028
Short name T1171
Test name
Test status
Simulation time 110135435163 ps
CPU time 646.16 seconds
Started Jan 21 01:27:01 PM PST 24
Finished Jan 21 01:37:51 PM PST 24
Peak memory 200016 kb
Host smart-6ed4000d-7556-48fe-9541-08b4980455d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656636028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2656636028
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3235175469
Short name T748
Test name
Test status
Simulation time 2174768468 ps
CPU time 1.87 seconds
Started Jan 21 02:01:57 PM PST 24
Finished Jan 21 02:02:00 PM PST 24
Peak memory 196932 kb
Host smart-7a3b264f-b0f2-4898-b797-f7c42fdd3cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235175469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3235175469
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2348652981
Short name T730
Test name
Test status
Simulation time 49189194239 ps
CPU time 76.42 seconds
Started Jan 21 01:26:49 PM PST 24
Finished Jan 21 01:28:07 PM PST 24
Peak memory 208184 kb
Host smart-a7936a4d-c917-4cd0-b2b8-47fb7a2b2d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348652981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2348652981
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.256723198
Short name T814
Test name
Test status
Simulation time 23202198254 ps
CPU time 297.58 seconds
Started Jan 21 02:13:09 PM PST 24
Finished Jan 21 02:18:07 PM PST 24
Peak memory 199868 kb
Host smart-1c1a2956-d40a-478a-a68e-e59774276424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256723198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.256723198
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3014197773
Short name T1116
Test name
Test status
Simulation time 3456059603 ps
CPU time 6.79 seconds
Started Jan 21 01:26:51 PM PST 24
Finished Jan 21 01:26:58 PM PST 24
Peak memory 198248 kb
Host smart-a3f48de7-42c0-4c80-8d06-39339333568a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014197773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3014197773
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1464310853
Short name T1004
Test name
Test status
Simulation time 56376116919 ps
CPU time 18.24 seconds
Started Jan 21 01:26:50 PM PST 24
Finished Jan 21 01:27:09 PM PST 24
Peak memory 199660 kb
Host smart-4e3b2452-b44d-4905-91da-5dc628eeb218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464310853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1464310853
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3434452459
Short name T741
Test name
Test status
Simulation time 39468869304 ps
CPU time 5.48 seconds
Started Jan 21 01:26:50 PM PST 24
Finished Jan 21 01:26:56 PM PST 24
Peak memory 195584 kb
Host smart-6ea26686-7938-4acb-a36c-384ff702588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434452459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3434452459
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3845590394
Short name T1214
Test name
Test status
Simulation time 6290932719 ps
CPU time 14.42 seconds
Started Jan 21 02:24:55 PM PST 24
Finished Jan 21 02:25:10 PM PST 24
Peak memory 198616 kb
Host smart-407f6196-4026-4201-9129-93bea2be4089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845590394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3845590394
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.996211875
Short name T944
Test name
Test status
Simulation time 86658806742 ps
CPU time 136.03 seconds
Started Jan 21 01:41:19 PM PST 24
Finished Jan 21 01:43:36 PM PST 24
Peak memory 199940 kb
Host smart-7b7dc1d1-e37b-44c8-b9e5-7a1ebc493271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996211875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.996211875
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.861710035
Short name T1108
Test name
Test status
Simulation time 120002033346 ps
CPU time 1853.93 seconds
Started Jan 21 01:27:08 PM PST 24
Finished Jan 21 01:58:03 PM PST 24
Peak memory 224848 kb
Host smart-8dd0a691-3e28-4598-8a80-4d5d82e95281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861710035 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.861710035
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2016905351
Short name T518
Test name
Test status
Simulation time 620956484 ps
CPU time 1.96 seconds
Started Jan 21 03:45:59 PM PST 24
Finished Jan 21 03:46:11 PM PST 24
Peak memory 197892 kb
Host smart-0b8bcc32-32f7-4cde-9db1-41fd32f2a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016905351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2016905351
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.415241135
Short name T1035
Test name
Test status
Simulation time 37908921770 ps
CPU time 13.85 seconds
Started Jan 21 01:26:51 PM PST 24
Finished Jan 21 01:27:06 PM PST 24
Peak memory 196996 kb
Host smart-7c5ae258-df35-4c52-8909-9c78c8cfea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415241135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.415241135
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.842808060
Short name T632
Test name
Test status
Simulation time 57332579867 ps
CPU time 19.38 seconds
Started Jan 21 02:57:03 PM PST 24
Finished Jan 21 02:57:23 PM PST 24
Peak memory 199920 kb
Host smart-0bad6ba8-4d02-49b8-9e69-a99faae1a70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842808060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.842808060
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1955596003
Short name T193
Test name
Test status
Simulation time 73088608408 ps
CPU time 29.51 seconds
Started Jan 21 02:23:11 PM PST 24
Finished Jan 21 02:23:42 PM PST 24
Peak memory 200020 kb
Host smart-e910fc1a-6209-42b7-ae74-ed2ddeed9aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955596003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1955596003
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2076947915
Short name T71
Test name
Test status
Simulation time 1240114287404 ps
CPU time 728.91 seconds
Started Jan 21 01:41:17 PM PST 24
Finished Jan 21 01:53:27 PM PST 24
Peak memory 224940 kb
Host smart-6d81af4e-6b59-457b-a561-046fbb3b1ffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076947915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2076947915
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1735283305
Short name T173
Test name
Test status
Simulation time 46897865149 ps
CPU time 53.11 seconds
Started Jan 21 01:41:20 PM PST 24
Finished Jan 21 01:42:13 PM PST 24
Peak memory 200004 kb
Host smart-4919fc91-1ed5-4664-88c3-9cbaf3735491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735283305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1735283305
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1570519184
Short name T442
Test name
Test status
Simulation time 33098270267 ps
CPU time 339.27 seconds
Started Jan 21 01:41:20 PM PST 24
Finished Jan 21 01:47:00 PM PST 24
Peak memory 216288 kb
Host smart-c88e17ea-d7de-4731-b7f1-dda8b5bcafd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570519184 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1570519184
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.521259601
Short name T187
Test name
Test status
Simulation time 141596027152 ps
CPU time 350.98 seconds
Started Jan 21 01:41:19 PM PST 24
Finished Jan 21 01:47:11 PM PST 24
Peak memory 199968 kb
Host smart-da7abc0e-31ba-4250-858b-3380165b79f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521259601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.521259601
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3742011498
Short name T309
Test name
Test status
Simulation time 288051937186 ps
CPU time 1658.23 seconds
Started Jan 21 02:34:07 PM PST 24
Finished Jan 21 03:01:46 PM PST 24
Peak memory 227548 kb
Host smart-bb1ce7be-01e8-42ac-ab3c-bbd0efc026ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742011498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3742011498
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2231781462
Short name T1098
Test name
Test status
Simulation time 36386742172 ps
CPU time 19.69 seconds
Started Jan 21 01:41:19 PM PST 24
Finished Jan 21 01:41:39 PM PST 24
Peak memory 199292 kb
Host smart-55dd596d-ebd3-437c-8c7b-3158e4ea6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231781462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2231781462
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1082446868
Short name T515
Test name
Test status
Simulation time 14535763963 ps
CPU time 168.1 seconds
Started Jan 21 01:41:19 PM PST 24
Finished Jan 21 01:44:08 PM PST 24
Peak memory 215100 kb
Host smart-7af159ed-3ffe-466a-b74d-0379c4b9bfd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082446868 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1082446868
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2986035123
Short name T189
Test name
Test status
Simulation time 20108464926 ps
CPU time 33.31 seconds
Started Jan 21 01:41:16 PM PST 24
Finished Jan 21 01:41:50 PM PST 24
Peak memory 199728 kb
Host smart-c004f170-aed5-4f0e-9f95-52488dbf071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986035123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2986035123
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.602208334
Short name T325
Test name
Test status
Simulation time 81395631048 ps
CPU time 437.99 seconds
Started Jan 21 01:41:18 PM PST 24
Finished Jan 21 01:48:37 PM PST 24
Peak memory 224904 kb
Host smart-4ebb9806-68a7-4ad9-a6fe-a16a3bf74c1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602208334 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.602208334
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1474134554
Short name T927
Test name
Test status
Simulation time 16476707155 ps
CPU time 27.33 seconds
Started Jan 21 01:41:19 PM PST 24
Finished Jan 21 01:41:47 PM PST 24
Peak memory 199976 kb
Host smart-093a7fce-18b1-4b19-86ac-ae717541b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474134554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1474134554
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1096718805
Short name T686
Test name
Test status
Simulation time 344321948622 ps
CPU time 358.31 seconds
Started Jan 21 01:41:26 PM PST 24
Finished Jan 21 01:47:25 PM PST 24
Peak memory 215376 kb
Host smart-2705bb0f-0020-4a1b-8bd2-badb796a4331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096718805 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1096718805
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2753719775
Short name T1126
Test name
Test status
Simulation time 137539892088 ps
CPU time 124.33 seconds
Started Jan 21 01:41:22 PM PST 24
Finished Jan 21 01:43:27 PM PST 24
Peak memory 200032 kb
Host smart-2bee6f51-a133-4511-8c6f-74a4a00e62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753719775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2753719775
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4240897108
Short name T1227
Test name
Test status
Simulation time 63462495875 ps
CPU time 638.83 seconds
Started Jan 21 01:41:25 PM PST 24
Finished Jan 21 01:52:05 PM PST 24
Peak memory 216524 kb
Host smart-4eb45a94-bb60-4487-8eb2-f35770fee0e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240897108 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4240897108
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3757793135
Short name T409
Test name
Test status
Simulation time 69591033503 ps
CPU time 390.99 seconds
Started Jan 21 01:41:25 PM PST 24
Finished Jan 21 01:47:57 PM PST 24
Peak memory 215928 kb
Host smart-1ac75284-a40a-49c4-b05d-8cc232ac7fe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757793135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3757793135
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3421684501
Short name T18
Test name
Test status
Simulation time 40695613789 ps
CPU time 67.7 seconds
Started Jan 21 01:41:27 PM PST 24
Finished Jan 21 01:42:35 PM PST 24
Peak memory 199888 kb
Host smart-d2b2670c-8798-4bf4-aa7f-71c1f3efd805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421684501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3421684501
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.4236851566
Short name T202
Test name
Test status
Simulation time 21734929521 ps
CPU time 195.72 seconds
Started Jan 21 01:41:29 PM PST 24
Finished Jan 21 01:44:45 PM PST 24
Peak memory 208288 kb
Host smart-3a8b5da7-30e2-4814-b856-33e38997aa6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236851566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4236851566
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.434177950
Short name T1092
Test name
Test status
Simulation time 18470205 ps
CPU time 0.54 seconds
Started Jan 21 01:27:44 PM PST 24
Finished Jan 21 01:27:48 PM PST 24
Peak memory 194600 kb
Host smart-7100628f-385e-4cc2-9ddc-d0e6f788e9f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434177950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.434177950
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2467436401
Short name T286
Test name
Test status
Simulation time 15852904929 ps
CPU time 5.92 seconds
Started Jan 21 02:57:03 PM PST 24
Finished Jan 21 02:57:10 PM PST 24
Peak memory 199224 kb
Host smart-7cc36e54-c9ef-45aa-97f3-8b3208962fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467436401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2467436401
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1138870224
Short name T326
Test name
Test status
Simulation time 229398595554 ps
CPU time 37.88 seconds
Started Jan 21 01:27:18 PM PST 24
Finished Jan 21 01:27:57 PM PST 24
Peak memory 199988 kb
Host smart-17d18b74-ae4d-43b6-bec8-eb494f3078b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138870224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1138870224
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1236608711
Short name T158
Test name
Test status
Simulation time 40746669192 ps
CPU time 19.34 seconds
Started Jan 21 01:27:27 PM PST 24
Finished Jan 21 01:27:47 PM PST 24
Peak memory 199832 kb
Host smart-7d46a0f4-d586-49b6-9de2-29dd968d52e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236608711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1236608711
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1574735178
Short name T636
Test name
Test status
Simulation time 140809603237 ps
CPU time 226.53 seconds
Started Jan 21 01:27:25 PM PST 24
Finished Jan 21 01:31:12 PM PST 24
Peak memory 199876 kb
Host smart-7e290c6b-9433-4f16-9571-bc36a61b1694
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574735178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1574735178
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.275744520
Short name T517
Test name
Test status
Simulation time 40816701444 ps
CPU time 271.49 seconds
Started Jan 21 01:27:37 PM PST 24
Finished Jan 21 01:32:09 PM PST 24
Peak memory 200028 kb
Host smart-5b25df68-b89b-4ab3-8f8e-8cace8851f33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275744520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.275744520
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1237889065
Short name T526
Test name
Test status
Simulation time 2710961688 ps
CPU time 5.61 seconds
Started Jan 21 01:27:27 PM PST 24
Finished Jan 21 01:27:34 PM PST 24
Peak memory 198004 kb
Host smart-42a5e77e-d1bc-456a-8c75-33cb1a09a1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237889065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1237889065
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1232494001
Short name T1052
Test name
Test status
Simulation time 212820208445 ps
CPU time 34.08 seconds
Started Jan 21 01:27:28 PM PST 24
Finished Jan 21 01:28:03 PM PST 24
Peak memory 197492 kb
Host smart-ebfe0311-d988-4abe-8798-c01a1d154ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232494001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1232494001
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1102104052
Short name T1084
Test name
Test status
Simulation time 15336261464 ps
CPU time 961.67 seconds
Started Jan 21 01:59:49 PM PST 24
Finished Jan 21 02:15:52 PM PST 24
Peak memory 199928 kb
Host smart-b07211f3-473e-4ef5-b93b-50472eb38d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102104052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1102104052
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3023736641
Short name T220
Test name
Test status
Simulation time 95456906123 ps
CPU time 34.89 seconds
Started Jan 21 01:27:26 PM PST 24
Finished Jan 21 01:28:03 PM PST 24
Peak memory 200012 kb
Host smart-28c1d2f5-d6ce-487d-9ed3-14d2b41b35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023736641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3023736641
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1240657866
Short name T672
Test name
Test status
Simulation time 3006328413 ps
CPU time 5.86 seconds
Started Jan 21 02:21:44 PM PST 24
Finished Jan 21 02:21:51 PM PST 24
Peak memory 195564 kb
Host smart-dd1e6d94-e734-4953-bded-fc964717c396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240657866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1240657866
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1711530185
Short name T1121
Test name
Test status
Simulation time 799719850 ps
CPU time 1.33 seconds
Started Jan 21 01:27:09 PM PST 24
Finished Jan 21 01:27:11 PM PST 24
Peak memory 199220 kb
Host smart-165f9012-cc39-4c03-95b7-19116bb99acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711530185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1711530185
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1309077882
Short name T723
Test name
Test status
Simulation time 316070727949 ps
CPU time 348.23 seconds
Started Jan 21 01:27:46 PM PST 24
Finished Jan 21 01:33:38 PM PST 24
Peak memory 199920 kb
Host smart-b14530aa-bfcf-4f3d-803b-3952f7f1163c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309077882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1309077882
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.4109629782
Short name T446
Test name
Test status
Simulation time 30598469227 ps
CPU time 278.78 seconds
Started Jan 21 01:27:46 PM PST 24
Finished Jan 21 01:32:27 PM PST 24
Peak memory 212092 kb
Host smart-a4043498-92be-4981-955a-a637df47b245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109629782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.4109629782
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1976893372
Short name T452
Test name
Test status
Simulation time 9146014241 ps
CPU time 8.44 seconds
Started Jan 21 01:27:27 PM PST 24
Finished Jan 21 01:27:36 PM PST 24
Peak memory 199228 kb
Host smart-4ba890e3-10ba-45a9-a5d2-27ddc7032fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976893372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1976893372
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1882085142
Short name T682
Test name
Test status
Simulation time 25854663909 ps
CPU time 28.7 seconds
Started Jan 21 01:27:08 PM PST 24
Finished Jan 21 01:27:37 PM PST 24
Peak memory 199912 kb
Host smart-49e89998-bb76-44cf-bbd7-a99f185e3f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882085142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1882085142
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.615408428
Short name T745
Test name
Test status
Simulation time 36666184475 ps
CPU time 744.3 seconds
Started Jan 21 01:41:26 PM PST 24
Finished Jan 21 01:53:51 PM PST 24
Peak memory 210240 kb
Host smart-ed39ebab-e424-43fc-85dd-4e40d930f38c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615408428 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.615408428
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2307452913
Short name T162
Test name
Test status
Simulation time 129907332377 ps
CPU time 284.37 seconds
Started Jan 21 01:41:26 PM PST 24
Finished Jan 21 01:46:11 PM PST 24
Peak memory 200020 kb
Host smart-620a57c3-ec20-49bf-b296-62857c5773df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307452913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2307452913
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.4221858642
Short name T417
Test name
Test status
Simulation time 75024284051 ps
CPU time 688.06 seconds
Started Jan 21 01:41:25 PM PST 24
Finished Jan 21 01:52:54 PM PST 24
Peak memory 224940 kb
Host smart-44f51b02-0c10-4fe6-a6e5-cf8ad3ac0a56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221858642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.4221858642
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2346422313
Short name T196
Test name
Test status
Simulation time 68784125652 ps
CPU time 64.89 seconds
Started Jan 21 01:41:25 PM PST 24
Finished Jan 21 01:42:31 PM PST 24
Peak memory 200228 kb
Host smart-a86cf1ad-c799-403b-adab-ce5741be3833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346422313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2346422313
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2351585477
Short name T1187
Test name
Test status
Simulation time 96232528970 ps
CPU time 997.52 seconds
Started Jan 21 01:41:29 PM PST 24
Finished Jan 21 01:58:08 PM PST 24
Peak memory 213604 kb
Host smart-c89c1830-e9dc-45a8-afa2-466929bc61c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351585477 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2351585477
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.867950739
Short name T898
Test name
Test status
Simulation time 58285763669 ps
CPU time 325.37 seconds
Started Jan 21 01:41:28 PM PST 24
Finished Jan 21 01:46:54 PM PST 24
Peak memory 214084 kb
Host smart-4457c3da-1d71-4ab7-8c66-ead7b838501e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867950739 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.867950739
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3693458545
Short name T188
Test name
Test status
Simulation time 65564387468 ps
CPU time 54.58 seconds
Started Jan 21 01:41:38 PM PST 24
Finished Jan 21 01:42:39 PM PST 24
Peak memory 200000 kb
Host smart-3370a1b4-f745-4a22-8dfc-d5e83c7ecfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693458545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3693458545
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2602951879
Short name T1130
Test name
Test status
Simulation time 74927508192 ps
CPU time 140.1 seconds
Started Jan 21 01:41:35 PM PST 24
Finished Jan 21 01:44:04 PM PST 24
Peak memory 214980 kb
Host smart-2c0c8cf1-4def-4807-897f-4585d9e970f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602951879 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2602951879
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3887630095
Short name T315
Test name
Test status
Simulation time 7120729635 ps
CPU time 134.77 seconds
Started Jan 21 01:57:26 PM PST 24
Finished Jan 21 01:59:42 PM PST 24
Peak memory 200308 kb
Host smart-bb6486e3-20fd-4532-a38c-bcfe79ab7e69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887630095 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3887630095
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.669047944
Short name T778
Test name
Test status
Simulation time 137746837704 ps
CPU time 300.54 seconds
Started Jan 21 01:41:35 PM PST 24
Finished Jan 21 01:46:45 PM PST 24
Peak memory 199984 kb
Host smart-57fb629b-8914-40b2-beae-4127091e6db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669047944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.669047944
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2770816095
Short name T1207
Test name
Test status
Simulation time 28473286411 ps
CPU time 171.58 seconds
Started Jan 21 01:41:37 PM PST 24
Finished Jan 21 01:44:36 PM PST 24
Peak memory 200160 kb
Host smart-cb259ee8-9be8-4303-9367-d782dfcdbc4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770816095 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2770816095
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1263758953
Short name T191
Test name
Test status
Simulation time 234300411320 ps
CPU time 20.31 seconds
Started Jan 21 02:30:43 PM PST 24
Finished Jan 21 02:31:04 PM PST 24
Peak memory 199636 kb
Host smart-329cd8aa-aa62-441b-897d-840e2e9df5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263758953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1263758953
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2208736493
Short name T308
Test name
Test status
Simulation time 36490811650 ps
CPU time 52.13 seconds
Started Jan 21 01:55:57 PM PST 24
Finished Jan 21 01:56:50 PM PST 24
Peak memory 199208 kb
Host smart-ac6d3cd4-c1e1-4a42-9ac2-17ac8f5dfbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208736493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2208736493
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3273422164
Short name T932
Test name
Test status
Simulation time 27899551 ps
CPU time 0.55 seconds
Started Jan 21 01:28:01 PM PST 24
Finished Jan 21 01:28:03 PM PST 24
Peak memory 195556 kb
Host smart-904a1d4e-832c-487a-821f-0e799c3b60c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273422164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3273422164
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.927076303
Short name T775
Test name
Test status
Simulation time 47076118282 ps
CPU time 81.32 seconds
Started Jan 21 01:27:44 PM PST 24
Finished Jan 21 01:29:08 PM PST 24
Peak memory 200016 kb
Host smart-8bc5e2e1-a43c-4148-ba2d-cf7de3caeaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927076303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.927076303
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3218625515
Short name T725
Test name
Test status
Simulation time 79672920766 ps
CPU time 113.9 seconds
Started Jan 21 01:27:46 PM PST 24
Finished Jan 21 01:29:42 PM PST 24
Peak memory 199472 kb
Host smart-77745216-27c6-4772-b4d3-4d01b457f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218625515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3218625515
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.731812712
Short name T866
Test name
Test status
Simulation time 160659389753 ps
CPU time 57.54 seconds
Started Jan 21 01:27:46 PM PST 24
Finished Jan 21 01:28:47 PM PST 24
Peak memory 199772 kb
Host smart-7a54a681-a0b8-4080-bc5b-750b76f2330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731812712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.731812712
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3065788105
Short name T1174
Test name
Test status
Simulation time 391354204642 ps
CPU time 534.64 seconds
Started Jan 21 01:27:44 PM PST 24
Finished Jan 21 01:36:42 PM PST 24
Peak memory 200000 kb
Host smart-102ce7a4-f3af-44a7-b214-d550dca0a922
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065788105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3065788105
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1705219664
Short name T842
Test name
Test status
Simulation time 141836689379 ps
CPU time 632.57 seconds
Started Jan 21 01:28:03 PM PST 24
Finished Jan 21 01:38:37 PM PST 24
Peak memory 199960 kb
Host smart-3cd49805-72eb-4198-a707-8d062b77c74c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705219664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1705219664
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.216531826
Short name T1132
Test name
Test status
Simulation time 2644521059 ps
CPU time 2.17 seconds
Started Jan 21 01:27:52 PM PST 24
Finished Jan 21 01:27:55 PM PST 24
Peak memory 198696 kb
Host smart-bc4e4680-2ce1-422f-a634-1c225f258bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216531826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.216531826
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.461707196
Short name T904
Test name
Test status
Simulation time 94815703717 ps
CPU time 43.95 seconds
Started Jan 21 01:27:52 PM PST 24
Finished Jan 21 01:28:37 PM PST 24
Peak memory 200056 kb
Host smart-21905399-3020-408b-a71a-ce4cc7b076c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461707196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.461707196
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.398987550
Short name T497
Test name
Test status
Simulation time 3206110497 ps
CPU time 18.92 seconds
Started Jan 21 01:27:45 PM PST 24
Finished Jan 21 01:28:06 PM PST 24
Peak memory 198232 kb
Host smart-6c1654c4-65b2-4a12-868d-10009f85b935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398987550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.398987550
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.253441280
Short name T352
Test name
Test status
Simulation time 100609729635 ps
CPU time 44.12 seconds
Started Jan 21 02:33:36 PM PST 24
Finished Jan 21 02:34:21 PM PST 24
Peak memory 199436 kb
Host smart-1c0b51c8-f69c-409c-8458-5f489bcd0c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253441280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.253441280
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1449555512
Short name T760
Test name
Test status
Simulation time 2050126608 ps
CPU time 4.11 seconds
Started Jan 21 01:27:52 PM PST 24
Finished Jan 21 01:27:57 PM PST 24
Peak memory 195368 kb
Host smart-0eae887e-797a-4592-bf89-700d984c82a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449555512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1449555512
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3126892061
Short name T665
Test name
Test status
Simulation time 628346769 ps
CPU time 3.25 seconds
Started Jan 21 01:27:47 PM PST 24
Finished Jan 21 01:27:54 PM PST 24
Peak memory 198344 kb
Host smart-9c450328-2238-4cb1-a44c-e1d996a20b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126892061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3126892061
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.819477734
Short name T810
Test name
Test status
Simulation time 3584963706 ps
CPU time 2.33 seconds
Started Jan 21 01:36:47 PM PST 24
Finished Jan 21 01:36:53 PM PST 24
Peak memory 198124 kb
Host smart-b52b78bc-a2b0-44dd-9257-2ab4c85f002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819477734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.819477734
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.218032755
Short name T183
Test name
Test status
Simulation time 53430371756 ps
CPU time 83.61 seconds
Started Jan 21 01:27:44 PM PST 24
Finished Jan 21 01:29:11 PM PST 24
Peak memory 199972 kb
Host smart-e03d1b41-3176-4bf2-8cbe-98276480e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218032755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.218032755
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.797300293
Short name T1148
Test name
Test status
Simulation time 107229705623 ps
CPU time 175.92 seconds
Started Jan 21 01:41:48 PM PST 24
Finished Jan 21 01:44:49 PM PST 24
Peak memory 199888 kb
Host smart-0cf46a19-ceab-4ce8-8575-c3ee125f236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797300293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.797300293
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1233266223
Short name T164
Test name
Test status
Simulation time 475931155157 ps
CPU time 1646.12 seconds
Started Jan 21 02:13:36 PM PST 24
Finished Jan 21 02:41:06 PM PST 24
Peak memory 230828 kb
Host smart-a10abb29-c6c0-428b-93bc-7915de875f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233266223 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1233266223
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2025656124
Short name T1192
Test name
Test status
Simulation time 18517052580 ps
CPU time 27.45 seconds
Started Jan 21 01:41:48 PM PST 24
Finished Jan 21 01:42:20 PM PST 24
Peak memory 198564 kb
Host smart-b37e7e1b-fd00-4241-8a04-26ddd20dbc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025656124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2025656124
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.61417299
Short name T180
Test name
Test status
Simulation time 169387184246 ps
CPU time 75.63 seconds
Started Jan 21 01:41:45 PM PST 24
Finished Jan 21 01:43:08 PM PST 24
Peak memory 199924 kb
Host smart-614a4aab-1bb0-4416-a29b-4c1dba73d978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61417299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.61417299
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1259875183
Short name T959
Test name
Test status
Simulation time 14977630188 ps
CPU time 225.3 seconds
Started Jan 21 02:12:08 PM PST 24
Finished Jan 21 02:15:54 PM PST 24
Peak memory 208400 kb
Host smart-12e2dfd3-8bdf-44d3-a1e5-d475d3b25e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259875183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1259875183
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3062133324
Short name T843
Test name
Test status
Simulation time 55487332709 ps
CPU time 19.07 seconds
Started Jan 21 02:07:59 PM PST 24
Finished Jan 21 02:08:18 PM PST 24
Peak memory 198424 kb
Host smart-80f8b058-ff1a-4914-9f8f-d3ff12e1e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062133324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3062133324
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1221741623
Short name T246
Test name
Test status
Simulation time 96240910454 ps
CPU time 47.45 seconds
Started Jan 21 01:41:55 PM PST 24
Finished Jan 21 01:42:44 PM PST 24
Peak memory 199944 kb
Host smart-561c4998-2fe7-43d3-b161-5fe0aeaaa4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221741623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1221741623
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2636160215
Short name T953
Test name
Test status
Simulation time 7802312331 ps
CPU time 101.52 seconds
Started Jan 21 01:41:53 PM PST 24
Finished Jan 21 01:43:37 PM PST 24
Peak memory 208396 kb
Host smart-816fe7d7-7150-42be-a6c5-60c0d265c756
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636160215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2636160215
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1571173806
Short name T256
Test name
Test status
Simulation time 34911536676 ps
CPU time 17.72 seconds
Started Jan 21 01:41:52 PM PST 24
Finished Jan 21 01:42:13 PM PST 24
Peak memory 199376 kb
Host smart-5056810d-3e1a-477b-acab-e1645e64f6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571173806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1571173806
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1392443434
Short name T824
Test name
Test status
Simulation time 15307643532 ps
CPU time 172.04 seconds
Started Jan 21 01:41:54 PM PST 24
Finished Jan 21 01:44:48 PM PST 24
Peak memory 209612 kb
Host smart-e2136235-35f5-42a0-bdbf-47fb0d18df30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392443434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1392443434
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2599288821
Short name T208
Test name
Test status
Simulation time 29732233370 ps
CPU time 44.42 seconds
Started Jan 21 01:41:55 PM PST 24
Finished Jan 21 01:42:41 PM PST 24
Peak memory 199960 kb
Host smart-236af27a-be62-43d5-aa7c-5b0e5d54f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599288821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2599288821
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1868839988
Short name T975
Test name
Test status
Simulation time 46302274079 ps
CPU time 736.49 seconds
Started Jan 21 01:41:56 PM PST 24
Finished Jan 21 01:54:13 PM PST 24
Peak memory 216232 kb
Host smart-bc546f03-fac2-4d6f-a8df-481624d57026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868839988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1868839988
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.927153051
Short name T804
Test name
Test status
Simulation time 15495755155 ps
CPU time 136.38 seconds
Started Jan 21 01:41:55 PM PST 24
Finished Jan 21 01:44:13 PM PST 24
Peak memory 215888 kb
Host smart-3bce9519-fd58-4323-9242-f272eafce690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927153051 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.927153051
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.938616173
Short name T929
Test name
Test status
Simulation time 39392944683 ps
CPU time 29.6 seconds
Started Jan 21 01:41:52 PM PST 24
Finished Jan 21 01:42:25 PM PST 24
Peak memory 199768 kb
Host smart-a71ea805-d968-4f92-8094-e908acd9210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938616173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.938616173
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3285911732
Short name T967
Test name
Test status
Simulation time 20807010846 ps
CPU time 236.85 seconds
Started Jan 21 01:41:56 PM PST 24
Finished Jan 21 01:45:54 PM PST 24
Peak memory 215864 kb
Host smart-cf355b58-ebf4-46da-a930-8e089fcb7fbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285911732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3285911732
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3684026793
Short name T528
Test name
Test status
Simulation time 11232425 ps
CPU time 0.54 seconds
Started Jan 21 01:28:29 PM PST 24
Finished Jan 21 01:28:30 PM PST 24
Peak memory 194556 kb
Host smart-23692e89-18f5-41cf-a6a7-2ebfcd7cc9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684026793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3684026793
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.133356571
Short name T349
Test name
Test status
Simulation time 46949394313 ps
CPU time 21.4 seconds
Started Jan 21 01:28:02 PM PST 24
Finished Jan 21 01:28:25 PM PST 24
Peak memory 200016 kb
Host smart-8d9e9a49-7389-4ece-9d46-efee9b3cdbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133356571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.133356571
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.859072822
Short name T1151
Test name
Test status
Simulation time 33434383209 ps
CPU time 15.39 seconds
Started Jan 21 01:28:12 PM PST 24
Finished Jan 21 01:28:28 PM PST 24
Peak memory 199972 kb
Host smart-bdba6791-6683-4af2-a868-e8a08e329ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859072822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.859072822
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.441777343
Short name T439
Test name
Test status
Simulation time 35939997230 ps
CPU time 54.3 seconds
Started Jan 21 01:28:15 PM PST 24
Finished Jan 21 01:29:10 PM PST 24
Peak memory 196580 kb
Host smart-56d1b653-f9d4-4070-bb2c-bca731c78039
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441777343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.441777343
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_loopback.1424576731
Short name T1145
Test name
Test status
Simulation time 4745862483 ps
CPU time 8.44 seconds
Started Jan 21 01:45:11 PM PST 24
Finished Jan 21 01:45:20 PM PST 24
Peak memory 195464 kb
Host smart-cacdfa74-9f62-44dd-b25d-997479beb6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424576731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1424576731
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.153296374
Short name T612
Test name
Test status
Simulation time 119652314289 ps
CPU time 145.5 seconds
Started Jan 21 01:28:12 PM PST 24
Finished Jan 21 01:30:39 PM PST 24
Peak memory 198020 kb
Host smart-37eaeb3e-9826-4f98-9156-899d41484ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153296374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.153296374
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.802857844
Short name T889
Test name
Test status
Simulation time 15125047413 ps
CPU time 200.07 seconds
Started Jan 21 01:28:21 PM PST 24
Finished Jan 21 01:31:42 PM PST 24
Peak memory 199872 kb
Host smart-2c61a4f0-bde2-4f57-aeab-363be187d401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=802857844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.802857844
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1094663313
Short name T1040
Test name
Test status
Simulation time 1572894276 ps
CPU time 14.52 seconds
Started Jan 21 01:28:15 PM PST 24
Finished Jan 21 01:28:30 PM PST 24
Peak memory 198064 kb
Host smart-4d1841b2-64d0-4213-a61e-f2e994efbc7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094663313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1094663313
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4105020295
Short name T1153
Test name
Test status
Simulation time 23063168577 ps
CPU time 11.46 seconds
Started Jan 21 01:28:11 PM PST 24
Finished Jan 21 01:28:23 PM PST 24
Peak memory 199844 kb
Host smart-1e235604-da5c-416d-9ae2-1ecb4eb69a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105020295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4105020295
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3653139337
Short name T1034
Test name
Test status
Simulation time 4013059930 ps
CPU time 4.02 seconds
Started Jan 21 01:28:13 PM PST 24
Finished Jan 21 01:28:18 PM PST 24
Peak memory 195536 kb
Host smart-57ea60be-dec6-49f6-a3df-f957b711e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653139337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3653139337
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4267491751
Short name T756
Test name
Test status
Simulation time 647301201 ps
CPU time 2.01 seconds
Started Jan 21 01:52:48 PM PST 24
Finished Jan 21 01:52:53 PM PST 24
Peak memory 199132 kb
Host smart-d638b616-e132-41a3-ae6d-05a2b6747b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267491751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4267491751
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1089514521
Short name T205
Test name
Test status
Simulation time 263194792780 ps
CPU time 1651.62 seconds
Started Jan 21 01:28:21 PM PST 24
Finished Jan 21 01:55:53 PM PST 24
Peak memory 199848 kb
Host smart-9916fd8b-8c4b-4ecf-9813-c6fde6ea9172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089514521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1089514521
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2545077882
Short name T635
Test name
Test status
Simulation time 23171777563 ps
CPU time 82.34 seconds
Started Jan 21 01:28:24 PM PST 24
Finished Jan 21 01:29:47 PM PST 24
Peak memory 210388 kb
Host smart-b905b7a1-323f-4873-ab92-d5a407f2c12b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545077882 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2545077882
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.919949844
Short name T992
Test name
Test status
Simulation time 294832458 ps
CPU time 1.23 seconds
Started Jan 21 01:28:23 PM PST 24
Finished Jan 21 01:28:25 PM PST 24
Peak memory 196412 kb
Host smart-a4aaa662-ec00-47ca-b579-39df0b755c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919949844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.919949844
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3936690583
Short name T411
Test name
Test status
Simulation time 15780133916 ps
CPU time 27.82 seconds
Started Jan 21 01:27:59 PM PST 24
Finished Jan 21 01:28:28 PM PST 24
Peak memory 199880 kb
Host smart-1c8a8460-761d-42f2-b4e3-c439c7edb570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936690583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3936690583
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1107433823
Short name T362
Test name
Test status
Simulation time 39943881602 ps
CPU time 56.7 seconds
Started Jan 21 02:02:14 PM PST 24
Finished Jan 21 02:03:11 PM PST 24
Peak memory 199892 kb
Host smart-adbfc317-c086-445b-9bf7-acdb6781c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107433823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1107433823
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1210217359
Short name T878
Test name
Test status
Simulation time 20915612725 ps
CPU time 187.21 seconds
Started Jan 21 02:04:16 PM PST 24
Finished Jan 21 02:07:25 PM PST 24
Peak memory 216756 kb
Host smart-cd5761aa-b1e6-406a-8f6b-25bbfdecdabf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210217359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1210217359
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3877113926
Short name T165
Test name
Test status
Simulation time 182903963217 ps
CPU time 59.74 seconds
Started Jan 21 01:42:04 PM PST 24
Finished Jan 21 01:43:04 PM PST 24
Peak memory 199672 kb
Host smart-d0ef0e8e-181e-4ea1-84fd-fb9755a8d368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877113926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3877113926
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.539965265
Short name T657
Test name
Test status
Simulation time 236190402754 ps
CPU time 748.59 seconds
Started Jan 21 02:08:22 PM PST 24
Finished Jan 21 02:20:51 PM PST 24
Peak memory 224944 kb
Host smart-c5b2c51a-9b8e-48e7-8474-86b25391c784
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539965265 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.539965265
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3069060020
Short name T1080
Test name
Test status
Simulation time 149408723843 ps
CPU time 55.55 seconds
Started Jan 21 01:42:15 PM PST 24
Finished Jan 21 01:43:11 PM PST 24
Peak memory 199976 kb
Host smart-d0e4da6d-8c8f-45ae-8c2e-b96739db606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069060020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3069060020
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2474345592
Short name T366
Test name
Test status
Simulation time 39492448414 ps
CPU time 823.09 seconds
Started Jan 21 02:12:18 PM PST 24
Finished Jan 21 02:26:02 PM PST 24
Peak memory 216756 kb
Host smart-250a515b-0fae-421e-bf37-b4218c08a5df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474345592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2474345592
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4121298193
Short name T355
Test name
Test status
Simulation time 25196923842 ps
CPU time 18.24 seconds
Started Jan 21 01:42:16 PM PST 24
Finished Jan 21 01:42:40 PM PST 24
Peak memory 199404 kb
Host smart-9a05e312-d0b7-443e-b6d6-5244a9ff1f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121298193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4121298193
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1389310414
Short name T60
Test name
Test status
Simulation time 204423145551 ps
CPU time 943.11 seconds
Started Jan 21 01:42:16 PM PST 24
Finished Jan 21 01:58:04 PM PST 24
Peak memory 224584 kb
Host smart-9d588215-afe0-4707-adf8-f6baa6285ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389310414 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1389310414
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3996592708
Short name T94
Test name
Test status
Simulation time 37499511757 ps
CPU time 23.19 seconds
Started Jan 21 01:42:16 PM PST 24
Finished Jan 21 01:42:45 PM PST 24
Peak memory 199940 kb
Host smart-222b22f1-f7b6-4fe2-bbca-d21a525bb40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996592708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3996592708
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2936822074
Short name T70
Test name
Test status
Simulation time 65456521405 ps
CPU time 818.5 seconds
Started Jan 21 01:42:12 PM PST 24
Finished Jan 21 01:55:52 PM PST 24
Peak memory 211624 kb
Host smart-daf810af-c42e-40cb-a500-542f0fec3ae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936822074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2936822074
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.132910249
Short name T1196
Test name
Test status
Simulation time 73421662294 ps
CPU time 61.35 seconds
Started Jan 21 01:42:13 PM PST 24
Finished Jan 21 01:43:16 PM PST 24
Peak memory 199572 kb
Host smart-d9080910-c225-49bc-af08-9f5ee4b315aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132910249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.132910249
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3903616439
Short name T1189
Test name
Test status
Simulation time 148373366988 ps
CPU time 669.71 seconds
Started Jan 21 01:42:15 PM PST 24
Finished Jan 21 01:53:26 PM PST 24
Peak memory 216552 kb
Host smart-76aec2b0-2322-4fd7-80ac-4f08f55cae34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903616439 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3903616439
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3649043745
Short name T445
Test name
Test status
Simulation time 13454078045 ps
CPU time 177.45 seconds
Started Jan 21 01:42:15 PM PST 24
Finished Jan 21 01:45:13 PM PST 24
Peak memory 209592 kb
Host smart-a31e810b-ce57-4580-87ec-7dfa48330b2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649043745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3649043745
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3965449544
Short name T265
Test name
Test status
Simulation time 66658188945 ps
CPU time 55.66 seconds
Started Jan 21 01:58:38 PM PST 24
Finished Jan 21 01:59:35 PM PST 24
Peak memory 200024 kb
Host smart-6bc764a8-f284-4665-8120-130244a44982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965449544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3965449544
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2311013874
Short name T960
Test name
Test status
Simulation time 104825405770 ps
CPU time 902.91 seconds
Started Jan 21 01:42:16 PM PST 24
Finished Jan 21 01:57:24 PM PST 24
Peak memory 221264 kb
Host smart-653bbf90-cbe9-4000-a0b7-a7b61242a646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311013874 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2311013874
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1273628734
Short name T155
Test name
Test status
Simulation time 88486191078 ps
CPU time 38.88 seconds
Started Jan 21 01:56:12 PM PST 24
Finished Jan 21 01:56:52 PM PST 24
Peak memory 199404 kb
Host smart-a143f758-bf95-4a85-a231-97e44924133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273628734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1273628734
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2231437953
Short name T62
Test name
Test status
Simulation time 39583221124 ps
CPU time 139.74 seconds
Started Jan 21 01:42:15 PM PST 24
Finished Jan 21 01:44:36 PM PST 24
Peak memory 213504 kb
Host smart-88801057-7d5e-4825-a8aa-a32a74252b88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231437953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2231437953
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2969001449
Short name T87
Test name
Test status
Simulation time 12552309 ps
CPU time 0.55 seconds
Started Jan 21 01:28:57 PM PST 24
Finished Jan 21 01:28:58 PM PST 24
Peak memory 195640 kb
Host smart-9a2d54ef-85c1-4274-9887-23b01d60de81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969001449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2969001449
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2483076884
Short name T351
Test name
Test status
Simulation time 52105263622 ps
CPU time 51.1 seconds
Started Jan 21 01:28:35 PM PST 24
Finished Jan 21 01:29:27 PM PST 24
Peak memory 200024 kb
Host smart-edbb68c3-2e13-4401-b9a8-0cb4943b31c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483076884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2483076884
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1522136228
Short name T774
Test name
Test status
Simulation time 31509983837 ps
CPU time 32.39 seconds
Started Jan 21 01:28:35 PM PST 24
Finished Jan 21 01:29:08 PM PST 24
Peak memory 199976 kb
Host smart-00676362-3795-4316-8543-2cc4aaba1c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522136228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1522136228
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1813612195
Short name T1209
Test name
Test status
Simulation time 461311520416 ps
CPU time 563.82 seconds
Started Jan 21 02:11:42 PM PST 24
Finished Jan 21 02:21:07 PM PST 24
Peak memory 199912 kb
Host smart-614e2205-ea77-4951-8642-4f27b5d3d7a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813612195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1813612195
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1582527025
Short name T902
Test name
Test status
Simulation time 116443655593 ps
CPU time 857.23 seconds
Started Jan 21 01:28:45 PM PST 24
Finished Jan 21 01:43:03 PM PST 24
Peak memory 199972 kb
Host smart-1c5a73c2-1aa8-45f2-856e-9f20c8865f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582527025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1582527025
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.527439749
Short name T1198
Test name
Test status
Simulation time 7091554872 ps
CPU time 7.23 seconds
Started Jan 21 01:28:50 PM PST 24
Finished Jan 21 01:28:58 PM PST 24
Peak memory 198556 kb
Host smart-9840923f-9aa1-48f8-9cc7-76f71bd193a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527439749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.527439749
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3109110704
Short name T643
Test name
Test status
Simulation time 62931979303 ps
CPU time 30.85 seconds
Started Jan 21 01:28:45 PM PST 24
Finished Jan 21 01:29:17 PM PST 24
Peak memory 198824 kb
Host smart-7f197d6e-5b20-4992-a320-09e370b2ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109110704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3109110704
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1486939985
Short name T839
Test name
Test status
Simulation time 22181646826 ps
CPU time 969.12 seconds
Started Jan 21 01:28:50 PM PST 24
Finished Jan 21 01:45:00 PM PST 24
Peak memory 199844 kb
Host smart-ea6477b2-316e-47b1-8fbe-fd9cb861aad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486939985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1486939985
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1212489899
Short name T696
Test name
Test status
Simulation time 2544432924 ps
CPU time 29.4 seconds
Started Jan 21 01:28:35 PM PST 24
Finished Jan 21 01:29:05 PM PST 24
Peak memory 198316 kb
Host smart-350695e2-fe6c-4445-844e-c5955b9c7745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212489899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1212489899
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.589213706
Short name T1161
Test name
Test status
Simulation time 68919245038 ps
CPU time 65.62 seconds
Started Jan 21 01:28:50 PM PST 24
Finished Jan 21 01:29:56 PM PST 24
Peak memory 199936 kb
Host smart-5f297b81-896f-4f55-81b4-66c55b60f883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589213706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.589213706
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.480162294
Short name T789
Test name
Test status
Simulation time 3248760346 ps
CPU time 1.1 seconds
Started Jan 21 01:28:47 PM PST 24
Finished Jan 21 01:28:49 PM PST 24
Peak memory 195720 kb
Host smart-32a85467-73bc-40f9-b345-a88e3c15add1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480162294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.480162294
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3268959493
Short name T649
Test name
Test status
Simulation time 5814371299 ps
CPU time 21 seconds
Started Jan 21 01:28:30 PM PST 24
Finished Jan 21 01:28:52 PM PST 24
Peak memory 199320 kb
Host smart-4f7af726-b5f8-4ca9-a2cd-ff408be241d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268959493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3268959493
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.942253715
Short name T864
Test name
Test status
Simulation time 24628179915 ps
CPU time 253.86 seconds
Started Jan 21 01:28:57 PM PST 24
Finished Jan 21 01:33:11 PM PST 24
Peak memory 215576 kb
Host smart-abea4a40-b1e3-45e3-bb5f-848b22501e95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942253715 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.942253715
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2591588715
Short name T874
Test name
Test status
Simulation time 12739036370 ps
CPU time 23.24 seconds
Started Jan 21 01:28:50 PM PST 24
Finished Jan 21 01:29:14 PM PST 24
Peak memory 200044 kb
Host smart-0b95290c-ac47-47a0-888b-b4917b70be2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591588715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2591588715
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3405949819
Short name T712
Test name
Test status
Simulation time 2150219420 ps
CPU time 2.37 seconds
Started Jan 21 01:28:34 PM PST 24
Finished Jan 21 01:28:37 PM PST 24
Peak memory 196812 kb
Host smart-e5ac833f-dbde-4453-87dc-062817575387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405949819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3405949819
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2890514176
Short name T1157
Test name
Test status
Simulation time 33636621140 ps
CPU time 17.88 seconds
Started Jan 21 01:42:13 PM PST 24
Finished Jan 21 01:42:32 PM PST 24
Peak memory 197972 kb
Host smart-971e53ae-0bbd-4e73-8968-3f689def89e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890514176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2890514176
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1985721106
Short name T868
Test name
Test status
Simulation time 207655556991 ps
CPU time 1121.83 seconds
Started Jan 21 01:42:24 PM PST 24
Finished Jan 21 02:01:07 PM PST 24
Peak memory 224880 kb
Host smart-8cfc1b76-6d32-40e7-941c-a2e68b8123bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985721106 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1985721106
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1862462277
Short name T32
Test name
Test status
Simulation time 53519924896 ps
CPU time 545.17 seconds
Started Jan 21 01:54:01 PM PST 24
Finished Jan 21 02:03:07 PM PST 24
Peak memory 215804 kb
Host smart-e91698e4-e3c0-4ef9-998c-d878b1b366e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862462277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1862462277
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4107688746
Short name T1093
Test name
Test status
Simulation time 12337886419 ps
CPU time 11.76 seconds
Started Jan 21 02:39:28 PM PST 24
Finished Jan 21 02:39:41 PM PST 24
Peak memory 199640 kb
Host smart-68c86555-9e02-4292-9e01-445f949cf2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107688746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4107688746
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3868487981
Short name T339
Test name
Test status
Simulation time 118014927797 ps
CPU time 584.12 seconds
Started Jan 21 01:42:32 PM PST 24
Finished Jan 21 01:52:17 PM PST 24
Peak memory 224944 kb
Host smart-338c39a1-e064-4fed-bac6-1cbda297d137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868487981 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3868487981
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1642101067
Short name T225
Test name
Test status
Simulation time 44161560470 ps
CPU time 51.73 seconds
Started Jan 21 01:42:31 PM PST 24
Finished Jan 21 01:43:24 PM PST 24
Peak memory 199952 kb
Host smart-51c9f9ff-82eb-4713-8ec3-421442852dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642101067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1642101067
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2599863997
Short name T209
Test name
Test status
Simulation time 257613259576 ps
CPU time 989.48 seconds
Started Jan 21 01:42:31 PM PST 24
Finished Jan 21 01:59:01 PM PST 24
Peak memory 216516 kb
Host smart-99f325b3-d160-40ad-b99d-357bc2539148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599863997 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2599863997
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1773122149
Short name T327
Test name
Test status
Simulation time 205042655601 ps
CPU time 300.46 seconds
Started Jan 21 01:42:33 PM PST 24
Finished Jan 21 01:47:35 PM PST 24
Peak memory 216688 kb
Host smart-c5e4c4ba-2e4c-4663-a334-7a2af18a67ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773122149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1773122149
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2294569560
Short name T542
Test name
Test status
Simulation time 37237644353 ps
CPU time 14.4 seconds
Started Jan 21 01:42:32 PM PST 24
Finished Jan 21 01:42:47 PM PST 24
Peak memory 199824 kb
Host smart-083139cf-b04e-4b0a-9da1-0deec9762898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294569560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2294569560
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.138710619
Short name T753
Test name
Test status
Simulation time 85051553808 ps
CPU time 68.12 seconds
Started Jan 21 02:52:34 PM PST 24
Finished Jan 21 02:53:48 PM PST 24
Peak memory 208296 kb
Host smart-1b01003c-0f79-458b-8777-291454dc728f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138710619 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.138710619
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.21331420
Short name T154
Test name
Test status
Simulation time 8607482970 ps
CPU time 19.08 seconds
Started Jan 21 01:42:32 PM PST 24
Finished Jan 21 01:42:52 PM PST 24
Peak memory 199924 kb
Host smart-9f5029b9-3838-48e5-beb4-9a51613e7090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21331420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.21331420
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3238981163
Short name T404
Test name
Test status
Simulation time 68298091809 ps
CPU time 185.33 seconds
Started Jan 21 01:42:44 PM PST 24
Finished Jan 21 01:45:51 PM PST 24
Peak memory 216004 kb
Host smart-3eb04732-4a41-4e1f-80fc-35c23b76f81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238981163 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3238981163
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2636018678
Short name T1053
Test name
Test status
Simulation time 68195389294 ps
CPU time 27.55 seconds
Started Jan 21 02:33:35 PM PST 24
Finished Jan 21 02:34:05 PM PST 24
Peak memory 199316 kb
Host smart-b48510f2-cb83-455b-98fe-245eb1f87d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636018678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2636018678
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.4187807109
Short name T671
Test name
Test status
Simulation time 53306888609 ps
CPU time 815.2 seconds
Started Jan 21 01:42:40 PM PST 24
Finished Jan 21 01:56:17 PM PST 24
Peak memory 209620 kb
Host smart-38189d4c-3d02-438e-b36e-cf36e9e4a6ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187807109 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.4187807109
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2810328818
Short name T297
Test name
Test status
Simulation time 144104292603 ps
CPU time 221.45 seconds
Started Jan 21 01:42:40 PM PST 24
Finished Jan 21 01:46:22 PM PST 24
Peak memory 199816 kb
Host smart-5073fb48-2e05-4d76-8c7f-bccdeebb6385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810328818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2810328818
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.970063040
Short name T1191
Test name
Test status
Simulation time 57749855014 ps
CPU time 1916.56 seconds
Started Jan 21 01:42:42 PM PST 24
Finished Jan 21 02:14:39 PM PST 24
Peak memory 216552 kb
Host smart-ca1125c1-88ed-4d90-a9a9-d69278afbb0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970063040 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.970063040
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3391183726
Short name T717
Test name
Test status
Simulation time 9041870778 ps
CPU time 15.35 seconds
Started Jan 21 01:42:42 PM PST 24
Finished Jan 21 01:42:58 PM PST 24
Peak memory 198680 kb
Host smart-bfb3661b-9833-403d-84e7-b0677c7653d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391183726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3391183726
Directory /workspace/99.uart_fifo_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%