Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	125030	1			T1	5		T2	8		T4	8
all_values[1]	125030	1			T1	5		T2	8		T4	8
all_values[2]	125030	1			T1	5		T2	8		T4	8
all_values[3]	125030	1			T1	5		T2	8		T4	8
all_values[4]	125030	1			T1	5		T2	8		T4	8
all_values[5]	125030	1			T1	5		T2	8		T4	8
all_values[6]	125030	1			T1	5		T2	8		T4	8
all_values[7]	125030	1			T1	5		T2	8		T4	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

495760

1

T1

24

T2

38

T4

25

auto[1]

504480

1

T1

16

T2

26

T4

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

982422

1

T1

28

T2

40

T4

40

auto[1]

17818

1

T1

12

T2

24

T4

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	58358	1			T1	1		T2	4		T4	2
all_values[0]	auto[0]	auto[1]	2742	1			T1	1		T2	2		T4	1
all_values[0]	auto[1]	auto[0]	61539	1			T1	1		T2	2		T4	2
all_values[0]	auto[1]	auto[1]	2391	1			T1	2		T4	3		T7	1
all_values[1]	auto[0]	auto[0]	58675	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	2448	1			T1	1		T2	1		T7	1
all_values[1]	auto[1]	auto[0]	61736	1			T1	1		T2	3		T4	5
all_values[1]	auto[1]	auto[1]	2171	1			T1	2		T2	3		T4	2
all_values[2]	auto[0]	auto[0]	60992	1			T1	4		T4	5		T7	1
all_values[2]	auto[0]	auto[1]	2595	1			T1	1		T10	2		T45	1
all_values[2]	auto[1]	auto[0]	58993	1			T2	6		T4	2		T7	1
all_values[2]	auto[1]	auto[1]	2450	1			T2	2		T4	1		T7	3
all_values[3]	auto[0]	auto[0]	65150	1			T1	2		T2	4		T4	1
all_values[3]	auto[0]	auto[1]	263	1			T2	4		T7	1		T46	5
all_values[3]	auto[1]	auto[0]	59364	1			T1	3		T4	2		T7	1
all_values[3]	auto[1]	auto[1]	253	1			T4	5		T10	4		T46	1
all_values[4]	auto[0]	auto[0]	56521	1			T1	3		T2	3		T4	2
all_values[4]	auto[0]	auto[1]	466	1			T2	2		T4	1		T7	3
all_values[4]	auto[1]	auto[0]	67597	1			T1	2		T2	1		T4	4
all_values[4]	auto[1]	auto[1]	446	1			T2	2		T4	1		T46	1
all_values[5]	auto[0]	auto[0]	58775	1			T2	6		T4	2		T7	3
all_values[5]	auto[0]	auto[1]	181	1			T1	1		T2	1		T4	5
all_values[5]	auto[1]	auto[0]	65824	1			T1	1		T2	1		T4	1
all_values[5]	auto[1]	auto[1]	250	1			T1	3		T7	1		T45	1
all_values[6]	auto[0]	auto[0]	67550	1			T1	4		T2	3		T7	1
all_values[6]	auto[0]	auto[1]	202	1			T2	1		T4	2		T47	2
all_values[6]	auto[1]	auto[0]	57070	1			T1	1		T2	1		T4	3
all_values[6]	auto[1]	auto[1]	208	1			T2	3		T4	3		T7	2
all_values[7]	auto[0]	auto[0]	60430	1			T1	4		T2	4		T4	3
all_values[7]	auto[0]	auto[1]	412	1			T1	1		T2	2		T10	1
all_values[7]	auto[1]	auto[0]	63848	1			T2	1		T4	5		T7	1
all_values[7]	auto[1]	auto[1]	340	1			T2	1		T7	4		T10	2