Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2588

1

T1

1

T2

1

T3

2

auto[UartRx]

2588

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4532	1			T1	2		T2	2		T3	4
values[1]	46	1			T14	1		T27	1		T86	1
values[2]	52	1			T27	4		T86	1		T321	1
values[3]	58	1			T27	3		T86	1		T319	3
values[4]	64	1			T86	1		T319	1		T321	1
values[5]	60	1			T14	1		T86	1		T321	4
values[6]	65	1			T14	1		T27	1		T86	4
values[7]	60	1			T14	1		T27	1		T319	1
values[8]	64	1			T401	2		T126	1		T345	1
values[9]	48	1			T14	1		T401	1		T87	1
values[10]	81	1			T27	1		T86	1		T87	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2360	1			T1	1		T2	1		T3	2
auto[UartTx]	values[1]	16	1			T86	1		T401	1		T195	1
auto[UartTx]	values[2]	20	1			T27	1		T321	1		T164	1
auto[UartTx]	values[3]	18	1			T27	1		T319	2		T401	1
auto[UartTx]	values[4]	24	1			T128	1		T313	1		T444	1
auto[UartTx]	values[5]	19	1			T86	1		T321	2		T345	1
auto[UartTx]	values[6]	28	1			T14	1		T27	1		T86	1
auto[UartTx]	values[7]	21	1			T14	1		T345	1		T128	1
auto[UartTx]	values[8]	24	1			T126	1		T345	1		T144	1
auto[UartTx]	values[9]	19	1			T401	1		T164	2		T420	1
auto[UartTx]	values[10]	22	1			T87	1		T361	1		T128	1
auto[UartRx]	values[0]	2172	1			T1	1		T2	1		T3	2
auto[UartRx]	values[1]	30	1			T14	1		T27	1		T321	1
auto[UartRx]	values[2]	32	1			T27	3		T86	1		T89	1
auto[UartRx]	values[3]	40	1			T27	2		T86	1		T319	1
auto[UartRx]	values[4]	40	1			T86	1		T319	1		T321	1
auto[UartRx]	values[5]	41	1			T14	1		T321	2		T87	2
auto[UartRx]	values[6]	37	1			T86	3		T126	1		T345	1
auto[UartRx]	values[7]	39	1			T27	1		T319	1		T401	1
auto[UartRx]	values[8]	40	1			T401	2		T195	1		T445	1
auto[UartRx]	values[9]	29	1			T14	1		T87	1		T164	2
auto[UartRx]	values[10]	59	1			T27	1		T86	1		T87	1