Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2067	1			T11	1		T12	1		T13	3
auto[BaudRate115200]	2206	1			T11	2		T12	1		T13	1
auto[BaudRate230400]	1970	1			T11	1		T19	4		T21	1
auto[BaudRate128Kbps]	1992	1			T12	1		T19	1		T14	3
auto[BaudRate256Kbps]	2262	1			T12	1		T19	1		T14	6
auto[BaudRate1Mbps]	1860	1			T11	1		T19	3		T14	13
auto[BaudRate1p5Mbps]	1318	1			T11	1		T12	1		T21	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1545	1			T20	14		T17	7		T446	13
freqs[25]	1168	1			T12	5		T13	4		T14	50
freqs[48]	547	1			T21	6		T398	8		T408	5
freqs[50]	792	1			T413	7		T304	19		T126	54
freqs[100]	996	1			T11	6		T436	2		T162	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	251	1			T20	7		T446	7		T254	2
auto[BaudRate9600]	freqs[25]	175	1			T12	1		T13	3		T14	4
auto[BaudRate9600]	freqs[48]	60	1			T21	2		T87	2		T399	1
auto[BaudRate9600]	freqs[50]	105	1			T304	5		T126	4		T447	9
auto[BaudRate9600]	freqs[100]	168	1			T11	1		T86	5		T116	2
auto[BaudRate115200]	freqs[24]	249	1			T20	7		T17	2		T446	6
auto[BaudRate115200]	freqs[25]	180	1			T12	1		T13	1		T14	9
auto[BaudRate115200]	freqs[48]	98	1			T21	1		T87	8		T426	1
auto[BaudRate115200]	freqs[50]	117	1			T413	2		T304	2		T126	5
auto[BaudRate115200]	freqs[100]	180	1			T11	2		T436	1		T162	2
auto[BaudRate230400]	freqs[24]	230	1			T254	2		T331	1		T140	2
auto[BaudRate230400]	freqs[25]	166	1			T14	7		T160	3		T319	4
auto[BaudRate230400]	freqs[48]	72	1			T21	1		T87	10		T399	3
auto[BaudRate230400]	freqs[50]	93	1			T413	1		T304	4		T126	1
auto[BaudRate230400]	freqs[100]	112	1			T11	1		T162	3		T86	7
auto[BaudRate128Kbps]	freqs[24]	172	1			T17	2		T331	2		T140	2
auto[BaudRate128Kbps]	freqs[25]	162	1			T12	1		T14	3		T124	3
auto[BaudRate128Kbps]	freqs[48]	59	1			T87	7		T399	1		T89	10
auto[BaudRate128Kbps]	freqs[50]	131	1			T413	2		T304	2		T126	7
auto[BaudRate128Kbps]	freqs[100]	142	1			T436	1		T86	11		T424	2
auto[BaudRate256Kbps]	freqs[24]	260	1			T17	1		T331	1		T140	2
auto[BaudRate256Kbps]	freqs[25]	180	1			T12	1		T14	6		T124	3
auto[BaudRate256Kbps]	freqs[48]	92	1			T398	3		T408	2		T87	8
auto[BaudRate256Kbps]	freqs[50]	121	1			T413	1		T304	1		T126	11
auto[BaudRate256Kbps]	freqs[100]	121	1			T162	2		T86	6		T409	2
auto[BaudRate1Mbps]	freqs[24]	267	1			T17	2		T254	4		T331	2
auto[BaudRate1Mbps]	freqs[25]	197	1			T14	13		T124	2		T319	7
auto[BaudRate1Mbps]	freqs[48]	89	1			T398	2		T408	1		T87	11
auto[BaudRate1Mbps]	freqs[50]	97	1			T304	2		T126	14		T345	7
auto[BaudRate1Mbps]	freqs[100]	142	1			T11	1		T162	2		T86	13
auto[BaudRate1p5Mbps]	freqs[25]	108	1			T12	1		T14	8		T124	1
auto[BaudRate1p5Mbps]	freqs[48]	77	1			T21	2		T398	3		T408	2
auto[BaudRate1p5Mbps]	freqs[50]	128	1			T413	1		T304	3		T126	12
auto[BaudRate1p5Mbps]	freqs[100]	131	1			T11	1		T162	1		T86	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded