Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 8 0 8 100.00 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_watermark_lvl

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 2209 1 T1 3 T2 4 T4 2
all_levels[1] 567 1 T14 4 T23 1 T18 2
all_levels[2] 382 1 T19 1 T14 2 T302 1
all_levels[3] 326 1 T145 4 T25 2 T112 2
all_levels[4] 297 1 T16 1 T304 2 T85 2
all_levels[5] 385 1 T14 6 T23 2 T18 3
all_levels[6] 291 1 T11 1 T14 1 T24 1
all_levels[7] 159 1 T12 1 T14 2 T23 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%