Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	125030	1			T1	5		T2	8		T4	8
all_pins[1]	125030	1			T1	5		T2	8		T4	8
all_pins[2]	125030	1			T1	5		T2	8		T4	8
all_pins[3]	125030	1			T1	5		T2	8		T4	8
all_pins[4]	125030	1			T1	5		T2	8		T4	8
all_pins[5]	125030	1			T1	5		T2	8		T4	8
all_pins[6]	125030	1			T1	5		T2	8		T4	8
all_pins[7]	125030	1			T1	5		T2	8		T4	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	990958	1			T1	33		T2	53		T4	49
values[0x1]	9282	1			T1	7		T2	11		T4	15
transitions[0x0=>0x1]	8349	1			T1	5		T2	9		T4	12
transitions[0x1=>0x0]	8364	1			T1	5		T2	9		T4	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	122569	1			T1	3		T2	8		T4	5
all_pins[0]	values[0x1]	2461	1			T1	2		T4	3		T7	1
all_pins[0]	transitions[0x0=>0x1]	2180	1			T4	2		T7	1		T10	1
all_pins[0]	transitions[0x1=>0x0]	1888	1			T2	3		T4	1		T7	2
all_pins[1]	values[0x0]	122861	1			T1	3		T2	5		T4	6
all_pins[1]	values[0x1]	2169	1			T1	2		T2	3		T4	2
all_pins[1]	transitions[0x0=>0x1]	1875	1			T1	2		T2	1		T4	1
all_pins[1]	transitions[0x1=>0x0]	2212	1			T7	1		T45	2		T47	2
all_pins[2]	values[0x0]	122524	1			T1	5		T2	6		T4	7
all_pins[2]	values[0x1]	2506	1			T2	2		T4	1		T7	3
all_pins[2]	transitions[0x0=>0x1]	2453	1			T2	2		T7	3		T45	2
all_pins[2]	transitions[0x1=>0x0]	200	1			T4	4		T10	4		T49	2
all_pins[3]	values[0x0]	124777	1			T1	5		T2	8		T4	3
all_pins[3]	values[0x1]	253	1			T4	5		T10	4		T46	1
all_pins[3]	transitions[0x0=>0x1]	222	1			T4	5		T10	4		T46	1
all_pins[3]	transitions[0x1=>0x0]	415	1			T2	2		T4	1		T46	1
all_pins[4]	values[0x0]	124584	1			T1	5		T2	6		T4	7
all_pins[4]	values[0x1]	446	1			T2	2		T4	1		T46	1
all_pins[4]	transitions[0x0=>0x1]	365	1			T2	2		T4	1		T46	1
all_pins[4]	transitions[0x1=>0x0]	218	1			T1	3		T7	1		T45	1
all_pins[5]	values[0x0]	124731	1			T1	2		T2	8		T4	8
all_pins[5]	values[0x1]	299	1			T1	3		T7	1		T45	1
all_pins[5]	transitions[0x0=>0x1]	233	1			T1	3		T7	1		T45	1
all_pins[5]	transitions[0x1=>0x0]	742	1			T2	3		T4	3		T7	2
all_pins[6]	values[0x0]	124222	1			T1	5		T2	5		T4	5
all_pins[6]	values[0x1]	808	1			T2	3		T4	3		T7	2
all_pins[6]	transitions[0x0=>0x1]	743	1			T2	3		T4	3		T46	4
all_pins[6]	transitions[0x1=>0x0]	275	1			T2	1		T7	2		T46	1
all_pins[7]	values[0x0]	124690	1			T1	5		T2	7		T4	8
all_pins[7]	values[0x1]	340	1			T2	1		T7	4		T10	2
all_pins[7]	transitions[0x0=>0x1]	278	1			T2	1		T7	2		T46	3
all_pins[7]	transitions[0x1=>0x0]	2414	1			T1	2		T4	3		T10	2