Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	854	1			T1	4		T2	7		T4	7
all_values[1]	854	1			T1	4		T2	7		T4	7
all_values[2]	854	1			T1	4		T2	7		T4	7
all_values[3]	854	1			T1	4		T2	7		T4	7
all_values[4]	854	1			T1	4		T2	7		T4	7
all_values[5]	854	1			T1	4		T2	7		T4	7
all_values[6]	854	1			T1	4		T2	7		T4	7
all_values[7]	854	1			T1	4		T2	7		T4	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3665

1

T1

22

T2

40

T4

29

auto[1]

3167

1

T1

10

T2

16

T4

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2637

1

T1

18

T2

24

T4

22

auto[1]

4195

1

T1

14

T2

32

T4

34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3998

1

T1

21

T2

34

T4

31

auto[1]

2834

1

T1

11

T2

22

T4

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	183	1			T1	1		T2	2		T4	1
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T45	1		T46	2		T47	1
all_values[0]	auto[0]	auto[1]	auto[0]	161	1			T2	1		T4	1		T7	2
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T1	1		T4	1		T10	3
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T1	2		T2	4		T4	3
all_values[0]	auto[1]	auto[1]	auto[1]	163	1			T4	1		T7	1		T10	1
all_values[1]	auto[0]	auto[0]	auto[0]	189	1			T1	1		T2	1		T4	2
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T46	1		T47	2		T48	1
all_values[1]	auto[0]	auto[1]	auto[0]	145	1			T2	1		T4	2		T10	1
all_values[1]	auto[0]	auto[1]	auto[1]	93	1			T1	1		T2	1		T7	1
all_values[1]	auto[1]	auto[0]	auto[1]	201	1			T1	2		T2	3		T4	1
all_values[1]	auto[1]	auto[1]	auto[1]	151	1			T2	1		T4	2		T7	1
all_values[2]	auto[0]	auto[0]	auto[0]	182	1			T1	2		T2	1		T4	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T10	1		T46	1		T49	1
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T2	3		T4	2		T46	1
all_values[2]	auto[0]	auto[1]	auto[1]	88	1			T2	1		T4	1		T7	1
all_values[2]	auto[1]	auto[0]	auto[1]	198	1			T1	2		T4	2		T10	2
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T2	2		T4	1		T7	2
all_values[3]	auto[0]	auto[0]	auto[0]	182	1			T1	3		T2	1		T7	2
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T2	2		T46	2		T55	1
all_values[3]	auto[0]	auto[1]	auto[0]	130	1			T1	1		T4	1		T7	1
all_values[3]	auto[0]	auto[1]	auto[1]	89	1			T4	3		T10	1		T48	1
all_values[3]	auto[1]	auto[0]	auto[1]	205	1			T2	4		T4	2		T7	1
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T4	1		T10	3		T46	2
all_values[4]	auto[0]	auto[0]	auto[0]	193	1			T1	2		T2	3		T4	1
all_values[4]	auto[0]	auto[0]	auto[1]	95	1			T2	1		T7	2		T47	1
all_values[4]	auto[0]	auto[1]	auto[0]	153	1			T1	2		T4	2		T10	2
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T2	1		T55	1		T395	1
all_values[4]	auto[1]	auto[0]	auto[1]	179	1			T2	2		T4	3		T7	1
all_values[4]	auto[1]	auto[1]	auto[1]	160	1			T4	1		T46	3		T47	1
all_values[5]	auto[0]	auto[0]	auto[0]	181	1			T2	4		T7	2		T46	2
all_values[5]	auto[0]	auto[0]	auto[1]	65	1			T4	1		T10	1		T47	1
all_values[5]	auto[0]	auto[1]	auto[0]	137	1			T2	1		T4	1		T10	1
all_values[5]	auto[0]	auto[1]	auto[1]	104	1			T1	1		T7	1		T45	1
all_values[5]	auto[1]	auto[0]	auto[1]	193	1			T1	1		T2	2		T4	5
all_values[5]	auto[1]	auto[1]	auto[1]	174	1			T1	2		T47	2		T48	3
all_values[6]	auto[0]	auto[0]	auto[0]	187	1			T1	2		T2	3		T4	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T4	1		T47	1		T48	1
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T1	2		T4	1		T7	1
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T2	1		T4	2		T7	1
all_values[6]	auto[1]	auto[0]	auto[1]	186	1			T2	1		T46	1		T47	3
all_values[6]	auto[1]	auto[1]	auto[1]	169	1			T2	2		T4	2		T7	1
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T1	2		T2	3		T4	4
all_values[7]	auto[0]	auto[0]	auto[1]	104	1			T2	2		T48	1		T49	1
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T4	2		T10	1		T45	1
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T2	1		T7	3		T10	2
all_values[7]	auto[1]	auto[0]	auto[1]	190	1			T1	2		T2	1		T4	1
all_values[7]	auto[1]	auto[1]	auto[1]	172	1			T7	1		T46	3		T48	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal