Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.79 98.45 100.00 99.76 100.00 97.44


Total test records in report: 1296
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T93 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3322396772 Jan 24 11:14:30 PM PST 24 Jan 24 11:14:32 PM PST 24 97338573 ps
T1254 /workspace/coverage/cover_reg_top/46.uart_intr_test.3511199386 Jan 24 11:16:23 PM PST 24 Jan 24 11:16:26 PM PST 24 14764036 ps
T1255 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3668582837 Jan 24 11:15:47 PM PST 24 Jan 24 11:15:50 PM PST 24 364180959 ps
T1256 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2840975859 Jan 24 11:11:50 PM PST 24 Jan 24 11:11:52 PM PST 24 363539756 ps
T1257 /workspace/coverage/cover_reg_top/13.uart_intr_test.1756467336 Jan 24 11:14:24 PM PST 24 Jan 24 11:14:26 PM PST 24 14853934 ps
T72 /workspace/coverage/cover_reg_top/12.uart_csr_rw.324482581 Jan 24 11:14:24 PM PST 24 Jan 24 11:14:26 PM PST 24 11964692 ps
T1258 /workspace/coverage/cover_reg_top/8.uart_intr_test.98177798 Jan 24 11:13:59 PM PST 24 Jan 24 11:14:01 PM PST 24 14550018 ps
T1259 /workspace/coverage/cover_reg_top/24.uart_intr_test.889949752 Jan 24 11:15:53 PM PST 24 Jan 24 11:15:56 PM PST 24 12840927 ps
T1260 /workspace/coverage/cover_reg_top/32.uart_intr_test.3928547739 Jan 24 11:16:05 PM PST 24 Jan 24 11:16:07 PM PST 24 30083674 ps
T1261 /workspace/coverage/cover_reg_top/1.uart_intr_test.1567690348 Jan 25 12:21:20 AM PST 24 Jan 25 12:21:23 AM PST 24 61120359 ps
T1262 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2121500214 Jan 24 11:13:00 PM PST 24 Jan 24 11:13:02 PM PST 24 114292747 ps
T1263 /workspace/coverage/cover_reg_top/2.uart_intr_test.3628311232 Jan 24 11:12:38 PM PST 24 Jan 24 11:12:43 PM PST 24 34635529 ps
T1264 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.895110195 Jan 24 11:15:46 PM PST 24 Jan 24 11:15:48 PM PST 24 20234725 ps
T73 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.260520116 Jan 24 11:12:41 PM PST 24 Jan 24 11:12:45 PM PST 24 21501258 ps
T1265 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1218065232 Jan 24 11:15:49 PM PST 24 Jan 24 11:15:53 PM PST 24 26320050 ps
T1266 /workspace/coverage/cover_reg_top/11.uart_tl_errors.316287131 Jan 24 11:14:01 PM PST 24 Jan 24 11:14:04 PM PST 24 271037374 ps
T1267 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2508067847 Jan 24 11:15:50 PM PST 24 Jan 24 11:15:55 PM PST 24 13861846 ps
T1268 /workspace/coverage/cover_reg_top/31.uart_intr_test.365834199 Jan 25 12:00:31 AM PST 24 Jan 25 12:00:34 AM PST 24 11526708 ps
T1269 /workspace/coverage/cover_reg_top/29.uart_intr_test.3171017349 Jan 25 01:19:22 AM PST 24 Jan 25 01:19:23 AM PST 24 50400998 ps
T1270 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3089594873 Jan 24 11:14:23 PM PST 24 Jan 24 11:14:25 PM PST 24 102442429 ps
T1271 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3930095028 Jan 24 11:13:55 PM PST 24 Jan 24 11:13:57 PM PST 24 54233768 ps
T1272 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3148612872 Jan 25 12:49:37 AM PST 24 Jan 25 12:49:40 AM PST 24 24371319 ps
T1273 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.423246263 Jan 24 11:13:56 PM PST 24 Jan 24 11:13:58 PM PST 24 165651714 ps
T1274 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3475222758 Jan 24 11:11:49 PM PST 24 Jan 24 11:11:51 PM PST 24 17617984 ps
T1275 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3634355892 Jan 25 12:25:20 AM PST 24 Jan 25 12:25:24 AM PST 24 585961391 ps
T1276 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2858141766 Jan 25 06:35:58 AM PST 24 Jan 25 06:36:01 AM PST 24 64308818 ps
T1277 /workspace/coverage/cover_reg_top/4.uart_intr_test.1211071935 Jan 24 11:13:00 PM PST 24 Jan 24 11:13:02 PM PST 24 50097937 ps
T1278 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.41332541 Jan 24 11:14:24 PM PST 24 Jan 24 11:14:26 PM PST 24 33061883 ps
T1279 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1987596087 Jan 24 11:14:30 PM PST 24 Jan 24 11:14:32 PM PST 24 23556099 ps
T1280 /workspace/coverage/cover_reg_top/17.uart_intr_test.132298760 Jan 24 11:15:48 PM PST 24 Jan 24 11:15:50 PM PST 24 45199323 ps
T1281 /workspace/coverage/cover_reg_top/48.uart_intr_test.4132486762 Jan 24 11:16:24 PM PST 24 Jan 24 11:16:26 PM PST 24 14955653 ps
T1282 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.852815238 Jan 24 11:15:47 PM PST 24 Jan 24 11:15:49 PM PST 24 76470903 ps
T1283 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4067914854 Jan 24 11:15:54 PM PST 24 Jan 24 11:15:58 PM PST 24 342196909 ps
T1284 /workspace/coverage/cover_reg_top/11.uart_intr_test.4044114951 Jan 24 11:14:19 PM PST 24 Jan 24 11:14:22 PM PST 24 14380638 ps
T1285 /workspace/coverage/cover_reg_top/18.uart_tl_errors.551071316 Jan 24 11:15:49 PM PST 24 Jan 24 11:15:54 PM PST 24 381549735 ps
T1286 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3265603216 Jan 24 11:13:53 PM PST 24 Jan 24 11:13:55 PM PST 24 51725681 ps
T1287 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.746982886 Jan 24 11:13:59 PM PST 24 Jan 24 11:14:01 PM PST 24 24275102 ps
T1288 /workspace/coverage/cover_reg_top/22.uart_intr_test.125007680 Jan 24 11:15:53 PM PST 24 Jan 24 11:15:57 PM PST 24 98715198 ps
T1289 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2649685703 Jan 25 12:49:34 AM PST 24 Jan 25 12:49:36 AM PST 24 13686181 ps
T1290 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1139036654 Jan 24 11:14:24 PM PST 24 Jan 24 11:14:26 PM PST 24 93778068 ps
T1291 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2835845067 Jan 24 11:13:57 PM PST 24 Jan 24 11:13:58 PM PST 24 15912189 ps
T1292 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3730600484 Jan 24 11:14:23 PM PST 24 Jan 24 11:14:25 PM PST 24 65144163 ps
T1293 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2884046587 Jan 24 11:13:53 PM PST 24 Jan 24 11:13:55 PM PST 24 15235580 ps
T1294 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2128436500 Jan 24 11:12:41 PM PST 24 Jan 24 11:12:47 PM PST 24 4970008663 ps
T1295 /workspace/coverage/cover_reg_top/35.uart_intr_test.4018965104 Jan 24 11:16:05 PM PST 24 Jan 24 11:16:07 PM PST 24 22627757 ps
T1296 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.272625258 Jan 24 11:13:24 PM PST 24 Jan 24 11:13:27 PM PST 24 23307430 ps

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2354088816
Short name T8
Test name
Test status
Simulation time 47601974 ps
CPU time 0.72 seconds
Started Jan 24 11:15:48 PM PST 24
Finished Jan 24 11:15:50 PM PST 24
Peak memory 196460 kb
Host smart-5c165b3e-6856-4d3a-b37a-0c8a3ad2cd80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354088816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2354088816
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2808041774
Short name T14
Test name
Test status
Simulation time 354119331505 ps
CPU time 1594.93 seconds
Started Jan 25 02:36:53 AM PST 24
Finished Jan 25 03:03:29 AM PST 24
Peak memory 233204 kb
Host smart-6364cfd5-5885-411e-9c46-07e80adba793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808041774 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2808041774
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1712801389
Short name T4
Test name
Test status
Simulation time 28445868 ps
CPU time 0.59 seconds
Started Jan 24 11:13:22 PM PST 24
Finished Jan 24 11:13:26 PM PST 24
Peak memory 194288 kb
Host smart-ad485c5e-6aef-490c-9e2e-5b46541504c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712801389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1712801389
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/default/32.uart_stress_all.2927780906
Short name T16
Test name
Test status
Simulation time 1453808801619 ps
CPU time 566.87 seconds
Started Jan 25 02:25:13 AM PST 24
Finished Jan 25 02:34:47 AM PST 24
Peak memory 208452 kb
Host smart-66ec5f0a-9981-4ab9-967d-9bf58aa8a01f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927780906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2927780906
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3834787422
Short name T87
Test name
Test status
Simulation time 280517094965 ps
CPU time 2573.91 seconds
Started Jan 25 02:38:52 AM PST 24
Finished Jan 25 03:21:56 AM PST 24
Peak memory 226496 kb
Host smart-5bf1cab3-4b62-44b3-9063-63e63224f430
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834787422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3834787422
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4130076238
Short name T42
Test name
Test status
Simulation time 97972016 ps
CPU time 1.86 seconds
Started Jan 24 11:12:59 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 199860 kb
Host smart-84f633f1-b698-4439-95c0-403a6b56b3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130076238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4130076238
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/default/47.uart_stress_all.3544523777
Short name T145
Test name
Test status
Simulation time 381935232420 ps
CPU time 780.78 seconds
Started Jan 25 02:35:11 AM PST 24
Finished Jan 25 02:48:14 AM PST 24
Peak memory 200568 kb
Host smart-0c8cbcd6-4a00-4e37-8b3d-2f8fefb9148a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544523777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3544523777
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1062459157
Short name T41
Test name
Test status
Simulation time 97775671 ps
CPU time 1.35 seconds
Started Jan 24 11:13:24 PM PST 24
Finished Jan 24 11:13:28 PM PST 24
Peak memory 199044 kb
Host smart-d3017910-5717-4a04-8d5c-96094d626b56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062459157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1062459157
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.177236507
Short name T321
Test name
Test status
Simulation time 259729807358 ps
CPU time 1003.91 seconds
Started Jan 25 04:43:51 AM PST 24
Finished Jan 25 05:01:06 AM PST 24
Peak memory 225024 kb
Host smart-6492657f-b52a-4468-a830-87b317533f3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177236507 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.177236507
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all.3832302991
Short name T120
Test name
Test status
Simulation time 644621821787 ps
CPU time 403.61 seconds
Started Jan 25 04:58:10 AM PST 24
Finished Jan 25 05:04:54 AM PST 24
Peak memory 208524 kb
Host smart-114a78a0-d6b3-4721-9f9d-df22752019db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832302991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3832302991
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all.23130034
Short name T85
Test name
Test status
Simulation time 277826904420 ps
CPU time 282.21 seconds
Started Jan 25 02:14:20 AM PST 24
Finished Jan 25 02:19:03 AM PST 24
Peak memory 208516 kb
Host smart-1b702348-80ea-441b-bbde-c1410e818c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23130034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.23130034
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1927526682
Short name T60
Test name
Test status
Simulation time 17282457 ps
CPU time 0.68 seconds
Started Jan 25 12:38:05 AM PST 24
Finished Jan 25 12:38:07 AM PST 24
Peak memory 195388 kb
Host smart-dd1b6643-bb55-4481-87b2-d7198649eb67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927526682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1927526682
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/default/39.uart_stress_all.1782049400
Short name T150
Test name
Test status
Simulation time 498255506386 ps
CPU time 2490.13 seconds
Started Jan 25 02:32:23 AM PST 24
Finished Jan 25 03:13:54 AM PST 24
Peak memory 200068 kb
Host smart-6d20cd97-5d08-4d7b-ade3-aa53f4acc9ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782049400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1782049400
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2840245113
Short name T128
Test name
Test status
Simulation time 474619597820 ps
CPU time 1125.69 seconds
Started Jan 25 02:49:14 AM PST 24
Finished Jan 25 03:08:01 AM PST 24
Peak memory 227748 kb
Host smart-08287ba3-5eab-4cf6-ad03-13f8f180ab25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840245113 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2840245113
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1503974167
Short name T116
Test name
Test status
Simulation time 673667616191 ps
CPU time 1202.11 seconds
Started Jan 25 02:20:33 AM PST 24
Finished Jan 25 02:40:36 AM PST 24
Peak memory 199164 kb
Host smart-eee03199-3cc5-4a49-9290-cd963a963475
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503974167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1503974167
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_perf.960754403
Short name T410
Test name
Test status
Simulation time 23324404064 ps
CPU time 328.96 seconds
Started Jan 25 02:20:30 AM PST 24
Finished Jan 25 02:26:00 AM PST 24
Peak memory 200068 kb
Host smart-05b7b5cd-5312-491e-b91f-aa42a3b69adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960754403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.960754403
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3824332374
Short name T84
Test name
Test status
Simulation time 35584940 ps
CPU time 0.85 seconds
Started Jan 25 02:21:47 AM PST 24
Finished Jan 25 02:21:58 AM PST 24
Peak memory 217288 kb
Host smart-cc0e8fa0-cffc-494a-aa32-7950363b7e0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824332374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3824332374
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2894556232
Short name T76
Test name
Test status
Simulation time 863325568674 ps
CPU time 1123.14 seconds
Started Jan 25 02:35:37 AM PST 24
Finished Jan 25 02:54:27 AM PST 24
Peak memory 226064 kb
Host smart-221c8766-7d19-4bd7-9aa6-7ba266f4b279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894556232 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2894556232
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2663646708
Short name T302
Test name
Test status
Simulation time 59060539537 ps
CPU time 19.93 seconds
Started Jan 25 02:05:17 AM PST 24
Finished Jan 25 02:05:45 AM PST 24
Peak memory 200064 kb
Host smart-ea0de288-d423-4699-b9a8-b5ddafc07b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663646708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2663646708
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2333346458
Short name T164
Test name
Test status
Simulation time 111083204637 ps
CPU time 573.24 seconds
Started Jan 25 04:31:01 AM PST 24
Finished Jan 25 04:40:45 AM PST 24
Peak memory 228748 kb
Host smart-9302c4ec-ce99-4ea4-b3d3-fb372dff4927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333346458 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2333346458
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3436711709
Short name T526
Test name
Test status
Simulation time 33812042 ps
CPU time 0.61 seconds
Started Jan 25 02:11:25 AM PST 24
Finished Jan 25 02:11:33 AM PST 24
Peak memory 194696 kb
Host smart-90a2162b-32f6-4e72-9d4e-9a6b6f98d743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436711709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3436711709
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1553892571
Short name T304
Test name
Test status
Simulation time 234925047236 ps
CPU time 252.46 seconds
Started Jan 25 02:32:39 AM PST 24
Finished Jan 25 02:36:52 AM PST 24
Peak memory 200004 kb
Host smart-6f77dccd-007e-4363-87e4-812d52e1b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553892571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1553892571
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.24105998
Short name T47
Test name
Test status
Simulation time 14969522 ps
CPU time 0.6 seconds
Started Jan 24 11:13:59 PM PST 24
Finished Jan 24 11:14:01 PM PST 24
Peak memory 185052 kb
Host smart-49249abe-c626-4517-9f14-4c057905967b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24105998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.24105998
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3678843360
Short name T195
Test name
Test status
Simulation time 282944062506 ps
CPU time 780.75 seconds
Started Jan 25 02:25:09 AM PST 24
Finished Jan 25 02:38:20 AM PST 24
Peak memory 230908 kb
Host smart-f75114ee-44d8-4372-a5e9-88acfb7bf7b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678843360 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3678843360
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.600218606
Short name T39
Test name
Test status
Simulation time 96618430 ps
CPU time 0.97 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 198808 kb
Host smart-57d90e3c-05ca-4bd1-af55-3a9fc8ecd798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600218606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.600218606
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/45.uart_tx_rx.4266858701
Short name T407
Test name
Test status
Simulation time 136294441694 ps
CPU time 315.47 seconds
Started Jan 25 02:34:22 AM PST 24
Finished Jan 25 02:39:46 AM PST 24
Peak memory 200004 kb
Host smart-40e2e9e2-085a-4d21-8218-7ffedbc586c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266858701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4266858701
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2314288652
Short name T319
Test name
Test status
Simulation time 81213514020 ps
CPU time 358.27 seconds
Started Jan 25 02:40:25 AM PST 24
Finished Jan 25 02:46:34 AM PST 24
Peak memory 216040 kb
Host smart-59df048a-4642-4fdf-99b3-67faaf3fbaee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314288652 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2314288652
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2577117905
Short name T219
Test name
Test status
Simulation time 235545386658 ps
CPU time 336.3 seconds
Started Jan 25 02:43:23 AM PST 24
Finished Jan 25 02:49:13 AM PST 24
Peak memory 200076 kb
Host smart-5c1cd3be-6d4c-45d8-8fa2-4a83d6b9ca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577117905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2577117905
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3351922628
Short name T312
Test name
Test status
Simulation time 62913657707 ps
CPU time 83.39 seconds
Started Jan 25 02:48:12 AM PST 24
Finished Jan 25 02:49:37 AM PST 24
Peak memory 200072 kb
Host smart-0c0802b1-cad8-40d7-b457-f5e04d4e2814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351922628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3351922628
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1550956655
Short name T146
Test name
Test status
Simulation time 60190406364 ps
CPU time 25.53 seconds
Started Jan 25 05:03:07 AM PST 24
Finished Jan 25 05:03:41 AM PST 24
Peak memory 200092 kb
Host smart-834b4f96-e895-40c2-8362-925be1cf7157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550956655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1550956655
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.4224518170
Short name T126
Test name
Test status
Simulation time 44654037098 ps
CPU time 324.87 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:38:15 AM PST 24
Peak memory 216836 kb
Host smart-4e988607-550f-4ffd-8ee5-2a56a6aae334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224518170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.4224518170
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1338319560
Short name T189
Test name
Test status
Simulation time 163407851328 ps
CPU time 496.61 seconds
Started Jan 25 05:00:10 AM PST 24
Finished Jan 25 05:08:42 AM PST 24
Peak memory 211544 kb
Host smart-23d16c94-8389-4069-9743-0292c44088f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338319560 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1338319560
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2633662109
Short name T395
Test name
Test status
Simulation time 14876551 ps
CPU time 0.59 seconds
Started Jan 24 11:14:25 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 194296 kb
Host smart-abf5d47e-f821-43f3-8420-133b6b424241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633662109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2633662109
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2766045798
Short name T51
Test name
Test status
Simulation time 176095560 ps
CPU time 1.39 seconds
Started Jan 24 11:13:59 PM PST 24
Finished Jan 24 11:14:02 PM PST 24
Peak memory 198676 kb
Host smart-5c42c0cf-0222-45d6-af5f-38803950ae07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766045798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2766045798
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/17.uart_perf.2731424015
Short name T17
Test name
Test status
Simulation time 12321136020 ps
CPU time 158.58 seconds
Started Jan 25 03:34:28 AM PST 24
Finished Jan 25 03:37:13 AM PST 24
Peak memory 200096 kb
Host smart-df0be286-1190-48c8-a0b6-d226184d6616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731424015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2731424015
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1613144642
Short name T354
Test name
Test status
Simulation time 315341870121 ps
CPU time 754.63 seconds
Started Jan 25 02:15:44 AM PST 24
Finished Jan 25 02:28:21 AM PST 24
Peak memory 213948 kb
Host smart-92a4d9ad-44c9-4957-b73e-6f3cf1dc6aba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613144642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1613144642
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2929202197
Short name T77
Test name
Test status
Simulation time 675656542185 ps
CPU time 975.6 seconds
Started Jan 25 02:20:56 AM PST 24
Finished Jan 25 02:37:13 AM PST 24
Peak memory 227340 kb
Host smart-b2c66309-b6a4-4b72-a1f9-60267f6165a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929202197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2929202197
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.4189354096
Short name T317
Test name
Test status
Simulation time 91733526492 ps
CPU time 77.52 seconds
Started Jan 25 02:45:41 AM PST 24
Finished Jan 25 02:47:00 AM PST 24
Peak memory 200060 kb
Host smart-77846841-abe1-414e-996f-912a9c893b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189354096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.4189354096
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.912047427
Short name T176
Test name
Test status
Simulation time 133056413758 ps
CPU time 35.55 seconds
Started Jan 25 02:46:54 AM PST 24
Finished Jan 25 02:47:36 AM PST 24
Peak memory 199696 kb
Host smart-5f193cbc-3b80-4bf8-9e3e-9740b7ee54ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912047427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.912047427
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.217412615
Short name T291
Test name
Test status
Simulation time 1322560337493 ps
CPU time 623.83 seconds
Started Jan 25 02:39:56 AM PST 24
Finished Jan 25 02:50:22 AM PST 24
Peak memory 213232 kb
Host smart-3cdb5776-1862-4e87-bbe1-fc019cefb14d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217412615 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.217412615
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3777917018
Short name T393
Test name
Test status
Simulation time 269648627155 ps
CPU time 50.91 seconds
Started Jan 25 02:09:47 AM PST 24
Finished Jan 25 02:10:43 AM PST 24
Peak memory 200120 kb
Host smart-91f1d019-cb45-4163-9397-e257b0f41d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777917018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3777917018
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2815630800
Short name T216
Test name
Test status
Simulation time 16960581394 ps
CPU time 21.52 seconds
Started Jan 25 02:41:26 AM PST 24
Finished Jan 25 02:41:48 AM PST 24
Peak memory 200076 kb
Host smart-34f26cf4-26e2-4cf2-aaac-e11a3ef2c400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815630800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2815630800
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3798852202
Short name T260
Test name
Test status
Simulation time 40282609722 ps
CPU time 47.13 seconds
Started Jan 25 02:43:11 AM PST 24
Finished Jan 25 02:44:08 AM PST 24
Peak memory 200024 kb
Host smart-57f2ee24-3b9c-49bd-b3f5-2141afa652a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798852202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3798852202
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.2230733359
Short name T347
Test name
Test status
Simulation time 671264471495 ps
CPU time 743.03 seconds
Started Jan 25 03:08:00 AM PST 24
Finished Jan 25 03:20:24 AM PST 24
Peak memory 200316 kb
Host smart-e130b93b-f777-4e94-a0a3-1f3e1b4d5817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230733359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2230733359
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2425157719
Short name T137
Test name
Test status
Simulation time 14129543154 ps
CPU time 35.35 seconds
Started Jan 25 02:43:22 AM PST 24
Finished Jan 25 02:44:09 AM PST 24
Peak memory 200048 kb
Host smart-d79f1a4f-8e4f-49be-8377-8d6cdde10680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425157719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2425157719
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3611943636
Short name T344
Test name
Test status
Simulation time 108523258717 ps
CPU time 80.06 seconds
Started Jan 25 02:44:50 AM PST 24
Finished Jan 25 02:46:11 AM PST 24
Peak memory 199612 kb
Host smart-f270d8d0-78cd-4d57-a17e-6ddb4a756d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611943636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3611943636
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_full.747229616
Short name T366
Test name
Test status
Simulation time 108276086990 ps
CPU time 55.5 seconds
Started Jan 25 02:23:49 AM PST 24
Finished Jan 25 02:24:45 AM PST 24
Peak memory 200064 kb
Host smart-b645cf3b-b442-44b0-ae8b-7d11e024ebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747229616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.747229616
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.418453318
Short name T267
Test name
Test status
Simulation time 595553319952 ps
CPU time 1495.69 seconds
Started Jan 25 03:18:30 AM PST 24
Finished Jan 25 03:43:28 AM PST 24
Peak memory 228112 kb
Host smart-bd37395d-eae9-4b92-a7e2-3ebbda33f6ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418453318 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.418453318
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3624737057
Short name T327
Test name
Test status
Simulation time 110339830775 ps
CPU time 97.79 seconds
Started Jan 25 02:41:14 AM PST 24
Finished Jan 25 02:42:53 AM PST 24
Peak memory 200120 kb
Host smart-1eab83f2-c136-4ec7-b202-77a74ea6da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624737057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3624737057
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.993199758
Short name T149
Test name
Test status
Simulation time 17575895550 ps
CPU time 29.1 seconds
Started Jan 25 02:42:16 AM PST 24
Finished Jan 25 02:43:03 AM PST 24
Peak memory 199516 kb
Host smart-451cc762-3f1f-4014-8c3f-64c7906db5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993199758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.993199758
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1733672039
Short name T233
Test name
Test status
Simulation time 93481838853 ps
CPU time 204.06 seconds
Started Jan 25 02:45:43 AM PST 24
Finished Jan 25 02:49:08 AM PST 24
Peak memory 200052 kb
Host smart-7f7e58df-f043-4e3e-aa45-d640b75121e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733672039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1733672039
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3247076705
Short name T142
Test name
Test status
Simulation time 20697665552 ps
CPU time 33.81 seconds
Started Jan 25 02:47:16 AM PST 24
Finished Jan 25 02:47:53 AM PST 24
Peak memory 199896 kb
Host smart-8b8d61c0-a3a9-4211-8263-4a45e6e38da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247076705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3247076705
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.146508496
Short name T156
Test name
Test status
Simulation time 1028579751583 ps
CPU time 466.33 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:40:37 AM PST 24
Peak memory 200072 kb
Host smart-1b5bf240-f039-4af3-b163-0d0f1d5ef737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146508496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.146508496
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4280752848
Short name T450
Test name
Test status
Simulation time 10995937 ps
CPU time 0.62 seconds
Started Jan 24 11:16:13 PM PST 24
Finished Jan 24 11:16:15 PM PST 24
Peak memory 185000 kb
Host smart-d6a20043-0f10-4a95-95c2-32bfd32fcd42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280752848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4280752848
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2365206560
Short name T202
Test name
Test status
Simulation time 114355784817 ps
CPU time 40.07 seconds
Started Jan 25 04:10:43 AM PST 24
Finished Jan 25 04:11:24 AM PST 24
Peak memory 199676 kb
Host smart-2c1d98ff-534b-455a-ac77-564988e2a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365206560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2365206560
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2266533510
Short name T275
Test name
Test status
Simulation time 226779781171 ps
CPU time 125.47 seconds
Started Jan 25 02:41:40 AM PST 24
Finished Jan 25 02:43:47 AM PST 24
Peak memory 200012 kb
Host smart-de6ff2fa-2891-49f5-806a-fe0ef64e42ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266533510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2266533510
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1876142755
Short name T370
Test name
Test status
Simulation time 34286210852 ps
CPU time 30.25 seconds
Started Jan 25 02:41:42 AM PST 24
Finished Jan 25 02:42:14 AM PST 24
Peak memory 200148 kb
Host smart-44e2a2f4-195c-4916-9a98-609d0bbc91a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876142755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1876142755
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2073934790
Short name T100
Test name
Test status
Simulation time 14774633585 ps
CPU time 28.17 seconds
Started Jan 25 02:42:26 AM PST 24
Finished Jan 25 02:43:07 AM PST 24
Peak memory 200040 kb
Host smart-989a18ad-b7b6-420f-95f7-78f97c42d7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073934790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2073934790
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3151403291
Short name T171
Test name
Test status
Simulation time 12797637190 ps
CPU time 10.37 seconds
Started Jan 25 02:43:24 AM PST 24
Finished Jan 25 02:43:48 AM PST 24
Peak memory 199864 kb
Host smart-40de94d7-855b-4d25-9769-11cbd88efc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151403291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3151403291
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1120872907
Short name T372
Test name
Test status
Simulation time 128123321129 ps
CPU time 78.88 seconds
Started Jan 25 02:44:07 AM PST 24
Finished Jan 25 02:45:31 AM PST 24
Peak memory 199900 kb
Host smart-f0bfaca1-9645-47b5-aacc-71213f163d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120872907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1120872907
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.371076677
Short name T174
Test name
Test status
Simulation time 13175947727 ps
CPU time 10.37 seconds
Started Jan 25 02:44:19 AM PST 24
Finished Jan 25 02:44:33 AM PST 24
Peak memory 199428 kb
Host smart-ce60a5ed-f9fb-4bcf-82c6-69c5ffe6188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371076677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.371076677
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4153474221
Short name T178
Test name
Test status
Simulation time 15654879222 ps
CPU time 13.78 seconds
Started Jan 25 02:44:21 AM PST 24
Finished Jan 25 02:44:38 AM PST 24
Peak memory 199904 kb
Host smart-8162a41e-4649-4475-bf02-869aadac1c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153474221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4153474221
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3687607382
Short name T263
Test name
Test status
Simulation time 512373718032 ps
CPU time 99.1 seconds
Started Jan 25 02:15:39 AM PST 24
Finished Jan 25 02:17:20 AM PST 24
Peak memory 200076 kb
Host smart-f7360584-60e5-4c62-ae71-80328cd3d8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687607382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3687607382
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3521544492
Short name T293
Test name
Test status
Simulation time 155455194270 ps
CPU time 53.85 seconds
Started Jan 25 02:45:25 AM PST 24
Finished Jan 25 02:46:20 AM PST 24
Peak memory 199728 kb
Host smart-0f430fa0-f720-41ec-bac2-0af3e1221f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521544492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3521544492
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.744915280
Short name T280
Test name
Test status
Simulation time 521383647564 ps
CPU time 207.99 seconds
Started Jan 25 02:18:29 AM PST 24
Finished Jan 25 02:22:04 AM PST 24
Peak memory 200076 kb
Host smart-55c4e17b-6a63-4591-8531-7ff15b0f6066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744915280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.744915280
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3404992703
Short name T182
Test name
Test status
Simulation time 58086216632 ps
CPU time 13.97 seconds
Started Jan 25 02:45:30 AM PST 24
Finished Jan 25 02:45:45 AM PST 24
Peak memory 199288 kb
Host smart-a82bfdb0-16b1-4ca9-a59a-6aa4f6669728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404992703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3404992703
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3673055707
Short name T338
Test name
Test status
Simulation time 296711389517 ps
CPU time 235.03 seconds
Started Jan 25 02:45:57 AM PST 24
Finished Jan 25 02:49:54 AM PST 24
Peak memory 200068 kb
Host smart-fb091468-e745-477d-8bc2-1349ae9a1f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673055707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3673055707
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.493591843
Short name T300
Test name
Test status
Simulation time 92327379599 ps
CPU time 38.09 seconds
Started Jan 25 04:17:42 AM PST 24
Finished Jan 25 04:18:21 AM PST 24
Peak memory 200032 kb
Host smart-38eb5cba-c20e-40b1-8de2-affe72fe77ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493591843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.493591843
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2232228520
Short name T307
Test name
Test status
Simulation time 127206584848 ps
CPU time 189.55 seconds
Started Jan 25 02:46:32 AM PST 24
Finished Jan 25 02:49:46 AM PST 24
Peak memory 200028 kb
Host smart-6bd0bc55-0d62-48cd-b2c1-6920f4332c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232228520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2232228520
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2728276749
Short name T1142
Test name
Test status
Simulation time 71735442053 ps
CPU time 68.48 seconds
Started Jan 25 02:47:37 AM PST 24
Finished Jan 25 02:48:47 AM PST 24
Peak memory 199896 kb
Host smart-aad355fe-365d-4fa8-927f-d511af85d48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728276749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2728276749
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1515648097
Short name T350
Test name
Test status
Simulation time 73145401386 ps
CPU time 118.61 seconds
Started Jan 25 02:22:44 AM PST 24
Finished Jan 25 02:24:43 AM PST 24
Peak memory 200100 kb
Host smart-5816982b-4af4-4dfe-a862-cccbf2789c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515648097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1515648097
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2502418423
Short name T264
Test name
Test status
Simulation time 20565134966 ps
CPU time 39.06 seconds
Started Jan 25 02:25:56 AM PST 24
Finished Jan 25 02:26:42 AM PST 24
Peak memory 200024 kb
Host smart-fe0fa266-3cc9-427d-a980-912403cf54cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502418423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2502418423
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1537555857
Short name T388
Test name
Test status
Simulation time 42795531057 ps
CPU time 20.17 seconds
Started Jan 25 02:26:58 AM PST 24
Finished Jan 25 02:27:19 AM PST 24
Peak memory 198960 kb
Host smart-f52dc116-1512-4385-945e-a81a22906752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537555857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1537555857
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1976892861
Short name T230
Test name
Test status
Simulation time 498526177757 ps
CPU time 763.16 seconds
Started Jan 25 02:39:09 AM PST 24
Finished Jan 25 02:51:56 AM PST 24
Peak memory 225312 kb
Host smart-4ff76ce1-90f5-48fa-abf3-1d1fefda8b8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976892861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1976892861
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1258991972
Short name T268
Test name
Test status
Simulation time 189034130784 ps
CPU time 276.93 seconds
Started Jan 25 02:39:59 AM PST 24
Finished Jan 25 02:44:38 AM PST 24
Peak memory 200088 kb
Host smart-c040f3d1-f3a5-4be8-9da4-8d818b7b56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258991972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1258991972
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3695976597
Short name T458
Test name
Test status
Simulation time 43501460 ps
CPU time 0.99 seconds
Started Jan 24 11:11:36 PM PST 24
Finished Jan 24 11:11:40 PM PST 24
Peak memory 198720 kb
Host smart-7b4f64c5-690d-408d-82aa-3736828a8183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695976597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3695976597
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.4215827060
Short name T239
Test name
Test status
Simulation time 445723597046 ps
CPU time 477.21 seconds
Started Jan 25 01:57:45 AM PST 24
Finished Jan 25 02:05:43 AM PST 24
Peak memory 225288 kb
Host smart-24021d91-bffb-4ef1-9a5e-0fbc0586143a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215827060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.4215827060
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_perf.1802290073
Short name T523
Test name
Test status
Simulation time 14574593221 ps
CPU time 372.66 seconds
Started Jan 25 02:31:06 AM PST 24
Finished Jan 25 02:37:23 AM PST 24
Peak memory 200132 kb
Host smart-ee3fee09-6c12-401d-8c89-09b5ae96b605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802290073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1802290073
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4013081770
Short name T113
Test name
Test status
Simulation time 50895763543 ps
CPU time 47.98 seconds
Started Jan 25 02:40:39 AM PST 24
Finished Jan 25 02:41:34 AM PST 24
Peak memory 199664 kb
Host smart-da0b64d2-31b6-44ee-a8d3-c4e212d76aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013081770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4013081770
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1809976524
Short name T328
Test name
Test status
Simulation time 214650063770 ps
CPU time 50.44 seconds
Started Jan 25 02:41:17 AM PST 24
Finished Jan 25 02:42:08 AM PST 24
Peak memory 199668 kb
Host smart-ed6194a9-7147-495f-b336-086d818793d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809976524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1809976524
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3213451325
Short name T190
Test name
Test status
Simulation time 103576205515 ps
CPU time 95.89 seconds
Started Jan 25 03:58:03 AM PST 24
Finished Jan 25 03:59:40 AM PST 24
Peak memory 200068 kb
Host smart-d1fa64d7-200d-446e-8c19-b9e204365aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213451325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3213451325
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.760289096
Short name T130
Test name
Test status
Simulation time 49838485444 ps
CPU time 58.91 seconds
Started Jan 25 02:41:40 AM PST 24
Finished Jan 25 02:42:41 AM PST 24
Peak memory 200076 kb
Host smart-3f7e37ec-6b9e-42e9-813b-b7e060cdd534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760289096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.760289096
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.941715822
Short name T223
Test name
Test status
Simulation time 44788043024 ps
CPU time 17.41 seconds
Started Jan 25 02:41:40 AM PST 24
Finished Jan 25 02:41:59 AM PST 24
Peak memory 200052 kb
Host smart-6151473f-c2e7-47f8-854b-2043cc066b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941715822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.941715822
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2029490515
Short name T284
Test name
Test status
Simulation time 184674415155 ps
CPU time 298.91 seconds
Started Jan 25 02:41:40 AM PST 24
Finished Jan 25 02:46:41 AM PST 24
Peak memory 200120 kb
Host smart-162243ad-d334-4163-b0f7-52acc7d223ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029490515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2029490515
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2714540872
Short name T206
Test name
Test status
Simulation time 12648181547 ps
CPU time 19.84 seconds
Started Jan 25 02:12:10 AM PST 24
Finished Jan 25 02:12:35 AM PST 24
Peak memory 199996 kb
Host smart-97cdac72-b943-4499-9c4a-c548071bc0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714540872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2714540872
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2125076757
Short name T75
Test name
Test status
Simulation time 80251316616 ps
CPU time 820.91 seconds
Started Jan 25 02:12:21 AM PST 24
Finished Jan 25 02:26:03 AM PST 24
Peak memory 214420 kb
Host smart-0dc2f174-7201-4bd8-9d99-769977aa6819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125076757 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2125076757
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.148310895
Short name T318
Test name
Test status
Simulation time 45846089022 ps
CPU time 37.11 seconds
Started Jan 25 04:47:52 AM PST 24
Finished Jan 25 04:48:45 AM PST 24
Peak memory 200044 kb
Host smart-de1771e8-c349-4642-8ef9-78e13e309456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148310895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.148310895
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2425466013
Short name T215
Test name
Test status
Simulation time 181196906685 ps
CPU time 85.47 seconds
Started Jan 25 02:43:10 AM PST 24
Finished Jan 25 02:44:46 AM PST 24
Peak memory 200092 kb
Host smart-117a9fe5-3308-428a-a865-8b427162d3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425466013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2425466013
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.939426230
Short name T346
Test name
Test status
Simulation time 105007810426 ps
CPU time 29.21 seconds
Started Jan 25 02:43:10 AM PST 24
Finished Jan 25 02:43:49 AM PST 24
Peak memory 199608 kb
Host smart-b56fc98d-764c-4b2b-a42e-ff042917ab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939426230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.939426230
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.952340579
Short name T292
Test name
Test status
Simulation time 22327785807 ps
CPU time 36.83 seconds
Started Jan 25 02:13:49 AM PST 24
Finished Jan 25 02:14:27 AM PST 24
Peak memory 199900 kb
Host smart-0f15407b-1db7-4bc6-8408-3892c119ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952340579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.952340579
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3710517701
Short name T229
Test name
Test status
Simulation time 10500791415 ps
CPU time 15.74 seconds
Started Jan 25 02:44:54 AM PST 24
Finished Jan 25 02:45:10 AM PST 24
Peak memory 200076 kb
Host smart-54ca7bc3-d675-40d6-bf5f-a5ab0a666cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710517701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3710517701
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1011556125
Short name T135
Test name
Test status
Simulation time 33774953534 ps
CPU time 75.04 seconds
Started Jan 25 04:11:06 AM PST 24
Finished Jan 25 04:12:24 AM PST 24
Peak memory 200092 kb
Host smart-12e7d5ee-a293-4bc3-8664-8d06ba89aaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011556125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1011556125
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4104238251
Short name T288
Test name
Test status
Simulation time 104934286578 ps
CPU time 162.22 seconds
Started Jan 25 02:16:12 AM PST 24
Finished Jan 25 02:19:01 AM PST 24
Peak memory 199840 kb
Host smart-92e4a94b-6079-43ab-8df3-e21e29d18412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104238251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4104238251
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.1615882942
Short name T153
Test name
Test status
Simulation time 45988736235 ps
CPU time 78.58 seconds
Started Jan 25 02:18:39 AM PST 24
Finished Jan 25 02:20:02 AM PST 24
Peak memory 199140 kb
Host smart-66113bde-845b-46fc-bf47-258ab38eb3ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615882942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1615882942
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2523272591
Short name T203
Test name
Test status
Simulation time 23026617932 ps
CPU time 46.62 seconds
Started Jan 25 02:45:43 AM PST 24
Finished Jan 25 02:46:31 AM PST 24
Peak memory 200128 kb
Host smart-bebc0129-5543-4dec-abce-e5224f5528d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523272591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2523272591
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2677419201
Short name T335
Test name
Test status
Simulation time 67674874778 ps
CPU time 31.66 seconds
Started Jan 25 02:46:15 AM PST 24
Finished Jan 25 02:46:50 AM PST 24
Peak memory 198932 kb
Host smart-1db597ef-45a5-4c38-b3ad-e48d46dce476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677419201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2677419201
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_perf.153264790
Short name T297
Test name
Test status
Simulation time 15415192889 ps
CPU time 924.65 seconds
Started Jan 25 02:21:10 AM PST 24
Finished Jan 25 02:36:36 AM PST 24
Peak memory 200048 kb
Host smart-5a698edf-6b69-4b6b-a4e0-ff987ca2e10a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153264790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.153264790
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.645825101
Short name T364
Test name
Test status
Simulation time 64297959816 ps
CPU time 54.45 seconds
Started Jan 25 02:46:36 AM PST 24
Finished Jan 25 02:47:34 AM PST 24
Peak memory 200068 kb
Host smart-59d54bbf-9857-4ae2-bb61-8384ed6a3edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645825101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.645825101
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.683797658
Short name T273
Test name
Test status
Simulation time 102874502028 ps
CPU time 20.07 seconds
Started Jan 25 02:46:36 AM PST 24
Finished Jan 25 02:47:00 AM PST 24
Peak memory 199856 kb
Host smart-a3113b8f-468c-4c2b-a661-dc659f3350fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683797658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.683797658
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3210295912
Short name T242
Test name
Test status
Simulation time 118068951373 ps
CPU time 103.42 seconds
Started Jan 25 02:21:26 AM PST 24
Finished Jan 25 02:23:10 AM PST 24
Peak memory 199616 kb
Host smart-8c4e46ce-fb24-4f76-b703-e039c4eb6da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210295912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3210295912
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3683708000
Short name T177
Test name
Test status
Simulation time 82647895566 ps
CPU time 64.15 seconds
Started Jan 25 02:47:34 AM PST 24
Finished Jan 25 02:48:39 AM PST 24
Peak memory 200092 kb
Host smart-88109f4d-4d75-4727-b13c-d15446bb7c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683708000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3683708000
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2887755810
Short name T184
Test name
Test status
Simulation time 48222025021 ps
CPU time 93.68 seconds
Started Jan 25 02:26:58 AM PST 24
Finished Jan 25 02:28:33 AM PST 24
Peak memory 200016 kb
Host smart-e8235f0f-f8bb-44cb-9437-a89a0379eb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887755810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2887755810
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1802807132
Short name T243
Test name
Test status
Simulation time 32815129292 ps
CPU time 54.13 seconds
Started Jan 25 02:31:54 AM PST 24
Finished Jan 25 02:32:49 AM PST 24
Peak memory 199828 kb
Host smart-474b33f9-82cc-4ff4-a7ec-e81020c178e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802807132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1802807132
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.602586407
Short name T299
Test name
Test status
Simulation time 46720458900 ps
CPU time 21.1 seconds
Started Jan 25 02:33:17 AM PST 24
Finished Jan 25 02:33:45 AM PST 24
Peak memory 200080 kb
Host smart-51fbd551-4cef-48a2-8689-1a33af065480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602586407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.602586407
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1922568827
Short name T389
Test name
Test status
Simulation time 262119281916 ps
CPU time 105.54 seconds
Started Jan 25 02:36:29 AM PST 24
Finished Jan 25 02:38:15 AM PST 24
Peak memory 200072 kb
Host smart-6f5ae255-cc91-4b53-94f3-996f212b1000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922568827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1922568827
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3051231687
Short name T287
Test name
Test status
Simulation time 29164276674 ps
CPU time 45.64 seconds
Started Jan 25 02:36:48 AM PST 24
Finished Jan 25 02:37:35 AM PST 24
Peak memory 199612 kb
Host smart-dbe97bc4-297f-4d7d-ae94-255998133fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051231687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3051231687
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1428351027
Short name T290
Test name
Test status
Simulation time 377564234224 ps
CPU time 868.91 seconds
Started Jan 25 02:38:48 AM PST 24
Finished Jan 25 02:53:31 AM PST 24
Peak memory 216188 kb
Host smart-24bd3d61-50f1-4853-a255-c99056452cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428351027 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1428351027
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3082076120
Short name T295
Test name
Test status
Simulation time 119675461802 ps
CPU time 214.61 seconds
Started Jan 25 02:38:37 AM PST 24
Finished Jan 25 02:42:14 AM PST 24
Peak memory 200048 kb
Host smart-bcc41d0f-50e7-4700-b190-6ebec12e50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082076120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3082076120
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.707578639
Short name T326
Test name
Test status
Simulation time 17401046995 ps
CPU time 14.38 seconds
Started Jan 25 03:12:40 AM PST 24
Finished Jan 25 03:13:05 AM PST 24
Peak memory 198076 kb
Host smart-565f92eb-5d2f-4347-b365-35fffb3536de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707578639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.707578639
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1091700882
Short name T379
Test name
Test status
Simulation time 33556130244 ps
CPU time 47.73 seconds
Started Jan 25 03:57:51 AM PST 24
Finished Jan 25 03:58:40 AM PST 24
Peak memory 200048 kb
Host smart-3800a35f-a54c-44dd-b1ca-0e776d5d70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091700882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1091700882
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3179367747
Short name T355
Test name
Test status
Simulation time 92816206782 ps
CPU time 151.92 seconds
Started Jan 25 02:39:22 AM PST 24
Finished Jan 25 02:42:05 AM PST 24
Peak memory 200064 kb
Host smart-92db88b9-e13f-4fc5-9ed3-5707e21e758b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179367747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3179367747
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2337198958
Short name T369
Test name
Test status
Simulation time 150313165250 ps
CPU time 1212.2 seconds
Started Jan 25 02:39:21 AM PST 24
Finished Jan 25 02:59:39 AM PST 24
Peak memory 225948 kb
Host smart-77edcb99-c2bb-4c17-a554-218f38faf49d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337198958 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2337198958
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_perf.4104644267
Short name T298
Test name
Test status
Simulation time 6204919149 ps
CPU time 375.83 seconds
Started Jan 25 04:30:48 AM PST 24
Finished Jan 25 04:37:17 AM PST 24
Peak memory 200100 kb
Host smart-83ca0a5b-c2c2-4726-86e0-efa2dbe14a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104644267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.4104644267
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1423280646
Short name T1244
Test name
Test status
Simulation time 113124518 ps
CPU time 0.66 seconds
Started Jan 24 11:11:51 PM PST 24
Finished Jan 24 11:11:53 PM PST 24
Peak memory 194832 kb
Host smart-c67275c1-1b8b-47b2-97f8-c625c33a626c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423280646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1423280646
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1003135819
Short name T70
Test name
Test status
Simulation time 199193546 ps
CPU time 1.46 seconds
Started Jan 24 11:11:48 PM PST 24
Finished Jan 24 11:11:52 PM PST 24
Peak memory 196976 kb
Host smart-b0e4cb5b-c273-4675-b398-625a0e482194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003135819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1003135819
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.756606787
Short name T1249
Test name
Test status
Simulation time 46443415 ps
CPU time 0.6 seconds
Started Jan 24 11:11:47 PM PST 24
Finished Jan 24 11:11:50 PM PST 24
Peak memory 195392 kb
Host smart-75f85f94-599c-41ae-9d7a-d33b12cccf74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756606787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.756606787
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1018740214
Short name T459
Test name
Test status
Simulation time 13724525 ps
CPU time 0.63 seconds
Started Jan 24 11:11:50 PM PST 24
Finished Jan 24 11:11:52 PM PST 24
Peak memory 195344 kb
Host smart-eac8c4c3-d281-4ca3-a073-3c4703b3fed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018740214 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1018740214
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3475222758
Short name T1274
Test name
Test status
Simulation time 17617984 ps
CPU time 0.64 seconds
Started Jan 24 11:11:49 PM PST 24
Finished Jan 24 11:11:51 PM PST 24
Peak memory 195292 kb
Host smart-73d1270e-2ecb-4581-8c67-5852b100e8a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475222758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3475222758
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.75985869
Short name T1245
Test name
Test status
Simulation time 19894416 ps
CPU time 0.58 seconds
Started Jan 24 11:11:36 PM PST 24
Finished Jan 24 11:11:40 PM PST 24
Peak memory 194260 kb
Host smart-e1a30959-be85-4acc-8c7f-ca8f2a46501e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75985869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.75985869
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1838104664
Short name T464
Test name
Test status
Simulation time 61462851 ps
CPU time 0.79 seconds
Started Jan 24 11:11:49 PM PST 24
Finished Jan 24 11:11:52 PM PST 24
Peak memory 196832 kb
Host smart-071d82f5-7402-4bf7-9e81-3b3fdafe09e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838104664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1838104664
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3634355892
Short name T1275
Test name
Test status
Simulation time 585961391 ps
CPU time 2.82 seconds
Started Jan 25 12:25:20 AM PST 24
Finished Jan 25 12:25:24 AM PST 24
Peak memory 199900 kb
Host smart-44ac1198-6e0a-461a-9323-abfdfc9bbcf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634355892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3634355892
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.317744645
Short name T5
Test name
Test status
Simulation time 81292086 ps
CPU time 0.67 seconds
Started Jan 24 11:12:37 PM PST 24
Finished Jan 24 11:12:42 PM PST 24
Peak memory 195360 kb
Host smart-0f81e468-3ef3-4cff-8639-03cb2d96474f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317744645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.317744645
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2689285821
Short name T462
Test name
Test status
Simulation time 506010959 ps
CPU time 1.57 seconds
Started Jan 24 11:12:39 PM PST 24
Finished Jan 24 11:12:44 PM PST 24
Peak memory 197732 kb
Host smart-c4ad3372-fbc8-4646-b9ca-cb3810a95e56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689285821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2689285821
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1554577941
Short name T62
Test name
Test status
Simulation time 40224485 ps
CPU time 0.57 seconds
Started Jan 24 11:12:37 PM PST 24
Finished Jan 24 11:12:42 PM PST 24
Peak memory 195332 kb
Host smart-848f11d3-6f60-4c5c-8f44-c49f8444e135
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554577941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1554577941
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1159307839
Short name T108
Test name
Test status
Simulation time 13006836 ps
CPU time 0.63 seconds
Started Jan 24 11:12:39 PM PST 24
Finished Jan 24 11:12:43 PM PST 24
Peak memory 195800 kb
Host smart-27a18e8e-d53d-4f0d-ab38-aca960c5be21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159307839 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1159307839
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2686253233
Short name T59
Test name
Test status
Simulation time 50668384 ps
CPU time 0.59 seconds
Started Jan 24 11:12:42 PM PST 24
Finished Jan 24 11:12:45 PM PST 24
Peak memory 195372 kb
Host smart-853da727-0127-4232-b365-ddad76f952b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686253233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2686253233
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1567690348
Short name T1261
Test name
Test status
Simulation time 61120359 ps
CPU time 0.63 seconds
Started Jan 25 12:21:20 AM PST 24
Finished Jan 25 12:21:23 AM PST 24
Peak memory 185080 kb
Host smart-38e56714-9a6f-4d08-a9fd-df296a2fd0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567690348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1567690348
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1169822091
Short name T50
Test name
Test status
Simulation time 31073979 ps
CPU time 0.67 seconds
Started Jan 24 11:12:39 PM PST 24
Finished Jan 24 11:12:43 PM PST 24
Peak memory 195432 kb
Host smart-e39d7bd4-720a-443e-91d7-3309aa0c44d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169822091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1169822091
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.405251648
Short name T34
Test name
Test status
Simulation time 154898142 ps
CPU time 1.92 seconds
Started Jan 25 03:49:13 AM PST 24
Finished Jan 25 03:49:19 AM PST 24
Peak memory 199932 kb
Host smart-722d4d12-9cdc-4352-a4f2-4662221c1229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405251648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.405251648
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2840975859
Short name T1256
Test name
Test status
Simulation time 363539756 ps
CPU time 1.31 seconds
Started Jan 24 11:11:50 PM PST 24
Finished Jan 24 11:11:52 PM PST 24
Peak memory 198916 kb
Host smart-f999c961-6891-4133-837e-126ff87ced09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840975859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2840975859
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1999969549
Short name T461
Test name
Test status
Simulation time 22224313 ps
CPU time 0.7 seconds
Started Jan 24 11:13:57 PM PST 24
Finished Jan 24 11:13:58 PM PST 24
Peak memory 197512 kb
Host smart-7f81f4d8-42a1-4537-8ccc-7c4c55321706
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999969549 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1999969549
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3387097104
Short name T69
Test name
Test status
Simulation time 23162415 ps
CPU time 0.63 seconds
Started Jan 24 11:13:56 PM PST 24
Finished Jan 24 11:13:58 PM PST 24
Peak memory 195376 kb
Host smart-29bbd2c0-a846-4b08-9541-085c0dee4599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387097104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3387097104
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.746982886
Short name T1287
Test name
Test status
Simulation time 24275102 ps
CPU time 0.75 seconds
Started Jan 24 11:13:59 PM PST 24
Finished Jan 24 11:14:01 PM PST 24
Peak memory 196292 kb
Host smart-de39cfc5-725c-4f17-8ca6-b494d9b7f469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746982886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.746982886
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3843779832
Short name T53
Test name
Test status
Simulation time 96239608 ps
CPU time 1.35 seconds
Started Jan 24 11:13:55 PM PST 24
Finished Jan 24 11:13:57 PM PST 24
Peak memory 199820 kb
Host smart-4e2ea789-a8a0-4e2e-815b-e0d4559a0197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843779832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3843779832
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3853559814
Short name T1247
Test name
Test status
Simulation time 109245382 ps
CPU time 1.31 seconds
Started Jan 24 11:13:54 PM PST 24
Finished Jan 24 11:13:56 PM PST 24
Peak memory 198824 kb
Host smart-0da26f66-7ff5-4375-b12c-18c456c1b1fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853559814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3853559814
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1284008117
Short name T1250
Test name
Test status
Simulation time 56845335 ps
CPU time 0.8 seconds
Started Jan 24 11:14:21 PM PST 24
Finished Jan 24 11:14:24 PM PST 24
Peak memory 198240 kb
Host smart-b1c21c0e-2b5f-4979-bda9-134921cd8c41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284008117 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1284008117
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2444145216
Short name T71
Test name
Test status
Simulation time 35451337 ps
CPU time 0.6 seconds
Started Jan 24 11:14:30 PM PST 24
Finished Jan 24 11:14:31 PM PST 24
Peak memory 195372 kb
Host smart-df962c15-6606-4e93-8d2e-f1cf9019ad69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444145216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2444145216
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4044114951
Short name T1284
Test name
Test status
Simulation time 14380638 ps
CPU time 0.57 seconds
Started Jan 24 11:14:19 PM PST 24
Finished Jan 24 11:14:22 PM PST 24
Peak memory 185036 kb
Host smart-89f02efd-d0b8-4c28-9c0b-1bc57d0e4354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044114951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4044114951
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1139036654
Short name T1290
Test name
Test status
Simulation time 93778068 ps
CPU time 0.78 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 195916 kb
Host smart-6f03219f-c465-473e-94ac-9d1de7aa024e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139036654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1139036654
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.316287131
Short name T1266
Test name
Test status
Simulation time 271037374 ps
CPU time 2.1 seconds
Started Jan 24 11:14:01 PM PST 24
Finished Jan 24 11:14:04 PM PST 24
Peak memory 199908 kb
Host smart-9e7ebfd9-82e7-4947-9a35-ddf6fbd63555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316287131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.316287131
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2489583252
Short name T52
Test name
Test status
Simulation time 329014666 ps
CPU time 1.38 seconds
Started Jan 24 11:14:21 PM PST 24
Finished Jan 24 11:14:24 PM PST 24
Peak memory 199004 kb
Host smart-d4814ac7-fe45-4002-aaed-f8d4db1efe95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489583252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2489583252
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1587198799
Short name T54
Test name
Test status
Simulation time 97116083 ps
CPU time 0.94 seconds
Started Jan 24 11:14:22 PM PST 24
Finished Jan 24 11:14:24 PM PST 24
Peak memory 199732 kb
Host smart-a6cf0f3c-cde6-4ff3-a933-346dbe16c836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587198799 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1587198799
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.324482581
Short name T72
Test name
Test status
Simulation time 11964692 ps
CPU time 0.61 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 195356 kb
Host smart-2868e1f4-70d9-4e7a-a0f3-332487209557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324482581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.324482581
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3730600484
Short name T1292
Test name
Test status
Simulation time 65144163 ps
CPU time 0.66 seconds
Started Jan 24 11:14:23 PM PST 24
Finished Jan 24 11:14:25 PM PST 24
Peak memory 195696 kb
Host smart-987a6f5b-3c6a-4126-bd19-62c24099d2a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730600484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3730600484
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1987596087
Short name T1279
Test name
Test status
Simulation time 23556099 ps
CPU time 1.13 seconds
Started Jan 24 11:14:30 PM PST 24
Finished Jan 24 11:14:32 PM PST 24
Peak memory 199776 kb
Host smart-3c65ca52-9b0f-4b03-9122-5a1009299ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987596087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1987596087
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3462289054
Short name T1238
Test name
Test status
Simulation time 339018331 ps
CPU time 1.48 seconds
Started Jan 24 11:14:21 PM PST 24
Finished Jan 24 11:14:24 PM PST 24
Peak memory 199096 kb
Host smart-71695c24-b06c-4bc1-acee-7fa7acaa8ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462289054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3462289054
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.41332541
Short name T1278
Test name
Test status
Simulation time 33061883 ps
CPU time 0.89 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 199124 kb
Host smart-8d4708bc-1158-47a8-ae1d-b3b3d6a8c50a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41332541 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.41332541
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.545071905
Short name T479
Test name
Test status
Simulation time 40895613 ps
CPU time 0.6 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 195356 kb
Host smart-02ecba48-f779-4f00-b464-87202f8d9db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545071905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.545071905
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1756467336
Short name T1257
Test name
Test status
Simulation time 14853934 ps
CPU time 0.63 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 185060 kb
Host smart-f3f8c2d4-39e8-4d91-81a0-14b6cb49ea24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756467336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1756467336
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3740909541
Short name T455
Test name
Test status
Simulation time 18832959 ps
CPU time 0.79 seconds
Started Jan 24 11:14:22 PM PST 24
Finished Jan 24 11:14:24 PM PST 24
Peak memory 195864 kb
Host smart-20c357a6-ea3c-4b91-b9fb-553aaf3d3ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740909541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3740909541
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3691182936
Short name T465
Test name
Test status
Simulation time 312730941 ps
CPU time 1.39 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:27 PM PST 24
Peak memory 199848 kb
Host smart-9b95e9a6-9fad-48a9-8b36-f9b57f364ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691182936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3691182936
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3322396772
Short name T93
Test name
Test status
Simulation time 97338573 ps
CPU time 0.94 seconds
Started Jan 24 11:14:30 PM PST 24
Finished Jan 24 11:14:32 PM PST 24
Peak memory 198464 kb
Host smart-7e53fae3-caf2-454a-b1b5-4565661600ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322396772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3322396772
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4079940247
Short name T1243
Test name
Test status
Simulation time 24300874 ps
CPU time 0.89 seconds
Started Jan 24 11:14:30 PM PST 24
Finished Jan 24 11:14:32 PM PST 24
Peak memory 199760 kb
Host smart-1f1ea7c3-b5c1-4d6a-b9fd-d2715d10ba16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079940247 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4079940247
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3089594873
Short name T1270
Test name
Test status
Simulation time 102442429 ps
CPU time 0.63 seconds
Started Jan 24 11:14:23 PM PST 24
Finished Jan 24 11:14:25 PM PST 24
Peak memory 195348 kb
Host smart-68f44453-cef0-4275-b988-293873173d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089594873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3089594873
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1341506978
Short name T57
Test name
Test status
Simulation time 45734155 ps
CPU time 0.58 seconds
Started Jan 24 11:14:24 PM PST 24
Finished Jan 24 11:14:26 PM PST 24
Peak memory 185072 kb
Host smart-2fe3fb54-02de-470c-80c8-630cf00a2b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341506978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1341506978
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1359294751
Short name T79
Test name
Test status
Simulation time 24047150 ps
CPU time 0.71 seconds
Started Jan 24 11:14:30 PM PST 24
Finished Jan 24 11:14:31 PM PST 24
Peak memory 197460 kb
Host smart-fd5fdb4e-b3e0-4796-9bc2-33586e50434c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359294751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1359294751
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.544040376
Short name T1239
Test name
Test status
Simulation time 63376085 ps
CPU time 1.47 seconds
Started Jan 24 11:14:20 PM PST 24
Finished Jan 24 11:14:23 PM PST 24
Peak memory 199888 kb
Host smart-94e2fdd5-89bf-44a8-b8c0-94564c35aecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544040376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.544040376
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3364770980
Short name T44
Test name
Test status
Simulation time 33903795 ps
CPU time 0.89 seconds
Started Jan 24 11:14:44 PM PST 24
Finished Jan 24 11:14:47 PM PST 24
Peak memory 199748 kb
Host smart-c8f0f2d6-54ed-4502-9008-e049ed12ce39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364770980 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3364770980
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3185352373
Short name T1248
Test name
Test status
Simulation time 47876868 ps
CPU time 0.59 seconds
Started Jan 24 11:14:47 PM PST 24
Finished Jan 24 11:14:50 PM PST 24
Peak memory 195320 kb
Host smart-c621a7cb-fc61-4219-a355-fcb94b44e145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185352373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3185352373
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3647548812
Short name T1237
Test name
Test status
Simulation time 52219739 ps
CPU time 0.58 seconds
Started Jan 24 11:14:57 PM PST 24
Finished Jan 24 11:14:58 PM PST 24
Peak memory 194284 kb
Host smart-4a600b80-5fc2-4a0b-986c-c7b64e7fdd4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647548812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3647548812
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1011864952
Short name T474
Test name
Test status
Simulation time 137573600 ps
CPU time 0.76 seconds
Started Jan 24 11:14:47 PM PST 24
Finished Jan 24 11:14:51 PM PST 24
Peak memory 195928 kb
Host smart-50243156-5304-4acc-b581-a3f4de8b7f30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011864952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1011864952
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.8379087
Short name T467
Test name
Test status
Simulation time 397292672 ps
CPU time 1.94 seconds
Started Jan 24 11:14:30 PM PST 24
Finished Jan 24 11:14:33 PM PST 24
Peak memory 199852 kb
Host smart-77f49e6d-bc14-473a-b4ca-c4a900ea0d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8379087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.8379087
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3363006923
Short name T43
Test name
Test status
Simulation time 278625892 ps
CPU time 0.94 seconds
Started Jan 24 11:14:41 PM PST 24
Finished Jan 24 11:14:47 PM PST 24
Peak memory 198516 kb
Host smart-3a5c3383-3ffa-4370-8162-616b4dcf6e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363006923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3363006923
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2184887656
Short name T457
Test name
Test status
Simulation time 161288529 ps
CPU time 1.12 seconds
Started Jan 24 11:15:49 PM PST 24
Finished Jan 24 11:15:52 PM PST 24
Peak memory 199868 kb
Host smart-42029b4a-e54a-44fd-b5d1-27e4cc4f180b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184887656 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2184887656
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2508067847
Short name T1267
Test name
Test status
Simulation time 13861846 ps
CPU time 0.59 seconds
Started Jan 24 11:15:50 PM PST 24
Finished Jan 24 11:15:55 PM PST 24
Peak memory 195400 kb
Host smart-7c39215e-aa5f-4105-98dc-2f712adf2475
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508067847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2508067847
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1391710183
Short name T451
Test name
Test status
Simulation time 35666742 ps
CPU time 0.58 seconds
Started Jan 24 11:15:49 PM PST 24
Finished Jan 24 11:15:53 PM PST 24
Peak memory 185032 kb
Host smart-0a8139f3-cb12-4549-931a-be3c532b1229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391710183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1391710183
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1218065232
Short name T1265
Test name
Test status
Simulation time 26320050 ps
CPU time 0.68 seconds
Started Jan 24 11:15:49 PM PST 24
Finished Jan 24 11:15:53 PM PST 24
Peak memory 195428 kb
Host smart-f65c5c82-fa8d-4db0-845d-ae9d3899c333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218065232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1218065232
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2135845873
Short name T1242
Test name
Test status
Simulation time 301526785 ps
CPU time 1.6 seconds
Started Jan 24 11:14:41 PM PST 24
Finished Jan 24 11:14:47 PM PST 24
Peak memory 199836 kb
Host smart-be910b4b-567b-4cde-92b4-c75175a5ddb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135845873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2135845873
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.852815238
Short name T1282
Test name
Test status
Simulation time 76470903 ps
CPU time 1.28 seconds
Started Jan 24 11:15:47 PM PST 24
Finished Jan 24 11:15:49 PM PST 24
Peak memory 198956 kb
Host smart-87eb73eb-f395-4801-aec0-0acb8a4720ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852815238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.852815238
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.895110195
Short name T1264
Test name
Test status
Simulation time 20234725 ps
CPU time 0.99 seconds
Started Jan 24 11:15:46 PM PST 24
Finished Jan 24 11:15:48 PM PST 24
Peak memory 199748 kb
Host smart-aa64490a-ba74-408f-bcd8-94735ac74ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895110195 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.895110195
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3395199522
Short name T66
Test name
Test status
Simulation time 42317263 ps
CPU time 0.64 seconds
Started Jan 24 11:15:46 PM PST 24
Finished Jan 24 11:15:48 PM PST 24
Peak memory 195376 kb
Host smart-bd913639-469a-42e9-977a-05e48886077d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395199522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3395199522
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.132298760
Short name T1280
Test name
Test status
Simulation time 45199323 ps
CPU time 0.56 seconds
Started Jan 24 11:15:48 PM PST 24
Finished Jan 24 11:15:50 PM PST 24
Peak memory 194260 kb
Host smart-1defe49a-2ccd-47aa-8e19-6e93400579b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132298760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.132298760
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2517128219
Short name T1240
Test name
Test status
Simulation time 64912077 ps
CPU time 0.62 seconds
Started Jan 24 11:15:48 PM PST 24
Finished Jan 24 11:15:50 PM PST 24
Peak memory 195388 kb
Host smart-49282ce4-c036-4fbd-b702-1c94b95cf0f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517128219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2517128219
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3668582837
Short name T1255
Test name
Test status
Simulation time 364180959 ps
CPU time 1.25 seconds
Started Jan 24 11:15:47 PM PST 24
Finished Jan 24 11:15:50 PM PST 24
Peak memory 199896 kb
Host smart-7a8a3bea-95d5-43d6-abd9-6ec9b92bc23a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668582837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3668582837
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4067914854
Short name T1283
Test name
Test status
Simulation time 342196909 ps
CPU time 1.41 seconds
Started Jan 24 11:15:54 PM PST 24
Finished Jan 24 11:15:58 PM PST 24
Peak memory 198932 kb
Host smart-aee8b140-03aa-4a5b-93fc-d30559345ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067914854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4067914854
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3197104010
Short name T3
Test name
Test status
Simulation time 22132069 ps
CPU time 0.73 seconds
Started Jan 24 11:15:50 PM PST 24
Finished Jan 24 11:15:55 PM PST 24
Peak memory 196768 kb
Host smart-ad058d2f-2da1-4b64-bf51-4259dfc8b1b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197104010 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3197104010
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1805760350
Short name T1234
Test name
Test status
Simulation time 15829115 ps
CPU time 0.58 seconds
Started Jan 24 11:15:48 PM PST 24
Finished Jan 24 11:15:51 PM PST 24
Peak memory 195360 kb
Host smart-07b0ca01-c501-4679-8cf6-e79024a3a735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805760350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1805760350
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1915661385
Short name T482
Test name
Test status
Simulation time 21018414 ps
CPU time 0.64 seconds
Started Jan 24 11:15:44 PM PST 24
Finished Jan 24 11:15:46 PM PST 24
Peak memory 185032 kb
Host smart-71548ba0-ef95-40a5-a18e-4bd5ab35734b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915661385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1915661385
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.551071316
Short name T1285
Test name
Test status
Simulation time 381549735 ps
CPU time 2.19 seconds
Started Jan 24 11:15:49 PM PST 24
Finished Jan 24 11:15:54 PM PST 24
Peak memory 199848 kb
Host smart-27d18193-5f94-4ab6-b1e9-5252cb19bfed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551071316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.551071316
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1622204364
Short name T91
Test name
Test status
Simulation time 52942148 ps
CPU time 1.01 seconds
Started Jan 24 11:15:50 PM PST 24
Finished Jan 24 11:15:55 PM PST 24
Peak memory 198668 kb
Host smart-6f8f0def-45ee-4bf2-af41-8ae7b099996c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622204364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1622204364
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4252191039
Short name T396
Test name
Test status
Simulation time 19495676 ps
CPU time 0.69 seconds
Started Jan 24 11:15:53 PM PST 24
Finished Jan 24 11:15:56 PM PST 24
Peak memory 196632 kb
Host smart-b16710e0-2e33-402a-8b30-5dbe8cbaffcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252191039 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4252191039
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1271128412
Short name T78
Test name
Test status
Simulation time 154917328 ps
CPU time 0.6 seconds
Started Jan 25 03:01:05 AM PST 24
Finished Jan 25 03:01:17 AM PST 24
Peak memory 195380 kb
Host smart-99df7bf9-e5ba-44dc-98f7-87ab19c42b46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271128412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1271128412
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2860060260
Short name T1235
Test name
Test status
Simulation time 64253751 ps
CPU time 0.56 seconds
Started Jan 24 11:15:49 PM PST 24
Finished Jan 24 11:15:53 PM PST 24
Peak memory 194256 kb
Host smart-43684563-e7fc-492d-a123-f5213906e021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860060260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2860060260
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1779658994
Short name T6
Test name
Test status
Simulation time 14169916 ps
CPU time 0.63 seconds
Started Jan 24 11:15:53 PM PST 24
Finished Jan 24 11:15:57 PM PST 24
Peak memory 195388 kb
Host smart-7ce64007-e554-407e-9c4d-edcd547557d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779658994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1779658994
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3369035383
Short name T1241
Test name
Test status
Simulation time 31575090 ps
CPU time 1.54 seconds
Started Jan 24 11:15:49 PM PST 24
Finished Jan 24 11:15:55 PM PST 24
Peak memory 199872 kb
Host smart-130ec835-8175-47bd-b346-79f859db9ca5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369035383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3369035383
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.97607180
Short name T470
Test name
Test status
Simulation time 188353750 ps
CPU time 1.3 seconds
Started Jan 24 11:15:49 PM PST 24
Finished Jan 24 11:15:54 PM PST 24
Peak memory 198776 kb
Host smart-6dc1f2d8-6e6f-442a-a98a-2ae69878aee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97607180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.97607180
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.260520116
Short name T73
Test name
Test status
Simulation time 21501258 ps
CPU time 0.67 seconds
Started Jan 24 11:12:41 PM PST 24
Finished Jan 24 11:12:45 PM PST 24
Peak memory 194580 kb
Host smart-5bd13925-03ff-4c09-bf04-5922bda3759a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260520116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.260520116
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2128436500
Short name T1294
Test name
Test status
Simulation time 4970008663 ps
CPU time 2.59 seconds
Started Jan 24 11:12:41 PM PST 24
Finished Jan 24 11:12:47 PM PST 24
Peak memory 197860 kb
Host smart-dbb7e5af-f103-4ca8-b203-80e0481c649a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128436500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2128436500
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2728752183
Short name T35
Test name
Test status
Simulation time 59131618 ps
CPU time 0.62 seconds
Started Jan 24 11:12:38 PM PST 24
Finished Jan 24 11:12:43 PM PST 24
Peak memory 195360 kb
Host smart-181a746b-a467-456a-9fbb-fd8bc84f5fa4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728752183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2728752183
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2979581159
Short name T38
Test name
Test status
Simulation time 25812122 ps
CPU time 1.35 seconds
Started Jan 24 11:12:37 PM PST 24
Finished Jan 24 11:12:43 PM PST 24
Peak memory 199844 kb
Host smart-ecaabbb9-2a15-41fc-a074-ebbf8d0610fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979581159 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2979581159
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2023623533
Short name T9
Test name
Test status
Simulation time 37266666 ps
CPU time 0.63 seconds
Started Jan 24 11:12:35 PM PST 24
Finished Jan 24 11:12:40 PM PST 24
Peak memory 195348 kb
Host smart-6d5ca8ab-6323-4413-be7d-d07079fbcdea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023623533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2023623533
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3628311232
Short name T1263
Test name
Test status
Simulation time 34635529 ps
CPU time 0.58 seconds
Started Jan 24 11:12:38 PM PST 24
Finished Jan 24 11:12:43 PM PST 24
Peak memory 185012 kb
Host smart-8430836e-82ac-4158-aeee-a7236c8c0b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628311232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3628311232
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2483088707
Short name T80
Test name
Test status
Simulation time 19284591 ps
CPU time 0.66 seconds
Started Jan 24 11:12:41 PM PST 24
Finished Jan 24 11:12:45 PM PST 24
Peak memory 195740 kb
Host smart-8af94710-b1aa-4f44-8111-86d1a2dba330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483088707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2483088707
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2362769858
Short name T469
Test name
Test status
Simulation time 97901626 ps
CPU time 2.07 seconds
Started Jan 24 11:12:38 PM PST 24
Finished Jan 24 11:12:44 PM PST 24
Peak memory 199936 kb
Host smart-a609a5c7-4c5a-4489-b6a6-4a534e9aff36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362769858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2362769858
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2454483434
Short name T481
Test name
Test status
Simulation time 122619597 ps
CPU time 1.35 seconds
Started Jan 24 11:12:38 PM PST 24
Finished Jan 24 11:12:44 PM PST 24
Peak memory 198868 kb
Host smart-490877fd-bdb7-4779-b305-bfe161ae6790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454483434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2454483434
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2266821631
Short name T463
Test name
Test status
Simulation time 16803830 ps
CPU time 0.56 seconds
Started Jan 24 11:30:08 PM PST 24
Finished Jan 24 11:30:15 PM PST 24
Peak memory 185044 kb
Host smart-2672243f-f7c5-429d-8696-dec463202edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266821631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2266821631
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4030736089
Short name T480
Test name
Test status
Simulation time 46436654 ps
CPU time 0.57 seconds
Started Jan 24 11:33:15 PM PST 24
Finished Jan 24 11:33:26 PM PST 24
Peak memory 185040 kb
Host smart-71a9bca7-f067-44c2-8ad8-f09d5231fed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030736089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4030736089
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.125007680
Short name T1288
Test name
Test status
Simulation time 98715198 ps
CPU time 0.56 seconds
Started Jan 24 11:15:53 PM PST 24
Finished Jan 24 11:15:57 PM PST 24
Peak memory 185080 kb
Host smart-192c04b4-dc17-424a-8948-263c1c8cbd35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125007680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.125007680
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3612400874
Short name T1253
Test name
Test status
Simulation time 18509829 ps
CPU time 0.57 seconds
Started Jan 24 11:15:48 PM PST 24
Finished Jan 24 11:15:50 PM PST 24
Peak memory 185068 kb
Host smart-e1c8c921-46e9-4335-972a-18da8380fcae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612400874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3612400874
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.889949752
Short name T1259
Test name
Test status
Simulation time 12840927 ps
CPU time 0.57 seconds
Started Jan 24 11:15:53 PM PST 24
Finished Jan 24 11:15:56 PM PST 24
Peak memory 185080 kb
Host smart-39ade8c9-bb21-4c5f-96ce-8b8d3639e0ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889949752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.889949752
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2476035943
Short name T45
Test name
Test status
Simulation time 39765079 ps
CPU time 0.6 seconds
Started Jan 24 11:15:53 PM PST 24
Finished Jan 24 11:15:56 PM PST 24
Peak memory 185080 kb
Host smart-564bdfae-f3ef-48f0-8d1f-48c1d654a00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476035943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2476035943
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2701825973
Short name T472
Test name
Test status
Simulation time 49486767 ps
CPU time 0.56 seconds
Started Jan 24 11:35:30 PM PST 24
Finished Jan 24 11:35:33 PM PST 24
Peak memory 185040 kb
Host smart-0528db60-f118-4d58-bcec-c5b38e625a46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701825973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2701825973
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3951765501
Short name T483
Test name
Test status
Simulation time 22764698 ps
CPU time 0.63 seconds
Started Jan 24 11:15:54 PM PST 24
Finished Jan 24 11:15:57 PM PST 24
Peak memory 194284 kb
Host smart-591ac737-044d-4899-87ed-acc1d503e5eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951765501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3951765501
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.4113136192
Short name T7
Test name
Test status
Simulation time 13638712 ps
CPU time 0.61 seconds
Started Jan 24 11:15:48 PM PST 24
Finished Jan 24 11:15:52 PM PST 24
Peak memory 185000 kb
Host smart-1811113e-971e-493a-909b-a1fcd06f8b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113136192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4113136192
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3171017349
Short name T1269
Test name
Test status
Simulation time 50400998 ps
CPU time 0.6 seconds
Started Jan 25 01:19:22 AM PST 24
Finished Jan 25 01:19:23 AM PST 24
Peak memory 185040 kb
Host smart-5c221d7c-0bb2-40f0-ab64-82dbbad16853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171017349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3171017349
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2777687202
Short name T58
Test name
Test status
Simulation time 47151206 ps
CPU time 0.8 seconds
Started Jan 25 02:51:45 AM PST 24
Finished Jan 25 02:51:47 AM PST 24
Peak memory 195988 kb
Host smart-83120b9a-0528-4b58-9eaf-f927f24b09f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777687202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2777687202
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.665851749
Short name T81
Test name
Test status
Simulation time 67293742 ps
CPU time 1.6 seconds
Started Jan 24 11:55:30 PM PST 24
Finished Jan 24 11:55:33 PM PST 24
Peak memory 197100 kb
Host smart-250d8693-ecff-49fe-a911-d6b0d723b4c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665851749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.665851749
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.710694590
Short name T37
Test name
Test status
Simulation time 41381737 ps
CPU time 0.58 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 195348 kb
Host smart-1390b3f4-2880-4a6e-a538-f893cc1ea815
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710694590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.710694590
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2136157321
Short name T477
Test name
Test status
Simulation time 29839469 ps
CPU time 0.66 seconds
Started Jan 24 11:13:05 PM PST 24
Finished Jan 24 11:13:07 PM PST 24
Peak memory 196616 kb
Host smart-262d446a-1d23-480d-800c-806a4429ed87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136157321 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2136157321
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.859190551
Short name T65
Test name
Test status
Simulation time 17787763 ps
CPU time 0.64 seconds
Started Jan 24 11:13:05 PM PST 24
Finished Jan 24 11:13:07 PM PST 24
Peak memory 195372 kb
Host smart-37f73e32-4cf2-41bb-b3af-27b454636b5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859190551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.859190551
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1777648661
Short name T2
Test name
Test status
Simulation time 55781642 ps
CPU time 0.61 seconds
Started Jan 24 11:12:58 PM PST 24
Finished Jan 24 11:13:00 PM PST 24
Peak memory 194228 kb
Host smart-432b8b81-4e5e-4524-9889-79cc1dc1fb31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777648661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1777648661
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.344258130
Short name T67
Test name
Test status
Simulation time 22827414 ps
CPU time 0.67 seconds
Started Jan 24 11:57:45 PM PST 24
Finished Jan 24 11:57:47 PM PST 24
Peak memory 195424 kb
Host smart-dc5c0819-0ac0-42ed-902b-58cfa34204df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344258130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.344258130
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2436950576
Short name T32
Test name
Test status
Simulation time 2054768825 ps
CPU time 2.11 seconds
Started Jan 24 11:12:59 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 199884 kb
Host smart-7edf6987-4c91-4ccd-81de-e1fbd427f201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436950576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2436950576
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.162195396
Short name T92
Test name
Test status
Simulation time 81240941 ps
CPU time 0.91 seconds
Started Jan 24 11:12:59 PM PST 24
Finished Jan 24 11:13:01 PM PST 24
Peak memory 198640 kb
Host smart-318f9636-2081-4c0f-9e32-d21f6776b47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162195396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.162195396
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2114712257
Short name T56
Test name
Test status
Simulation time 12938556 ps
CPU time 0.56 seconds
Started Jan 24 11:16:12 PM PST 24
Finished Jan 24 11:16:13 PM PST 24
Peak memory 185000 kb
Host smart-b0e9ebb2-2f5a-4d4a-8888-271497fd9ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114712257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2114712257
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.365834199
Short name T1268
Test name
Test status
Simulation time 11526708 ps
CPU time 0.57 seconds
Started Jan 25 12:00:31 AM PST 24
Finished Jan 25 12:00:34 AM PST 24
Peak memory 185060 kb
Host smart-beb9def6-98ac-40e1-bc7e-76c78d13d8a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365834199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.365834199
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3928547739
Short name T1260
Test name
Test status
Simulation time 30083674 ps
CPU time 0.6 seconds
Started Jan 24 11:16:05 PM PST 24
Finished Jan 24 11:16:07 PM PST 24
Peak memory 185044 kb
Host smart-1a1a669b-a150-4d81-9c60-34fc6884c13f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928547739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3928547739
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3467681634
Short name T49
Test name
Test status
Simulation time 44298094 ps
CPU time 0.56 seconds
Started Jan 24 11:16:12 PM PST 24
Finished Jan 24 11:16:14 PM PST 24
Peak memory 194224 kb
Host smart-a7426805-b6f4-4650-b926-acbde14c12c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467681634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3467681634
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1206222824
Short name T453
Test name
Test status
Simulation time 42987622 ps
CPU time 0.61 seconds
Started Jan 24 11:16:02 PM PST 24
Finished Jan 24 11:16:05 PM PST 24
Peak memory 185036 kb
Host smart-3387f163-3147-4a09-936a-e3b6fb216b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206222824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1206222824
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.4018965104
Short name T1295
Test name
Test status
Simulation time 22627757 ps
CPU time 0.58 seconds
Started Jan 24 11:16:05 PM PST 24
Finished Jan 24 11:16:07 PM PST 24
Peak memory 185020 kb
Host smart-2aed0430-2a7f-45b5-ba3d-2fb55c66ed76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018965104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.4018965104
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2573543281
Short name T109
Test name
Test status
Simulation time 50574276 ps
CPU time 0.58 seconds
Started Jan 24 11:16:07 PM PST 24
Finished Jan 24 11:16:09 PM PST 24
Peak memory 185056 kb
Host smart-7281b5c7-adca-4e59-92ce-204f3f0ec57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573543281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2573543281
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3551656109
Short name T10
Test name
Test status
Simulation time 29293519 ps
CPU time 0.58 seconds
Started Jan 24 11:16:12 PM PST 24
Finished Jan 24 11:16:15 PM PST 24
Peak memory 185000 kb
Host smart-8042d71d-e2b5-4ec3-9213-72dc12ce5e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551656109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3551656109
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.580785850
Short name T456
Test name
Test status
Simulation time 13198267 ps
CPU time 0.57 seconds
Started Jan 24 11:16:12 PM PST 24
Finished Jan 24 11:16:13 PM PST 24
Peak memory 185004 kb
Host smart-71801de6-a614-490f-81af-7deb39e36751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580785850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.580785850
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3666924412
Short name T63
Test name
Test status
Simulation time 58717126 ps
CPU time 0.78 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 196136 kb
Host smart-0f0bb96a-a2fe-460b-a8ab-eaceea7d91c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666924412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3666924412
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1473834243
Short name T397
Test name
Test status
Simulation time 174533418 ps
CPU time 2.51 seconds
Started Jan 24 11:13:05 PM PST 24
Finished Jan 24 11:13:09 PM PST 24
Peak memory 197560 kb
Host smart-773cc54b-3c6e-4338-828b-c96588ad5f78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473834243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1473834243
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2067765730
Short name T36
Test name
Test status
Simulation time 27657759 ps
CPU time 0.62 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 195348 kb
Host smart-5c7477c7-8a98-4b3b-a6b7-9d4b2abf5dfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067765730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2067765730
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2726772001
Short name T468
Test name
Test status
Simulation time 70771005 ps
CPU time 0.73 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 197196 kb
Host smart-a12cc44f-dff4-4bf9-af6a-651882b67606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726772001 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2726772001
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1211071935
Short name T1277
Test name
Test status
Simulation time 50097937 ps
CPU time 0.59 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 194248 kb
Host smart-f5217cc8-b4c1-4cb7-932c-de5f93bfa6f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211071935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1211071935
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2649685703
Short name T1289
Test name
Test status
Simulation time 13686181 ps
CPU time 0.7 seconds
Started Jan 25 12:49:34 AM PST 24
Finished Jan 25 12:49:36 AM PST 24
Peak memory 195628 kb
Host smart-e85ff6e2-7435-4275-abbc-b73b47205c79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649685703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2649685703
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1425688043
Short name T40
Test name
Test status
Simulation time 176339700 ps
CPU time 1.29 seconds
Started Jan 24 11:12:59 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 198796 kb
Host smart-2d81bef8-3156-4d5a-835b-a81610439ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425688043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1425688043
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2466297401
Short name T1246
Test name
Test status
Simulation time 11268694 ps
CPU time 0.65 seconds
Started Jan 24 11:16:06 PM PST 24
Finished Jan 24 11:16:08 PM PST 24
Peak memory 185044 kb
Host smart-4f2bdfa2-d147-42fc-996a-bf1eb9c6cb8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466297401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2466297401
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1688239690
Short name T55
Test name
Test status
Simulation time 32305107 ps
CPU time 0.6 seconds
Started Jan 24 11:16:06 PM PST 24
Finished Jan 24 11:16:08 PM PST 24
Peak memory 185068 kb
Host smart-83f240a7-a6ca-4fdb-b132-11e4d0a2cb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688239690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1688239690
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.821045312
Short name T1
Test name
Test status
Simulation time 17140686 ps
CPU time 0.59 seconds
Started Jan 24 11:16:13 PM PST 24
Finished Jan 24 11:16:15 PM PST 24
Peak memory 194228 kb
Host smart-613e1dd7-8aa5-4ed5-9303-f974e517076c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821045312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.821045312
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.78958625
Short name T1236
Test name
Test status
Simulation time 16242688 ps
CPU time 0.55 seconds
Started Jan 24 11:37:53 PM PST 24
Finished Jan 24 11:37:56 PM PST 24
Peak memory 185076 kb
Host smart-9da39a1d-0115-4f53-9100-ec81b481078c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78958625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.78958625
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.4131504275
Short name T449
Test name
Test status
Simulation time 90603360 ps
CPU time 0.58 seconds
Started Jan 25 02:46:50 AM PST 24
Finished Jan 25 02:47:00 AM PST 24
Peak memory 185064 kb
Host smart-f709ed0c-0cc5-4fb1-9bad-bcfc1e32ff64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131504275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.4131504275
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2399187176
Short name T460
Test name
Test status
Simulation time 18152050 ps
CPU time 0.58 seconds
Started Jan 24 11:16:23 PM PST 24
Finished Jan 24 11:16:26 PM PST 24
Peak memory 185068 kb
Host smart-8dee5ba9-ec70-4392-a0d1-c5666e6c77df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399187176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2399187176
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3511199386
Short name T1254
Test name
Test status
Simulation time 14764036 ps
CPU time 0.57 seconds
Started Jan 24 11:16:23 PM PST 24
Finished Jan 24 11:16:26 PM PST 24
Peak memory 194196 kb
Host smart-00ef8f7c-a7ab-4f0f-b098-fe6675ffd992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511199386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3511199386
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.610869661
Short name T466
Test name
Test status
Simulation time 38019669 ps
CPU time 0.63 seconds
Started Jan 24 11:16:24 PM PST 24
Finished Jan 24 11:16:26 PM PST 24
Peak memory 185068 kb
Host smart-9de99824-9204-4c58-9e3f-a4bd363fd852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610869661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.610869661
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4132486762
Short name T1281
Test name
Test status
Simulation time 14955653 ps
CPU time 0.58 seconds
Started Jan 24 11:16:24 PM PST 24
Finished Jan 24 11:16:26 PM PST 24
Peak memory 184972 kb
Host smart-ad67bfbc-c6a5-445f-81d2-f1251539c222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132486762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4132486762
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1230273568
Short name T68
Test name
Test status
Simulation time 39871235 ps
CPU time 0.55 seconds
Started Jan 24 11:16:18 PM PST 24
Finished Jan 24 11:16:21 PM PST 24
Peak memory 185060 kb
Host smart-2d037a1c-fe69-414b-a76c-0edbe0f809b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230273568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1230273568
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2858141766
Short name T1276
Test name
Test status
Simulation time 64308818 ps
CPU time 0.95 seconds
Started Jan 25 06:35:58 AM PST 24
Finished Jan 25 06:36:01 AM PST 24
Peak memory 199824 kb
Host smart-acd26ed3-882f-4d3b-957b-d40112bf4ee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858141766 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2858141766
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3845016272
Short name T74
Test name
Test status
Simulation time 65024396 ps
CPU time 0.6 seconds
Started Jan 25 01:57:57 AM PST 24
Finished Jan 25 01:57:58 AM PST 24
Peak memory 195388 kb
Host smart-fd7333c9-a3d2-4823-a21a-5f4ed5c50496
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845016272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3845016272
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3536720397
Short name T478
Test name
Test status
Simulation time 36756914 ps
CPU time 0.58 seconds
Started Jan 25 12:13:30 AM PST 24
Finished Jan 25 12:13:32 AM PST 24
Peak memory 185076 kb
Host smart-e418f1c3-949f-484c-a7af-e35057549151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536720397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3536720397
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2121500214
Short name T1262
Test name
Test status
Simulation time 114292747 ps
CPU time 0.77 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 196824 kb
Host smart-1fa73f27-27a9-41c2-a3fe-7023bf6d773c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121500214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2121500214
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.84175752
Short name T476
Test name
Test status
Simulation time 157971925 ps
CPU time 2.14 seconds
Started Jan 24 11:13:05 PM PST 24
Finished Jan 24 11:13:08 PM PST 24
Peak memory 199928 kb
Host smart-4a4c26c4-302c-42ff-a841-d40cf653af63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84175752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.84175752
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2772576257
Short name T1252
Test name
Test status
Simulation time 845674050 ps
CPU time 1.22 seconds
Started Jan 24 11:34:33 PM PST 24
Finished Jan 24 11:34:36 PM PST 24
Peak memory 198896 kb
Host smart-476922f3-f5cf-4a66-91ee-a2b0907d3a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772576257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2772576257
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.272625258
Short name T1296
Test name
Test status
Simulation time 23307430 ps
CPU time 0.67 seconds
Started Jan 24 11:13:24 PM PST 24
Finished Jan 24 11:13:27 PM PST 24
Peak memory 197612 kb
Host smart-b5666814-f738-4176-8d2a-37e0f92b01aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272625258 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.272625258
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.880021295
Short name T64
Test name
Test status
Simulation time 33144878 ps
CPU time 0.6 seconds
Started Jan 24 11:13:26 PM PST 24
Finished Jan 24 11:13:29 PM PST 24
Peak memory 195332 kb
Host smart-ef61a310-555c-4b74-b3c1-5bbfe82d05bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880021295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.880021295
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3051885233
Short name T46
Test name
Test status
Simulation time 114211915 ps
CPU time 0.58 seconds
Started Jan 24 11:13:22 PM PST 24
Finished Jan 24 11:13:25 PM PST 24
Peak memory 185080 kb
Host smart-cd20098a-5551-47b0-b1ff-07d540940f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051885233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3051885233
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2756744856
Short name T454
Test name
Test status
Simulation time 17629514 ps
CPU time 0.61 seconds
Started Jan 24 11:13:29 PM PST 24
Finished Jan 24 11:13:31 PM PST 24
Peak memory 195560 kb
Host smart-5285ad81-8cbd-4dbe-91cd-25a26304e3d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756744856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2756744856
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3148612872
Short name T1272
Test name
Test status
Simulation time 24371319 ps
CPU time 1.2 seconds
Started Jan 25 12:49:37 AM PST 24
Finished Jan 25 12:49:40 AM PST 24
Peak memory 199912 kb
Host smart-998dc66e-3960-4a56-9dbb-1cbc844b244c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148612872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3148612872
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.849190027
Short name T90
Test name
Test status
Simulation time 206694898 ps
CPU time 0.93 seconds
Started Jan 24 11:13:00 PM PST 24
Finished Jan 24 11:13:02 PM PST 24
Peak memory 198664 kb
Host smart-29c87b78-e5be-4344-bbf1-42d43d822357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849190027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.849190027
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3853837393
Short name T1251
Test name
Test status
Simulation time 31590278 ps
CPU time 0.92 seconds
Started Jan 24 11:13:56 PM PST 24
Finished Jan 24 11:13:57 PM PST 24
Peak memory 199408 kb
Host smart-79e44797-65c8-419e-9e84-a1b467965cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853837393 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3853837393
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4279310488
Short name T61
Test name
Test status
Simulation time 21679955 ps
CPU time 0.61 seconds
Started Jan 24 11:13:24 PM PST 24
Finished Jan 24 11:13:27 PM PST 24
Peak memory 195356 kb
Host smart-8fb87f4c-308a-4ecb-ad0b-a8bd4780d5dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279310488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4279310488
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.986241156
Short name T475
Test name
Test status
Simulation time 66403480 ps
CPU time 0.85 seconds
Started Jan 24 11:13:23 PM PST 24
Finished Jan 24 11:13:26 PM PST 24
Peak memory 196408 kb
Host smart-a358acb5-6e5a-4db7-8861-e6fc2fb6eddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986241156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.986241156
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.25861498
Short name T471
Test name
Test status
Simulation time 79549481 ps
CPU time 1.32 seconds
Started Jan 24 11:13:23 PM PST 24
Finished Jan 24 11:13:27 PM PST 24
Peak memory 199852 kb
Host smart-5f1ca9f5-b270-412b-8267-5fa75b1fd74d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25861498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.25861498
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1336524851
Short name T452
Test name
Test status
Simulation time 43222501 ps
CPU time 0.77 seconds
Started Jan 24 11:13:53 PM PST 24
Finished Jan 24 11:13:55 PM PST 24
Peak memory 197888 kb
Host smart-247a5bfb-dc58-432f-9455-10f85996d86b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336524851 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1336524851
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2884046587
Short name T1293
Test name
Test status
Simulation time 15235580 ps
CPU time 0.62 seconds
Started Jan 24 11:13:53 PM PST 24
Finished Jan 24 11:13:55 PM PST 24
Peak memory 195356 kb
Host smart-b2732227-271f-4a8b-a2c7-7d61fbeaac5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884046587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2884046587
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.98177798
Short name T1258
Test name
Test status
Simulation time 14550018 ps
CPU time 0.6 seconds
Started Jan 24 11:13:59 PM PST 24
Finished Jan 24 11:14:01 PM PST 24
Peak memory 193756 kb
Host smart-8c557faf-75a3-4d87-9917-7caba3cc04cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98177798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.98177798
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3265603216
Short name T1286
Test name
Test status
Simulation time 51725681 ps
CPU time 0.73 seconds
Started Jan 24 11:13:53 PM PST 24
Finished Jan 24 11:13:55 PM PST 24
Peak memory 196728 kb
Host smart-4b5aeabb-dc12-46e7-9db5-e6ea9908c430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265603216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3265603216
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1810321851
Short name T473
Test name
Test status
Simulation time 58465951 ps
CPU time 1.12 seconds
Started Jan 24 11:13:54 PM PST 24
Finished Jan 24 11:13:56 PM PST 24
Peak memory 199888 kb
Host smart-a129904b-3e31-4926-bb90-ad65e00ccb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810321851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1810321851
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.423246263
Short name T1273
Test name
Test status
Simulation time 165651714 ps
CPU time 0.74 seconds
Started Jan 24 11:13:56 PM PST 24
Finished Jan 24 11:13:58 PM PST 24
Peak memory 198056 kb
Host smart-b10a1207-db3e-415f-a517-ae6256c97869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423246263 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.423246263
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3930095028
Short name T1271
Test name
Test status
Simulation time 54233768 ps
CPU time 0.6 seconds
Started Jan 24 11:13:55 PM PST 24
Finished Jan 24 11:13:57 PM PST 24
Peak memory 195392 kb
Host smart-5963148c-637f-408a-ae69-c5346704ea8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930095028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3930095028
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1059924169
Short name T48
Test name
Test status
Simulation time 34566454 ps
CPU time 0.57 seconds
Started Jan 24 11:13:55 PM PST 24
Finished Jan 24 11:13:57 PM PST 24
Peak memory 185048 kb
Host smart-c3346d5d-5734-4a04-934d-3ca9ded9f91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059924169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1059924169
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2835845067
Short name T1291
Test name
Test status
Simulation time 15912189 ps
CPU time 0.74 seconds
Started Jan 24 11:13:57 PM PST 24
Finished Jan 24 11:13:58 PM PST 24
Peak memory 195640 kb
Host smart-ffcbc4c0-0763-498a-8a1d-093463bab277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835845067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2835845067
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1460163654
Short name T33
Test name
Test status
Simulation time 158182829 ps
CPU time 1.41 seconds
Started Jan 24 11:13:57 PM PST 24
Finished Jan 24 11:13:59 PM PST 24
Peak memory 199912 kb
Host smart-f2e53464-0427-4b0a-9a6e-e11fbf7cca21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460163654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1460163654
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2750766848
Short name T31
Test name
Test status
Simulation time 45150624 ps
CPU time 0.88 seconds
Started Jan 24 11:13:56 PM PST 24
Finished Jan 24 11:13:58 PM PST 24
Peak memory 198444 kb
Host smart-682f80bc-13a1-4def-bab9-067610786478
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750766848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2750766848
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2192920606
Short name T892
Test name
Test status
Simulation time 29185057 ps
CPU time 0.59 seconds
Started Jan 25 01:58:06 AM PST 24
Finished Jan 25 01:58:09 AM PST 24
Peak memory 194700 kb
Host smart-00ea0c44-b149-4a69-a4e0-c853aa67b8f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192920606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2192920606
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2234025697
Short name T799
Test name
Test status
Simulation time 265148271128 ps
CPU time 50.89 seconds
Started Jan 25 05:17:45 AM PST 24
Finished Jan 25 05:18:36 AM PST 24
Peak memory 200152 kb
Host smart-94e90203-7cbd-4a01-9cb1-8c2ca89f53a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234025697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2234025697
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1209714779
Short name T739
Test name
Test status
Simulation time 110445194563 ps
CPU time 44.86 seconds
Started Jan 25 01:56:59 AM PST 24
Finished Jan 25 01:57:45 AM PST 24
Peak memory 200068 kb
Host smart-9aff5b04-3d93-41e5-846f-5404646306e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209714779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1209714779
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3977955036
Short name T12
Test name
Test status
Simulation time 51871995209 ps
CPU time 24.24 seconds
Started Jan 25 05:00:05 AM PST 24
Finished Jan 25 05:00:41 AM PST 24
Peak memory 199744 kb
Host smart-166c3459-cc54-495e-8c93-88053f6854c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977955036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3977955036
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1913823986
Short name T759
Test name
Test status
Simulation time 112003565904 ps
CPU time 170.81 seconds
Started Jan 25 04:02:29 AM PST 24
Finished Jan 25 04:05:21 AM PST 24
Peak memory 198852 kb
Host smart-571648af-33f9-4d77-8902-33873497c2c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913823986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1913823986
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3787302257
Short name T414
Test name
Test status
Simulation time 118699740783 ps
CPU time 486.86 seconds
Started Jan 25 01:57:38 AM PST 24
Finished Jan 25 02:05:46 AM PST 24
Peak memory 200028 kb
Host smart-ccf90d0c-d248-445b-a157-a8ab83192c62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787302257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3787302257
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3705512756
Short name T512
Test name
Test status
Simulation time 33866385606 ps
CPU time 26.17 seconds
Started Jan 25 02:19:52 AM PST 24
Finished Jan 25 02:20:19 AM PST 24
Peak memory 199040 kb
Host smart-ed0baf9b-d9d3-4798-bc09-61a6f5eaa936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705512756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3705512756
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3128912452
Short name T1186
Test name
Test status
Simulation time 19504493698 ps
CPU time 1167.48 seconds
Started Jan 25 02:57:50 AM PST 24
Finished Jan 25 03:17:20 AM PST 24
Peak memory 200108 kb
Host smart-dffd6a45-869f-4688-8c01-52c2972d4ae8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3128912452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3128912452
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3796989978
Short name T504
Test name
Test status
Simulation time 2082586859 ps
CPU time 13.25 seconds
Started Jan 25 03:29:45 AM PST 24
Finished Jan 25 03:29:59 AM PST 24
Peak memory 198156 kb
Host smart-b7a45c35-9890-470b-998e-c92fb27c1baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796989978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3796989978
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3228738015
Short name T101
Test name
Test status
Simulation time 125687123440 ps
CPU time 169.64 seconds
Started Jan 25 01:57:25 AM PST 24
Finished Jan 25 02:00:17 AM PST 24
Peak memory 199340 kb
Host smart-785e0644-3408-42cd-bca2-8df1af42a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228738015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3228738015
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1622728616
Short name T434
Test name
Test status
Simulation time 2794435567 ps
CPU time 1.46 seconds
Started Jan 25 01:58:05 AM PST 24
Finished Jan 25 01:58:10 AM PST 24
Peak memory 195644 kb
Host smart-9eec5892-41b6-4844-b871-d3c21fb0ca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622728616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1622728616
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.581500605
Short name T729
Test name
Test status
Simulation time 695933915 ps
CPU time 2.35 seconds
Started Jan 25 04:31:58 AM PST 24
Finished Jan 25 04:32:20 AM PST 24
Peak memory 198224 kb
Host smart-24ec9e56-7fdf-43f9-ad48-0932724894f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581500605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.581500605
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.144511891
Short name T794
Test name
Test status
Simulation time 274691598887 ps
CPU time 211.23 seconds
Started Jan 25 01:57:50 AM PST 24
Finished Jan 25 02:01:23 AM PST 24
Peak memory 208436 kb
Host smart-d07afc4d-306e-4644-8566-75f12a27116a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144511891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.144511891
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3601620025
Short name T530
Test name
Test status
Simulation time 1658133518 ps
CPU time 2.5 seconds
Started Jan 25 01:57:25 AM PST 24
Finished Jan 25 01:57:30 AM PST 24
Peak memory 199108 kb
Host smart-202b9f7e-c374-44dd-806f-932fca5fd497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601620025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3601620025
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1522782441
Short name T564
Test name
Test status
Simulation time 42549911422 ps
CPU time 40.43 seconds
Started Jan 25 01:56:42 AM PST 24
Finished Jan 25 01:57:23 AM PST 24
Peak memory 200120 kb
Host smart-96a4c9c5-b951-4553-8dfc-70e0a59514c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522782441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1522782441
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.4077345094
Short name T709
Test name
Test status
Simulation time 17275667 ps
CPU time 0.61 seconds
Started Jan 25 03:34:09 AM PST 24
Finished Jan 25 03:34:26 AM PST 24
Peak memory 195716 kb
Host smart-29af24c4-60f7-4c07-9309-5d79d8dab407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077345094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4077345094
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.117051991
Short name T667
Test name
Test status
Simulation time 115330193973 ps
CPU time 187.74 seconds
Started Jan 25 02:18:56 AM PST 24
Finished Jan 25 02:22:06 AM PST 24
Peak memory 200032 kb
Host smart-c64b1555-26e8-4de0-b1b9-51ad01680f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117051991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.117051991
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2535101646
Short name T382
Test name
Test status
Simulation time 75610027108 ps
CPU time 72.41 seconds
Started Jan 25 01:59:11 AM PST 24
Finished Jan 25 02:00:25 AM PST 24
Peak memory 199948 kb
Host smart-6b797a71-dbb8-49c2-ab5b-1977195765e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535101646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2535101646
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1252720278
Short name T181
Test name
Test status
Simulation time 44089119289 ps
CPU time 45.67 seconds
Started Jan 25 01:58:41 AM PST 24
Finished Jan 25 01:59:28 AM PST 24
Peak memory 200092 kb
Host smart-8272ae8c-d16f-4102-9f33-2843836980bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252720278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1252720278
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.181894884
Short name T421
Test name
Test status
Simulation time 104450670935 ps
CPU time 186.35 seconds
Started Jan 25 02:12:27 AM PST 24
Finished Jan 25 02:15:35 AM PST 24
Peak memory 200076 kb
Host smart-1e8060cc-518d-4d1f-b995-186674b6ece7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181894884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.181894884
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1987117240
Short name T617
Test name
Test status
Simulation time 118664811589 ps
CPU time 228.56 seconds
Started Jan 25 01:59:28 AM PST 24
Finished Jan 25 02:03:18 AM PST 24
Peak memory 208316 kb
Host smart-cb41f70b-d330-4b3c-90cd-a006b3984891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987117240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1987117240
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.58237934
Short name T1097
Test name
Test status
Simulation time 20267475209 ps
CPU time 303.44 seconds
Started Jan 25 01:59:02 AM PST 24
Finished Jan 25 02:04:06 AM PST 24
Peak memory 200048 kb
Host smart-53d4f5ed-9875-4d90-bede-f99fa4559ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58237934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.58237934
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2618647004
Short name T782
Test name
Test status
Simulation time 2563474655 ps
CPU time 26.36 seconds
Started Jan 25 01:59:01 AM PST 24
Finished Jan 25 01:59:28 AM PST 24
Peak memory 198336 kb
Host smart-270a980f-2591-403b-b9dd-0ab65da6cb7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618647004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2618647004
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1412058720
Short name T880
Test name
Test status
Simulation time 61577201846 ps
CPU time 86.58 seconds
Started Jan 25 01:59:01 AM PST 24
Finished Jan 25 02:00:28 AM PST 24
Peak memory 200028 kb
Host smart-786507a1-a9e3-47fc-9e77-8f22cb606a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412058720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1412058720
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.306350827
Short name T621
Test name
Test status
Simulation time 3514780974 ps
CPU time 5.9 seconds
Started Jan 25 04:26:30 AM PST 24
Finished Jan 25 04:26:50 AM PST 24
Peak memory 195920 kb
Host smart-9cff010a-edf1-4418-97ef-01dc6727c1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306350827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.306350827
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4008242745
Short name T82
Test name
Test status
Simulation time 176206277 ps
CPU time 0.99 seconds
Started Jan 25 05:06:38 AM PST 24
Finished Jan 25 05:06:51 AM PST 24
Peak memory 217252 kb
Host smart-6d1dbf05-f539-40bf-94e2-68ba7d60dd91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008242745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4008242745
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.58015494
Short name T762
Test name
Test status
Simulation time 246358338 ps
CPU time 1.37 seconds
Started Jan 25 02:37:29 AM PST 24
Finished Jan 25 02:37:31 AM PST 24
Peak memory 198220 kb
Host smart-c47aefc7-3a12-4a1b-8649-c958bda950cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58015494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.58015494
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.563136099
Short name T718
Test name
Test status
Simulation time 216681286584 ps
CPU time 205.21 seconds
Started Jan 25 02:19:54 AM PST 24
Finished Jan 25 02:23:21 AM PST 24
Peak memory 200068 kb
Host smart-42da7e3a-a896-4fbb-b568-838544f89011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563136099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.563136099
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.909038512
Short name T1034
Test name
Test status
Simulation time 15070214018 ps
CPU time 445.3 seconds
Started Jan 25 01:59:17 AM PST 24
Finished Jan 25 02:06:43 AM PST 24
Peak memory 216732 kb
Host smart-c423c067-dd5b-422a-81f9-13fbc6ed46d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909038512 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.909038512
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.584487803
Short name T1079
Test name
Test status
Simulation time 2712563311 ps
CPU time 1.69 seconds
Started Jan 25 01:59:01 AM PST 24
Finished Jan 25 01:59:03 AM PST 24
Peak memory 198368 kb
Host smart-54e20a97-6677-455c-bee5-0efb3ee78deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584487803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.584487803
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2901332815
Short name T127
Test name
Test status
Simulation time 8967526316 ps
CPU time 14.82 seconds
Started Jan 25 01:58:48 AM PST 24
Finished Jan 25 01:59:04 AM PST 24
Peak memory 199976 kb
Host smart-9a8475ee-9070-415a-a21b-d2346963e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901332815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2901332815
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3919876415
Short name T610
Test name
Test status
Simulation time 31374916 ps
CPU time 0.55 seconds
Started Jan 25 02:09:11 AM PST 24
Finished Jan 25 02:09:14 AM PST 24
Peak memory 195700 kb
Host smart-edf69528-30b2-427f-a67b-3a7e34a045e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919876415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3919876415
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2928025528
Short name T151
Test name
Test status
Simulation time 138126541872 ps
CPU time 31.87 seconds
Started Jan 25 02:09:14 AM PST 24
Finished Jan 25 02:09:48 AM PST 24
Peak memory 199012 kb
Host smart-bc1b1fcf-da4d-4036-b8d7-e4b078318783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928025528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2928025528
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2532704644
Short name T894
Test name
Test status
Simulation time 64538208968 ps
CPU time 50.53 seconds
Started Jan 25 04:04:47 AM PST 24
Finished Jan 25 04:05:40 AM PST 24
Peak memory 200024 kb
Host smart-7082a536-4749-4b81-8690-b69593b30e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532704644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2532704644
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.4030871142
Short name T964
Test name
Test status
Simulation time 612085541266 ps
CPU time 515.17 seconds
Started Jan 25 02:09:09 AM PST 24
Finished Jan 25 02:17:47 AM PST 24
Peak memory 199892 kb
Host smart-99faf5a3-f5ca-415b-81c5-d59c7a1b8917
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030871142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.4030871142
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2139725461
Short name T566
Test name
Test status
Simulation time 102689528576 ps
CPU time 808.83 seconds
Started Jan 25 02:59:37 AM PST 24
Finished Jan 25 03:13:07 AM PST 24
Peak memory 200120 kb
Host smart-6293c387-e0a8-46ee-ac5b-2fd7ccb8a894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139725461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2139725461
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3011150456
Short name T573
Test name
Test status
Simulation time 8268911040 ps
CPU time 6.58 seconds
Started Jan 25 02:09:09 AM PST 24
Finished Jan 25 02:09:17 AM PST 24
Peak memory 198424 kb
Host smart-a447a917-5070-4419-bc72-2d2f8181964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011150456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3011150456
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.777971400
Short name T994
Test name
Test status
Simulation time 127663793098 ps
CPU time 59.12 seconds
Started Jan 25 02:09:10 AM PST 24
Finished Jan 25 02:10:12 AM PST 24
Peak memory 200280 kb
Host smart-b120fe8b-bf62-46e4-bc82-4c240b2506d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777971400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.777971400
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1977228460
Short name T29
Test name
Test status
Simulation time 4293647744 ps
CPU time 16.56 seconds
Started Jan 25 02:09:13 AM PST 24
Finished Jan 25 02:09:32 AM PST 24
Peak memory 198292 kb
Host smart-63a21b65-23c5-41fc-bec7-7cbd961ba71a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977228460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1977228460
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2987419048
Short name T778
Test name
Test status
Simulation time 85169413359 ps
CPU time 57.25 seconds
Started Jan 25 04:11:15 AM PST 24
Finished Jan 25 04:12:20 AM PST 24
Peak memory 200024 kb
Host smart-0da79218-7d71-4684-bcc3-9569393a6f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987419048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2987419048
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.830306917
Short name T507
Test name
Test status
Simulation time 4376271549 ps
CPU time 4.84 seconds
Started Jan 25 02:09:14 AM PST 24
Finished Jan 25 02:09:21 AM PST 24
Peak memory 195600 kb
Host smart-37b1f30d-e4c6-4b74-8cae-560f6d3bcc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830306917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.830306917
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1030800044
Short name T738
Test name
Test status
Simulation time 6072203597 ps
CPU time 38.96 seconds
Started Jan 25 02:09:16 AM PST 24
Finished Jan 25 02:09:57 AM PST 24
Peak memory 199476 kb
Host smart-eeb2d849-9c3c-48fa-a6d1-7c8b803021ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030800044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1030800044
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.363696732
Short name T571
Test name
Test status
Simulation time 561079783957 ps
CPU time 226.18 seconds
Started Jan 25 02:09:13 AM PST 24
Finished Jan 25 02:13:02 AM PST 24
Peak memory 200080 kb
Host smart-666be957-0637-4333-b6a3-e24b3b77287f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363696732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.363696732
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3968850795
Short name T904
Test name
Test status
Simulation time 558062672 ps
CPU time 2.16 seconds
Started Jan 25 02:09:14 AM PST 24
Finished Jan 25 02:09:18 AM PST 24
Peak memory 197768 kb
Host smart-31f37bd0-1b25-4247-bb7a-3ecfeed3cf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968850795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3968850795
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1333526678
Short name T1159
Test name
Test status
Simulation time 22494250441 ps
CPU time 16.38 seconds
Started Jan 25 03:10:55 AM PST 24
Finished Jan 25 03:11:12 AM PST 24
Peak memory 198724 kb
Host smart-b19c7ba7-106c-4789-ae25-ca1ca1bd4a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333526678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1333526678
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.572809806
Short name T331
Test name
Test status
Simulation time 78668416224 ps
CPU time 37.2 seconds
Started Jan 25 02:40:35 AM PST 24
Finished Jan 25 02:41:22 AM PST 24
Peak memory 200068 kb
Host smart-a5318627-79ad-4a3a-8c14-fd5646e5cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572809806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.572809806
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.754252938
Short name T217
Test name
Test status
Simulation time 192592163467 ps
CPU time 344.37 seconds
Started Jan 25 02:40:55 AM PST 24
Finished Jan 25 02:46:41 AM PST 24
Peak memory 200064 kb
Host smart-97ba74cb-ff9b-4ac4-97c7-94b56ac26e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754252938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.754252938
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3097572651
Short name T197
Test name
Test status
Simulation time 62245027231 ps
CPU time 25.28 seconds
Started Jan 25 02:40:55 AM PST 24
Finished Jan 25 02:41:22 AM PST 24
Peak memory 199960 kb
Host smart-605d4c5e-e034-4209-8a9d-eabd9fb8eead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097572651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3097572651
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3081462619
Short name T1107
Test name
Test status
Simulation time 50510129907 ps
CPU time 44.3 seconds
Started Jan 25 02:40:59 AM PST 24
Finished Jan 25 02:41:44 AM PST 24
Peak memory 200052 kb
Host smart-cbf9f148-f02b-4c7f-82bf-3561afa638fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081462619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3081462619
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3836803871
Short name T332
Test name
Test status
Simulation time 9079072898 ps
CPU time 16.07 seconds
Started Jan 25 02:40:54 AM PST 24
Finished Jan 25 02:41:11 AM PST 24
Peak memory 199968 kb
Host smart-025ea232-e684-44bf-86e1-08302dd42a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836803871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3836803871
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3321804122
Short name T791
Test name
Test status
Simulation time 71319748804 ps
CPU time 29.55 seconds
Started Jan 25 02:40:54 AM PST 24
Finished Jan 25 02:41:24 AM PST 24
Peak memory 200068 kb
Host smart-1c07bc92-acbc-4c00-939e-fc445a13dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321804122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3321804122
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1539291670
Short name T949
Test name
Test status
Simulation time 34641474751 ps
CPU time 50.54 seconds
Started Jan 25 02:40:55 AM PST 24
Finished Jan 25 02:41:47 AM PST 24
Peak memory 200112 kb
Host smart-7d1ed657-f93c-448f-8bbc-46dc1a2e2a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539291670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1539291670
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2412923374
Short name T871
Test name
Test status
Simulation time 13320863584 ps
CPU time 19.46 seconds
Started Jan 25 02:40:53 AM PST 24
Finished Jan 25 02:41:14 AM PST 24
Peak memory 199952 kb
Host smart-337de8ef-ae67-417b-a6d3-68535c45bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412923374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2412923374
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2690908985
Short name T123
Test name
Test status
Simulation time 108314982194 ps
CPU time 15.58 seconds
Started Jan 25 02:41:14 AM PST 24
Finished Jan 25 02:41:30 AM PST 24
Peak memory 200068 kb
Host smart-bd18f5d7-c759-4984-81bb-25f419782b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690908985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2690908985
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4294258450
Short name T1132
Test name
Test status
Simulation time 15083187 ps
CPU time 0.61 seconds
Started Jan 25 04:11:33 AM PST 24
Finished Jan 25 04:11:36 AM PST 24
Peak memory 195708 kb
Host smart-b4be8738-6305-49ee-8302-e01fd319b652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294258450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4294258450
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.652786459
Short name T822
Test name
Test status
Simulation time 44957660688 ps
CPU time 72.42 seconds
Started Jan 25 02:09:47 AM PST 24
Finished Jan 25 02:11:03 AM PST 24
Peak memory 199372 kb
Host smart-bebd417b-b8ff-42b2-8895-b2e5a9dd4ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652786459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.652786459
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1131653768
Short name T509
Test name
Test status
Simulation time 46836890632 ps
CPU time 52.65 seconds
Started Jan 25 02:09:52 AM PST 24
Finished Jan 25 02:10:47 AM PST 24
Peak memory 200060 kb
Host smart-b783a61a-45e5-4b39-83a2-8b53a345b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131653768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1131653768
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2479590155
Short name T741
Test name
Test status
Simulation time 110905827247 ps
CPU time 113.4 seconds
Started Jan 25 02:10:16 AM PST 24
Finished Jan 25 02:12:14 AM PST 24
Peak memory 200020 kb
Host smart-14b17ecb-af97-4c0c-a715-b79996a877c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479590155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2479590155
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2803597285
Short name T882
Test name
Test status
Simulation time 5802971215 ps
CPU time 7.31 seconds
Started Jan 25 06:35:58 AM PST 24
Finished Jan 25 06:36:06 AM PST 24
Peak memory 198688 kb
Host smart-c387b740-56e5-4b42-af0e-d31bba08a0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803597285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2803597285
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2139110277
Short name T857
Test name
Test status
Simulation time 44012743485 ps
CPU time 73.26 seconds
Started Jan 25 02:10:18 AM PST 24
Finished Jan 25 02:11:39 AM PST 24
Peak memory 198984 kb
Host smart-3d247f89-b3d5-4613-bad5-ac5fa311bca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139110277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2139110277
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2549854320
Short name T877
Test name
Test status
Simulation time 16049163943 ps
CPU time 879.76 seconds
Started Jan 25 02:10:22 AM PST 24
Finished Jan 25 02:25:08 AM PST 24
Peak memory 199360 kb
Host smart-c7c9bfaa-62ba-4a47-b71a-02c729044c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549854320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2549854320
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2885028615
Short name T658
Test name
Test status
Simulation time 3235355525 ps
CPU time 33.88 seconds
Started Jan 25 02:10:16 AM PST 24
Finished Jan 25 02:10:56 AM PST 24
Peak memory 198260 kb
Host smart-8571233e-af0c-483b-8100-458671eaf97f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885028615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2885028615
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1612591221
Short name T673
Test name
Test status
Simulation time 104857466515 ps
CPU time 15.62 seconds
Started Jan 25 02:10:17 AM PST 24
Finished Jan 25 02:10:39 AM PST 24
Peak memory 199436 kb
Host smart-7fbe8104-99b1-43af-8d92-bbdecf61103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612591221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1612591221
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.889877866
Short name T1125
Test name
Test status
Simulation time 2683001966 ps
CPU time 4.66 seconds
Started Jan 25 02:10:21 AM PST 24
Finished Jan 25 02:10:32 AM PST 24
Peak memory 195640 kb
Host smart-423e36c0-cfb7-4541-882e-568738992a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889877866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.889877866
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.196606506
Short name T1098
Test name
Test status
Simulation time 607273868 ps
CPU time 2.62 seconds
Started Jan 25 04:31:43 AM PST 24
Finished Jan 25 04:31:48 AM PST 24
Peak memory 198336 kb
Host smart-f1afbc16-4b60-44f0-bdce-771a1dcc0cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196606506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.196606506
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1569611572
Short name T1152
Test name
Test status
Simulation time 1532361814007 ps
CPU time 1423.78 seconds
Started Jan 25 02:10:16 AM PST 24
Finished Jan 25 02:34:06 AM PST 24
Peak memory 199992 kb
Host smart-59d5c819-16ae-4ab9-95df-ff483d04ab91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569611572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1569611572
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.316186478
Short name T802
Test name
Test status
Simulation time 316074955735 ps
CPU time 1139.42 seconds
Started Jan 25 02:10:19 AM PST 24
Finished Jan 25 02:29:26 AM PST 24
Peak memory 225132 kb
Host smart-3c81657d-4b36-4126-98b6-2b2fbe058d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316186478 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.316186478
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2971115233
Short name T958
Test name
Test status
Simulation time 2483110475 ps
CPU time 1.25 seconds
Started Jan 25 02:10:15 AM PST 24
Finished Jan 25 02:10:20 AM PST 24
Peak memory 197900 kb
Host smart-66230710-f226-434b-a353-c2ececf8bc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971115233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2971115233
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.991606211
Short name T644
Test name
Test status
Simulation time 5499642192 ps
CPU time 11.09 seconds
Started Jan 25 02:09:45 AM PST 24
Finished Jan 25 02:09:58 AM PST 24
Peak memory 200144 kb
Host smart-6f894d19-1c71-40ed-9f87-d74ba5a61bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991606211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.991606211
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3540674869
Short name T425
Test name
Test status
Simulation time 52031004691 ps
CPU time 19.25 seconds
Started Jan 25 02:41:14 AM PST 24
Finished Jan 25 02:41:34 AM PST 24
Peak memory 200120 kb
Host smart-766ce956-29cf-4395-a4ee-8f281236a21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540674869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3540674869
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2208570881
Short name T119
Test name
Test status
Simulation time 133913053699 ps
CPU time 104.34 seconds
Started Jan 25 02:41:13 AM PST 24
Finished Jan 25 02:42:58 AM PST 24
Peak memory 200016 kb
Host smart-2b7f373f-22db-4ec6-9ba9-856007df429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208570881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2208570881
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1730291913
Short name T231
Test name
Test status
Simulation time 44400426947 ps
CPU time 38.83 seconds
Started Jan 25 02:41:21 AM PST 24
Finished Jan 25 02:42:00 AM PST 24
Peak memory 200020 kb
Host smart-d5875fc2-7972-4bdf-b4a1-3d8a976518a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730291913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1730291913
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1710193706
Short name T1200
Test name
Test status
Simulation time 23765031962 ps
CPU time 36.74 seconds
Started Jan 25 02:41:14 AM PST 24
Finished Jan 25 02:41:51 AM PST 24
Peak memory 200064 kb
Host smart-79a77be0-ebaa-42e6-8f92-346c8bddd32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710193706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1710193706
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2982421857
Short name T797
Test name
Test status
Simulation time 95579013589 ps
CPU time 172.37 seconds
Started Jan 25 02:41:31 AM PST 24
Finished Jan 25 02:44:25 AM PST 24
Peak memory 200096 kb
Host smart-d33bb230-e086-4394-9f1c-34279c477902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982421857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2982421857
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2581915182
Short name T967
Test name
Test status
Simulation time 77067960051 ps
CPU time 21.89 seconds
Started Jan 25 02:41:28 AM PST 24
Finished Jan 25 02:41:51 AM PST 24
Peak memory 199836 kb
Host smart-86c2a258-7526-4f23-a754-db5b0760dfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581915182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2581915182
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2433598115
Short name T228
Test name
Test status
Simulation time 72912155361 ps
CPU time 57.96 seconds
Started Jan 25 02:41:31 AM PST 24
Finished Jan 25 02:42:30 AM PST 24
Peak memory 200080 kb
Host smart-d02196fb-572b-46d3-958a-e4519bffabaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433598115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2433598115
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3415186965
Short name T805
Test name
Test status
Simulation time 40929321 ps
CPU time 0.59 seconds
Started Jan 25 02:11:04 AM PST 24
Finished Jan 25 02:11:06 AM PST 24
Peak memory 195712 kb
Host smart-5f3607ba-453e-4d5d-8755-3b75ba197ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415186965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3415186965
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3041756912
Short name T1154
Test name
Test status
Simulation time 122921444470 ps
CPU time 181.69 seconds
Started Jan 25 02:10:39 AM PST 24
Finished Jan 25 02:13:43 AM PST 24
Peak memory 200044 kb
Host smart-84350685-808c-4abe-99da-2e4e87638fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041756912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3041756912
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3018344185
Short name T1203
Test name
Test status
Simulation time 243076593438 ps
CPU time 401.41 seconds
Started Jan 25 02:10:42 AM PST 24
Finished Jan 25 02:17:24 AM PST 24
Peak memory 200036 kb
Host smart-897bd9fb-193c-4afc-a3fb-773c7e761c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018344185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3018344185
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.1536679661
Short name T923
Test name
Test status
Simulation time 286588789353 ps
CPU time 63.3 seconds
Started Jan 25 06:22:29 AM PST 24
Finished Jan 25 06:23:32 AM PST 24
Peak memory 199788 kb
Host smart-584dd4c6-d92f-48c0-8c2d-484d909435d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536679661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1536679661
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1581316521
Short name T1102
Test name
Test status
Simulation time 34588830167 ps
CPU time 225.57 seconds
Started Jan 25 02:11:06 AM PST 24
Finished Jan 25 02:14:53 AM PST 24
Peak memory 200016 kb
Host smart-0e4c1111-e72d-4098-8a21-33b2f90b0eb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581316521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1581316521
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2193369165
Short name T734
Test name
Test status
Simulation time 96253866 ps
CPU time 0.83 seconds
Started Jan 25 04:02:19 AM PST 24
Finished Jan 25 04:02:21 AM PST 24
Peak memory 195556 kb
Host smart-bd4e2053-0cb5-4c59-9db8-8393b0d1b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193369165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2193369165
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1370018877
Short name T1052
Test name
Test status
Simulation time 101158318308 ps
CPU time 151.32 seconds
Started Jan 25 02:44:00 AM PST 24
Finished Jan 25 02:46:39 AM PST 24
Peak memory 199788 kb
Host smart-b71a9a7b-e09e-4d08-bf3f-a830fe389911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370018877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1370018877
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1678847676
Short name T1058
Test name
Test status
Simulation time 17483611704 ps
CPU time 870.07 seconds
Started Jan 25 02:10:41 AM PST 24
Finished Jan 25 02:25:12 AM PST 24
Peak memory 200092 kb
Host smart-c3866905-b0d5-4825-97ed-e5ba3d3b0bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678847676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1678847676
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1215431322
Short name T501
Test name
Test status
Simulation time 5045334105 ps
CPU time 43.26 seconds
Started Jan 25 02:10:40 AM PST 24
Finished Jan 25 02:11:24 AM PST 24
Peak memory 198144 kb
Host smart-e1513ee5-99c8-4823-be69-5da88f7ca159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215431322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1215431322
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4223452419
Short name T676
Test name
Test status
Simulation time 58726936325 ps
CPU time 52.84 seconds
Started Jan 25 03:00:14 AM PST 24
Finished Jan 25 03:01:10 AM PST 24
Peak memory 200088 kb
Host smart-91328c05-3761-438a-a880-0077a3481f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223452419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4223452419
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3865991460
Short name T850
Test name
Test status
Simulation time 33181830109 ps
CPU time 41.6 seconds
Started Jan 25 02:10:44 AM PST 24
Finished Jan 25 02:11:27 AM PST 24
Peak memory 195640 kb
Host smart-cc3f8670-3801-43cf-83a4-3f7e0480ff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865991460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3865991460
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3172107883
Short name T854
Test name
Test status
Simulation time 6334255262 ps
CPU time 28.63 seconds
Started Jan 25 03:30:42 AM PST 24
Finished Jan 25 03:31:14 AM PST 24
Peak memory 199412 kb
Host smart-fb11c9bc-c36c-4d2c-9210-22dc25bf8f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172107883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3172107883
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3904658131
Short name T833
Test name
Test status
Simulation time 52677428251 ps
CPU time 131.44 seconds
Started Jan 25 02:11:07 AM PST 24
Finished Jan 25 02:13:20 AM PST 24
Peak memory 199944 kb
Host smart-bf5fc09f-29b9-4fd0-b511-da53bceac715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904658131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3904658131
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4124303683
Short name T742
Test name
Test status
Simulation time 94909297973 ps
CPU time 1049.16 seconds
Started Jan 25 02:11:08 AM PST 24
Finished Jan 25 02:28:38 AM PST 24
Peak memory 216552 kb
Host smart-6466b23f-78b2-4a45-b2d9-9b120cd7c5dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124303683 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4124303683
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1234192769
Short name T443
Test name
Test status
Simulation time 1126168500 ps
CPU time 4 seconds
Started Jan 25 02:10:39 AM PST 24
Finished Jan 25 02:10:45 AM PST 24
Peak memory 197856 kb
Host smart-7a59d804-b5a9-4dd2-95c0-5d6f7ac18e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234192769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1234192769
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.821580225
Short name T413
Test name
Test status
Simulation time 36717178455 ps
CPU time 31.7 seconds
Started Jan 25 02:10:17 AM PST 24
Finished Jan 25 02:10:56 AM PST 24
Peak memory 199900 kb
Host smart-fbbd0074-092a-4bc7-94fe-01232e2b62fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821580225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.821580225
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1113348611
Short name T271
Test name
Test status
Simulation time 57294127302 ps
CPU time 16.02 seconds
Started Jan 25 03:38:42 AM PST 24
Finished Jan 25 03:38:59 AM PST 24
Peak memory 200088 kb
Host smart-87dc46cc-463f-4958-9fa9-871cb7aea329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113348611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1113348611
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3510156325
Short name T570
Test name
Test status
Simulation time 193444352576 ps
CPU time 301.86 seconds
Started Jan 25 02:41:28 AM PST 24
Finished Jan 25 02:46:30 AM PST 24
Peak memory 200120 kb
Host smart-ab64f38f-647c-46b6-a15b-08cf0d66cd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510156325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3510156325
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.4201493309
Short name T1129
Test name
Test status
Simulation time 41789899343 ps
CPU time 72.28 seconds
Started Jan 25 02:41:27 AM PST 24
Finished Jan 25 02:42:40 AM PST 24
Peak memory 200024 kb
Host smart-7b5c2d7e-2655-4d8a-b306-4da8a6d58e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201493309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.4201493309
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3278030026
Short name T629
Test name
Test status
Simulation time 21995265337 ps
CPU time 10.65 seconds
Started Jan 25 02:41:27 AM PST 24
Finished Jan 25 02:41:39 AM PST 24
Peak memory 199952 kb
Host smart-ef2cdfd8-dd0f-467d-b201-dad9325c2646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278030026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3278030026
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1696231765
Short name T1220
Test name
Test status
Simulation time 7084573033 ps
CPU time 6.81 seconds
Started Jan 25 02:41:43 AM PST 24
Finished Jan 25 02:41:51 AM PST 24
Peak memory 199272 kb
Host smart-269d2294-d442-4773-a1c2-93d357b97409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696231765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1696231765
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2016621207
Short name T283
Test name
Test status
Simulation time 64812892272 ps
CPU time 24.51 seconds
Started Jan 25 02:41:43 AM PST 24
Finished Jan 25 02:42:09 AM PST 24
Peak memory 199236 kb
Host smart-a2b3b153-84ca-4cd5-9694-22cf9d7bed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016621207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2016621207
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2029503089
Short name T582
Test name
Test status
Simulation time 237329587781 ps
CPU time 186.93 seconds
Started Jan 25 02:11:08 AM PST 24
Finished Jan 25 02:14:16 AM PST 24
Peak memory 200068 kb
Host smart-24a3e914-d2cb-46f1-bbf0-8066a525dbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029503089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2029503089
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3137997639
Short name T1178
Test name
Test status
Simulation time 118091944142 ps
CPU time 158.95 seconds
Started Jan 25 02:11:07 AM PST 24
Finished Jan 25 02:13:48 AM PST 24
Peak memory 200028 kb
Host smart-cae0e9ce-4dce-459f-b60a-adbdce3e365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137997639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3137997639
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3125948502
Short name T760
Test name
Test status
Simulation time 614604154349 ps
CPU time 476.59 seconds
Started Jan 25 02:11:07 AM PST 24
Finished Jan 25 02:19:05 AM PST 24
Peak memory 199892 kb
Host smart-96cc9e83-b42a-44b2-b25c-4cef31f82b12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125948502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3125948502
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.920598024
Short name T721
Test name
Test status
Simulation time 60449826025 ps
CPU time 215.8 seconds
Started Jan 25 02:11:26 AM PST 24
Finished Jan 25 02:15:10 AM PST 24
Peak memory 200052 kb
Host smart-79195d0f-5cbb-40f7-8ae5-57a283e162fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920598024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.920598024
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.498351013
Short name T1015
Test name
Test status
Simulation time 5155077180 ps
CPU time 11.69 seconds
Started Jan 25 05:03:10 AM PST 24
Finished Jan 25 05:03:27 AM PST 24
Peak memory 198164 kb
Host smart-ea90f65b-0592-4ca6-9a69-7790f68eaf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498351013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.498351013
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2099780908
Short name T635
Test name
Test status
Simulation time 62947235530 ps
CPU time 25.47 seconds
Started Jan 25 03:29:54 AM PST 24
Finished Jan 25 03:30:24 AM PST 24
Peak memory 199336 kb
Host smart-9fccd993-ccb6-4c5b-b034-16875a367810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099780908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2099780908
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.988337056
Short name T1108
Test name
Test status
Simulation time 18933496870 ps
CPU time 103.14 seconds
Started Jan 25 02:35:36 AM PST 24
Finished Jan 25 02:37:27 AM PST 24
Peak memory 200068 kb
Host smart-7746c753-00fe-4fa7-8cab-d8d68ed104b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988337056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.988337056
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.246860191
Short name T447
Test name
Test status
Simulation time 3246334250 ps
CPU time 17.74 seconds
Started Jan 25 02:11:07 AM PST 24
Finished Jan 25 02:11:26 AM PST 24
Peak memory 198756 kb
Host smart-7c99654b-0a71-472a-87e1-d8f3c5dbf69e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246860191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.246860191
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2734781799
Short name T1138
Test name
Test status
Simulation time 113195336700 ps
CPU time 182.6 seconds
Started Jan 25 04:07:24 AM PST 24
Finished Jan 25 04:10:28 AM PST 24
Peak memory 200076 kb
Host smart-346c5a14-b214-4024-b69a-fdef8307af9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734781799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2734781799
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.4253889878
Short name T1118
Test name
Test status
Simulation time 43937809951 ps
CPU time 12.78 seconds
Started Jan 25 02:11:06 AM PST 24
Finished Jan 25 02:11:20 AM PST 24
Peak memory 195588 kb
Host smart-a635f745-f333-43ae-b0e8-41daf69e40e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253889878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4253889878
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2300376206
Short name T653
Test name
Test status
Simulation time 554563827 ps
CPU time 1.86 seconds
Started Jan 25 02:10:50 AM PST 24
Finished Jan 25 02:10:53 AM PST 24
Peak memory 198240 kb
Host smart-b1fddb0d-f7f2-461a-bd84-6d8ce018a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300376206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2300376206
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1794765728
Short name T872
Test name
Test status
Simulation time 101948272574 ps
CPU time 851.72 seconds
Started Jan 25 02:11:33 AM PST 24
Finished Jan 25 02:25:50 AM PST 24
Peak memory 200088 kb
Host smart-7bd9d857-4106-4716-8d95-fccfec96b474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794765728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1794765728
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1641062045
Short name T191
Test name
Test status
Simulation time 321924704986 ps
CPU time 746.54 seconds
Started Jan 25 05:01:07 AM PST 24
Finished Jan 25 05:13:35 AM PST 24
Peak memory 230104 kb
Host smart-129a7a48-e06a-4a73-94cf-3a9f1aed62da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641062045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1641062045
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.324867203
Short name T106
Test name
Test status
Simulation time 1474956809 ps
CPU time 1.99 seconds
Started Jan 25 02:11:07 AM PST 24
Finished Jan 25 02:11:10 AM PST 24
Peak memory 197820 kb
Host smart-198abb79-f9a0-4cdc-be0f-4194f4e7dd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324867203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.324867203
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1170784424
Short name T1005
Test name
Test status
Simulation time 3390871453 ps
CPU time 5.08 seconds
Started Jan 25 06:49:52 AM PST 24
Finished Jan 25 06:49:58 AM PST 24
Peak memory 196044 kb
Host smart-30c7d3fc-fece-4a08-b6df-9eb7a241f7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170784424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1170784424
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3945020802
Short name T201
Test name
Test status
Simulation time 41147301005 ps
CPU time 35.39 seconds
Started Jan 25 02:41:40 AM PST 24
Finished Jan 25 02:42:18 AM PST 24
Peak memory 200076 kb
Host smart-78f58a80-568c-43b2-aa25-25fbf539ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945020802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3945020802
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3716248526
Short name T24
Test name
Test status
Simulation time 97521883292 ps
CPU time 173.28 seconds
Started Jan 25 02:53:16 AM PST 24
Finished Jan 25 02:56:13 AM PST 24
Peak memory 200064 kb
Host smart-9366671c-50f0-4b10-9086-350046774f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716248526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3716248526
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1846582380
Short name T1086
Test name
Test status
Simulation time 5153522381 ps
CPU time 5.22 seconds
Started Jan 25 06:08:51 AM PST 24
Finished Jan 25 06:08:57 AM PST 24
Peak memory 199736 kb
Host smart-195e91f6-354e-4eb6-a294-4d253d9cea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846582380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1846582380
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1808286175
Short name T720
Test name
Test status
Simulation time 93103521379 ps
CPU time 43.5 seconds
Started Jan 25 02:42:13 AM PST 24
Finished Jan 25 02:43:17 AM PST 24
Peak memory 200028 kb
Host smart-84024035-615e-4b71-b42e-bc0085e95c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808286175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1808286175
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.816909972
Short name T278
Test name
Test status
Simulation time 242283991967 ps
CPU time 492.47 seconds
Started Jan 25 02:42:13 AM PST 24
Finished Jan 25 02:50:46 AM PST 24
Peak memory 200068 kb
Host smart-7e8d3c0d-f500-4933-ba4e-e38809dbebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816909972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.816909972
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.908114628
Short name T212
Test name
Test status
Simulation time 34704885886 ps
CPU time 23.15 seconds
Started Jan 25 02:42:12 AM PST 24
Finished Jan 25 02:42:56 AM PST 24
Peak memory 200072 kb
Host smart-972ead22-76a1-41de-bc5f-d04267505fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908114628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.908114628
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3665148915
Short name T1184
Test name
Test status
Simulation time 28023473861 ps
CPU time 16.21 seconds
Started Jan 25 02:42:25 AM PST 24
Finished Jan 25 02:42:52 AM PST 24
Peak memory 199888 kb
Host smart-f529a4f4-5bc0-4735-bc32-2039304aab05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665148915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3665148915
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3828398650
Short name T498
Test name
Test status
Simulation time 13583973 ps
CPU time 0.62 seconds
Started Jan 25 02:33:30 AM PST 24
Finished Jan 25 02:33:32 AM PST 24
Peak memory 195732 kb
Host smart-e389b245-a1ca-49f5-9ae1-0b5dabc965d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828398650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3828398650
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4246472152
Short name T953
Test name
Test status
Simulation time 28456409146 ps
CPU time 48.16 seconds
Started Jan 25 02:11:26 AM PST 24
Finished Jan 25 02:12:20 AM PST 24
Peak memory 200068 kb
Host smart-00e63a93-cb9b-4ef4-b6c0-515043e90e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246472152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4246472152
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2788084961
Short name T612
Test name
Test status
Simulation time 21274365259 ps
CPU time 17.17 seconds
Started Jan 25 02:11:24 AM PST 24
Finished Jan 25 02:11:48 AM PST 24
Peak memory 199152 kb
Host smart-acf86fa7-9932-4b9b-9632-871b856ec4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788084961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2788084961
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2902177988
Short name T823
Test name
Test status
Simulation time 188673669206 ps
CPU time 51.72 seconds
Started Jan 25 02:11:25 AM PST 24
Finished Jan 25 02:12:23 AM PST 24
Peak memory 200028 kb
Host smart-da3ebfa3-90f0-4f3d-bada-404d24e91f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902177988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2902177988
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2577910817
Short name T821
Test name
Test status
Simulation time 51470937663 ps
CPU time 84.93 seconds
Started Jan 25 02:11:32 AM PST 24
Finished Jan 25 02:13:03 AM PST 24
Peak memory 199968 kb
Host smart-4d53483d-7f08-4f7e-a126-b2ff77da5ada
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577910817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2577910817
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1802973477
Short name T674
Test name
Test status
Simulation time 165251241546 ps
CPU time 371.63 seconds
Started Jan 25 02:11:42 AM PST 24
Finished Jan 25 02:17:54 AM PST 24
Peak memory 199964 kb
Host smart-88b0a274-c99c-4e28-bd7b-ea2a9df6f8f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802973477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1802973477
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1507182203
Short name T1072
Test name
Test status
Simulation time 15942177973 ps
CPU time 17.34 seconds
Started Jan 25 04:39:19 AM PST 24
Finished Jan 25 04:39:46 AM PST 24
Peak memory 199128 kb
Host smart-9739dec2-71ae-4737-a389-1b4cb4e91a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507182203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1507182203
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1094232171
Short name T757
Test name
Test status
Simulation time 21241170618 ps
CPU time 39.93 seconds
Started Jan 25 02:11:41 AM PST 24
Finished Jan 25 02:12:22 AM PST 24
Peak memory 199060 kb
Host smart-682e1f38-e505-4977-a42b-7d23d054b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094232171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1094232171
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3364793081
Short name T1007
Test name
Test status
Simulation time 6459917887 ps
CPU time 14.81 seconds
Started Jan 25 02:11:45 AM PST 24
Finished Jan 25 02:12:01 AM PST 24
Peak memory 200004 kb
Host smart-ad6735fb-ced2-406d-aea1-442b1cea46fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364793081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3364793081
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3349249583
Short name T944
Test name
Test status
Simulation time 3939526283 ps
CPU time 39.09 seconds
Started Jan 25 02:11:25 AM PST 24
Finished Jan 25 02:12:11 AM PST 24
Peak memory 198672 kb
Host smart-d32ab894-9cd3-46af-8d57-22a10b07f6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349249583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3349249583
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3719990685
Short name T285
Test name
Test status
Simulation time 162104180236 ps
CPU time 39.86 seconds
Started Jan 25 02:11:43 AM PST 24
Finished Jan 25 02:12:24 AM PST 24
Peak memory 200072 kb
Host smart-c1118831-01c6-47b8-ba5d-6d4ae6b236da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719990685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3719990685
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2622418444
Short name T773
Test name
Test status
Simulation time 3502519489 ps
CPU time 3.28 seconds
Started Jan 25 02:11:42 AM PST 24
Finished Jan 25 02:11:46 AM PST 24
Peak memory 195492 kb
Host smart-18b115b6-db59-4b3d-9a35-79f0de96afb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622418444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2622418444
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1258327962
Short name T736
Test name
Test status
Simulation time 838234729 ps
CPU time 4.6 seconds
Started Jan 25 03:08:32 AM PST 24
Finished Jan 25 03:08:38 AM PST 24
Peak memory 199364 kb
Host smart-b252877a-e401-4334-be90-26bb014fb7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258327962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1258327962
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2586460780
Short name T703
Test name
Test status
Simulation time 493390501622 ps
CPU time 1809.04 seconds
Started Jan 25 04:34:39 AM PST 24
Finished Jan 25 05:04:54 AM PST 24
Peak memory 216048 kb
Host smart-c0b9d2b8-4627-4105-a845-7319f14db4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586460780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2586460780
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4080479665
Short name T86
Test name
Test status
Simulation time 31954545561 ps
CPU time 396.56 seconds
Started Jan 25 04:04:52 AM PST 24
Finished Jan 25 04:11:37 AM PST 24
Peak memory 216660 kb
Host smart-c6dcf99d-9697-42c2-9c8e-e9583e76eb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080479665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4080479665
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3769366045
Short name T863
Test name
Test status
Simulation time 112915584 ps
CPU time 1.03 seconds
Started Jan 25 02:58:20 AM PST 24
Finished Jan 25 02:58:22 AM PST 24
Peak memory 197904 kb
Host smart-bd3c5c5d-1cc5-4614-ba67-6af504df2687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769366045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3769366045
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2964517129
Short name T1139
Test name
Test status
Simulation time 42143042371 ps
CPU time 66.03 seconds
Started Jan 25 05:46:50 AM PST 24
Finished Jan 25 05:48:03 AM PST 24
Peak memory 200136 kb
Host smart-11e44bf7-568d-4b00-9df9-1fe0d34c1c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964517129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2964517129
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1673627194
Short name T1122
Test name
Test status
Simulation time 85399456003 ps
CPU time 142.69 seconds
Started Jan 25 02:42:26 AM PST 24
Finished Jan 25 02:45:01 AM PST 24
Peak memory 200048 kb
Host smart-5c54a1ad-f3e2-4c73-8d33-4ac4365bca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673627194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1673627194
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1502724446
Short name T183
Test name
Test status
Simulation time 35688442926 ps
CPU time 62.68 seconds
Started Jan 25 02:42:27 AM PST 24
Finished Jan 25 02:43:42 AM PST 24
Peak memory 200064 kb
Host smart-07ebad38-3e07-4f27-94c3-0d192f25b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502724446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1502724446
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2085781459
Short name T943
Test name
Test status
Simulation time 71913339366 ps
CPU time 43.21 seconds
Started Jan 25 02:42:26 AM PST 24
Finished Jan 25 02:43:22 AM PST 24
Peak memory 200044 kb
Host smart-a61c042f-8234-4a48-a77f-2d00682b3480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085781459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2085781459
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2886386924
Short name T121
Test name
Test status
Simulation time 161850612433 ps
CPU time 22.39 seconds
Started Jan 25 02:42:25 AM PST 24
Finished Jan 25 02:42:59 AM PST 24
Peak memory 199212 kb
Host smart-5792d1c6-90e4-4fdb-b4cc-525e584c392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886386924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2886386924
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3071934262
Short name T978
Test name
Test status
Simulation time 170122799187 ps
CPU time 267.91 seconds
Started Jan 25 02:42:26 AM PST 24
Finished Jan 25 02:47:05 AM PST 24
Peak memory 200036 kb
Host smart-173c5d72-6ecb-41fb-a92c-98285a4722d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071934262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3071934262
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1073265583
Short name T133
Test name
Test status
Simulation time 68854322522 ps
CPU time 119.16 seconds
Started Jan 25 02:42:27 AM PST 24
Finished Jan 25 02:44:39 AM PST 24
Peak memory 200120 kb
Host smart-d3c11c86-b734-4db5-9236-bcd1ceba53cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073265583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1073265583
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.853063332
Short name T969
Test name
Test status
Simulation time 10321294043 ps
CPU time 19.02 seconds
Started Jan 25 02:42:44 AM PST 24
Finished Jan 25 02:43:10 AM PST 24
Peak memory 200128 kb
Host smart-63381970-368f-4de5-a4de-1d6328784204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853063332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.853063332
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4151857730
Short name T246
Test name
Test status
Simulation time 173117133003 ps
CPU time 79.67 seconds
Started Jan 25 02:42:44 AM PST 24
Finished Jan 25 02:44:11 AM PST 24
Peak memory 199556 kb
Host smart-124bd7cf-151c-4cd1-b09d-4c811633b304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151857730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4151857730
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.89936049
Short name T1103
Test name
Test status
Simulation time 36246579634 ps
CPU time 35.58 seconds
Started Jan 25 02:42:44 AM PST 24
Finished Jan 25 02:43:27 AM PST 24
Peak memory 200020 kb
Host smart-fd12e93d-bf7a-42b2-9681-b98ab173067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89936049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.89936049
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.444051888
Short name T1116
Test name
Test status
Simulation time 14554046 ps
CPU time 0.6 seconds
Started Jan 25 02:12:25 AM PST 24
Finished Jan 25 02:12:27 AM PST 24
Peak memory 195700 kb
Host smart-6d82417d-801c-4b59-a24f-04eeb7f75db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444051888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.444051888
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1407251720
Short name T753
Test name
Test status
Simulation time 123468009956 ps
CPU time 46.03 seconds
Started Jan 25 02:12:05 AM PST 24
Finished Jan 25 02:12:56 AM PST 24
Peak memory 200116 kb
Host smart-9ce668df-69d9-4a8f-abeb-409c7a5c8f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407251720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1407251720
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1541344907
Short name T258
Test name
Test status
Simulation time 138354555720 ps
CPU time 59.77 seconds
Started Jan 25 02:12:06 AM PST 24
Finished Jan 25 02:13:10 AM PST 24
Peak memory 198924 kb
Host smart-cb980f17-9399-4047-8163-4a6d9b23e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541344907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1541344907
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.657697121
Short name T562
Test name
Test status
Simulation time 2423003550086 ps
CPU time 1018.44 seconds
Started Jan 25 03:14:56 AM PST 24
Finished Jan 25 03:32:02 AM PST 24
Peak memory 200092 kb
Host smart-37829214-e49a-4c49-9bbf-7e8c19da309b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657697121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.657697121
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1342880179
Short name T988
Test name
Test status
Simulation time 109849465680 ps
CPU time 604.36 seconds
Started Jan 25 02:12:24 AM PST 24
Finished Jan 25 02:22:30 AM PST 24
Peak memory 200060 kb
Host smart-79ad28c7-46c3-40a9-b0d2-0e27d1756773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342880179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1342880179
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2766467532
Short name T725
Test name
Test status
Simulation time 7913180786 ps
CPU time 4.93 seconds
Started Jan 25 02:12:24 AM PST 24
Finished Jan 25 02:12:29 AM PST 24
Peak memory 197896 kb
Host smart-152c2ca3-703e-4b36-bf43-4cc9f6f3bb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766467532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2766467532
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1750021577
Short name T599
Test name
Test status
Simulation time 10014982853 ps
CPU time 17.21 seconds
Started Jan 25 02:12:25 AM PST 24
Finished Jan 25 02:12:44 AM PST 24
Peak memory 195848 kb
Host smart-b4b1dc13-3027-4837-9a10-7eda85bcbb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750021577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1750021577
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2487809815
Short name T938
Test name
Test status
Simulation time 24177814522 ps
CPU time 246.96 seconds
Started Jan 25 02:12:27 AM PST 24
Finished Jan 25 02:16:36 AM PST 24
Peak memory 200092 kb
Host smart-08f2b34f-8a11-4bd4-822b-633233a03131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487809815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2487809815
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.185510625
Short name T1000
Test name
Test status
Simulation time 30910176918 ps
CPU time 46.6 seconds
Started Jan 25 02:12:23 AM PST 24
Finished Jan 25 02:13:11 AM PST 24
Peak memory 200004 kb
Host smart-5365b97f-f9de-41da-884e-323d7af3a8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185510625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.185510625
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3815893550
Short name T432
Test name
Test status
Simulation time 1403158707 ps
CPU time 2.97 seconds
Started Jan 25 02:12:26 AM PST 24
Finished Jan 25 02:12:31 AM PST 24
Peak memory 195568 kb
Host smart-8110e2f8-ef92-49dc-8920-9b018824005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815893550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3815893550
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3617126040
Short name T1233
Test name
Test status
Simulation time 748421587 ps
CPU time 1.85 seconds
Started Jan 25 02:53:15 AM PST 24
Finished Jan 25 02:53:19 AM PST 24
Peak memory 198348 kb
Host smart-9266c04f-b1a2-4a3c-8efa-a18aab5c707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617126040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3617126040
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2649053948
Short name T266
Test name
Test status
Simulation time 266656703492 ps
CPU time 1345.99 seconds
Started Jan 25 02:12:26 AM PST 24
Finished Jan 25 02:34:53 AM PST 24
Peak memory 200128 kb
Host smart-b9491fda-f9aa-4da9-9131-91083bb2ad22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649053948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2649053948
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.4253106307
Short name T524
Test name
Test status
Simulation time 1001588944 ps
CPU time 3.51 seconds
Started Jan 25 02:12:26 AM PST 24
Finished Jan 25 02:12:31 AM PST 24
Peak memory 198544 kb
Host smart-26c09b28-341e-428f-9a49-4cf4476486d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253106307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.4253106307
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3157748762
Short name T769
Test name
Test status
Simulation time 28217726472 ps
CPU time 11.62 seconds
Started Jan 25 02:12:05 AM PST 24
Finished Jan 25 02:12:21 AM PST 24
Peak memory 197508 kb
Host smart-01ed5790-dd57-43a1-adcd-f7ea05e5cbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157748762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3157748762
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.990607957
Short name T1042
Test name
Test status
Simulation time 25833908344 ps
CPU time 48.55 seconds
Started Jan 25 02:45:48 AM PST 24
Finished Jan 25 02:46:38 AM PST 24
Peak memory 199824 kb
Host smart-eac43bf5-8b98-47ee-814c-967c96232c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990607957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.990607957
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.4006027224
Short name T926
Test name
Test status
Simulation time 132461564235 ps
CPU time 56.98 seconds
Started Jan 25 02:43:09 AM PST 24
Finished Jan 25 02:44:16 AM PST 24
Peak memory 199972 kb
Host smart-3055c0bb-0b85-42af-8479-f4bef9bfcc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006027224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4006027224
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1181147806
Short name T117
Test name
Test status
Simulation time 37516028312 ps
CPU time 33.79 seconds
Started Jan 25 02:43:13 AM PST 24
Finished Jan 25 02:43:56 AM PST 24
Peak memory 200100 kb
Host smart-535bef2e-fd10-4c3d-aa5c-6d960cf8674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181147806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1181147806
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.440093314
Short name T1054
Test name
Test status
Simulation time 408902140242 ps
CPU time 62.27 seconds
Started Jan 25 02:43:10 AM PST 24
Finished Jan 25 02:44:23 AM PST 24
Peak memory 200028 kb
Host smart-88eb7a0c-3a31-4f08-87c7-40f37c6f8a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440093314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.440093314
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4096753597
Short name T196
Test name
Test status
Simulation time 132895238088 ps
CPU time 217.71 seconds
Started Jan 25 02:43:25 AM PST 24
Finished Jan 25 02:47:16 AM PST 24
Peak memory 200096 kb
Host smart-931a2a6f-aab9-43f3-9212-8104bcc749b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096753597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4096753597
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2491054175
Short name T1185
Test name
Test status
Simulation time 15473731 ps
CPU time 0.6 seconds
Started Jan 25 03:28:20 AM PST 24
Finished Jan 25 03:28:21 AM PST 24
Peak memory 195708 kb
Host smart-a7bb260a-8da1-485d-b11e-f0124b7fefa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491054175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2491054175
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1291242059
Short name T761
Test name
Test status
Simulation time 130762527705 ps
CPU time 128.6 seconds
Started Jan 25 02:12:25 AM PST 24
Finished Jan 25 02:14:35 AM PST 24
Peak memory 200092 kb
Host smart-44f92774-3807-4e52-a0a7-7e69f3f1dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291242059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1291242059
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1707390950
Short name T645
Test name
Test status
Simulation time 124805302619 ps
CPU time 199.72 seconds
Started Jan 25 02:12:45 AM PST 24
Finished Jan 25 02:16:07 AM PST 24
Peak memory 200052 kb
Host smart-08fa066c-0d49-4b13-a25a-fdfc9415e36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707390950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1707390950
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.606935821
Short name T879
Test name
Test status
Simulation time 377662001651 ps
CPU time 37.36 seconds
Started Jan 25 02:12:43 AM PST 24
Finished Jan 25 02:13:24 AM PST 24
Peak memory 200016 kb
Host smart-e711ac04-17cd-4efa-b25c-3cdd50b354b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606935821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.606935821
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.120451331
Short name T226
Test name
Test status
Simulation time 137039060135 ps
CPU time 233.17 seconds
Started Jan 25 02:12:45 AM PST 24
Finished Jan 25 02:16:40 AM PST 24
Peak memory 200072 kb
Host smart-c398ec2d-04ee-4c16-a262-f974a10f9d25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120451331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.120451331
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.323078989
Short name T614
Test name
Test status
Simulation time 199666627994 ps
CPU time 97.08 seconds
Started Jan 25 02:12:58 AM PST 24
Finished Jan 25 02:14:36 AM PST 24
Peak memory 200108 kb
Host smart-bb2952fa-f70f-41ea-85bf-36b8722960cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323078989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.323078989
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2053326816
Short name T490
Test name
Test status
Simulation time 2049225646 ps
CPU time 2.46 seconds
Started Jan 25 02:12:54 AM PST 24
Finished Jan 25 02:12:57 AM PST 24
Peak memory 196908 kb
Host smart-45b81c32-0359-483d-98e8-ae2ef5d6dd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053326816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2053326816
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3608095931
Short name T847
Test name
Test status
Simulation time 41375470464 ps
CPU time 61.71 seconds
Started Jan 25 02:12:44 AM PST 24
Finished Jan 25 02:13:49 AM PST 24
Peak memory 199892 kb
Host smart-27024a20-836f-4810-bf9e-c5b45fc36d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608095931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3608095931
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2103566335
Short name T889
Test name
Test status
Simulation time 38630122027 ps
CPU time 424.26 seconds
Started Jan 25 04:34:24 AM PST 24
Finished Jan 25 04:41:31 AM PST 24
Peak memory 200088 kb
Host smart-af049993-6a97-4d65-8072-5083246b007a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103566335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2103566335
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.371934328
Short name T666
Test name
Test status
Simulation time 1443769279 ps
CPU time 4.23 seconds
Started Jan 25 02:12:40 AM PST 24
Finished Jan 25 02:12:48 AM PST 24
Peak memory 197552 kb
Host smart-2325c7df-b750-4a7d-beda-d051589d7045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371934328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.371934328
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.363107939
Short name T1044
Test name
Test status
Simulation time 194630601400 ps
CPU time 108.86 seconds
Started Jan 25 02:12:53 AM PST 24
Finished Jan 25 02:14:44 AM PST 24
Peak memory 200112 kb
Host smart-424dd6da-1551-4e84-9b67-20ffaf913965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363107939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.363107939
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.240987489
Short name T758
Test name
Test status
Simulation time 3290049593 ps
CPU time 6.27 seconds
Started Jan 25 02:12:52 AM PST 24
Finished Jan 25 02:13:00 AM PST 24
Peak memory 195600 kb
Host smart-c56299fd-1164-4973-b163-2c9e27067df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240987489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.240987489
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.153710245
Short name T22
Test name
Test status
Simulation time 693696241 ps
CPU time 1.6 seconds
Started Jan 25 02:12:27 AM PST 24
Finished Jan 25 02:12:30 AM PST 24
Peak memory 199080 kb
Host smart-3df15eb7-7b3e-4d36-bdcc-9d72e11c0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153710245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.153710245
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1351003885
Short name T1119
Test name
Test status
Simulation time 79908427088 ps
CPU time 1411.31 seconds
Started Jan 25 02:12:56 AM PST 24
Finished Jan 25 02:36:28 AM PST 24
Peak memory 216188 kb
Host smart-810b7540-7c7c-46a6-bd26-8d64227f10d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351003885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1351003885
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3728344499
Short name T529
Test name
Test status
Simulation time 6727429403 ps
CPU time 23.19 seconds
Started Jan 25 02:12:53 AM PST 24
Finished Jan 25 02:13:18 AM PST 24
Peak memory 200104 kb
Host smart-21b27315-77ea-4e67-9b6d-ae247f102622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728344499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3728344499
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3251181984
Short name T908
Test name
Test status
Simulation time 56063516660 ps
CPU time 99.15 seconds
Started Jan 25 02:12:31 AM PST 24
Finished Jan 25 02:14:11 AM PST 24
Peak memory 200144 kb
Host smart-df0b433a-77a8-46c9-bbb9-db0b92a24443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251181984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3251181984
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.499639694
Short name T1004
Test name
Test status
Simulation time 8146086074 ps
CPU time 17.7 seconds
Started Jan 25 03:12:18 AM PST 24
Finished Jan 25 03:12:43 AM PST 24
Peak memory 199816 kb
Host smart-c24caac8-a29b-4938-879f-255621c5f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499639694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.499639694
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.4209055950
Short name T1198
Test name
Test status
Simulation time 153436961937 ps
CPU time 276 seconds
Started Jan 25 02:43:25 AM PST 24
Finished Jan 25 02:48:14 AM PST 24
Peak memory 200044 kb
Host smart-16da4273-8480-4678-bdcc-1d066877335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209055950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4209055950
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3003229823
Short name T1168
Test name
Test status
Simulation time 22857569097 ps
CPU time 9.57 seconds
Started Jan 25 02:43:23 AM PST 24
Finished Jan 25 02:43:46 AM PST 24
Peak memory 199872 kb
Host smart-65e733a3-dd3e-4392-ad4a-33d0a7da20ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003229823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3003229823
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1144125476
Short name T845
Test name
Test status
Simulation time 22550960434 ps
CPU time 41.15 seconds
Started Jan 25 02:56:20 AM PST 24
Finished Jan 25 02:57:04 AM PST 24
Peak memory 200060 kb
Host smart-cf14fc9e-4b46-4361-b0a5-af4d9c67b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144125476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1144125476
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2832251554
Short name T651
Test name
Test status
Simulation time 217433697609 ps
CPU time 92.35 seconds
Started Jan 25 04:08:52 AM PST 24
Finished Jan 25 04:10:26 AM PST 24
Peak memory 200004 kb
Host smart-b229c024-d47a-4509-b825-cfc23f9fe979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832251554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2832251554
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3562637154
Short name T207
Test name
Test status
Simulation time 316970852250 ps
CPU time 96.46 seconds
Started Jan 25 02:43:27 AM PST 24
Finished Jan 25 02:45:15 AM PST 24
Peak memory 199876 kb
Host smart-742c5ec7-ec59-4202-b12e-c992eab9e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562637154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3562637154
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2847758997
Short name T157
Test name
Test status
Simulation time 119967250655 ps
CPU time 192.49 seconds
Started Jan 25 02:43:48 AM PST 24
Finished Jan 25 02:47:07 AM PST 24
Peak memory 199292 kb
Host smart-56bb2a06-3daa-4525-900f-2a15e60e0e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847758997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2847758997
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.302950802
Short name T680
Test name
Test status
Simulation time 21529079146 ps
CPU time 17.65 seconds
Started Jan 25 02:43:46 AM PST 24
Finished Jan 25 02:44:09 AM PST 24
Peak memory 198000 kb
Host smart-810ccf8d-b9a3-42cb-a7a7-1fe051af05e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302950802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.302950802
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3804829066
Short name T1078
Test name
Test status
Simulation time 14729529 ps
CPU time 0.6 seconds
Started Jan 25 02:13:48 AM PST 24
Finished Jan 25 02:13:49 AM PST 24
Peak memory 195708 kb
Host smart-1a6db970-b0e5-4d01-9254-b623f4dfe030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804829066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3804829066
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2895990697
Short name T726
Test name
Test status
Simulation time 22015719187 ps
CPU time 40.52 seconds
Started Jan 25 02:13:45 AM PST 24
Finished Jan 25 02:14:27 AM PST 24
Peak memory 199636 kb
Host smart-d80afc58-aba9-41c1-a2a1-356b78eb6651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895990697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2895990697
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3936782666
Short name T708
Test name
Test status
Simulation time 20379323714 ps
CPU time 32.4 seconds
Started Jan 25 02:13:49 AM PST 24
Finished Jan 25 02:14:23 AM PST 24
Peak memory 198096 kb
Host smart-71fa24ec-6fa4-4851-bec3-5c36ad611389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936782666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3936782666
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2035002753
Short name T1157
Test name
Test status
Simulation time 37280874565 ps
CPU time 26.23 seconds
Started Jan 25 02:13:55 AM PST 24
Finished Jan 25 02:14:22 AM PST 24
Peak memory 199884 kb
Host smart-55e70ad4-cba3-4b83-85ec-21aea2930e34
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035002753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2035002753
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1054113537
Short name T993
Test name
Test status
Simulation time 179022906944 ps
CPU time 341.05 seconds
Started Jan 25 03:54:40 AM PST 24
Finished Jan 25 04:00:22 AM PST 24
Peak memory 200092 kb
Host smart-e2ac3156-7b09-4cce-a893-3a741cbbc29a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1054113537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1054113537
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2960623647
Short name T553
Test name
Test status
Simulation time 11353656314 ps
CPU time 17.56 seconds
Started Jan 25 02:13:49 AM PST 24
Finished Jan 25 02:14:08 AM PST 24
Peak memory 198696 kb
Host smart-62381018-9cd7-45dc-aa89-032ae7b0dd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960623647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2960623647
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.448195057
Short name T749
Test name
Test status
Simulation time 45662526025 ps
CPU time 38.87 seconds
Started Jan 25 02:13:51 AM PST 24
Finished Jan 25 02:14:31 AM PST 24
Peak memory 199284 kb
Host smart-b47026ce-b243-444a-865d-ce4e77e426a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448195057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.448195057
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1507797827
Short name T1066
Test name
Test status
Simulation time 3641191189 ps
CPU time 9.08 seconds
Started Jan 25 02:13:49 AM PST 24
Finished Jan 25 02:13:59 AM PST 24
Peak memory 198332 kb
Host smart-09a9e07c-5d8b-4740-98ec-b56ce1c7cf20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507797827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1507797827
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.2598107460
Short name T952
Test name
Test status
Simulation time 33627919627 ps
CPU time 17.46 seconds
Started Jan 25 02:13:55 AM PST 24
Finished Jan 25 02:14:13 AM PST 24
Peak memory 199136 kb
Host smart-51d135b1-91c8-42a7-a915-0fc0789e42a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598107460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2598107460
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3004608841
Short name T716
Test name
Test status
Simulation time 1938677857 ps
CPU time 2.43 seconds
Started Jan 25 02:13:48 AM PST 24
Finished Jan 25 02:13:52 AM PST 24
Peak memory 195580 kb
Host smart-ef27edc4-9647-448f-93a5-496211722eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004608841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3004608841
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1790007702
Short name T825
Test name
Test status
Simulation time 552772210 ps
CPU time 1.59 seconds
Started Jan 25 02:13:25 AM PST 24
Finished Jan 25 02:13:27 AM PST 24
Peak memory 198192 kb
Host smart-d52cff55-abb2-4dd8-94f6-48f9a64a03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790007702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1790007702
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3949032169
Short name T253
Test name
Test status
Simulation time 302663388197 ps
CPU time 933.94 seconds
Started Jan 25 02:13:50 AM PST 24
Finished Jan 25 02:29:26 AM PST 24
Peak memory 216072 kb
Host smart-adb097d4-d9f4-4b56-8fa1-d805952b43a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949032169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3949032169
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2038203819
Short name T248
Test name
Test status
Simulation time 88594907689 ps
CPU time 276.1 seconds
Started Jan 25 02:13:58 AM PST 24
Finished Jan 25 02:18:35 AM PST 24
Peak memory 215160 kb
Host smart-dfb37995-a902-4895-96b2-63525e897f60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038203819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2038203819
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1712174642
Short name T671
Test name
Test status
Simulation time 7146107198 ps
CPU time 14.52 seconds
Started Jan 25 05:02:15 AM PST 24
Finished Jan 25 05:02:30 AM PST 24
Peak memory 199536 kb
Host smart-b5f01de3-d7d3-4015-af01-b6d628755271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712174642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1712174642
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.4137925296
Short name T597
Test name
Test status
Simulation time 86509661963 ps
CPU time 208.31 seconds
Started Jan 25 02:13:26 AM PST 24
Finished Jan 25 02:16:55 AM PST 24
Peak memory 200076 kb
Host smart-835b3056-daf5-4db4-a38a-01ff7c8209dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137925296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4137925296
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2357112990
Short name T915
Test name
Test status
Simulation time 21115514270 ps
CPU time 38.38 seconds
Started Jan 25 02:43:44 AM PST 24
Finished Jan 25 02:44:27 AM PST 24
Peak memory 199948 kb
Host smart-6f255e68-f371-4fc0-894f-ba66deb3b4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357112990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2357112990
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.103703197
Short name T1114
Test name
Test status
Simulation time 32404871801 ps
CPU time 47.21 seconds
Started Jan 25 02:43:44 AM PST 24
Finished Jan 25 02:44:35 AM PST 24
Peak memory 199752 kb
Host smart-63da283c-7532-484a-8a76-55ede02450e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103703197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.103703197
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3126169744
Short name T329
Test name
Test status
Simulation time 145911277307 ps
CPU time 69.07 seconds
Started Jan 25 02:43:44 AM PST 24
Finished Jan 25 02:44:58 AM PST 24
Peak memory 199628 kb
Host smart-4168c563-e01b-49fb-a89b-0d6b62da6a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126169744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3126169744
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1331257848
Short name T224
Test name
Test status
Simulation time 35038002434 ps
CPU time 15.69 seconds
Started Jan 25 02:43:45 AM PST 24
Finished Jan 25 02:44:06 AM PST 24
Peak memory 200092 kb
Host smart-b22df3af-25c2-46c3-bbed-2aae115abad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331257848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1331257848
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1744822201
Short name T147
Test name
Test status
Simulation time 13401581406 ps
CPU time 28.28 seconds
Started Jan 25 02:43:53 AM PST 24
Finished Jan 25 02:44:29 AM PST 24
Peak memory 200120 kb
Host smart-de00c889-d18f-4bb9-afeb-105df28e489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744822201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1744822201
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.261505144
Short name T375
Test name
Test status
Simulation time 48687744489 ps
CPU time 83.37 seconds
Started Jan 25 02:43:54 AM PST 24
Finished Jan 25 02:45:24 AM PST 24
Peak memory 200040 kb
Host smart-ba51e203-6fbe-4d07-af11-6b2f920270ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261505144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.261505144
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3424798288
Short name T1187
Test name
Test status
Simulation time 103842999386 ps
CPU time 37.6 seconds
Started Jan 25 02:43:56 AM PST 24
Finished Jan 25 02:44:40 AM PST 24
Peak memory 200068 kb
Host smart-3070745f-18af-4233-9a83-878c7e74f871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424798288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3424798288
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3309352018
Short name T371
Test name
Test status
Simulation time 30618567254 ps
CPU time 45.53 seconds
Started Jan 25 02:43:56 AM PST 24
Finished Jan 25 02:44:48 AM PST 24
Peak memory 199888 kb
Host smart-e16cdc60-edad-4b7e-a124-420032167c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309352018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3309352018
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2849355535
Short name T929
Test name
Test status
Simulation time 38197568953 ps
CPU time 18.14 seconds
Started Jan 25 02:43:55 AM PST 24
Finished Jan 25 02:44:20 AM PST 24
Peak memory 199684 kb
Host smart-1f67f5b9-7870-4e74-bda1-816e92be0bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849355535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2849355535
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.853460022
Short name T168
Test name
Test status
Simulation time 54922182945 ps
CPU time 81.45 seconds
Started Jan 25 02:43:55 AM PST 24
Finished Jan 25 02:45:23 AM PST 24
Peak memory 200088 kb
Host smart-ec6ac9e2-7861-42fe-bf43-39dd0246d707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853460022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.853460022
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3019953101
Short name T1019
Test name
Test status
Simulation time 30470281 ps
CPU time 0.58 seconds
Started Jan 25 02:14:20 AM PST 24
Finished Jan 25 02:14:22 AM PST 24
Peak memory 195712 kb
Host smart-40f4c9e1-26f0-49aa-aa48-8e7461b2fdb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019953101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3019953101
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.713935313
Short name T209
Test name
Test status
Simulation time 29065301652 ps
CPU time 49.2 seconds
Started Jan 25 02:14:04 AM PST 24
Finished Jan 25 02:14:55 AM PST 24
Peak memory 200060 kb
Host smart-8ac7f2ca-c149-47ab-8bdd-ff93c5c20539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713935313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.713935313
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3322671835
Short name T594
Test name
Test status
Simulation time 249847211973 ps
CPU time 185.23 seconds
Started Jan 25 05:41:20 AM PST 24
Finished Jan 25 05:44:26 AM PST 24
Peak memory 200156 kb
Host smart-275e2b1e-8167-4bd8-b808-4003159f5baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322671835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3322671835
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.479401548
Short name T798
Test name
Test status
Simulation time 39589384029 ps
CPU time 29.91 seconds
Started Jan 25 03:00:52 AM PST 24
Finished Jan 25 03:01:24 AM PST 24
Peak memory 200072 kb
Host smart-186f1146-1a59-46b5-9e8e-53e7f4794a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479401548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.479401548
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4120335849
Short name T227
Test name
Test status
Simulation time 798777874777 ps
CPU time 1441.27 seconds
Started Jan 25 04:03:07 AM PST 24
Finished Jan 25 04:27:13 AM PST 24
Peak memory 200048 kb
Host smart-e1f54a94-2ef2-416c-938e-942dc8cada54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120335849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4120335849
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2878577831
Short name T500
Test name
Test status
Simulation time 128584766211 ps
CPU time 871.49 seconds
Started Jan 25 02:14:21 AM PST 24
Finished Jan 25 02:28:53 AM PST 24
Peak memory 200124 kb
Host smart-9eed8e12-f884-4e0a-ba2f-edcdc7b29b8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878577831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2878577831
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.4087681642
Short name T707
Test name
Test status
Simulation time 9995837532 ps
CPU time 6.54 seconds
Started Jan 25 02:14:14 AM PST 24
Finished Jan 25 02:14:21 AM PST 24
Peak memory 199160 kb
Host smart-c81ccdd9-b058-41f3-af61-b299bab109fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087681642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.4087681642
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.1196668457
Short name T865
Test name
Test status
Simulation time 117624372508 ps
CPU time 280.53 seconds
Started Jan 25 02:13:57 AM PST 24
Finished Jan 25 02:18:39 AM PST 24
Peak memory 198700 kb
Host smart-102579c8-220c-4b7b-a46e-87435db05af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196668457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.1196668457
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1926266187
Short name T525
Test name
Test status
Simulation time 27914191085 ps
CPU time 362.7 seconds
Started Jan 25 02:14:17 AM PST 24
Finished Jan 25 02:20:20 AM PST 24
Peak memory 200140 kb
Host smart-f5a7ef74-17d5-4eea-9edd-e9851be3eac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926266187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1926266187
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2897959076
Short name T518
Test name
Test status
Simulation time 1570189331 ps
CPU time 5.86 seconds
Started Jan 25 02:34:43 AM PST 24
Finished Jan 25 02:34:53 AM PST 24
Peak memory 198184 kb
Host smart-d327c26b-9ff8-46a1-9e60-4f7c006592fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897959076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2897959076
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3598765711
Short name T995
Test name
Test status
Simulation time 360699764333 ps
CPU time 131.62 seconds
Started Jan 25 02:14:12 AM PST 24
Finished Jan 25 02:16:25 AM PST 24
Peak memory 199956 kb
Host smart-51f1bdd2-4a30-4fcd-b305-d955c4042820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598765711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3598765711
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4030670199
Short name T400
Test name
Test status
Simulation time 32483647823 ps
CPU time 27.66 seconds
Started Jan 25 03:18:56 AM PST 24
Finished Jan 25 03:19:24 AM PST 24
Peak memory 195756 kb
Host smart-9ea7651e-acd5-4615-b241-a7b90650719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030670199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4030670199
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3040918194
Short name T807
Test name
Test status
Simulation time 928278711 ps
CPU time 4.17 seconds
Started Jan 25 02:13:52 AM PST 24
Finished Jan 25 02:13:58 AM PST 24
Peak memory 198260 kb
Host smart-1cc3066f-47b3-4326-85c1-395b61f99614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040918194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3040918194
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2970167700
Short name T844
Test name
Test status
Simulation time 1302506772 ps
CPU time 1.84 seconds
Started Jan 25 02:14:17 AM PST 24
Finished Jan 25 02:14:20 AM PST 24
Peak memory 197476 kb
Host smart-ac484e81-9a24-4bf7-813b-f2f8d245f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970167700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2970167700
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3375645207
Short name T855
Test name
Test status
Simulation time 83618872178 ps
CPU time 119.36 seconds
Started Jan 25 02:13:52 AM PST 24
Finished Jan 25 02:15:53 AM PST 24
Peak memory 200052 kb
Host smart-342b49ab-674e-4885-b334-9c60922d4c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375645207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3375645207
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.939112980
Short name T21
Test name
Test status
Simulation time 140456874813 ps
CPU time 94.85 seconds
Started Jan 25 02:43:53 AM PST 24
Finished Jan 25 02:45:35 AM PST 24
Peak memory 199452 kb
Host smart-20c12db0-78fb-41a9-88fa-b77a708942b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939112980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.939112980
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1932300543
Short name T342
Test name
Test status
Simulation time 16314797323 ps
CPU time 37.78 seconds
Started Jan 25 02:44:07 AM PST 24
Finished Jan 25 02:44:50 AM PST 24
Peak memory 199792 kb
Host smart-2249535b-fb66-4c8c-ac22-87a52e442f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932300543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1932300543
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3905413491
Short name T276
Test name
Test status
Simulation time 14072882635 ps
CPU time 20.26 seconds
Started Jan 25 02:44:08 AM PST 24
Finished Jan 25 02:44:32 AM PST 24
Peak memory 200060 kb
Host smart-a0ef58a3-d648-401e-9549-afe0f123aac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905413491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3905413491
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.331067492
Short name T747
Test name
Test status
Simulation time 10695601120 ps
CPU time 16.56 seconds
Started Jan 25 02:44:06 AM PST 24
Finished Jan 25 02:44:28 AM PST 24
Peak memory 200120 kb
Host smart-46e71363-1c50-4676-8cad-369bc02e42f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331067492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.331067492
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.4040286186
Short name T1219
Test name
Test status
Simulation time 49630254347 ps
CPU time 30.51 seconds
Started Jan 25 02:44:06 AM PST 24
Finished Jan 25 02:44:41 AM PST 24
Peak memory 200036 kb
Host smart-493a7a4c-3dbe-457e-b670-349e9324773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040286186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4040286186
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.732544652
Short name T154
Test name
Test status
Simulation time 33661735457 ps
CPU time 15.16 seconds
Started Jan 25 02:44:10 AM PST 24
Finished Jan 25 02:44:30 AM PST 24
Peak memory 200104 kb
Host smart-36c12556-8fd3-432b-86a7-089b0ea6c837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732544652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.732544652
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.129678235
Short name T125
Test name
Test status
Simulation time 70225011203 ps
CPU time 19.29 seconds
Started Jan 25 02:44:09 AM PST 24
Finished Jan 25 02:44:33 AM PST 24
Peak memory 200052 kb
Host smart-52509664-759a-487f-bf39-a20d8e3d1bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129678235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.129678235
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.957827996
Short name T921
Test name
Test status
Simulation time 136099207740 ps
CPU time 62.4 seconds
Started Jan 25 02:44:20 AM PST 24
Finished Jan 25 02:45:26 AM PST 24
Peak memory 199548 kb
Host smart-fdb89fd7-d572-4bdd-9364-bc528d926873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957827996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.957827996
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1318056605
Short name T717
Test name
Test status
Simulation time 12185987 ps
CPU time 0.59 seconds
Started Jan 25 02:15:09 AM PST 24
Finished Jan 25 02:15:11 AM PST 24
Peak memory 194692 kb
Host smart-7a4a5f26-ea52-4e9a-8538-7e2631075662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318056605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1318056605
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3793636775
Short name T928
Test name
Test status
Simulation time 52654646478 ps
CPU time 30.75 seconds
Started Jan 25 02:14:14 AM PST 24
Finished Jan 25 02:14:45 AM PST 24
Peak memory 199956 kb
Host smart-cb8a4fbc-b4a3-4220-a2b5-1403cc89d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793636775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3793636775
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.558228153
Short name T668
Test name
Test status
Simulation time 98338221068 ps
CPU time 158.24 seconds
Started Jan 25 02:14:19 AM PST 24
Finished Jan 25 02:16:58 AM PST 24
Peak memory 200116 kb
Host smart-ea8ed7b4-4a64-4842-8308-638bf1c7d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558228153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.558228153
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2440010064
Short name T198
Test name
Test status
Simulation time 64592091689 ps
CPU time 30.06 seconds
Started Jan 25 02:14:17 AM PST 24
Finished Jan 25 02:14:47 AM PST 24
Peak memory 200040 kb
Host smart-5e9a9d5a-215f-4508-9749-fe5de8ee8507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440010064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2440010064
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3321484228
Short name T864
Test name
Test status
Simulation time 190136149299 ps
CPU time 238.62 seconds
Started Jan 25 05:02:27 AM PST 24
Finished Jan 25 05:06:50 AM PST 24
Peak memory 199032 kb
Host smart-11e7b51b-472a-471e-97ae-b8ead9bcfcbf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321484228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3321484228
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3529472393
Short name T712
Test name
Test status
Simulation time 79341628910 ps
CPU time 697.42 seconds
Started Jan 25 02:15:09 AM PST 24
Finished Jan 25 02:26:47 AM PST 24
Peak memory 200120 kb
Host smart-fbf09e04-601e-42e0-8b81-d25e6ff59cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3529472393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3529472393
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1921035798
Short name T1060
Test name
Test status
Simulation time 81778121349 ps
CPU time 141.11 seconds
Started Jan 25 03:36:02 AM PST 24
Finished Jan 25 03:38:36 AM PST 24
Peak memory 208380 kb
Host smart-faa074cb-6340-44fb-95cc-1ae17454b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921035798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1921035798
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.151929673
Short name T235
Test name
Test status
Simulation time 18157122847 ps
CPU time 1058.19 seconds
Started Jan 25 02:15:10 AM PST 24
Finished Jan 25 02:32:49 AM PST 24
Peak memory 200076 kb
Host smart-26c6852e-fcd5-4150-802a-2700e9186e72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151929673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.151929673
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1982315200
Short name T601
Test name
Test status
Simulation time 4294587085 ps
CPU time 35.11 seconds
Started Jan 25 02:14:44 AM PST 24
Finished Jan 25 02:15:21 AM PST 24
Peak memory 198632 kb
Host smart-c80d7bcc-6f0f-4f3c-abf5-55e39c24d657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982315200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1982315200
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.574498204
Short name T1065
Test name
Test status
Simulation time 142918868152 ps
CPU time 55.31 seconds
Started Jan 25 03:52:10 AM PST 24
Finished Jan 25 03:53:07 AM PST 24
Peak memory 198648 kb
Host smart-670168ce-b38e-45b8-88cf-7ef5bbfd18c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574498204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.574498204
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.591885869
Short name T428
Test name
Test status
Simulation time 3953336392 ps
CPU time 3.5 seconds
Started Jan 25 03:14:36 AM PST 24
Finished Jan 25 03:14:41 AM PST 24
Peak memory 195612 kb
Host smart-f57b7926-04a6-400c-8ab6-2a8ecdcc8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591885869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.591885869
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1913710212
Short name T593
Test name
Test status
Simulation time 154156058 ps
CPU time 0.88 seconds
Started Jan 25 02:14:20 AM PST 24
Finished Jan 25 02:14:21 AM PST 24
Peak memory 197492 kb
Host smart-fd8d276d-f4b6-4627-a792-e9e0b5d70074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913710212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1913710212
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2793397463
Short name T282
Test name
Test status
Simulation time 197943159922 ps
CPU time 366.27 seconds
Started Jan 25 02:15:13 AM PST 24
Finished Jan 25 02:21:20 AM PST 24
Peak memory 216096 kb
Host smart-e120ce04-610c-479e-8b62-29f958734788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793397463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2793397463
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3401538833
Short name T27
Test name
Test status
Simulation time 69457843040 ps
CPU time 787.32 seconds
Started Jan 25 02:15:10 AM PST 24
Finished Jan 25 02:28:19 AM PST 24
Peak memory 224992 kb
Host smart-eacd8f5f-8ab2-4a77-be6c-fe710df63c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401538833 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3401538833
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1515584536
Short name T1199
Test name
Test status
Simulation time 1362403779 ps
CPU time 2.29 seconds
Started Jan 25 02:15:09 AM PST 24
Finished Jan 25 02:15:12 AM PST 24
Peak memory 198552 kb
Host smart-dd17c4e6-f7b7-4729-90ef-496331458aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515584536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1515584536
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4150559070
Short name T427
Test name
Test status
Simulation time 16590637973 ps
CPU time 41.84 seconds
Started Jan 25 02:14:14 AM PST 24
Finished Jan 25 02:14:57 AM PST 24
Peak memory 199520 kb
Host smart-f88c9d3d-7a68-459e-87d1-6f65eab0a560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150559070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4150559070
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.299853413
Short name T540
Test name
Test status
Simulation time 19156828817 ps
CPU time 34.28 seconds
Started Jan 25 02:44:25 AM PST 24
Finished Jan 25 02:45:02 AM PST 24
Peak memory 200100 kb
Host smart-1a8581fe-f0be-4efa-baca-8d4072878c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299853413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.299853413
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.219861815
Short name T679
Test name
Test status
Simulation time 9891536427 ps
CPU time 21.05 seconds
Started Jan 25 02:44:21 AM PST 24
Finished Jan 25 02:44:45 AM PST 24
Peak memory 199652 kb
Host smart-9542fef8-0594-43ed-9ff4-5beb2630a635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219861815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.219861815
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3794712834
Short name T1028
Test name
Test status
Simulation time 4959147267 ps
CPU time 11.07 seconds
Started Jan 25 02:44:33 AM PST 24
Finished Jan 25 02:44:46 AM PST 24
Peak memory 200040 kb
Host smart-ec58663d-d7eb-4473-a6cd-486cd7dea3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794712834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3794712834
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1180767352
Short name T1068
Test name
Test status
Simulation time 32727283040 ps
CPU time 30.62 seconds
Started Jan 25 02:44:34 AM PST 24
Finished Jan 25 02:45:06 AM PST 24
Peak memory 200112 kb
Host smart-b071156f-a0d9-44cb-8fc7-67faaf9c1518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180767352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1180767352
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1904545796
Short name T269
Test name
Test status
Simulation time 85838441867 ps
CPU time 38.02 seconds
Started Jan 25 02:44:33 AM PST 24
Finished Jan 25 02:45:13 AM PST 24
Peak memory 199956 kb
Host smart-28f422df-0949-42b3-bba0-89fd71b953ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904545796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1904545796
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2366902529
Short name T637
Test name
Test status
Simulation time 30260551743 ps
CPU time 15.85 seconds
Started Jan 25 02:44:36 AM PST 24
Finished Jan 25 02:44:54 AM PST 24
Peak memory 200052 kb
Host smart-29642a30-b4a6-4983-b0ba-e983ef586307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366902529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2366902529
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.260047647
Short name T745
Test name
Test status
Simulation time 37742957672 ps
CPU time 18.3 seconds
Started Jan 25 02:44:50 AM PST 24
Finished Jan 25 02:45:10 AM PST 24
Peak memory 200068 kb
Host smart-3d23258b-3fd6-4c77-8c99-f597d492ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260047647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.260047647
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3582410755
Short name T506
Test name
Test status
Simulation time 96845588307 ps
CPU time 42.48 seconds
Started Jan 25 02:44:49 AM PST 24
Finished Jan 25 02:45:33 AM PST 24
Peak memory 200080 kb
Host smart-2a2d32a9-e20e-45f3-bb5c-8f7346eaded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582410755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3582410755
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3943064276
Short name T1162
Test name
Test status
Simulation time 76052105489 ps
CPU time 117.46 seconds
Started Jan 25 02:44:51 AM PST 24
Finished Jan 25 02:46:49 AM PST 24
Peak memory 199692 kb
Host smart-f1a60724-943f-420a-9437-b1286dee3a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943064276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3943064276
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.154740302
Short name T1160
Test name
Test status
Simulation time 34781451 ps
CPU time 0.55 seconds
Started Jan 25 02:33:19 AM PST 24
Finished Jan 25 02:33:25 AM PST 24
Peak memory 194680 kb
Host smart-148db259-a4a4-48e0-8007-f3b11fb48b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154740302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.154740302
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3436573402
Short name T1224
Test name
Test status
Simulation time 543369275646 ps
CPU time 254.72 seconds
Started Jan 25 02:09:03 AM PST 24
Finished Jan 25 02:13:21 AM PST 24
Peak memory 200044 kb
Host smart-0d1ff812-453f-4871-9ee1-60dc523f00dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436573402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3436573402
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1343104450
Short name T555
Test name
Test status
Simulation time 23447185237 ps
CPU time 38.11 seconds
Started Jan 25 01:59:59 AM PST 24
Finished Jan 25 02:00:38 AM PST 24
Peak memory 200004 kb
Host smart-85e4a97c-0d68-4303-afb4-e2223790db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343104450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1343104450
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.106701540
Short name T1057
Test name
Test status
Simulation time 25970447124 ps
CPU time 58.07 seconds
Started Jan 25 02:00:01 AM PST 24
Finished Jan 25 02:01:01 AM PST 24
Peak memory 199804 kb
Host smart-b60c87a0-c4f5-4f5b-9184-a03ec5582513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106701540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.106701540
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.994376692
Short name T661
Test name
Test status
Simulation time 44036427099 ps
CPU time 82.92 seconds
Started Jan 25 02:00:36 AM PST 24
Finished Jan 25 02:02:00 AM PST 24
Peak memory 199068 kb
Host smart-155446e7-a928-4776-90b2-72e845a7e55a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994376692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.994376692
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2859249045
Short name T744
Test name
Test status
Simulation time 80087102384 ps
CPU time 375.49 seconds
Started Jan 25 02:01:39 AM PST 24
Finished Jan 25 02:07:59 AM PST 24
Peak memory 200116 kb
Host smart-b3930c82-fee2-4f53-98b3-4a1053bad851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2859249045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2859249045
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.790060537
Short name T966
Test name
Test status
Simulation time 5606292930 ps
CPU time 8.93 seconds
Started Jan 25 02:01:33 AM PST 24
Finished Jan 25 02:01:52 AM PST 24
Peak memory 198332 kb
Host smart-c97df97f-d451-45fe-af0f-8c810c1fea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790060537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.790060537
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.178320997
Short name T846
Test name
Test status
Simulation time 9923753519 ps
CPU time 16.69 seconds
Started Jan 25 05:28:40 AM PST 24
Finished Jan 25 05:29:04 AM PST 24
Peak memory 195820 kb
Host smart-988ca1a0-24b7-45ee-b57a-a8068cac692d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178320997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.178320997
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3516413171
Short name T620
Test name
Test status
Simulation time 23089535903 ps
CPU time 650.73 seconds
Started Jan 25 03:36:07 AM PST 24
Finished Jan 25 03:47:11 AM PST 24
Peak memory 200024 kb
Host smart-ad7d27fa-714b-42e5-972f-9e7fd7f04c0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516413171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3516413171
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1419754084
Short name T866
Test name
Test status
Simulation time 70831465238 ps
CPU time 26.95 seconds
Started Jan 25 02:01:38 AM PST 24
Finished Jan 25 02:02:10 AM PST 24
Peak memory 199276 kb
Host smart-281cb6c2-e371-483c-93ea-b48e599dbee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419754084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1419754084
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1289132542
Short name T909
Test name
Test status
Simulation time 42793040598 ps
CPU time 14.73 seconds
Started Jan 25 02:01:44 AM PST 24
Finished Jan 25 02:02:06 AM PST 24
Peak memory 195628 kb
Host smart-3c5e4762-6914-4020-b2bd-5add5864c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289132542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1289132542
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.823558671
Short name T97
Test name
Test status
Simulation time 268460680 ps
CPU time 0.92 seconds
Started Jan 25 02:01:38 AM PST 24
Finished Jan 25 02:01:44 AM PST 24
Peak memory 217228 kb
Host smart-5299191c-ebb5-45e7-b0ee-b1a9b713f6ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823558671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.823558671
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1289779960
Short name T580
Test name
Test status
Simulation time 724598540 ps
CPU time 2.93 seconds
Started Jan 25 03:05:49 AM PST 24
Finished Jan 25 03:05:54 AM PST 24
Peak memory 198360 kb
Host smart-51c75c3a-b221-4ac2-89db-b5ae441e5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289779960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1289779960
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.919570263
Short name T384
Test name
Test status
Simulation time 88523673106 ps
CPU time 136.53 seconds
Started Jan 25 02:01:37 AM PST 24
Finished Jan 25 02:04:00 AM PST 24
Peak memory 199888 kb
Host smart-876e6aeb-44c1-428a-90a7-5b7183382ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919570263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.919570263
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3846117702
Short name T368
Test name
Test status
Simulation time 107607990881 ps
CPU time 396.88 seconds
Started Jan 25 02:01:38 AM PST 24
Finished Jan 25 02:08:20 AM PST 24
Peak memory 216748 kb
Host smart-dba4fb8f-789e-462f-8b57-3c26ab43c832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846117702 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3846117702
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1803157371
Short name T30
Test name
Test status
Simulation time 1030627385 ps
CPU time 2.84 seconds
Started Jan 25 08:45:40 AM PST 24
Finished Jan 25 08:45:44 AM PST 24
Peak memory 198204 kb
Host smart-d371c7a7-1a5f-4c57-9adf-ba984858eeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803157371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1803157371
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4280198906
Short name T803
Test name
Test status
Simulation time 9309156152 ps
CPU time 18.72 seconds
Started Jan 25 01:59:45 AM PST 24
Finished Jan 25 02:00:04 AM PST 24
Peak memory 199828 kb
Host smart-48155cbd-fa0d-4762-a6c1-66b54db99e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280198906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4280198906
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2803889429
Short name T491
Test name
Test status
Simulation time 12679328 ps
CPU time 0.58 seconds
Started Jan 25 02:15:47 AM PST 24
Finished Jan 25 02:15:51 AM PST 24
Peak memory 195656 kb
Host smart-e8818811-35a9-4441-8c26-79ffcd4b7adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803889429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2803889429
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.11295811
Short name T1177
Test name
Test status
Simulation time 47896718365 ps
CPU time 84.36 seconds
Started Jan 25 02:15:08 AM PST 24
Finished Jan 25 02:16:33 AM PST 24
Peak memory 200088 kb
Host smart-190654ff-e562-4bc6-ba07-e979cf5594a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11295811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.11295811
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.31333861
Short name T706
Test name
Test status
Simulation time 119858307488 ps
CPU time 125.75 seconds
Started Jan 25 02:15:08 AM PST 24
Finished Jan 25 02:17:14 AM PST 24
Peak memory 200024 kb
Host smart-ddddd5e5-0a3b-4fa4-a7e3-8f200327af01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31333861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.31333861
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.1141296152
Short name T686
Test name
Test status
Simulation time 1007000290429 ps
CPU time 1849.23 seconds
Started Jan 25 02:15:47 AM PST 24
Finished Jan 25 02:46:39 AM PST 24
Peak memory 199316 kb
Host smart-a8ad2dd6-5f45-4d50-9c5d-1bd714edabe7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141296152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1141296152
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3854378319
Short name T701
Test name
Test status
Simulation time 162037106197 ps
CPU time 444.2 seconds
Started Jan 25 02:15:44 AM PST 24
Finished Jan 25 02:23:11 AM PST 24
Peak memory 200076 kb
Host smart-fc593d7a-a5d3-4fe0-97e1-39f6153dc582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854378319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3854378319
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3072978291
Short name T756
Test name
Test status
Simulation time 8535667172 ps
CPU time 11.21 seconds
Started Jan 25 02:15:43 AM PST 24
Finished Jan 25 02:15:57 AM PST 24
Peak memory 198612 kb
Host smart-bb49f4bd-2403-4952-a6ca-04d2329b5c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072978291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3072978291
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.4253134055
Short name T513
Test name
Test status
Simulation time 31581702763 ps
CPU time 8.78 seconds
Started Jan 25 02:15:46 AM PST 24
Finished Jan 25 02:15:58 AM PST 24
Peak memory 195788 kb
Host smart-9da33a3b-b86a-4aab-bbfb-e32e20424266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253134055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.4253134055
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.4285177692
Short name T971
Test name
Test status
Simulation time 45433213198 ps
CPU time 653.75 seconds
Started Jan 25 02:15:49 AM PST 24
Finished Jan 25 02:26:45 AM PST 24
Peak memory 200140 kb
Host smart-1a27f73f-3f6f-4db4-8333-a9efc7880d4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285177692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4285177692
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2432678466
Short name T789
Test name
Test status
Simulation time 72637424960 ps
CPU time 33.28 seconds
Started Jan 25 02:15:43 AM PST 24
Finished Jan 25 02:16:19 AM PST 24
Peak memory 199844 kb
Host smart-edecc910-05c9-47e4-897a-9c6300144805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432678466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2432678466
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3963805155
Short name T1113
Test name
Test status
Simulation time 6280447299 ps
CPU time 3.19 seconds
Started Jan 25 02:15:48 AM PST 24
Finished Jan 25 02:15:54 AM PST 24
Peak memory 195608 kb
Host smart-f8cbb1d8-abf3-43bb-9990-cf949644a43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963805155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3963805155
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1851739239
Short name T1013
Test name
Test status
Simulation time 306906902 ps
CPU time 1.91 seconds
Started Jan 25 02:15:17 AM PST 24
Finished Jan 25 02:15:28 AM PST 24
Peak memory 197872 kb
Host smart-7561c3ee-45fc-493c-9ed9-16dd8370142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851739239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1851739239
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2725679535
Short name T232
Test name
Test status
Simulation time 64410542113 ps
CPU time 64.84 seconds
Started Jan 25 02:15:50 AM PST 24
Finished Jan 25 02:16:57 AM PST 24
Peak memory 200080 kb
Host smart-6c9e8236-f9bd-41ef-90e4-65bb77a1969c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725679535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2725679535
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.976299851
Short name T640
Test name
Test status
Simulation time 708995221 ps
CPU time 2.14 seconds
Started Jan 25 02:15:42 AM PST 24
Finished Jan 25 02:15:46 AM PST 24
Peak memory 198868 kb
Host smart-9847303d-6e7a-4eba-9e85-f6c71e1b8f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976299851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.976299851
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2987561787
Short name T976
Test name
Test status
Simulation time 67747351953 ps
CPU time 132.4 seconds
Started Jan 25 02:15:09 AM PST 24
Finished Jan 25 02:17:23 AM PST 24
Peak memory 200148 kb
Host smart-a5961d6c-c5b0-4f92-820e-bb18584cdbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987561787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2987561787
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3565982501
Short name T270
Test name
Test status
Simulation time 14782843120 ps
CPU time 7.01 seconds
Started Jan 25 02:44:49 AM PST 24
Finished Jan 25 02:44:58 AM PST 24
Peak memory 197716 kb
Host smart-f0616a41-88c6-4913-acc4-3943f6490787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565982501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3565982501
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3059793375
Short name T1082
Test name
Test status
Simulation time 35191175500 ps
CPU time 18.91 seconds
Started Jan 25 02:44:50 AM PST 24
Finished Jan 25 02:45:11 AM PST 24
Peak memory 200084 kb
Host smart-785c0b2c-b7f2-457d-b0c1-9966addb6798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059793375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3059793375
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1663687817
Short name T1222
Test name
Test status
Simulation time 102609015967 ps
CPU time 91.38 seconds
Started Jan 25 02:44:53 AM PST 24
Finished Jan 25 02:46:26 AM PST 24
Peak memory 200028 kb
Host smart-688b059e-8780-4f44-92a4-170adfb882c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663687817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1663687817
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1107999720
Short name T337
Test name
Test status
Simulation time 33086454648 ps
CPU time 24.26 seconds
Started Jan 25 02:44:55 AM PST 24
Finished Jan 25 02:45:20 AM PST 24
Peak memory 200076 kb
Host smart-53bbf11f-0694-4503-8d37-adff53b2748d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107999720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1107999720
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.19237514
Short name T131
Test name
Test status
Simulation time 132146638500 ps
CPU time 212.76 seconds
Started Jan 25 02:45:13 AM PST 24
Finished Jan 25 02:48:47 AM PST 24
Peak memory 200040 kb
Host smart-7f01963f-8193-4d17-9a7d-36dc9807d7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19237514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.19237514
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.4213962637
Short name T141
Test name
Test status
Simulation time 124959419710 ps
CPU time 94.19 seconds
Started Jan 25 03:23:16 AM PST 24
Finished Jan 25 03:24:53 AM PST 24
Peak memory 200076 kb
Host smart-beeb2530-3266-4807-a3b5-24cffc08c489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213962637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4213962637
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2890153391
Short name T170
Test name
Test status
Simulation time 33615459579 ps
CPU time 46.17 seconds
Started Jan 25 04:58:08 AM PST 24
Finished Jan 25 04:58:55 AM PST 24
Peak memory 200000 kb
Host smart-aae7d806-f1d3-4983-bfe8-92a401e36320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890153391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2890153391
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1897555398
Short name T997
Test name
Test status
Simulation time 10677503 ps
CPU time 0.58 seconds
Started Jan 25 02:18:32 AM PST 24
Finished Jan 25 02:18:37 AM PST 24
Peak memory 194516 kb
Host smart-3ea20cb5-00e6-41fc-a02d-d37447b1ea86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897555398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1897555398
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3335722472
Short name T391
Test name
Test status
Simulation time 50073139039 ps
CPU time 20.75 seconds
Started Jan 25 02:16:12 AM PST 24
Finished Jan 25 02:16:40 AM PST 24
Peak memory 200072 kb
Host smart-d1d86899-3717-479b-b214-935790e90a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335722472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3335722472
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3507935778
Short name T208
Test name
Test status
Simulation time 167210777814 ps
CPU time 81.4 seconds
Started Jan 25 02:35:45 AM PST 24
Finished Jan 25 02:37:09 AM PST 24
Peak memory 200004 kb
Host smart-8056f7fb-9419-4886-82fb-60c3e1ef2985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507935778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3507935778
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.253371625
Short name T982
Test name
Test status
Simulation time 14241256905 ps
CPU time 24.27 seconds
Started Jan 25 02:16:10 AM PST 24
Finished Jan 25 02:16:43 AM PST 24
Peak memory 197080 kb
Host smart-1d985ca5-f6ae-471a-a602-13dc29c570e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253371625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.253371625
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2067923873
Short name T499
Test name
Test status
Simulation time 116850902595 ps
CPU time 337.53 seconds
Started Jan 25 02:16:11 AM PST 24
Finished Jan 25 02:21:56 AM PST 24
Peak memory 199912 kb
Host smart-e451db94-9c02-4af9-a680-4a4c407cfd60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067923873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2067923873
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4135730132
Short name T1164
Test name
Test status
Simulation time 7229208147 ps
CPU time 4.24 seconds
Started Jan 25 04:35:08 AM PST 24
Finished Jan 25 04:35:21 AM PST 24
Peak memory 199388 kb
Host smart-3dda6265-4f2b-42b5-8cea-2d15b59bc08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135730132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4135730132
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1760010315
Short name T873
Test name
Test status
Simulation time 100726712664 ps
CPU time 151.22 seconds
Started Jan 25 02:16:12 AM PST 24
Finished Jan 25 02:18:50 AM PST 24
Peak memory 198988 kb
Host smart-1ec1556c-d8ca-4980-a167-a1b186215031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760010315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1760010315
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1123446999
Short name T702
Test name
Test status
Simulation time 16319831079 ps
CPU time 163.33 seconds
Started Jan 25 02:54:58 AM PST 24
Finished Jan 25 02:57:42 AM PST 24
Peak memory 200096 kb
Host smart-56245fad-5389-41de-ac7c-7d7b05646e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123446999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1123446999
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1187479803
Short name T516
Test name
Test status
Simulation time 4513716364 ps
CPU time 36.71 seconds
Started Jan 25 02:16:05 AM PST 24
Finished Jan 25 02:16:53 AM PST 24
Peak memory 198716 kb
Host smart-09d80791-ffef-4ceb-b858-a0de86579e6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1187479803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1187479803
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3654809859
Short name T1140
Test name
Test status
Simulation time 30806885936 ps
CPU time 54.23 seconds
Started Jan 25 04:21:50 AM PST 24
Finished Jan 25 04:22:54 AM PST 24
Peak memory 199176 kb
Host smart-97cb5686-b255-42e4-9846-4a50aa0b9f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654809859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3654809859
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.682439125
Short name T442
Test name
Test status
Simulation time 3453134461 ps
CPU time 1.7 seconds
Started Jan 25 03:40:02 AM PST 24
Finished Jan 25 03:40:06 AM PST 24
Peak memory 195660 kb
Host smart-a5cb0438-79a8-405f-a4ab-00101936991b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682439125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.682439125
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.549970103
Short name T436
Test name
Test status
Simulation time 885237308 ps
CPU time 3.81 seconds
Started Jan 25 02:16:12 AM PST 24
Finished Jan 25 02:16:23 AM PST 24
Peak memory 197840 kb
Host smart-e8ee9f96-10f0-4332-95a8-81d8c53ad72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549970103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.549970103
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3344437288
Short name T1041
Test name
Test status
Simulation time 95429027235 ps
CPU time 249.25 seconds
Started Jan 25 02:18:42 AM PST 24
Finished Jan 25 02:22:54 AM PST 24
Peak memory 200032 kb
Host smart-c716a99d-300d-406c-9244-257c3502f8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344437288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3344437288
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2383232568
Short name T899
Test name
Test status
Simulation time 108392996817 ps
CPU time 607.19 seconds
Started Jan 25 02:18:41 AM PST 24
Finished Jan 25 02:28:52 AM PST 24
Peak memory 216608 kb
Host smart-0a26f09c-d0d6-46aa-9893-12a69250b03d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383232568 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2383232568
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2153407337
Short name T690
Test name
Test status
Simulation time 692149391 ps
CPU time 2.13 seconds
Started Jan 25 02:34:35 AM PST 24
Finished Jan 25 02:34:40 AM PST 24
Peak memory 198232 kb
Host smart-a451edaa-ab5d-4608-8768-e0a85df7a0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153407337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2153407337
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2080556467
Short name T211
Test name
Test status
Simulation time 126358510984 ps
CPU time 58.3 seconds
Started Jan 25 03:37:29 AM PST 24
Finished Jan 25 03:38:36 AM PST 24
Peak memory 200128 kb
Host smart-a174616e-ad36-4064-8d9e-3d3dcc683079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080556467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2080556467
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.4078143705
Short name T236
Test name
Test status
Simulation time 148572487921 ps
CPU time 198.54 seconds
Started Jan 25 02:45:11 AM PST 24
Finished Jan 25 02:48:31 AM PST 24
Peak memory 200032 kb
Host smart-89491fd9-3d3c-4540-b8dc-fa3bc7b59fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078143705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.4078143705
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1859639779
Short name T111
Test name
Test status
Simulation time 302785345821 ps
CPU time 51.13 seconds
Started Jan 25 02:45:09 AM PST 24
Finished Jan 25 02:46:02 AM PST 24
Peak memory 199456 kb
Host smart-81014a17-e24e-4e21-860e-6d2d4f48eb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859639779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1859639779
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4048758301
Short name T986
Test name
Test status
Simulation time 69462517865 ps
CPU time 41.15 seconds
Started Jan 25 02:45:09 AM PST 24
Finished Jan 25 02:45:51 AM PST 24
Peak memory 200092 kb
Host smart-f117fa9a-0c91-4e61-9b8e-2c63fa93da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048758301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4048758301
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1273100380
Short name T167
Test name
Test status
Simulation time 114081383823 ps
CPU time 28.07 seconds
Started Jan 25 02:45:24 AM PST 24
Finished Jan 25 02:45:53 AM PST 24
Peak memory 200120 kb
Host smart-8843de08-9291-4cf5-83ee-a4232b661d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273100380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1273100380
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2757082475
Short name T376
Test name
Test status
Simulation time 16171346644 ps
CPU time 24.07 seconds
Started Jan 25 02:45:26 AM PST 24
Finished Jan 25 02:45:51 AM PST 24
Peak memory 199388 kb
Host smart-1c6dd04a-051d-41b6-a2e4-410caa231d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757082475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2757082475
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3772966969
Short name T917
Test name
Test status
Simulation time 102781762670 ps
CPU time 85.44 seconds
Started Jan 25 02:45:25 AM PST 24
Finished Jan 25 02:46:51 AM PST 24
Peak memory 199740 kb
Host smart-8d4821e0-976e-429a-9271-26ff74f5769f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772966969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3772966969
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1332579274
Short name T139
Test name
Test status
Simulation time 38037123754 ps
CPU time 17.72 seconds
Started Jan 25 02:45:30 AM PST 24
Finished Jan 25 02:45:49 AM PST 24
Peak memory 199724 kb
Host smart-45b768ba-b307-4202-b88e-733110c4690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332579274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1332579274
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.210782256
Short name T340
Test name
Test status
Simulation time 7212965321 ps
CPU time 16 seconds
Started Jan 25 02:45:29 AM PST 24
Finished Jan 25 02:45:46 AM PST 24
Peak memory 200068 kb
Host smart-66c34130-6723-4aa6-a8d1-5e2822e06c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210782256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.210782256
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2036611860
Short name T309
Test name
Test status
Simulation time 76336762554 ps
CPU time 123.22 seconds
Started Jan 25 02:45:24 AM PST 24
Finished Jan 25 02:47:28 AM PST 24
Peak memory 200064 kb
Host smart-ae2f4c8a-0de2-480a-b4eb-d00a011557dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036611860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2036611860
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4146800521
Short name T579
Test name
Test status
Simulation time 12843971 ps
CPU time 0.66 seconds
Started Jan 25 02:18:31 AM PST 24
Finished Jan 25 02:18:37 AM PST 24
Peak memory 195128 kb
Host smart-265cda4f-e855-4a88-958c-4393d3492a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146800521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4146800521
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.857946529
Short name T1148
Test name
Test status
Simulation time 134434951261 ps
CPU time 218.32 seconds
Started Jan 25 02:18:30 AM PST 24
Finished Jan 25 02:22:15 AM PST 24
Peak memory 200124 kb
Host smart-b44cdfb9-0baf-481e-932c-202f2a3006ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857946529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.857946529
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1385607875
Short name T356
Test name
Test status
Simulation time 65882361009 ps
CPU time 108.35 seconds
Started Jan 25 02:18:30 AM PST 24
Finished Jan 25 02:20:25 AM PST 24
Peak memory 199920 kb
Host smart-20ccf719-66e4-4f00-9c8d-4a3056aaafab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385607875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1385607875
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2966931556
Short name T1080
Test name
Test status
Simulation time 8700408532 ps
CPU time 14.56 seconds
Started Jan 25 02:18:34 AM PST 24
Finished Jan 25 02:18:52 AM PST 24
Peak memory 199912 kb
Host smart-64e3a49a-d7c8-442d-aae9-83ea2762097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966931556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2966931556
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.127666484
Short name T683
Test name
Test status
Simulation time 36158168193 ps
CPU time 19.83 seconds
Started Jan 25 02:18:44 AM PST 24
Finished Jan 25 02:19:06 AM PST 24
Peak memory 197048 kb
Host smart-77363872-6044-48be-9d92-bef8eb6db58c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127666484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.127666484
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2293833854
Short name T1163
Test name
Test status
Simulation time 163678336133 ps
CPU time 577.42 seconds
Started Jan 25 02:18:29 AM PST 24
Finished Jan 25 02:28:14 AM PST 24
Peak memory 200016 kb
Host smart-e8bf04b1-6567-4dc8-88b1-5e52e5fd3a5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293833854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2293833854
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2566632535
Short name T484
Test name
Test status
Simulation time 4153412127 ps
CPU time 8.48 seconds
Started Jan 25 02:18:27 AM PST 24
Finished Jan 25 02:18:37 AM PST 24
Peak memory 198176 kb
Host smart-d0965bbb-9bbd-4d10-81a7-edc6902c153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566632535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2566632535
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.58881081
Short name T991
Test name
Test status
Simulation time 93411474990 ps
CPU time 183.13 seconds
Started Jan 25 02:18:30 AM PST 24
Finished Jan 25 02:21:39 AM PST 24
Peak memory 200244 kb
Host smart-ff8290e5-b045-4633-9819-76cb52e398a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58881081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.58881081
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.1548247729
Short name T595
Test name
Test status
Simulation time 29007500595 ps
CPU time 421.28 seconds
Started Jan 25 02:18:35 AM PST 24
Finished Jan 25 02:25:41 AM PST 24
Peak memory 200064 kb
Host smart-a22f6436-5840-4f1b-9dbc-55cbd3c3542b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1548247729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1548247729
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1228322248
Short name T1217
Test name
Test status
Simulation time 1317671664 ps
CPU time 4.31 seconds
Started Jan 25 02:18:31 AM PST 24
Finished Jan 25 02:18:41 AM PST 24
Peak memory 197540 kb
Host smart-781c276a-c381-47aa-8d5a-182e59179ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228322248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1228322248
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2014966325
Short name T1135
Test name
Test status
Simulation time 232082300655 ps
CPU time 563.26 seconds
Started Jan 25 02:18:34 AM PST 24
Finished Jan 25 02:28:01 AM PST 24
Peak memory 200072 kb
Host smart-68e06786-a9f6-47d2-afe4-95f86730840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014966325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2014966325
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2544929368
Short name T806
Test name
Test status
Simulation time 31859773400 ps
CPU time 43.03 seconds
Started Jan 25 02:18:29 AM PST 24
Finished Jan 25 02:19:19 AM PST 24
Peak memory 195644 kb
Host smart-0991ecf4-6811-470f-ac16-ea543f7fd8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544929368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2544929368
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1261532240
Short name T934
Test name
Test status
Simulation time 5736244624 ps
CPU time 11.96 seconds
Started Jan 25 02:18:32 AM PST 24
Finished Jan 25 02:18:48 AM PST 24
Peak memory 199432 kb
Host smart-dcd345a7-4867-4874-ba32-5deff2723bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261532240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1261532240
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3673354617
Short name T378
Test name
Test status
Simulation time 217282845455 ps
CPU time 553.72 seconds
Started Jan 25 02:18:42 AM PST 24
Finished Jan 25 02:27:59 AM PST 24
Peak memory 213596 kb
Host smart-254bcebe-304c-4921-a694-01d0bedde87a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673354617 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3673354617
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3258403698
Short name T672
Test name
Test status
Simulation time 1168733171 ps
CPU time 3.16 seconds
Started Jan 25 02:18:29 AM PST 24
Finished Jan 25 02:18:39 AM PST 24
Peak memory 198584 kb
Host smart-ce90cf8a-c66f-4fd5-b7a4-077be9072290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258403698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3258403698
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.143958480
Short name T859
Test name
Test status
Simulation time 47528051522 ps
CPU time 108 seconds
Started Jan 25 02:31:34 AM PST 24
Finished Jan 25 02:33:24 AM PST 24
Peak memory 200048 kb
Host smart-bd48984f-060e-4943-b5f8-0c8c5946ae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143958480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.143958480
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1582648548
Short name T179
Test name
Test status
Simulation time 271214101680 ps
CPU time 105.38 seconds
Started Jan 25 02:45:28 AM PST 24
Finished Jan 25 02:47:14 AM PST 24
Peak memory 200024 kb
Host smart-70be5df3-9ffe-44b7-b0f3-68aad14e7b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582648548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1582648548
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.998075965
Short name T811
Test name
Test status
Simulation time 27341195096 ps
CPU time 23.25 seconds
Started Jan 25 02:45:27 AM PST 24
Finished Jan 25 02:45:51 AM PST 24
Peak memory 200092 kb
Host smart-22e053db-92aa-40f5-8d7c-eb47bbbddb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998075965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.998075965
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1340317477
Short name T1210
Test name
Test status
Simulation time 87078499940 ps
CPU time 67.95 seconds
Started Jan 25 02:45:42 AM PST 24
Finished Jan 25 02:46:51 AM PST 24
Peak memory 200104 kb
Host smart-f5af3d09-0c29-482a-97ba-bb1b7651a1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340317477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1340317477
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.966067189
Short name T316
Test name
Test status
Simulation time 159381767846 ps
CPU time 41.78 seconds
Started Jan 25 02:45:40 AM PST 24
Finished Jan 25 02:46:24 AM PST 24
Peak memory 200120 kb
Host smart-d2aa1329-435d-42bc-8442-b0d1abfae236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966067189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.966067189
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3556052073
Short name T245
Test name
Test status
Simulation time 45594862949 ps
CPU time 72.47 seconds
Started Jan 25 02:45:43 AM PST 24
Finished Jan 25 02:46:56 AM PST 24
Peak memory 200076 kb
Host smart-01513d90-3e4c-456e-9a1e-c60c0996b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556052073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3556052073
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4068573091
Short name T1056
Test name
Test status
Simulation time 15564721112 ps
CPU time 55.22 seconds
Started Jan 25 03:31:35 AM PST 24
Finished Jan 25 03:32:31 AM PST 24
Peak memory 200028 kb
Host smart-ff8dafcb-aa64-43de-a11d-de8640e33982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068573091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4068573091
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3747341521
Short name T1194
Test name
Test status
Simulation time 9996026524 ps
CPU time 18.29 seconds
Started Jan 25 02:45:39 AM PST 24
Finished Jan 25 02:45:58 AM PST 24
Peak memory 200016 kb
Host smart-26a8e3b8-d90d-420e-a2db-1ed4837ead45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747341521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3747341521
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3195323410
Short name T392
Test name
Test status
Simulation time 245477792400 ps
CPU time 121.23 seconds
Started Jan 25 04:51:43 AM PST 24
Finished Jan 25 04:53:47 AM PST 24
Peak memory 200132 kb
Host smart-d0f901c4-f3f0-4070-92fd-101a5b3f19e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195323410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3195323410
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.610540605
Short name T779
Test name
Test status
Simulation time 70813608 ps
CPU time 0.6 seconds
Started Jan 25 03:36:09 AM PST 24
Finished Jan 25 03:36:28 AM PST 24
Peak memory 195712 kb
Host smart-9f32e5da-9f4d-4d54-b35e-b7897089795f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610540605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.610540605
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1174435744
Short name T1192
Test name
Test status
Simulation time 121220979414 ps
CPU time 190.53 seconds
Started Jan 25 02:18:32 AM PST 24
Finished Jan 25 02:21:47 AM PST 24
Peak memory 199868 kb
Host smart-70181ffd-cca3-4582-9809-e43bf5793003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174435744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1174435744
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1285485439
Short name T352
Test name
Test status
Simulation time 61614469671 ps
CPU time 25.47 seconds
Started Jan 25 02:46:20 AM PST 24
Finished Jan 25 02:46:55 AM PST 24
Peak memory 200048 kb
Host smart-2836f1e6-8cd9-466f-b075-7093b5f0a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285485439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1285485439
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.4009631019
Short name T193
Test name
Test status
Simulation time 114016656896 ps
CPU time 254.58 seconds
Started Jan 25 04:31:43 AM PST 24
Finished Jan 25 04:36:00 AM PST 24
Peak memory 200052 kb
Host smart-17073686-02c0-4359-a494-f4ae6656bf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009631019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4009631019
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3873845598
Short name T574
Test name
Test status
Simulation time 344494715614 ps
CPU time 154.56 seconds
Started Jan 25 03:21:26 AM PST 24
Finished Jan 25 03:24:02 AM PST 24
Peak memory 200060 kb
Host smart-aee31f9e-0abb-4071-a3fe-c7e56f8954ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873845598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3873845598
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.759751870
Short name T809
Test name
Test status
Simulation time 96532240366 ps
CPU time 757.53 seconds
Started Jan 25 02:32:34 AM PST 24
Finished Jan 25 02:45:13 AM PST 24
Peak memory 200120 kb
Host smart-8dc2753c-5064-4576-9f50-9756caf9a9b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759751870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.759751870
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_noise_filter.523578466
Short name T638
Test name
Test status
Simulation time 78417210028 ps
CPU time 70.37 seconds
Started Jan 25 05:08:57 AM PST 24
Finished Jan 25 05:10:10 AM PST 24
Peak memory 200088 kb
Host smart-faea4998-1907-456c-af66-f673bf59503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523578466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.523578466
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4272352199
Short name T404
Test name
Test status
Simulation time 24236241025 ps
CPU time 359.94 seconds
Started Jan 25 02:18:40 AM PST 24
Finished Jan 25 02:24:43 AM PST 24
Peak memory 200084 kb
Host smart-6446f857-d0d3-457f-b061-198387712343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272352199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4272352199
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3807275747
Short name T881
Test name
Test status
Simulation time 4626734957 ps
CPU time 11.14 seconds
Started Jan 25 02:18:41 AM PST 24
Finished Jan 25 02:18:55 AM PST 24
Peak memory 198804 kb
Host smart-018d7dcf-8541-48f8-ae89-0890d3f972c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807275747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3807275747
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.4159105157
Short name T563
Test name
Test status
Simulation time 23837055216 ps
CPU time 46.25 seconds
Started Jan 25 04:59:54 AM PST 24
Finished Jan 25 05:00:51 AM PST 24
Peak memory 200136 kb
Host smart-b2c4de1b-cdc6-49f2-8a47-527c9fa44a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159105157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.4159105157
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3903810394
Short name T746
Test name
Test status
Simulation time 1847993469 ps
CPU time 3.26 seconds
Started Jan 25 04:31:44 AM PST 24
Finished Jan 25 04:31:50 AM PST 24
Peak memory 195580 kb
Host smart-49e01182-6ef0-4574-a713-cad3f70ba583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903810394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3903810394
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.606615604
Short name T687
Test name
Test status
Simulation time 449567719 ps
CPU time 3.57 seconds
Started Jan 25 02:18:29 AM PST 24
Finished Jan 25 02:18:40 AM PST 24
Peak memory 198448 kb
Host smart-a6c54265-1650-4d2d-9e9d-6de5837bc444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606615604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.606615604
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3074288955
Short name T948
Test name
Test status
Simulation time 33394068840 ps
CPU time 372.85 seconds
Started Jan 25 02:18:44 AM PST 24
Finished Jan 25 02:24:59 AM PST 24
Peak memory 213848 kb
Host smart-5eb6d77d-01cf-4959-b335-a66f3efee814
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074288955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3074288955
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1027804654
Short name T960
Test name
Test status
Simulation time 9414755870 ps
CPU time 6.27 seconds
Started Jan 25 05:43:52 AM PST 24
Finished Jan 25 05:44:03 AM PST 24
Peak memory 199432 kb
Host smart-68334151-982d-4511-9c7a-dc3915c29da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027804654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1027804654
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.232841429
Short name T630
Test name
Test status
Simulation time 72661167908 ps
CPU time 17.95 seconds
Started Jan 25 02:18:30 AM PST 24
Finished Jan 25 02:18:54 AM PST 24
Peak memory 199932 kb
Host smart-4f2af2a2-d535-40b6-847b-7da7dbc1cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232841429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.232841429
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2034492083
Short name T1170
Test name
Test status
Simulation time 201498946905 ps
CPU time 34.33 seconds
Started Jan 25 02:45:41 AM PST 24
Finished Jan 25 02:46:17 AM PST 24
Peak memory 199972 kb
Host smart-4337e04a-ed40-4c4c-927c-670b3178da00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034492083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2034492083
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2055049249
Short name T1115
Test name
Test status
Simulation time 60956458250 ps
CPU time 86.75 seconds
Started Jan 25 02:45:41 AM PST 24
Finished Jan 25 02:47:09 AM PST 24
Peak memory 200052 kb
Host smart-1011be2b-1742-47cb-9cf8-d5cbc734073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055049249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2055049249
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1434183952
Short name T776
Test name
Test status
Simulation time 11163622840 ps
CPU time 9.94 seconds
Started Jan 25 02:45:42 AM PST 24
Finished Jan 25 02:45:52 AM PST 24
Peak memory 199520 kb
Host smart-cc9da0b4-826b-4eb9-8509-66ff86aaabd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434183952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1434183952
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2851389456
Short name T163
Test name
Test status
Simulation time 17238917204 ps
CPU time 27.7 seconds
Started Jan 25 02:45:42 AM PST 24
Finished Jan 25 02:46:11 AM PST 24
Peak memory 200080 kb
Host smart-ec9e1aa5-066d-4620-be18-c701c85b9874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851389456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2851389456
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3171549295
Short name T935
Test name
Test status
Simulation time 27965247067 ps
CPU time 60.53 seconds
Started Jan 25 02:45:59 AM PST 24
Finished Jan 25 02:47:07 AM PST 24
Peak memory 199856 kb
Host smart-226e6a1f-8be4-4d96-bd47-f13ce1891f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171549295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3171549295
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3943121218
Short name T257
Test name
Test status
Simulation time 145148105798 ps
CPU time 58.09 seconds
Started Jan 25 02:46:00 AM PST 24
Finished Jan 25 02:47:05 AM PST 24
Peak memory 200076 kb
Host smart-c4925263-2f5a-4bd9-b23e-91d8c920f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943121218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3943121218
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1995989259
Short name T95
Test name
Test status
Simulation time 43484949 ps
CPU time 0.58 seconds
Started Jan 25 02:20:33 AM PST 24
Finished Jan 25 02:20:34 AM PST 24
Peak memory 195724 kb
Host smart-77a1924f-6769-40f1-a452-7cc0af674177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995989259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1995989259
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.509702958
Short name T1048
Test name
Test status
Simulation time 67232322575 ps
CPU time 113.67 seconds
Started Jan 25 02:19:04 AM PST 24
Finished Jan 25 02:20:59 AM PST 24
Peak memory 200088 kb
Host smart-eb5e8b74-285e-480c-8550-1635073c06a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509702958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.509702958
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4289341936
Short name T925
Test name
Test status
Simulation time 216961804962 ps
CPU time 117.39 seconds
Started Jan 25 02:19:05 AM PST 24
Finished Jan 25 02:21:04 AM PST 24
Peak memory 200016 kb
Host smart-fbe55680-e6c9-40b5-9824-e36f2d1ff40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289341936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4289341936
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2355794972
Short name T1051
Test name
Test status
Simulation time 350370825142 ps
CPU time 106.44 seconds
Started Jan 25 02:19:06 AM PST 24
Finished Jan 25 02:20:54 AM PST 24
Peak memory 199868 kb
Host smart-234a18dc-e806-41c7-b36d-362d5a3494d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355794972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2355794972
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.595783496
Short name T675
Test name
Test status
Simulation time 134619603249 ps
CPU time 513.27 seconds
Started Jan 25 02:20:33 AM PST 24
Finished Jan 25 02:29:07 AM PST 24
Peak memory 200144 kb
Host smart-f5986569-d624-4fc7-9798-5e83713b2fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=595783496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.595783496
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1571772647
Short name T837
Test name
Test status
Simulation time 9045611053 ps
CPU time 15.68 seconds
Started Jan 25 02:20:29 AM PST 24
Finished Jan 25 02:20:46 AM PST 24
Peak memory 197940 kb
Host smart-52dcaa56-e493-4689-83f0-fab30d91006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571772647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1571772647
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.129945224
Short name T1231
Test name
Test status
Simulation time 144382305185 ps
CPU time 172.32 seconds
Started Jan 25 02:20:31 AM PST 24
Finished Jan 25 02:23:24 AM PST 24
Peak memory 200136 kb
Host smart-3e607ee1-6333-48b3-b907-bff2c9c52cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129945224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.129945224
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.364476931
Short name T1010
Test name
Test status
Simulation time 151616877 ps
CPU time 1.09 seconds
Started Jan 25 02:20:29 AM PST 24
Finished Jan 25 02:20:31 AM PST 24
Peak memory 197716 kb
Host smart-ff6342bf-8e7b-429b-8eaf-4ee996c4b113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364476931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.364476931
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2054144972
Short name T912
Test name
Test status
Simulation time 269364244497 ps
CPU time 232.94 seconds
Started Jan 25 02:20:30 AM PST 24
Finished Jan 25 02:24:24 AM PST 24
Peak memory 199796 kb
Host smart-9e6fbe0c-d829-4553-b649-98555e505574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054144972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2054144972
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3468256504
Short name T1123
Test name
Test status
Simulation time 40065009373 ps
CPU time 17.44 seconds
Started Jan 25 02:20:30 AM PST 24
Finished Jan 25 02:20:49 AM PST 24
Peak memory 195624 kb
Host smart-3126b6ea-8fbc-45dc-9e1c-1704318e9798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468256504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3468256504
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2666091366
Short name T576
Test name
Test status
Simulation time 5984483665 ps
CPU time 9.21 seconds
Started Jan 25 03:30:32 AM PST 24
Finished Jan 25 03:30:46 AM PST 24
Peak memory 198712 kb
Host smart-5617a5a1-c646-4a57-a5bd-d21b3055d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666091366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2666091366
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.386331831
Short name T1021
Test name
Test status
Simulation time 57338106092 ps
CPU time 102.98 seconds
Started Jan 25 02:20:31 AM PST 24
Finished Jan 25 02:22:15 AM PST 24
Peak memory 200148 kb
Host smart-29f758bc-e14b-4666-a50e-eca838a6d256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386331831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.386331831
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1674557477
Short name T510
Test name
Test status
Simulation time 25790899234 ps
CPU time 352.94 seconds
Started Jan 25 02:20:31 AM PST 24
Finished Jan 25 02:26:25 AM PST 24
Peak memory 211124 kb
Host smart-251ca12d-22f8-4a85-b61c-eee7c6949443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674557477 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1674557477
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.4222167479
Short name T711
Test name
Test status
Simulation time 674251544 ps
CPU time 3.92 seconds
Started Jan 25 02:20:32 AM PST 24
Finished Jan 25 02:20:36 AM PST 24
Peak memory 198460 kb
Host smart-61198cd4-2950-4e52-9ce4-bf15f720757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222167479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4222167479
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2362916529
Short name T439
Test name
Test status
Simulation time 207469421816 ps
CPU time 202.44 seconds
Started Jan 25 04:01:57 AM PST 24
Finished Jan 25 04:05:22 AM PST 24
Peak memory 200036 kb
Host smart-092f6424-d13d-4373-aacd-30a518e16314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362916529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2362916529
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3124759861
Short name T1067
Test name
Test status
Simulation time 42823828126 ps
CPU time 37.45 seconds
Started Jan 25 02:45:57 AM PST 24
Finished Jan 25 02:46:36 AM PST 24
Peak memory 197892 kb
Host smart-3df36181-50b5-4645-9f42-a33fe0ac5bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124759861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3124759861
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3038748593
Short name T159
Test name
Test status
Simulation time 33294735615 ps
CPU time 55.24 seconds
Started Jan 25 02:45:55 AM PST 24
Finished Jan 25 02:46:51 AM PST 24
Peak memory 200060 kb
Host smart-d05af188-b8ef-433d-8aa4-bacffb12f666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038748593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3038748593
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.677189315
Short name T748
Test name
Test status
Simulation time 6838173794 ps
CPU time 3.91 seconds
Started Jan 25 02:46:02 AM PST 24
Finished Jan 25 02:46:11 AM PST 24
Peak memory 199380 kb
Host smart-252c40ae-7376-4143-a89c-a1e7a66845a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677189315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.677189315
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3878656199
Short name T155
Test name
Test status
Simulation time 211185753682 ps
CPU time 173.43 seconds
Started Jan 25 02:45:57 AM PST 24
Finished Jan 25 02:48:52 AM PST 24
Peak memory 200008 kb
Host smart-f9a795e4-66db-4150-b8da-cf030c3adf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878656199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3878656199
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.564461443
Short name T187
Test name
Test status
Simulation time 18810883524 ps
CPU time 59.65 seconds
Started Jan 25 02:45:57 AM PST 24
Finished Jan 25 02:46:58 AM PST 24
Peak memory 200020 kb
Host smart-3dec03c3-ee13-4cad-acb5-cf73c32b0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564461443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.564461443
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2056605078
Short name T558
Test name
Test status
Simulation time 58638715341 ps
CPU time 20.76 seconds
Started Jan 25 02:45:57 AM PST 24
Finished Jan 25 02:46:19 AM PST 24
Peak memory 198676 kb
Host smart-ca6c80e8-122e-4346-abde-0f5f6579e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056605078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2056605078
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2027845765
Short name T180
Test name
Test status
Simulation time 84966951812 ps
CPU time 32.65 seconds
Started Jan 25 02:45:57 AM PST 24
Finished Jan 25 02:46:31 AM PST 24
Peak memory 199788 kb
Host smart-f0d95a31-d86a-43e3-b900-f2949c991f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027845765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2027845765
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4169915595
Short name T1188
Test name
Test status
Simulation time 27041773412 ps
CPU time 48.36 seconds
Started Jan 25 02:46:15 AM PST 24
Finished Jan 25 02:47:07 AM PST 24
Peak memory 200044 kb
Host smart-ca36d0ce-e220-4e18-9cdd-307a847393e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169915595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4169915595
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.791020479
Short name T1047
Test name
Test status
Simulation time 23386465414 ps
CPU time 32.36 seconds
Started Jan 25 02:46:16 AM PST 24
Finished Jan 25 02:46:52 AM PST 24
Peak memory 200048 kb
Host smart-47d4217a-3ddc-4ce6-ac10-412f0bfdb014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791020479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.791020479
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1069059056
Short name T750
Test name
Test status
Simulation time 114643319215 ps
CPU time 76.82 seconds
Started Jan 25 02:46:15 AM PST 24
Finished Jan 25 02:47:34 AM PST 24
Peak memory 200104 kb
Host smart-359af9c1-3d52-44f7-b628-ab4f44e98cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069059056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1069059056
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.516141514
Short name T652
Test name
Test status
Simulation time 19501580 ps
CPU time 0.58 seconds
Started Jan 25 02:20:49 AM PST 24
Finished Jan 25 02:20:51 AM PST 24
Peak memory 195656 kb
Host smart-087a9555-2665-4b99-9a98-5d02220a7e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516141514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.516141514
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1116198719
Short name T1040
Test name
Test status
Simulation time 60383344831 ps
CPU time 32.54 seconds
Started Jan 25 02:20:53 AM PST 24
Finished Jan 25 02:21:26 AM PST 24
Peak memory 200072 kb
Host smart-83dfd5e3-54dd-4ff4-b29b-3593e6b5d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116198719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1116198719
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2492324492
Short name T835
Test name
Test status
Simulation time 305839979431 ps
CPU time 278.61 seconds
Started Jan 25 02:20:53 AM PST 24
Finished Jan 25 02:25:32 AM PST 24
Peak memory 200084 kb
Host smart-accab1ba-a12b-4ecf-be53-162566f2fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492324492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2492324492
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1070695638
Short name T158
Test name
Test status
Simulation time 20467542788 ps
CPU time 16.87 seconds
Started Jan 25 02:21:23 AM PST 24
Finished Jan 25 02:21:40 AM PST 24
Peak memory 199988 kb
Host smart-df53014d-a563-43bc-88ff-82c2468d67e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070695638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1070695638
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3664603167
Short name T535
Test name
Test status
Simulation time 276494026982 ps
CPU time 130.55 seconds
Started Jan 25 05:11:42 AM PST 24
Finished Jan 25 05:14:02 AM PST 24
Peak memory 200148 kb
Host smart-ebd4e542-87db-4cdd-8343-554e9cdbc0cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664603167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3664603167
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2468257107
Short name T691
Test name
Test status
Simulation time 75538131164 ps
CPU time 441.06 seconds
Started Jan 25 02:20:55 AM PST 24
Finished Jan 25 02:28:18 AM PST 24
Peak memory 200100 kb
Host smart-37fa065a-ba94-4afb-a387-5143e9349069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2468257107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2468257107
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1146099130
Short name T1229
Test name
Test status
Simulation time 9059118365 ps
CPU time 14.76 seconds
Started Jan 25 02:20:50 AM PST 24
Finished Jan 25 02:21:05 AM PST 24
Peak memory 196980 kb
Host smart-ef8a13b6-9cd2-4f18-9d74-74b8486169a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146099130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1146099130
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.587465415
Short name T1023
Test name
Test status
Simulation time 86226788552 ps
CPU time 145.33 seconds
Started Jan 25 02:20:50 AM PST 24
Finished Jan 25 02:23:16 AM PST 24
Peak memory 200284 kb
Host smart-9049f45d-8a6f-4d79-8d26-a9f56ee11d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587465415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.587465415
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2760310921
Short name T541
Test name
Test status
Simulation time 21506858093 ps
CPU time 111.5 seconds
Started Jan 25 02:20:53 AM PST 24
Finished Jan 25 02:22:45 AM PST 24
Peak memory 199912 kb
Host smart-6524068d-e9ac-4295-9253-a24e2bf123dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760310921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2760310921
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3954135692
Short name T20
Test name
Test status
Simulation time 2297833826 ps
CPU time 7.01 seconds
Started Jan 25 02:20:48 AM PST 24
Finished Jan 25 02:20:57 AM PST 24
Peak memory 198256 kb
Host smart-9aa40ffb-e7fc-40e0-b0f4-473b3ae7ee41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954135692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3954135692
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.62023847
Short name T294
Test name
Test status
Simulation time 16749910014 ps
CPU time 30.12 seconds
Started Jan 25 02:20:52 AM PST 24
Finished Jan 25 02:21:23 AM PST 24
Peak memory 198592 kb
Host smart-64ea150b-d946-4756-98d9-33b502f299d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62023847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.62023847
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3386572136
Short name T1085
Test name
Test status
Simulation time 34948887435 ps
CPU time 14 seconds
Started Jan 25 02:20:51 AM PST 24
Finished Jan 25 02:21:06 AM PST 24
Peak memory 195668 kb
Host smart-7e188a4b-1885-4cb0-a36c-4bf34bc87544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386572136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3386572136
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1514833630
Short name T808
Test name
Test status
Simulation time 264815681 ps
CPU time 1.8 seconds
Started Jan 25 03:57:23 AM PST 24
Finished Jan 25 03:57:26 AM PST 24
Peak memory 198296 kb
Host smart-ef396eff-a084-4eef-9ced-c2cabd6fb29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514833630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1514833630
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3336174423
Short name T979
Test name
Test status
Simulation time 266043355501 ps
CPU time 102.34 seconds
Started Jan 25 02:20:55 AM PST 24
Finished Jan 25 02:22:39 AM PST 24
Peak memory 200072 kb
Host smart-efe051ca-0e83-414f-9842-b9e4c678bc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336174423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3336174423
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4247727751
Short name T1050
Test name
Test status
Simulation time 938545499 ps
CPU time 1.31 seconds
Started Jan 25 02:20:50 AM PST 24
Finished Jan 25 02:20:52 AM PST 24
Peak memory 196832 kb
Host smart-3663e3d6-c254-4f21-9fdc-bf7e90747aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247727751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4247727751
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2757186826
Short name T1167
Test name
Test status
Simulation time 266136847980 ps
CPU time 95.4 seconds
Started Jan 25 02:20:47 AM PST 24
Finished Jan 25 02:22:24 AM PST 24
Peak memory 200068 kb
Host smart-70a2bf05-466f-4e30-938e-6accfbc8e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757186826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2757186826
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1489553584
Short name T886
Test name
Test status
Simulation time 77580424490 ps
CPU time 35.76 seconds
Started Jan 25 02:46:18 AM PST 24
Finished Jan 25 02:47:01 AM PST 24
Peak memory 200104 kb
Host smart-43a7c6bc-4dd4-4256-8cb5-bc8b2f997a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489553584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1489553584
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.672015438
Short name T415
Test name
Test status
Simulation time 49019265730 ps
CPU time 27.11 seconds
Started Jan 25 02:46:15 AM PST 24
Finished Jan 25 02:46:46 AM PST 24
Peak memory 200028 kb
Host smart-e1637e9c-e7e7-4f5d-9321-0f0e93e8fc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672015438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.672015438
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1083833622
Short name T817
Test name
Test status
Simulation time 142096918540 ps
CPU time 217.49 seconds
Started Jan 25 02:46:20 AM PST 24
Finished Jan 25 02:50:07 AM PST 24
Peak memory 199900 kb
Host smart-7e096d74-b959-44c3-a69c-f03466fb1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083833622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1083833622
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.128163259
Short name T815
Test name
Test status
Simulation time 135722730542 ps
CPU time 203.53 seconds
Started Jan 25 02:46:20 AM PST 24
Finished Jan 25 02:49:53 AM PST 24
Peak memory 199456 kb
Host smart-2da8602d-f8bf-4b5b-9637-54973f26abd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128163259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.128163259
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2141642796
Short name T23
Test name
Test status
Simulation time 79517738506 ps
CPU time 26.81 seconds
Started Jan 25 02:46:20 AM PST 24
Finished Jan 25 02:46:56 AM PST 24
Peak memory 199900 kb
Host smart-826d0a2c-1481-4294-8a62-1f1de8e529c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141642796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2141642796
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.828162944
Short name T740
Test name
Test status
Simulation time 29518501937 ps
CPU time 49.41 seconds
Started Jan 25 02:46:17 AM PST 24
Finished Jan 25 02:47:14 AM PST 24
Peak memory 199436 kb
Host smart-015aac22-1b46-4b53-8de0-59046c55a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828162944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.828162944
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3497611342
Short name T1094
Test name
Test status
Simulation time 144936761913 ps
CPU time 22.81 seconds
Started Jan 25 02:46:31 AM PST 24
Finished Jan 25 02:46:59 AM PST 24
Peak memory 200028 kb
Host smart-c09f603c-fa32-4ee7-ad42-8f3857fbef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497611342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3497611342
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.246332738
Short name T143
Test name
Test status
Simulation time 36435579892 ps
CPU time 29.8 seconds
Started Jan 25 02:46:36 AM PST 24
Finished Jan 25 02:47:09 AM PST 24
Peak memory 199564 kb
Host smart-bcbf34ff-5f0f-4dfb-bed7-58ab0699bee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246332738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.246332738
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2898779537
Short name T714
Test name
Test status
Simulation time 19591409 ps
CPU time 0.57 seconds
Started Jan 25 02:21:22 AM PST 24
Finished Jan 25 02:21:23 AM PST 24
Peak memory 195716 kb
Host smart-bea5057e-76e4-4a2b-bca4-71b5b0bf48c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898779537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2898779537
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.613026214
Short name T502
Test name
Test status
Simulation time 38458219036 ps
CPU time 14.35 seconds
Started Jan 25 02:20:56 AM PST 24
Finished Jan 25 02:21:11 AM PST 24
Peak memory 199736 kb
Host smart-98b125dd-f03d-493d-a531-87288eca1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613026214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.613026214
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1295262273
Short name T1169
Test name
Test status
Simulation time 11875687349 ps
CPU time 17.67 seconds
Started Jan 25 02:21:12 AM PST 24
Finished Jan 25 02:21:30 AM PST 24
Peak memory 198340 kb
Host smart-1786ee2d-42c2-4517-9a53-52fbf631c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295262273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1295262273
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2982586568
Short name T188
Test name
Test status
Simulation time 78704352677 ps
CPU time 136.53 seconds
Started Jan 25 02:37:40 AM PST 24
Finished Jan 25 02:39:57 AM PST 24
Peak memory 199168 kb
Host smart-84d3fc27-b33b-43ea-b6db-7fcc2eaf1067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982586568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2982586568
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1359591555
Short name T659
Test name
Test status
Simulation time 24429208367 ps
CPU time 43.07 seconds
Started Jan 25 02:21:12 AM PST 24
Finished Jan 25 02:21:56 AM PST 24
Peak memory 200028 kb
Host smart-52e51d60-e2dd-416c-a257-d94891e928bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359591555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1359591555
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1760699838
Short name T503
Test name
Test status
Simulation time 82995237788 ps
CPU time 721.99 seconds
Started Jan 25 05:03:02 AM PST 24
Finished Jan 25 05:15:17 AM PST 24
Peak memory 200128 kb
Host smart-731b50c9-f09e-4667-8b04-f6e3ef0c46e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760699838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1760699838
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.601332395
Short name T1012
Test name
Test status
Simulation time 6979181360 ps
CPU time 9.52 seconds
Started Jan 25 02:21:09 AM PST 24
Finished Jan 25 02:21:19 AM PST 24
Peak memory 199076 kb
Host smart-3e139b8d-e5e4-4ede-b6e9-123d4b132aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601332395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.601332395
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.143383181
Short name T1121
Test name
Test status
Simulation time 55111333163 ps
CPU time 28.78 seconds
Started Jan 25 02:21:10 AM PST 24
Finished Jan 25 02:21:39 AM PST 24
Peak memory 200016 kb
Host smart-ef2cf7bb-da29-4f73-ae11-3dae45b83b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143383181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.143383181
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1171137099
Short name T819
Test name
Test status
Simulation time 1658008934 ps
CPU time 2.23 seconds
Started Jan 25 02:21:09 AM PST 24
Finished Jan 25 02:21:12 AM PST 24
Peak memory 197868 kb
Host smart-1da6ac29-5e5c-4e07-bf29-0252a2228bc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171137099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1171137099
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1278947582
Short name T431
Test name
Test status
Simulation time 95853621635 ps
CPU time 43.34 seconds
Started Jan 25 02:21:16 AM PST 24
Finished Jan 25 02:22:01 AM PST 24
Peak memory 200048 kb
Host smart-43821540-2950-4e4e-afaa-90d70688e016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278947582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1278947582
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4241833681
Short name T842
Test name
Test status
Simulation time 1564629331 ps
CPU time 1.68 seconds
Started Jan 25 03:17:52 AM PST 24
Finished Jan 25 03:17:55 AM PST 24
Peak memory 195608 kb
Host smart-503d6b6b-27ad-4bd7-b963-ca93b63453d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241833681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4241833681
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3506875778
Short name T765
Test name
Test status
Simulation time 528532652 ps
CPU time 1.5 seconds
Started Jan 25 02:20:53 AM PST 24
Finished Jan 25 02:20:56 AM PST 24
Peak memory 198480 kb
Host smart-3d9d681d-e210-453e-847a-f4c42814143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506875778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3506875778
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3530544601
Short name T1020
Test name
Test status
Simulation time 295071726513 ps
CPU time 424.65 seconds
Started Jan 25 02:30:22 AM PST 24
Finished Jan 25 02:37:28 AM PST 24
Peak memory 200136 kb
Host smart-cb318749-08e8-48a1-88d0-6beee6357c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530544601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3530544601
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2076031496
Short name T1002
Test name
Test status
Simulation time 1834228685 ps
CPU time 2.43 seconds
Started Jan 25 02:21:11 AM PST 24
Finished Jan 25 02:21:15 AM PST 24
Peak memory 198508 kb
Host smart-2a70907d-c3e7-4a71-809b-e556de883428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076031496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2076031496
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1804278522
Short name T521
Test name
Test status
Simulation time 30174181556 ps
CPU time 47.43 seconds
Started Jan 25 02:53:14 AM PST 24
Finished Jan 25 02:54:02 AM PST 24
Peak memory 200052 kb
Host smart-9248fa0c-f9f3-4b61-b975-a55eda3d7c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804278522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1804278522
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1931311826
Short name T1091
Test name
Test status
Simulation time 12060043531 ps
CPU time 20.77 seconds
Started Jan 25 02:46:35 AM PST 24
Finished Jan 25 02:47:00 AM PST 24
Peak memory 199356 kb
Host smart-9c6895e0-cc08-49e0-bfa2-71f5982d0775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931311826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1931311826
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2498017330
Short name T649
Test name
Test status
Simulation time 133162505734 ps
CPU time 241.32 seconds
Started Jan 25 02:46:28 AM PST 24
Finished Jan 25 02:50:37 AM PST 24
Peak memory 200048 kb
Host smart-604466a7-3803-4b36-9114-b8a66251b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498017330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2498017330
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1911650855
Short name T308
Test name
Test status
Simulation time 116069978711 ps
CPU time 271.48 seconds
Started Jan 25 03:55:12 AM PST 24
Finished Jan 25 03:59:46 AM PST 24
Peak memory 200068 kb
Host smart-3923b472-eae2-4304-b132-906c6cabc9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911650855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1911650855
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.803645180
Short name T115
Test name
Test status
Simulation time 194836887412 ps
CPU time 40.82 seconds
Started Jan 25 02:46:34 AM PST 24
Finished Jan 25 02:47:19 AM PST 24
Peak memory 200016 kb
Host smart-818e5b63-f77f-4063-ad74-5f8a98217be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803645180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.803645180
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2950746247
Short name T247
Test name
Test status
Simulation time 35514144823 ps
CPU time 31.66 seconds
Started Jan 25 02:46:35 AM PST 24
Finished Jan 25 02:47:10 AM PST 24
Peak memory 200056 kb
Host smart-40a5cae0-d01b-46b4-8d19-82772f6f73c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950746247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2950746247
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.714989733
Short name T336
Test name
Test status
Simulation time 58504655592 ps
CPU time 52.37 seconds
Started Jan 25 02:46:44 AM PST 24
Finished Jan 25 02:47:37 AM PST 24
Peak memory 199988 kb
Host smart-b8991744-f0fd-4055-8ba5-43ed39be7b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714989733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.714989733
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1833509080
Short name T1022
Test name
Test status
Simulation time 35610274326 ps
CPU time 52.16 seconds
Started Jan 25 02:46:46 AM PST 24
Finished Jan 25 02:47:40 AM PST 24
Peak memory 200044 kb
Host smart-2537093c-f782-4255-98c2-facefa7d52c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833509080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1833509080
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.213343106
Short name T936
Test name
Test status
Simulation time 14487664 ps
CPU time 0.6 seconds
Started Jan 25 02:22:07 AM PST 24
Finished Jan 25 02:22:08 AM PST 24
Peak memory 195684 kb
Host smart-76a553f1-3ebc-4d00-a194-846aed69e498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213343106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.213343106
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.1458749902
Short name T403
Test name
Test status
Simulation time 91355419552 ps
CPU time 35.39 seconds
Started Jan 25 02:21:29 AM PST 24
Finished Jan 25 02:22:05 AM PST 24
Peak memory 200040 kb
Host smart-a692b9fe-f73f-4dee-bab2-224c74b75975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458749902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1458749902
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3598220478
Short name T324
Test name
Test status
Simulation time 134305916928 ps
CPU time 101.66 seconds
Started Jan 25 02:21:51 AM PST 24
Finished Jan 25 02:23:40 AM PST 24
Peak memory 200048 kb
Host smart-2d234f85-6eac-4a64-b5a6-6714710ac120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598220478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3598220478
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.393778852
Short name T26
Test name
Test status
Simulation time 1565037325393 ps
CPU time 821.51 seconds
Started Jan 25 02:32:27 AM PST 24
Finished Jan 25 02:46:10 AM PST 24
Peak memory 199912 kb
Host smart-b7f95a98-8be5-4525-aba5-3ff2a3336ee7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393778852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.393778852
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.806106795
Short name T911
Test name
Test status
Simulation time 94262875921 ps
CPU time 418.98 seconds
Started Jan 25 02:22:05 AM PST 24
Finished Jan 25 02:29:06 AM PST 24
Peak memory 200040 kb
Host smart-a3e3ab45-edc5-48b4-b34f-4fadd428a208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806106795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.806106795
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.205144488
Short name T588
Test name
Test status
Simulation time 1320331854 ps
CPU time 1.18 seconds
Started Jan 25 02:22:06 AM PST 24
Finished Jan 25 02:22:08 AM PST 24
Peak memory 196704 kb
Host smart-4706ec24-9002-4480-b051-52ff7a8e810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205144488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.205144488
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1494499931
Short name T1006
Test name
Test status
Simulation time 76961540501 ps
CPU time 21.13 seconds
Started Jan 25 02:21:43 AM PST 24
Finished Jan 25 02:22:15 AM PST 24
Peak memory 197416 kb
Host smart-9febb61b-56bb-4708-98b3-90b6b744ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494499931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1494499931
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2478604512
Short name T1131
Test name
Test status
Simulation time 10299963931 ps
CPU time 156.2 seconds
Started Jan 25 05:43:00 AM PST 24
Finished Jan 25 05:45:36 AM PST 24
Peak memory 200208 kb
Host smart-eb320733-71d5-46a4-a51b-1a65df85b96b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478604512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2478604512
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3815137004
Short name T1176
Test name
Test status
Simulation time 57409758895 ps
CPU time 21.75 seconds
Started Jan 25 03:37:51 AM PST 24
Finished Jan 25 03:38:14 AM PST 24
Peak memory 198576 kb
Host smart-bc488f47-8aad-4eb2-93dc-0e3032f56b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815137004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3815137004
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2484939718
Short name T681
Test name
Test status
Simulation time 383894330 ps
CPU time 1.26 seconds
Started Jan 25 02:21:43 AM PST 24
Finished Jan 25 02:21:55 AM PST 24
Peak memory 195588 kb
Host smart-581081dc-710f-49b8-9938-2c299253b625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484939718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2484939718
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1131358978
Short name T724
Test name
Test status
Simulation time 271654079 ps
CPU time 1.05 seconds
Started Jan 25 02:21:23 AM PST 24
Finished Jan 25 02:21:25 AM PST 24
Peak memory 197968 kb
Host smart-ba2e4139-3cad-4392-a34b-abcf501458f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131358978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1131358978
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2568954670
Short name T931
Test name
Test status
Simulation time 1012674485676 ps
CPU time 2032.72 seconds
Started Jan 25 02:22:06 AM PST 24
Finished Jan 25 02:56:00 AM PST 24
Peak memory 200028 kb
Host smart-8fc9aecc-18c5-466b-89c9-e1fa1bbeeea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568954670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2568954670
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3617946052
Short name T959
Test name
Test status
Simulation time 35362709770 ps
CPU time 565.92 seconds
Started Jan 25 02:22:05 AM PST 24
Finished Jan 25 02:31:33 AM PST 24
Peak memory 208416 kb
Host smart-89bcff53-ae68-440f-9db7-9b1ab8d67c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617946052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3617946052
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1986207828
Short name T1024
Test name
Test status
Simulation time 784119506 ps
CPU time 1.7 seconds
Started Jan 25 02:22:06 AM PST 24
Finished Jan 25 02:22:09 AM PST 24
Peak memory 198528 kb
Host smart-45483a5a-b07b-4e1a-9a82-d9076a33fc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986207828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1986207828
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1474915278
Short name T965
Test name
Test status
Simulation time 55083016262 ps
CPU time 92.75 seconds
Started Jan 25 02:21:26 AM PST 24
Finished Jan 25 02:23:00 AM PST 24
Peak memory 200068 kb
Host smart-ac2d79d4-59aa-4f97-97ed-b685a34e3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474915278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1474915278
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3657484265
Short name T961
Test name
Test status
Simulation time 44724020072 ps
CPU time 20.16 seconds
Started Jan 25 02:46:46 AM PST 24
Finished Jan 25 02:47:08 AM PST 24
Peak memory 200052 kb
Host smart-a1a947c6-fea2-4396-a0e4-292ba5b88fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657484265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3657484265
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3786025240
Short name T173
Test name
Test status
Simulation time 113528786553 ps
CPU time 165.93 seconds
Started Jan 25 02:46:49 AM PST 24
Finished Jan 25 02:49:45 AM PST 24
Peak memory 199796 kb
Host smart-c1828eab-71c8-4aff-aab5-faca471515b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786025240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3786025240
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2483698359
Short name T616
Test name
Test status
Simulation time 10317849219 ps
CPU time 16.16 seconds
Started Jan 25 02:46:50 AM PST 24
Finished Jan 25 02:47:16 AM PST 24
Peak memory 198444 kb
Host smart-45343049-6e10-4a30-9de6-8cfdc478f196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483698359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2483698359
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3696639515
Short name T387
Test name
Test status
Simulation time 67512453132 ps
CPU time 38.7 seconds
Started Jan 25 02:46:44 AM PST 24
Finished Jan 25 02:47:24 AM PST 24
Peak memory 200092 kb
Host smart-1d817d06-e274-4c00-8165-c470a8a135f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696639515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3696639515
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2922671396
Short name T161
Test name
Test status
Simulation time 75704711104 ps
CPU time 107.74 seconds
Started Jan 25 02:46:44 AM PST 24
Finished Jan 25 02:48:32 AM PST 24
Peak memory 199152 kb
Host smart-919cc614-39d1-400c-abec-e0052f3037bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922671396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2922671396
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.563016111
Short name T1201
Test name
Test status
Simulation time 24384101388 ps
CPU time 21.7 seconds
Started Jan 25 04:42:53 AM PST 24
Finished Jan 25 04:43:18 AM PST 24
Peak memory 200100 kb
Host smart-92ca94bf-45fc-4566-b4d3-200385035956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563016111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.563016111
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3103872138
Short name T360
Test name
Test status
Simulation time 82215398309 ps
CPU time 141.24 seconds
Started Jan 25 02:46:54 AM PST 24
Finished Jan 25 02:49:21 AM PST 24
Peak memory 200136 kb
Host smart-66a4a895-861c-4903-8257-42e444dbe239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103872138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3103872138
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1791130999
Short name T186
Test name
Test status
Simulation time 67464579923 ps
CPU time 28.49 seconds
Started Jan 25 02:46:53 AM PST 24
Finished Jan 25 02:47:29 AM PST 24
Peak memory 200012 kb
Host smart-52db81cb-f015-4183-a5d8-f00edf933308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791130999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1791130999
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1406223524
Short name T334
Test name
Test status
Simulation time 91121946806 ps
CPU time 45.84 seconds
Started Jan 25 05:52:37 AM PST 24
Finished Jan 25 05:53:24 AM PST 24
Peak memory 200200 kb
Host smart-7071f2d9-663f-459d-846a-90c1599dbc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406223524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1406223524
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.4289805552
Short name T578
Test name
Test status
Simulation time 20864466 ps
CPU time 0.58 seconds
Started Jan 25 02:22:46 AM PST 24
Finished Jan 25 02:22:47 AM PST 24
Peak memory 195724 kb
Host smart-99831019-614d-4eb5-b8c0-fa516f2c585f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289805552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.4289805552
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2627720373
Short name T406
Test name
Test status
Simulation time 26821698684 ps
CPU time 41.28 seconds
Started Jan 25 02:22:04 AM PST 24
Finished Jan 25 02:22:48 AM PST 24
Peak memory 200040 kb
Host smart-49901f44-e332-4ec5-878a-fdc4f52a463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627720373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2627720373
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2192751717
Short name T1076
Test name
Test status
Simulation time 76382879484 ps
CPU time 129.99 seconds
Started Jan 25 02:22:22 AM PST 24
Finished Jan 25 02:24:34 AM PST 24
Peak memory 199320 kb
Host smart-69c934dc-af94-4d4f-bbe0-8e83cc22b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192751717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2192751717
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2935907884
Short name T220
Test name
Test status
Simulation time 14316901266 ps
CPU time 19.08 seconds
Started Jan 25 02:22:21 AM PST 24
Finished Jan 25 02:22:42 AM PST 24
Peak memory 200048 kb
Host smart-0469c301-af15-4bfc-8ec8-cd87af095811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935907884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2935907884
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.807857674
Short name T557
Test name
Test status
Simulation time 16204818660 ps
CPU time 25.3 seconds
Started Jan 25 03:24:08 AM PST 24
Finished Jan 25 03:24:35 AM PST 24
Peak memory 199420 kb
Host smart-96cc6d71-2fbd-4df2-8362-97e31eca1eb6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807857674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.807857674
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.749352228
Short name T1137
Test name
Test status
Simulation time 77795895449 ps
CPU time 302.61 seconds
Started Jan 25 02:22:47 AM PST 24
Finished Jan 25 02:27:50 AM PST 24
Peak memory 200144 kb
Host smart-c69d14ed-d47c-42bc-aaf8-d4d358eda636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749352228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.749352228
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1866155389
Short name T487
Test name
Test status
Simulation time 11755169082 ps
CPU time 6.51 seconds
Started Jan 25 02:22:16 AM PST 24
Finished Jan 25 02:22:24 AM PST 24
Peak memory 198720 kb
Host smart-afdf4b34-a477-42a4-be73-47219d2995e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866155389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1866155389
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2570914787
Short name T625
Test name
Test status
Simulation time 108974064625 ps
CPU time 136.54 seconds
Started Jan 25 04:24:48 AM PST 24
Finished Jan 25 04:27:07 AM PST 24
Peak memory 200224 kb
Host smart-6c597a3c-0502-4761-909e-180a50528919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570914787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2570914787
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3227222657
Short name T1208
Test name
Test status
Simulation time 12531595996 ps
CPU time 442.51 seconds
Started Jan 25 02:22:23 AM PST 24
Finished Jan 25 02:29:48 AM PST 24
Peak memory 200124 kb
Host smart-716698c9-37c1-4733-84a2-1052a0f7a095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227222657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3227222657
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3439193212
Short name T849
Test name
Test status
Simulation time 2020451726 ps
CPU time 2.8 seconds
Started Jan 25 03:10:40 AM PST 24
Finished Jan 25 03:10:44 AM PST 24
Peak memory 197692 kb
Host smart-84301b27-5cc3-45d3-951c-580c71ab8db3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439193212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3439193212
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3280017096
Short name T1141
Test name
Test status
Simulation time 153985664234 ps
CPU time 107.27 seconds
Started Jan 25 02:22:21 AM PST 24
Finished Jan 25 02:24:10 AM PST 24
Peak memory 199548 kb
Host smart-3d79c24c-ef9a-4851-a615-2b962e7d970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280017096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3280017096
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.244597649
Short name T1228
Test name
Test status
Simulation time 47362434841 ps
CPU time 36.4 seconds
Started Jan 25 02:22:22 AM PST 24
Finished Jan 25 02:23:01 AM PST 24
Peak memory 195648 kb
Host smart-2a28aaa5-1400-4c98-8fdb-5176ec3cc74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244597649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.244597649
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2574379655
Short name T851
Test name
Test status
Simulation time 703866709 ps
CPU time 1.53 seconds
Started Jan 25 02:36:32 AM PST 24
Finished Jan 25 02:36:35 AM PST 24
Peak memory 199476 kb
Host smart-5433e9c3-3be0-4b9d-9da5-eecf000554c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574379655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2574379655
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.582160068
Short name T727
Test name
Test status
Simulation time 679924979361 ps
CPU time 86.68 seconds
Started Jan 25 02:22:45 AM PST 24
Finished Jan 25 02:24:13 AM PST 24
Peak memory 200072 kb
Host smart-30fb03a2-903a-4ec3-b6b5-a918b0cb029a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582160068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.582160068
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3683565575
Short name T89
Test name
Test status
Simulation time 136800225398 ps
CPU time 630.48 seconds
Started Jan 25 04:29:26 AM PST 24
Finished Jan 25 04:40:08 AM PST 24
Peak memory 216576 kb
Host smart-15844d2f-1a0e-4d96-b77b-33776034e551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683565575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3683565575
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1270892164
Short name T486
Test name
Test status
Simulation time 384201053 ps
CPU time 1.66 seconds
Started Jan 25 02:22:19 AM PST 24
Finished Jan 25 02:22:22 AM PST 24
Peak memory 197844 kb
Host smart-7c3bfbec-b34a-4ba3-ac46-02cdb2a05564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270892164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1270892164
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3778581218
Short name T140
Test name
Test status
Simulation time 83993053298 ps
CPU time 38.42 seconds
Started Jan 25 02:22:06 AM PST 24
Finished Jan 25 02:22:46 AM PST 24
Peak memory 200084 kb
Host smart-38dac1f6-82a2-44af-96da-397d4e369c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778581218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3778581218
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.936587522
Short name T199
Test name
Test status
Simulation time 42432561320 ps
CPU time 38.23 seconds
Started Jan 25 03:34:49 AM PST 24
Finished Jan 25 03:35:29 AM PST 24
Peak memory 200084 kb
Host smart-6911d4a1-ddaf-4111-b2af-3cfeb0a2d869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936587522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.936587522
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4230278215
Short name T743
Test name
Test status
Simulation time 32117253390 ps
CPU time 11.73 seconds
Started Jan 25 02:47:27 AM PST 24
Finished Jan 25 02:47:40 AM PST 24
Peak memory 199212 kb
Host smart-435e432e-9170-4b07-a30b-ee294892b817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230278215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4230278215
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.690275127
Short name T628
Test name
Test status
Simulation time 32408921376 ps
CPU time 7.93 seconds
Started Jan 25 02:47:17 AM PST 24
Finished Jan 25 02:47:27 AM PST 24
Peak memory 200044 kb
Host smart-3684f4ed-db7e-4e8e-85b1-856b851296f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690275127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.690275127
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4042210918
Short name T1130
Test name
Test status
Simulation time 24118026117 ps
CPU time 41.61 seconds
Started Jan 25 02:47:18 AM PST 24
Finished Jan 25 02:48:02 AM PST 24
Peak memory 199952 kb
Host smart-2e85e047-7732-4ac5-936d-db63d08569f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042210918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4042210918
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3980274127
Short name T362
Test name
Test status
Simulation time 64059761698 ps
CPU time 34.32 seconds
Started Jan 25 02:47:23 AM PST 24
Finished Jan 25 02:47:59 AM PST 24
Peak memory 199528 kb
Host smart-8b56eaa0-1080-4861-8edc-77170744a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980274127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3980274127
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.150844491
Short name T165
Test name
Test status
Simulation time 135850453936 ps
CPU time 43.43 seconds
Started Jan 25 02:47:20 AM PST 24
Finished Jan 25 02:48:06 AM PST 24
Peak memory 200052 kb
Host smart-cad41c48-c11d-4d28-980e-9c127e13354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150844491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.150844491
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3444450987
Short name T788
Test name
Test status
Simulation time 113715865522 ps
CPU time 37.17 seconds
Started Jan 25 02:47:34 AM PST 24
Finished Jan 25 02:48:13 AM PST 24
Peak memory 200068 kb
Host smart-2bbefb1d-dbf8-4230-b7aa-365e4bd10210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444450987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3444450987
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.629983194
Short name T94
Test name
Test status
Simulation time 11973508 ps
CPU time 0.57 seconds
Started Jan 25 02:23:15 AM PST 24
Finished Jan 25 02:23:16 AM PST 24
Peak memory 194684 kb
Host smart-92be1743-8349-4aab-bad6-ce8b5cc83aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629983194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.629983194
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1532273443
Short name T272
Test name
Test status
Simulation time 71039820700 ps
CPU time 33.85 seconds
Started Jan 25 02:22:43 AM PST 24
Finished Jan 25 02:23:18 AM PST 24
Peak memory 200120 kb
Host smart-867e68fb-22ad-4764-af49-8da04ec41276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532273443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1532273443
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1538485268
Short name T394
Test name
Test status
Simulation time 240222872123 ps
CPU time 20 seconds
Started Jan 25 02:22:44 AM PST 24
Finished Jan 25 02:23:05 AM PST 24
Peak memory 199992 kb
Host smart-437376d2-2eb8-439c-851c-cd23cc3b2f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538485268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1538485268
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.1840976181
Short name T955
Test name
Test status
Simulation time 474408419262 ps
CPU time 114.83 seconds
Started Jan 25 02:23:12 AM PST 24
Finished Jan 25 02:25:07 AM PST 24
Peak memory 199228 kb
Host smart-6864561c-34f3-4368-ad4f-ce3619f41fbc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840976181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1840976181
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3847278785
Short name T1009
Test name
Test status
Simulation time 65151596418 ps
CPU time 107.93 seconds
Started Jan 25 02:23:17 AM PST 24
Finished Jan 25 02:25:06 AM PST 24
Peak memory 199956 kb
Host smart-ea775707-3ace-46d0-96dd-75f7cbb936c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3847278785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3847278785
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1176271991
Short name T813
Test name
Test status
Simulation time 7587863044 ps
CPU time 4.63 seconds
Started Jan 25 02:23:20 AM PST 24
Finished Jan 25 02:23:26 AM PST 24
Peak memory 198088 kb
Host smart-1e274aa3-adda-485a-80d2-dc20b22211ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176271991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1176271991
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.237192951
Short name T885
Test name
Test status
Simulation time 285419339397 ps
CPU time 66.48 seconds
Started Jan 25 02:23:25 AM PST 24
Finished Jan 25 02:24:32 AM PST 24
Peak memory 208452 kb
Host smart-db7beee3-d933-4806-b0d2-d242055da33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237192951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.237192951
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2874129480
Short name T1156
Test name
Test status
Simulation time 11116782950 ps
CPU time 630.38 seconds
Started Jan 25 02:23:21 AM PST 24
Finished Jan 25 02:33:53 AM PST 24
Peak memory 200080 kb
Host smart-761cd2d3-257d-409c-9a5b-7bfe5b0eede7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2874129480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2874129480
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1322910662
Short name T795
Test name
Test status
Simulation time 2684883436 ps
CPU time 8.72 seconds
Started Jan 25 02:23:14 AM PST 24
Finished Jan 25 02:23:24 AM PST 24
Peak memory 197840 kb
Host smart-5f273554-8e1b-468a-a2c7-823d64b80365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1322910662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1322910662
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.4052037346
Short name T254
Test name
Test status
Simulation time 96684243455 ps
CPU time 36.72 seconds
Started Jan 25 02:23:16 AM PST 24
Finished Jan 25 02:23:54 AM PST 24
Peak memory 199708 kb
Host smart-3033a2a4-55bb-4abc-9353-ecfce5daf431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052037346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4052037346
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.912846479
Short name T430
Test name
Test status
Simulation time 42198596900 ps
CPU time 15.76 seconds
Started Jan 25 02:23:15 AM PST 24
Finished Jan 25 02:23:31 AM PST 24
Peak memory 195672 kb
Host smart-b03fd973-1540-4f42-b294-5d4fbbf938ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912846479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.912846479
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1520802258
Short name T426
Test name
Test status
Simulation time 495653750 ps
CPU time 1.85 seconds
Started Jan 25 02:38:42 AM PST 24
Finished Jan 25 02:38:48 AM PST 24
Peak memory 197880 kb
Host smart-4dcc9539-a205-4573-8e95-be5bc7b48291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520802258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1520802258
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.4051295760
Short name T975
Test name
Test status
Simulation time 105155180974 ps
CPU time 606.53 seconds
Started Jan 25 02:23:12 AM PST 24
Finished Jan 25 02:33:20 AM PST 24
Peak memory 200212 kb
Host smart-2876505b-2f40-46dd-89cf-7e412719c1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051295760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.4051295760
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2231156217
Short name T390
Test name
Test status
Simulation time 78381075961 ps
CPU time 822.65 seconds
Started Jan 25 02:23:18 AM PST 24
Finished Jan 25 02:37:02 AM PST 24
Peak memory 216552 kb
Host smart-cfa1c957-92ea-422e-93b5-468d183a120b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231156217 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2231156217
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1256877139
Short name T631
Test name
Test status
Simulation time 7259786507 ps
CPU time 12.66 seconds
Started Jan 25 02:23:20 AM PST 24
Finished Jan 25 02:23:34 AM PST 24
Peak memory 199064 kb
Host smart-68ce7632-c193-476b-b6c1-35e9d3d5a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256877139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1256877139
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.833365328
Short name T132
Test name
Test status
Simulation time 21305127525 ps
CPU time 21.25 seconds
Started Jan 25 02:22:44 AM PST 24
Finished Jan 25 02:23:06 AM PST 24
Peak memory 200080 kb
Host smart-c00ea2bf-85fa-4597-91c8-9aba366821ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833365328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.833365328
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1637348964
Short name T891
Test name
Test status
Simulation time 132391121143 ps
CPU time 16.42 seconds
Started Jan 25 02:47:35 AM PST 24
Finished Jan 25 02:47:53 AM PST 24
Peak memory 199052 kb
Host smart-4f2787eb-9b01-4a82-ba3c-1f052d862e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637348964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1637348964
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3510486478
Short name T496
Test name
Test status
Simulation time 80021424694 ps
CPU time 133.15 seconds
Started Jan 25 02:47:37 AM PST 24
Finished Jan 25 02:49:51 AM PST 24
Peak memory 200028 kb
Host smart-91acfbfd-e43a-4da4-bc06-c62ece20f146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510486478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3510486478
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1333115890
Short name T655
Test name
Test status
Simulation time 101446930152 ps
CPU time 161.99 seconds
Started Jan 25 02:47:37 AM PST 24
Finished Jan 25 02:50:20 AM PST 24
Peak memory 199640 kb
Host smart-c4093891-8038-4ab8-adde-13fbc1e444b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333115890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1333115890
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.939554622
Short name T172
Test name
Test status
Simulation time 54710574906 ps
CPU time 76.35 seconds
Started Jan 25 02:47:32 AM PST 24
Finished Jan 25 02:48:50 AM PST 24
Peak memory 200028 kb
Host smart-cbe94d4f-f72b-49d0-a749-4c2afb90dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939554622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.939554622
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2654796513
Short name T357
Test name
Test status
Simulation time 62973785096 ps
CPU time 13.51 seconds
Started Jan 25 02:47:33 AM PST 24
Finished Jan 25 02:47:48 AM PST 24
Peak memory 199484 kb
Host smart-5702fbb6-28f6-4b79-9a42-bc0fccfebc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654796513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2654796513
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.171502263
Short name T102
Test name
Test status
Simulation time 286222514686 ps
CPU time 122.59 seconds
Started Jan 25 02:47:33 AM PST 24
Finished Jan 25 02:49:36 AM PST 24
Peak memory 199656 kb
Host smart-341d8513-78d3-43d3-b164-398eab682885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171502263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.171502263
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3456008400
Short name T274
Test name
Test status
Simulation time 230656770512 ps
CPU time 44.69 seconds
Started Jan 25 02:47:36 AM PST 24
Finished Jan 25 02:48:22 AM PST 24
Peak memory 200016 kb
Host smart-4073ee44-20d0-419a-828d-49f37603e1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456008400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3456008400
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1582224305
Short name T1088
Test name
Test status
Simulation time 84641018780 ps
CPU time 15.58 seconds
Started Jan 25 02:47:35 AM PST 24
Finished Jan 25 02:47:52 AM PST 24
Peak memory 199484 kb
Host smart-a8b439fa-28be-407d-a201-e1db41851251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582224305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1582224305
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1843282884
Short name T204
Test name
Test status
Simulation time 100378342420 ps
CPU time 141.4 seconds
Started Jan 25 02:47:37 AM PST 24
Finished Jan 25 02:49:59 AM PST 24
Peak memory 199824 kb
Host smart-d76b777d-87cd-4ee1-8a8e-655d74fe7b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843282884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1843282884
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3496715134
Short name T363
Test name
Test status
Simulation time 34291556067 ps
CPU time 13.75 seconds
Started Jan 25 02:47:45 AM PST 24
Finished Jan 25 02:48:00 AM PST 24
Peak memory 199336 kb
Host smart-14e707b0-54fa-400d-b498-802f76484002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496715134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3496715134
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3616082343
Short name T606
Test name
Test status
Simulation time 11884112 ps
CPU time 0.58 seconds
Started Jan 25 02:02:50 AM PST 24
Finished Jan 25 02:02:57 AM PST 24
Peak memory 194684 kb
Host smart-aed1bd45-f5e1-4cba-b9e4-60212da18afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616082343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3616082343
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1090011145
Short name T333
Test name
Test status
Simulation time 50191606313 ps
CPU time 21.03 seconds
Started Jan 25 02:02:02 AM PST 24
Finished Jan 25 02:02:45 AM PST 24
Peak memory 200024 kb
Host smart-8f10827b-6448-4a18-aecd-cd7d75f9eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090011145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1090011145
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.4143434803
Short name T602
Test name
Test status
Simulation time 157763747455 ps
CPU time 67.13 seconds
Started Jan 25 02:19:12 AM PST 24
Finished Jan 25 02:20:21 AM PST 24
Peak memory 200052 kb
Host smart-2f827eed-00cc-4f88-9795-f885cc8c9aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143434803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.4143434803
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.159190406
Short name T129
Test name
Test status
Simulation time 191102548764 ps
CPU time 49.96 seconds
Started Jan 25 02:48:26 AM PST 24
Finished Jan 25 02:49:16 AM PST 24
Peak memory 200036 kb
Host smart-dfcf69f2-d7e2-4898-b8f1-7c115ce7d372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159190406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.159190406
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.803290565
Short name T733
Test name
Test status
Simulation time 1365711644283 ps
CPU time 1214.15 seconds
Started Jan 25 06:36:50 AM PST 24
Finished Jan 25 06:57:11 AM PST 24
Peak memory 200160 kb
Host smart-a884cf48-9d65-4d2f-8785-7503120f0ed9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803290565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.803290565
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.464764577
Short name T632
Test name
Test status
Simulation time 130378431079 ps
CPU time 173.95 seconds
Started Jan 25 03:24:12 AM PST 24
Finished Jan 25 03:27:15 AM PST 24
Peak memory 200076 kb
Host smart-64e3e8fd-4d66-42b9-8b5b-2ea95e7bfee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464764577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.464764577
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3087068512
Short name T648
Test name
Test status
Simulation time 6826328290 ps
CPU time 20.55 seconds
Started Jan 25 02:02:30 AM PST 24
Finished Jan 25 02:03:07 AM PST 24
Peak memory 198892 kb
Host smart-93d23bcd-0940-4be4-ada7-dd81b5e15997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087068512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3087068512
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.4169818718
Short name T624
Test name
Test status
Simulation time 97967450921 ps
CPU time 24.13 seconds
Started Jan 25 02:02:01 AM PST 24
Finished Jan 25 02:02:49 AM PST 24
Peak memory 195932 kb
Host smart-2f9df095-d19b-4872-8bd8-b419cfe5d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169818718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4169818718
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1365923589
Short name T1193
Test name
Test status
Simulation time 12766691495 ps
CPU time 180.5 seconds
Started Jan 25 06:11:57 AM PST 24
Finished Jan 25 06:15:00 AM PST 24
Peak memory 200200 kb
Host smart-5053f905-73e5-45bd-b95c-c092551fa89c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365923589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1365923589
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3617681665
Short name T1126
Test name
Test status
Simulation time 2703719842 ps
CPU time 16.57 seconds
Started Jan 25 02:02:02 AM PST 24
Finished Jan 25 02:02:41 AM PST 24
Peak memory 197972 kb
Host smart-28d19a88-25c2-4c28-b69a-dca691f0c709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3617681665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3617681665
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1558920471
Short name T1112
Test name
Test status
Simulation time 147407266986 ps
CPU time 113.46 seconds
Started Jan 25 02:40:41 AM PST 24
Finished Jan 25 02:42:40 AM PST 24
Peak memory 200124 kb
Host smart-fb8aeaee-9b30-4c66-8b1e-4ce5bc26d9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558920471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1558920471
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.203387769
Short name T983
Test name
Test status
Simulation time 3080762476 ps
CPU time 6.03 seconds
Started Jan 25 02:02:01 AM PST 24
Finished Jan 25 02:02:31 AM PST 24
Peak memory 195624 kb
Host smart-517d023c-a5cd-4aef-9aa5-6ec13ceb4138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203387769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.203387769
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1982892964
Short name T98
Test name
Test status
Simulation time 140925603 ps
CPU time 0.89 seconds
Started Jan 25 03:15:05 AM PST 24
Finished Jan 25 03:15:10 AM PST 24
Peak memory 217320 kb
Host smart-a145bf34-11ee-4b2d-862c-8c4f092ee964
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982892964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1982892964
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.118671426
Short name T1073
Test name
Test status
Simulation time 282596662 ps
CPU time 1.81 seconds
Started Jan 25 02:02:04 AM PST 24
Finished Jan 25 02:02:27 AM PST 24
Peak memory 198968 kb
Host smart-f642d758-ffc8-4e74-be5a-3187d9839f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118671426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.118671426
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2662324162
Short name T1120
Test name
Test status
Simulation time 4781431803567 ps
CPU time 8228.84 seconds
Started Jan 25 02:02:24 AM PST 24
Finished Jan 25 04:19:54 AM PST 24
Peak memory 200048 kb
Host smart-27b96df9-fe79-4e00-9811-a7609e200321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662324162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2662324162
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3395357
Short name T289
Test name
Test status
Simulation time 173256523760 ps
CPU time 687.54 seconds
Started Jan 25 02:57:49 AM PST 24
Finished Jan 25 03:09:19 AM PST 24
Peak memory 212700 kb
Host smart-0b64cb5e-12d2-40ea-9f9f-915b99d16502
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395357 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3395357
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2685721744
Short name T780
Test name
Test status
Simulation time 1987110390 ps
CPU time 1.69 seconds
Started Jan 25 04:08:54 AM PST 24
Finished Jan 25 04:08:58 AM PST 24
Peak memory 198364 kb
Host smart-7f72e749-c027-454f-af6c-5da1fe0f5ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685721744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2685721744
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2132821011
Short name T804
Test name
Test status
Simulation time 57196909788 ps
CPU time 176.8 seconds
Started Jan 25 02:40:38 AM PST 24
Finished Jan 25 02:43:42 AM PST 24
Peak memory 200060 kb
Host smart-0cd8930d-5bd8-4582-80c5-a5c8c0eac8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132821011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2132821011
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3384331879
Short name T585
Test name
Test status
Simulation time 12233240 ps
CPU time 0.59 seconds
Started Jan 25 02:23:53 AM PST 24
Finished Jan 25 02:23:54 AM PST 24
Peak memory 195708 kb
Host smart-a3ca45d4-f8e7-4131-b231-238097376108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384331879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3384331879
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3730921864
Short name T954
Test name
Test status
Simulation time 48571505255 ps
CPU time 75.86 seconds
Started Jan 25 02:23:27 AM PST 24
Finished Jan 25 02:24:44 AM PST 24
Peak memory 200056 kb
Host smart-58aa50c1-802a-4340-b47a-5f853f3898a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730921864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3730921864
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3940280963
Short name T497
Test name
Test status
Simulation time 100636391701 ps
CPU time 169.07 seconds
Started Jan 25 02:23:28 AM PST 24
Finished Jan 25 02:26:18 AM PST 24
Peak memory 199868 kb
Host smart-7532f689-7164-4c9a-84c0-5bf6c76bf0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940280963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3940280963
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3176446924
Short name T692
Test name
Test status
Simulation time 63688427012 ps
CPU time 191.58 seconds
Started Jan 25 02:23:27 AM PST 24
Finished Jan 25 02:26:39 AM PST 24
Peak memory 200048 kb
Host smart-45b5bf66-07b6-4a16-8826-ffa5926ef66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176446924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3176446924
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.526830840
Short name T438
Test name
Test status
Simulation time 399417380232 ps
CPU time 292.36 seconds
Started Jan 25 02:23:18 AM PST 24
Finished Jan 25 02:28:12 AM PST 24
Peak memory 200068 kb
Host smart-422db13b-0fb2-4511-988e-9fb05faae329
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526830840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.526830840
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1892450195
Short name T611
Test name
Test status
Simulation time 61273583234 ps
CPU time 344.21 seconds
Started Jan 25 02:38:03 AM PST 24
Finished Jan 25 02:43:53 AM PST 24
Peak memory 200144 kb
Host smart-cb5e8897-6709-4fce-ad62-ee36bc81312c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892450195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1892450195
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3174603589
Short name T1035
Test name
Test status
Simulation time 3870160604 ps
CPU time 6.63 seconds
Started Jan 25 02:23:37 AM PST 24
Finished Jan 25 02:23:45 AM PST 24
Peak memory 198712 kb
Host smart-4123b481-49b0-436b-bfae-2fdd9410ed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174603589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3174603589
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.3974303639
Short name T221
Test name
Test status
Simulation time 71891847006 ps
CPU time 31.11 seconds
Started Jan 25 02:23:29 AM PST 24
Finished Jan 25 02:24:04 AM PST 24
Peak memory 198252 kb
Host smart-57dbca93-8390-4ad8-8ece-69e01ffb3143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974303639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3974303639
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.550814724
Short name T160
Test name
Test status
Simulation time 6837582902 ps
CPU time 91.06 seconds
Started Jan 25 02:23:51 AM PST 24
Finished Jan 25 02:25:23 AM PST 24
Peak memory 200016 kb
Host smart-2676e144-f6e0-48c7-b340-93650f57851d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550814724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.550814724
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1489443858
Short name T435
Test name
Test status
Simulation time 60501913875 ps
CPU time 11.4 seconds
Started Jan 25 02:23:30 AM PST 24
Finished Jan 25 02:23:45 AM PST 24
Peak memory 198376 kb
Host smart-20f2699e-86fc-475d-b660-739b987089c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489443858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1489443858
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.4022446643
Short name T1147
Test name
Test status
Simulation time 3613896397 ps
CPU time 6.89 seconds
Started Jan 25 02:23:26 AM PST 24
Finished Jan 25 02:23:34 AM PST 24
Peak memory 195936 kb
Host smart-567d2650-ed1d-4431-b69f-a363d4ec5772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022446643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.4022446643
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1083193601
Short name T508
Test name
Test status
Simulation time 98064801 ps
CPU time 0.98 seconds
Started Jan 25 02:23:19 AM PST 24
Finished Jan 25 02:23:21 AM PST 24
Peak memory 197572 kb
Host smart-cb397ecf-ebdb-465a-8854-f90517bab82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083193601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1083193601
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.219857386
Short name T353
Test name
Test status
Simulation time 88484598879 ps
CPU time 71.82 seconds
Started Jan 25 02:23:53 AM PST 24
Finished Jan 25 02:25:05 AM PST 24
Peak memory 200072 kb
Host smart-07e17806-2b50-41a1-8e37-d463a3b8c7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219857386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.219857386
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1181006134
Short name T144
Test name
Test status
Simulation time 66207822647 ps
CPU time 768.52 seconds
Started Jan 25 02:23:52 AM PST 24
Finished Jan 25 02:36:42 AM PST 24
Peak memory 216828 kb
Host smart-26fbeae1-c93b-4cad-8363-e7bce989b4a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181006134 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1181006134
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.98973749
Short name T488
Test name
Test status
Simulation time 846343077 ps
CPU time 2.33 seconds
Started Jan 25 02:23:34 AM PST 24
Finished Jan 25 02:23:38 AM PST 24
Peak memory 197392 kb
Host smart-446b02bc-e8a9-4068-b9a6-2477ee1a2980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98973749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.98973749
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.494096658
Short name T1173
Test name
Test status
Simulation time 94606238234 ps
CPU time 41.59 seconds
Started Jan 25 02:23:18 AM PST 24
Finished Jan 25 02:24:01 AM PST 24
Peak memory 199904 kb
Host smart-37b2b9be-4e71-410c-9abb-7ef4a21143ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494096658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.494096658
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1301498889
Short name T956
Test name
Test status
Simulation time 11088351 ps
CPU time 0.59 seconds
Started Jan 25 02:24:22 AM PST 24
Finished Jan 25 02:24:24 AM PST 24
Peak memory 194692 kb
Host smart-b7eae5c4-2fd8-413e-b5f6-9741c728bfda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301498889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1301498889
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3101593718
Short name T205
Test name
Test status
Simulation time 45976786686 ps
CPU time 66.6 seconds
Started Jan 25 02:23:51 AM PST 24
Finished Jan 25 02:24:59 AM PST 24
Peak memory 200056 kb
Host smart-e1cada22-768f-4a83-a3f4-df2de5888fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101593718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3101593718
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2577832843
Short name T678
Test name
Test status
Simulation time 3739568894 ps
CPU time 6.49 seconds
Started Jan 25 06:23:25 AM PST 24
Finished Jan 25 06:23:33 AM PST 24
Peak memory 198952 kb
Host smart-820bcf8a-c4f3-4d7e-9742-48a0c1b0b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577832843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2577832843
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.374748693
Short name T839
Test name
Test status
Simulation time 522515571297 ps
CPU time 437.42 seconds
Started Jan 25 02:24:09 AM PST 24
Finished Jan 25 02:31:27 AM PST 24
Peak memory 199796 kb
Host smart-3fe68783-2477-4bff-89da-7c56e9990aae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374748693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.374748693
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1972375156
Short name T561
Test name
Test status
Simulation time 65476279268 ps
CPU time 116.88 seconds
Started Jan 25 02:24:08 AM PST 24
Finished Jan 25 02:26:06 AM PST 24
Peak memory 200092 kb
Host smart-ddfb46e7-9a1f-4739-89df-006f21ad1270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972375156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1972375156
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.715332292
Short name T665
Test name
Test status
Simulation time 10985179463 ps
CPU time 8.92 seconds
Started Jan 25 02:24:07 AM PST 24
Finished Jan 25 02:24:17 AM PST 24
Peak memory 199488 kb
Host smart-ea784122-09ba-47ce-991b-4e8d80579bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715332292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.715332292
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3239157711
Short name T169
Test name
Test status
Simulation time 26572626354 ps
CPU time 45.79 seconds
Started Jan 25 02:24:07 AM PST 24
Finished Jan 25 02:24:54 AM PST 24
Peak memory 199716 kb
Host smart-55fdd63a-cd96-4191-9b7b-da9bd1ec14cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239157711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3239157711
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1720117661
Short name T1045
Test name
Test status
Simulation time 17606311351 ps
CPU time 867.76 seconds
Started Jan 25 02:24:08 AM PST 24
Finished Jan 25 02:38:37 AM PST 24
Peak memory 200084 kb
Host smart-16955188-7781-4bb3-aea7-1469f18021ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720117661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1720117661
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.515651579
Short name T1084
Test name
Test status
Simulation time 14775190290 ps
CPU time 12.77 seconds
Started Jan 25 02:24:10 AM PST 24
Finished Jan 25 02:24:24 AM PST 24
Peak memory 197880 kb
Host smart-de5508d4-3bd5-48ee-bdd9-dbfc9f7cf7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515651579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.515651579
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3338255807
Short name T618
Test name
Test status
Simulation time 27025072752 ps
CPU time 47.54 seconds
Started Jan 25 02:24:11 AM PST 24
Finished Jan 25 02:25:00 AM PST 24
Peak memory 195652 kb
Host smart-fb83a430-1f46-4c2f-90e6-ababfdd4d5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338255807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3338255807
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2707136368
Short name T1092
Test name
Test status
Simulation time 6063487463 ps
CPU time 11.62 seconds
Started Jan 25 03:18:33 AM PST 24
Finished Jan 25 03:18:46 AM PST 24
Peak memory 199328 kb
Host smart-d731ac7c-d007-4104-b85a-7ba8abe185d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707136368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2707136368
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1338706782
Short name T380
Test name
Test status
Simulation time 504989376075 ps
CPU time 418.55 seconds
Started Jan 25 02:24:26 AM PST 24
Finished Jan 25 02:31:25 AM PST 24
Peak memory 200072 kb
Host smart-db6370bb-efba-4a35-aae7-d1cbcf802374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338706782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1338706782
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2876517140
Short name T1134
Test name
Test status
Simulation time 71642784764 ps
CPU time 489.8 seconds
Started Jan 25 02:24:22 AM PST 24
Finished Jan 25 02:32:33 AM PST 24
Peak memory 211712 kb
Host smart-8df83c58-6255-4e83-b850-56ca0902ac7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876517140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2876517140
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1006608174
Short name T785
Test name
Test status
Simulation time 1298051783 ps
CPU time 3.14 seconds
Started Jan 25 02:24:06 AM PST 24
Finished Jan 25 02:24:10 AM PST 24
Peak memory 198276 kb
Host smart-8cb1b587-69c2-4a3d-aaad-82882e608da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006608174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1006608174
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1455726897
Short name T669
Test name
Test status
Simulation time 120435934465 ps
CPU time 216.36 seconds
Started Jan 25 02:23:51 AM PST 24
Finished Jan 25 02:27:29 AM PST 24
Peak memory 200076 kb
Host smart-4772c5dd-5434-4379-a816-c75e8034c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455726897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1455726897
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2406923654
Short name T1105
Test name
Test status
Simulation time 20180226 ps
CPU time 0.59 seconds
Started Jan 25 02:25:11 AM PST 24
Finished Jan 25 02:25:21 AM PST 24
Peak memory 194696 kb
Host smart-30405e0f-18d0-437e-8a25-7af4368f1c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406923654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2406923654
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.27753624
Short name T1189
Test name
Test status
Simulation time 223178779623 ps
CPU time 561.22 seconds
Started Jan 25 02:24:24 AM PST 24
Finished Jan 25 02:33:46 AM PST 24
Peak memory 199920 kb
Host smart-90b7b094-d8dd-48f6-93aa-8d3880a093a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27753624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.27753624
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3724169552
Short name T1089
Test name
Test status
Simulation time 77001443604 ps
CPU time 112.34 seconds
Started Jan 25 02:24:25 AM PST 24
Finished Jan 25 02:26:18 AM PST 24
Peak memory 200068 kb
Host smart-2c281f25-a111-44fd-a7a7-164d86e03464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724169552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3724169552
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2608230042
Short name T1149
Test name
Test status
Simulation time 100325876024 ps
CPU time 77.7 seconds
Started Jan 25 02:24:32 AM PST 24
Finished Jan 25 02:25:51 AM PST 24
Peak memory 200080 kb
Host smart-ecfb1a6d-9e55-4705-8788-19d376c04893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608230042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2608230042
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3694540630
Short name T534
Test name
Test status
Simulation time 2444916080007 ps
CPU time 268.45 seconds
Started Jan 25 02:24:39 AM PST 24
Finished Jan 25 02:29:09 AM PST 24
Peak memory 199168 kb
Host smart-fe65e443-66a0-4f65-a66b-f8221406b605
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694540630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3694540630
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1326940086
Short name T623
Test name
Test status
Simulation time 52608836306 ps
CPU time 263.42 seconds
Started Jan 25 02:24:39 AM PST 24
Finished Jan 25 02:29:04 AM PST 24
Peak memory 200076 kb
Host smart-084d4205-2ab8-43ca-9663-446145b4104d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326940086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1326940086
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1862640244
Short name T520
Test name
Test status
Simulation time 4608313605 ps
CPU time 8.24 seconds
Started Jan 25 02:24:37 AM PST 24
Finished Jan 25 02:24:46 AM PST 24
Peak memory 198912 kb
Host smart-7648027e-4872-4ab0-a6e3-4f384dd615b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862640244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1862640244
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3093164549
Short name T713
Test name
Test status
Simulation time 328719256823 ps
CPU time 43.86 seconds
Started Jan 25 02:24:37 AM PST 24
Finished Jan 25 02:25:22 AM PST 24
Peak memory 200128 kb
Host smart-5384ed3d-e572-4d70-83f3-b2bd788e5f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093164549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3093164549
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1714131574
Short name T957
Test name
Test status
Simulation time 14022930520 ps
CPU time 835.47 seconds
Started Jan 25 02:24:39 AM PST 24
Finished Jan 25 02:38:37 AM PST 24
Peak memory 200080 kb
Host smart-d9957881-8840-494a-a250-9a756be6d088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714131574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1714131574
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2261215830
Short name T1207
Test name
Test status
Simulation time 3322332033 ps
CPU time 6.15 seconds
Started Jan 25 02:24:32 AM PST 24
Finished Jan 25 02:24:39 AM PST 24
Peak memory 198520 kb
Host smart-dfb64f7e-aa2e-4fad-98e9-d879524ce138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261215830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2261215830
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3886733850
Short name T607
Test name
Test status
Simulation time 36628126310 ps
CPU time 17.13 seconds
Started Jan 25 02:24:38 AM PST 24
Finished Jan 25 02:24:56 AM PST 24
Peak memory 197904 kb
Host smart-a58b0a34-2d5a-43d9-8da6-24043e0ec091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886733850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3886733850
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1869547751
Short name T1150
Test name
Test status
Simulation time 5172749370 ps
CPU time 4.78 seconds
Started Jan 25 02:24:43 AM PST 24
Finished Jan 25 02:24:51 AM PST 24
Peak memory 195732 kb
Host smart-002f5df4-4042-434c-8f30-4e733b48f71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869547751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1869547751
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2391932787
Short name T495
Test name
Test status
Simulation time 484033376 ps
CPU time 2.5 seconds
Started Jan 25 02:24:27 AM PST 24
Finished Jan 25 02:24:31 AM PST 24
Peak memory 198328 kb
Host smart-8b8f5f2d-dd3b-4c79-9329-c466a5027057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391932787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2391932787
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3222664254
Short name T1204
Test name
Test status
Simulation time 1254561540 ps
CPU time 1.56 seconds
Started Jan 25 02:24:37 AM PST 24
Finished Jan 25 02:24:40 AM PST 24
Peak memory 198132 kb
Host smart-39d5310e-a61e-4b2d-9bb8-54f61e728093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222664254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3222664254
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1622648844
Short name T647
Test name
Test status
Simulation time 74059981677 ps
CPU time 175.8 seconds
Started Jan 25 02:24:24 AM PST 24
Finished Jan 25 02:27:21 AM PST 24
Peak memory 200052 kb
Host smart-0a84a372-788a-4522-9391-2dba6a71e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622648844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1622648844
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.630178475
Short name T1161
Test name
Test status
Simulation time 15703092 ps
CPU time 0.64 seconds
Started Jan 25 02:25:59 AM PST 24
Finished Jan 25 02:26:04 AM PST 24
Peak memory 195716 kb
Host smart-58852b34-1aec-498e-a4ba-d5c787dad4c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630178475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.630178475
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3609371809
Short name T365
Test name
Test status
Simulation time 32047851739 ps
CPU time 49.05 seconds
Started Jan 25 02:25:10 AM PST 24
Finished Jan 25 02:26:09 AM PST 24
Peak memory 199768 kb
Host smart-17c089e2-9821-481d-870a-951748d49417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609371809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3609371809
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.195686594
Short name T279
Test name
Test status
Simulation time 20434877590 ps
CPU time 37.82 seconds
Started Jan 25 02:25:12 AM PST 24
Finished Jan 25 02:25:58 AM PST 24
Peak memory 199148 kb
Host smart-ce9f0333-52b1-4fe2-92d4-7c4befdcae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195686594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.195686594
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1626072577
Short name T200
Test name
Test status
Simulation time 15543591309 ps
CPU time 14.15 seconds
Started Jan 25 02:25:36 AM PST 24
Finished Jan 25 02:26:04 AM PST 24
Peak memory 200068 kb
Host smart-48001063-340b-49a7-abb8-aaad541f99a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626072577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1626072577
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2243334533
Short name T656
Test name
Test status
Simulation time 331747330209 ps
CPU time 568.46 seconds
Started Jan 25 02:25:37 AM PST 24
Finished Jan 25 02:35:20 AM PST 24
Peak memory 200000 kb
Host smart-07c65843-e166-4378-a7b4-b1dd1070d346
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243334533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2243334533
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1253648162
Short name T947
Test name
Test status
Simulation time 75806451325 ps
CPU time 100.82 seconds
Started Jan 25 02:25:40 AM PST 24
Finished Jan 25 02:27:38 AM PST 24
Peak memory 200040 kb
Host smart-56f9e613-2061-4ca2-9283-4eafdc823f50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253648162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1253648162
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1368940045
Short name T663
Test name
Test status
Simulation time 97118702 ps
CPU time 0.65 seconds
Started Jan 25 02:57:25 AM PST 24
Finished Jan 25 02:57:28 AM PST 24
Peak memory 195548 kb
Host smart-e1df0ae2-dbd4-4e19-9517-f616f1f1f1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368940045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1368940045
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3934269173
Short name T18
Test name
Test status
Simulation time 114943704590 ps
CPU time 233.28 seconds
Started Jan 25 02:25:40 AM PST 24
Finished Jan 25 02:29:50 AM PST 24
Peak memory 200192 kb
Host smart-86702dd9-7c03-4537-9e66-8bf56215de58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934269173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3934269173
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3742415824
Short name T162
Test name
Test status
Simulation time 12678549542 ps
CPU time 730.55 seconds
Started Jan 25 02:25:40 AM PST 24
Finished Jan 25 02:38:08 AM PST 24
Peak memory 200012 kb
Host smart-2588a280-5e51-445e-81cc-13a5b895928f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742415824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3742415824
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.706461204
Short name T494
Test name
Test status
Simulation time 2652437503 ps
CPU time 6.67 seconds
Started Jan 25 02:25:35 AM PST 24
Finished Jan 25 02:25:46 AM PST 24
Peak memory 198080 kb
Host smart-9aaf5305-d7dd-446c-a382-f4a019ef6c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706461204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.706461204
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1196219676
Short name T136
Test name
Test status
Simulation time 140192946135 ps
CPU time 47.73 seconds
Started Jan 25 02:25:37 AM PST 24
Finished Jan 25 02:26:39 AM PST 24
Peak memory 199316 kb
Host smart-46102ad6-747e-4b08-8a7b-d81079d04c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196219676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1196219676
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3587065711
Short name T977
Test name
Test status
Simulation time 3918069865 ps
CPU time 7.37 seconds
Started Jan 25 02:25:38 AM PST 24
Finished Jan 25 02:25:59 AM PST 24
Peak memory 195936 kb
Host smart-ea27accf-498a-4d96-b932-c6f81f85ab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587065711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3587065711
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2903604231
Short name T423
Test name
Test status
Simulation time 884172376 ps
CPU time 4.24 seconds
Started Jan 25 02:25:16 AM PST 24
Finished Jan 25 02:25:27 AM PST 24
Peak memory 198392 kb
Host smart-05c2629a-ecbd-4ba0-8e46-f73c50c96d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903604231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2903604231
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2493278473
Short name T812
Test name
Test status
Simulation time 374252502722 ps
CPU time 767.13 seconds
Started Jan 25 04:25:19 AM PST 24
Finished Jan 25 04:38:08 AM PST 24
Peak memory 200088 kb
Host smart-ddc2b86f-61b0-49a3-a976-2ec853b23313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493278473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2493278473
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.299196367
Short name T445
Test name
Test status
Simulation time 111473224528 ps
CPU time 361.45 seconds
Started Jan 25 02:25:40 AM PST 24
Finished Jan 25 02:31:59 AM PST 24
Peak memory 209696 kb
Host smart-5a04261e-fd76-4288-ba2f-cd4bcde151e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299196367 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.299196367
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.636080944
Short name T1031
Test name
Test status
Simulation time 953561059 ps
CPU time 3.22 seconds
Started Jan 25 02:25:40 AM PST 24
Finished Jan 25 02:26:00 AM PST 24
Peak memory 198004 kb
Host smart-74b76f41-e185-48c1-a9cb-84c500597cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636080944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.636080944
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.754748897
Short name T138
Test name
Test status
Simulation time 35783915629 ps
CPU time 65.9 seconds
Started Jan 25 02:25:09 AM PST 24
Finished Jan 25 02:26:26 AM PST 24
Peak memory 199932 kb
Host smart-b88bd59a-7e5f-4205-8ab6-f3df2742ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754748897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.754748897
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1421940042
Short name T984
Test name
Test status
Simulation time 13436492 ps
CPU time 0.59 seconds
Started Jan 25 02:26:12 AM PST 24
Finished Jan 25 02:26:14 AM PST 24
Peak memory 195728 kb
Host smart-65485341-3f13-468e-97fd-e33ee66cacda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421940042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1421940042
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.938707640
Short name T1197
Test name
Test status
Simulation time 115236319687 ps
CPU time 41.53 seconds
Started Jan 25 02:26:01 AM PST 24
Finished Jan 25 02:26:47 AM PST 24
Peak memory 200036 kb
Host smart-5b62956e-f000-42bb-a3ed-175d3cfcf818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938707640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.938707640
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3990725257
Short name T700
Test name
Test status
Simulation time 110812648940 ps
CPU time 199.35 seconds
Started Jan 25 02:25:55 AM PST 24
Finished Jan 25 02:29:22 AM PST 24
Peak memory 200072 kb
Host smart-78a14fe3-94bf-4fc3-a482-767ea8718457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990725257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3990725257
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.681083361
Short name T913
Test name
Test status
Simulation time 127477902599 ps
CPU time 634.05 seconds
Started Jan 25 02:46:20 AM PST 24
Finished Jan 25 02:57:04 AM PST 24
Peak memory 200076 kb
Host smart-a7f8923d-7c23-4d2d-8591-e068cd49b0f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681083361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.681083361
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3257524175
Short name T492
Test name
Test status
Simulation time 1512847572 ps
CPU time 2.56 seconds
Started Jan 25 02:26:01 AM PST 24
Finished Jan 25 02:26:07 AM PST 24
Peak memory 196652 kb
Host smart-2ffde651-feec-4d77-b912-1dad9d0db1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257524175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3257524175
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3900699163
Short name T1136
Test name
Test status
Simulation time 233319792355 ps
CPU time 61.17 seconds
Started Jan 25 02:26:00 AM PST 24
Finished Jan 25 02:27:06 AM PST 24
Peak memory 200268 kb
Host smart-08395b3a-d72f-483d-ac48-edeba83d52c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900699163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3900699163
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1091011095
Short name T1081
Test name
Test status
Simulation time 15772998699 ps
CPU time 236.77 seconds
Started Jan 25 04:58:45 AM PST 24
Finished Jan 25 05:02:42 AM PST 24
Peak memory 200064 kb
Host smart-ea1a18e8-b0f3-46d2-9a04-489e042cc820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091011095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1091011095
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.677448201
Short name T213
Test name
Test status
Simulation time 46434211650 ps
CPU time 35.39 seconds
Started Jan 25 02:25:58 AM PST 24
Finished Jan 25 02:26:39 AM PST 24
Peak memory 199324 kb
Host smart-1d92505f-6d0a-4478-9e13-24d7039e4eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677448201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.677448201
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4020038200
Short name T840
Test name
Test status
Simulation time 3005071849 ps
CPU time 1.02 seconds
Started Jan 25 02:26:02 AM PST 24
Finished Jan 25 02:26:06 AM PST 24
Peak memory 195652 kb
Host smart-9d8a6027-05ee-44fb-8439-bf28c444cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020038200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4020038200
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1764793865
Short name T933
Test name
Test status
Simulation time 5875317460 ps
CPU time 46.59 seconds
Started Jan 25 02:25:57 AM PST 24
Finished Jan 25 02:26:50 AM PST 24
Peak memory 199396 kb
Host smart-9729f507-9093-472b-8024-89cc56fc26e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764793865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1764793865
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2330657890
Short name T1223
Test name
Test status
Simulation time 436117180011 ps
CPU time 464.61 seconds
Started Jan 25 02:26:13 AM PST 24
Finished Jan 25 02:34:00 AM PST 24
Peak memory 216428 kb
Host smart-48c822bf-eaad-44af-920b-6b75091947ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330657890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2330657890
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3009472917
Short name T999
Test name
Test status
Simulation time 9805696936 ps
CPU time 84.85 seconds
Started Jan 25 04:14:39 AM PST 24
Finished Jan 25 04:16:09 AM PST 24
Peak memory 208476 kb
Host smart-32e2cc00-24c2-41b0-83f8-baa26051bdfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009472917 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3009472917
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.260302043
Short name T695
Test name
Test status
Simulation time 903058602 ps
CPU time 3.65 seconds
Started Jan 25 03:03:49 AM PST 24
Finished Jan 25 03:04:00 AM PST 24
Peak memory 198508 kb
Host smart-d3112c0a-87cc-4660-914d-d9101843f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260302043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.260302043
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.267162910
Short name T883
Test name
Test status
Simulation time 48570830723 ps
CPU time 72.35 seconds
Started Jan 25 03:17:20 AM PST 24
Finished Jan 25 03:18:39 AM PST 24
Peak memory 200052 kb
Host smart-a83b973e-900d-4e68-8864-aeda7fd4c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267162910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.267162910
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.979761210
Short name T1027
Test name
Test status
Simulation time 35313164 ps
CPU time 0.57 seconds
Started Jan 25 02:26:28 AM PST 24
Finished Jan 25 02:26:30 AM PST 24
Peak memory 194704 kb
Host smart-bacf532b-0d5e-4a26-b2c8-cdad3ebde186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979761210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.979761210
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1236075525
Short name T385
Test name
Test status
Simulation time 229484870570 ps
CPU time 75.45 seconds
Started Jan 25 02:26:15 AM PST 24
Finished Jan 25 02:27:32 AM PST 24
Peak memory 200028 kb
Host smart-a1b81693-6175-40c7-9fa1-931f3a30a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236075525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1236075525
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.50864917
Short name T554
Test name
Test status
Simulation time 71605821373 ps
CPU time 52.02 seconds
Started Jan 25 02:26:11 AM PST 24
Finished Jan 25 02:27:04 AM PST 24
Peak memory 200112 kb
Host smart-c500fb99-62b9-4c0d-8b05-177085ecac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50864917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.50864917
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.989538010
Short name T924
Test name
Test status
Simulation time 11048197743 ps
CPU time 19.4 seconds
Started Jan 25 02:26:14 AM PST 24
Finished Jan 25 02:26:35 AM PST 24
Peak memory 199928 kb
Host smart-363011ad-8e55-4d51-b6c0-54123a5dd51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989538010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.989538010
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1492767912
Short name T633
Test name
Test status
Simulation time 12197016551 ps
CPU time 18.36 seconds
Started Jan 25 02:26:14 AM PST 24
Finished Jan 25 02:26:33 AM PST 24
Peak memory 197516 kb
Host smart-d7c3c634-3e50-4316-89ea-90982e69d664
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492767912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1492767912
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2909271877
Short name T1133
Test name
Test status
Simulation time 88846414738 ps
CPU time 748.62 seconds
Started Jan 25 03:15:03 AM PST 24
Finished Jan 25 03:27:35 AM PST 24
Peak memory 200120 kb
Host smart-5307e0a8-32bd-4e83-90fb-60561310e8d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2909271877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2909271877
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.4169264433
Short name T592
Test name
Test status
Simulation time 1761863583 ps
CPU time 1.01 seconds
Started Jan 25 02:26:28 AM PST 24
Finished Jan 25 02:26:30 AM PST 24
Peak memory 195596 kb
Host smart-c2b48ce3-3c33-4a29-8f43-4338964d091e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169264433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.4169264433
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3806766981
Short name T1218
Test name
Test status
Simulation time 90585193641 ps
CPU time 24.38 seconds
Started Jan 25 02:26:15 AM PST 24
Finished Jan 25 02:26:41 AM PST 24
Peak memory 196912 kb
Host smart-d103882e-6ea4-4c66-a157-6e097130d48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806766981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3806766981
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.4122790494
Short name T619
Test name
Test status
Simulation time 15577146310 ps
CPU time 831.54 seconds
Started Jan 25 02:26:28 AM PST 24
Finished Jan 25 02:40:21 AM PST 24
Peak memory 199912 kb
Host smart-9bb80c11-673d-436d-aa15-66cbfad14ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122790494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.4122790494
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3392114128
Short name T584
Test name
Test status
Simulation time 4918096573 ps
CPU time 21.13 seconds
Started Jan 25 02:26:12 AM PST 24
Finished Jan 25 02:26:35 AM PST 24
Peak memory 198200 kb
Host smart-fab1f783-8a70-4a70-aee0-60380d4b71f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3392114128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3392114128
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.4026893834
Short name T1095
Test name
Test status
Simulation time 39182171606 ps
CPU time 16.64 seconds
Started Jan 25 02:26:15 AM PST 24
Finished Jan 25 02:26:33 AM PST 24
Peak memory 199548 kb
Host smart-a9b1f9f0-7ac6-422b-af9a-cdac0b4c3575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026893834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4026893834
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1781844291
Short name T1032
Test name
Test status
Simulation time 4587345783 ps
CPU time 7.43 seconds
Started Jan 25 02:26:13 AM PST 24
Finished Jan 25 02:26:22 AM PST 24
Peak memory 195640 kb
Host smart-84984c43-27db-4bd7-b7d2-6c511cc52a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781844291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1781844291
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1135646231
Short name T596
Test name
Test status
Simulation time 134408833 ps
CPU time 0.88 seconds
Started Jan 25 02:26:12 AM PST 24
Finished Jan 25 02:26:14 AM PST 24
Peak memory 196640 kb
Host smart-10498fc7-d788-4200-b16a-59e415ab8da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135646231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1135646231
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2755764468
Short name T412
Test name
Test status
Simulation time 203355588246 ps
CPU time 411.51 seconds
Started Jan 25 02:26:32 AM PST 24
Finished Jan 25 02:33:24 AM PST 24
Peak memory 200056 kb
Host smart-4b5c461d-8b0d-4e0d-b983-182cf6fb84b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755764468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2755764468
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.257832602
Short name T577
Test name
Test status
Simulation time 6520897663 ps
CPU time 10.56 seconds
Started Jan 25 02:26:30 AM PST 24
Finished Jan 25 02:26:43 AM PST 24
Peak memory 199216 kb
Host smart-d2a9c2db-e94d-4331-80af-280a4b492b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257832602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.257832602
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.4260097256
Short name T772
Test name
Test status
Simulation time 233904586538 ps
CPU time 82.27 seconds
Started Jan 25 02:26:13 AM PST 24
Finished Jan 25 02:27:36 AM PST 24
Peak memory 200072 kb
Host smart-72f9c614-3684-497c-9f61-2d473147a1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260097256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4260097256
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.4131971118
Short name T963
Test name
Test status
Simulation time 14622933 ps
CPU time 0.68 seconds
Started Jan 25 02:27:24 AM PST 24
Finished Jan 25 02:27:25 AM PST 24
Peak memory 195716 kb
Host smart-a095703e-02ed-454c-94bc-8191f4e3effe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131971118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.4131971118
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.972064490
Short name T853
Test name
Test status
Simulation time 142786312972 ps
CPU time 60.58 seconds
Started Jan 25 02:26:59 AM PST 24
Finished Jan 25 02:28:01 AM PST 24
Peak memory 200064 kb
Host smart-90aa18ab-7d24-48dd-b620-2a305f1c384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972064490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.972064490
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.4158377996
Short name T902
Test name
Test status
Simulation time 16849726967 ps
CPU time 26.65 seconds
Started Jan 25 02:26:59 AM PST 24
Finished Jan 25 02:27:28 AM PST 24
Peak memory 200060 kb
Host smart-2d7711b4-8955-4b71-8dea-e15810c8172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158377996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.4158377996
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.3371425155
Short name T639
Test name
Test status
Simulation time 1010270194628 ps
CPU time 1689.74 seconds
Started Jan 25 02:26:59 AM PST 24
Finished Jan 25 02:55:11 AM PST 24
Peak memory 198748 kb
Host smart-f53cbaac-a22f-47f2-a474-5142fb24a74d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371425155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3371425155
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1742741606
Short name T559
Test name
Test status
Simulation time 83247148284 ps
CPU time 219.5 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:31:06 AM PST 24
Peak memory 200068 kb
Host smart-f386f63c-02db-42dd-bc92-30f4d9cbd18b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742741606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1742741606
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2985373812
Short name T1008
Test name
Test status
Simulation time 3571111046 ps
CPU time 2.25 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:27:29 AM PST 24
Peak memory 196008 kb
Host smart-fe1acb24-fc54-4c69-8e90-8d066f5f1e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985373812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2985373812
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2458243452
Short name T910
Test name
Test status
Simulation time 32520646998 ps
CPU time 14.61 seconds
Started Jan 25 02:26:56 AM PST 24
Finished Jan 25 02:27:12 AM PST 24
Peak memory 196236 kb
Host smart-f98539c7-83dd-473f-bb85-2b367f171adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458243452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2458243452
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4220104783
Short name T1038
Test name
Test status
Simulation time 26426411126 ps
CPU time 196.53 seconds
Started Jan 25 02:27:24 AM PST 24
Finished Jan 25 02:30:42 AM PST 24
Peak memory 200000 kb
Host smart-31f151ec-a461-4e73-88d2-f61952bb9fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220104783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4220104783
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2518044264
Short name T792
Test name
Test status
Simulation time 3543288875 ps
CPU time 9.01 seconds
Started Jan 25 02:26:55 AM PST 24
Finished Jan 25 02:27:05 AM PST 24
Peak memory 198344 kb
Host smart-d50cf1c9-d58e-4465-a18c-29eb27e43bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2518044264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2518044264
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.302135026
Short name T1001
Test name
Test status
Simulation time 46931409146 ps
CPU time 31.42 seconds
Started Jan 25 02:26:56 AM PST 24
Finished Jan 25 02:27:29 AM PST 24
Peak memory 195648 kb
Host smart-9816fd70-2b7b-4024-a33d-6490c6dd986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302135026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.302135026
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1858007862
Short name T1166
Test name
Test status
Simulation time 5768622938 ps
CPU time 13.64 seconds
Started Jan 25 02:26:38 AM PST 24
Finished Jan 25 02:27:00 AM PST 24
Peak memory 199488 kb
Host smart-2305605c-2aec-45b1-806f-0a6499b277c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858007862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1858007862
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.199718972
Short name T861
Test name
Test status
Simulation time 274996056510 ps
CPU time 121.67 seconds
Started Jan 25 02:27:26 AM PST 24
Finished Jan 25 02:29:29 AM PST 24
Peak memory 199272 kb
Host smart-431066ac-dbe4-4bf7-aa3b-1f3960896427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199718972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.199718972
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.338026308
Short name T770
Test name
Test status
Simulation time 63998033823 ps
CPU time 1197.68 seconds
Started Jan 25 02:27:22 AM PST 24
Finished Jan 25 02:47:21 AM PST 24
Peak memory 216532 kb
Host smart-33c829a1-3bb8-4021-8177-7142a58ef7c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338026308 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.338026308
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2964731563
Short name T567
Test name
Test status
Simulation time 2558328077 ps
CPU time 2.84 seconds
Started Jan 25 02:26:58 AM PST 24
Finished Jan 25 02:27:02 AM PST 24
Peak memory 199124 kb
Host smart-b0491b33-7c2f-4b67-9b16-2a5c51a25f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964731563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2964731563
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2220857225
Short name T613
Test name
Test status
Simulation time 13135005497 ps
CPU time 14.2 seconds
Started Jan 25 02:26:39 AM PST 24
Finished Jan 25 02:27:00 AM PST 24
Peak memory 200104 kb
Host smart-5f43cb49-793f-437b-910b-59ca54993d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220857225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2220857225
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2593301511
Short name T989
Test name
Test status
Simulation time 40824905 ps
CPU time 0.57 seconds
Started Jan 25 04:46:03 AM PST 24
Finished Jan 25 04:46:06 AM PST 24
Peak memory 194644 kb
Host smart-d35ae08a-37fa-4b30-ab35-04cde6be74df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593301511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2593301511
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.986705367
Short name T887
Test name
Test status
Simulation time 36383758440 ps
CPU time 22.04 seconds
Started Jan 25 02:27:26 AM PST 24
Finished Jan 25 02:27:49 AM PST 24
Peak memory 199128 kb
Host smart-63cb476b-5f59-4f4d-beaf-53f8e5222917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986705367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.986705367
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3573133589
Short name T218
Test name
Test status
Simulation time 156815045983 ps
CPU time 70.83 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:28:37 AM PST 24
Peak memory 200020 kb
Host smart-428e9fb2-b56f-4266-8c3e-3a924480533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573133589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3573133589
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2510045681
Short name T589
Test name
Test status
Simulation time 46828639622 ps
CPU time 9.97 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:27:36 AM PST 24
Peak memory 200092 kb
Host smart-111f62c7-07c6-4076-be02-26fe144cbcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510045681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2510045681
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2070846773
Short name T15
Test name
Test status
Simulation time 125131402596 ps
CPU time 418.89 seconds
Started Jan 25 03:06:00 AM PST 24
Finished Jan 25 03:13:00 AM PST 24
Peak memory 200092 kb
Host smart-7f5f8bb0-acbc-44b3-b6c7-5d4eae485b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070846773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2070846773
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1405049896
Short name T1191
Test name
Test status
Simulation time 2261057066 ps
CPU time 2.69 seconds
Started Jan 25 02:27:43 AM PST 24
Finished Jan 25 02:27:47 AM PST 24
Peak memory 198568 kb
Host smart-09db3790-34ec-42df-ad87-02194b1cae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405049896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1405049896
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3659632534
Short name T493
Test name
Test status
Simulation time 23003141646 ps
CPU time 19.27 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:27:45 AM PST 24
Peak memory 198632 kb
Host smart-61f894bd-4ffb-4e2f-a0ad-fba434a7a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659632534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3659632534
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3164447111
Short name T848
Test name
Test status
Simulation time 8561328250 ps
CPU time 231.65 seconds
Started Jan 25 02:27:46 AM PST 24
Finished Jan 25 02:31:38 AM PST 24
Peak memory 200088 kb
Host smart-48b4688e-7b37-42fc-beb4-51dcd32301b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3164447111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3164447111
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3010138780
Short name T560
Test name
Test status
Simulation time 1919655830 ps
CPU time 9.79 seconds
Started Jan 25 02:27:24 AM PST 24
Finished Jan 25 02:27:35 AM PST 24
Peak memory 197692 kb
Host smart-0825b4ab-3c44-4971-bea9-a5de414d0b5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010138780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3010138780
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3698652945
Short name T542
Test name
Test status
Simulation time 207593706510 ps
CPU time 46.61 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:28:13 AM PST 24
Peak memory 200028 kb
Host smart-7922d26e-cbab-4a50-8a63-60b265f206c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698652945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3698652945
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3862376246
Short name T784
Test name
Test status
Simulation time 38431491331 ps
CPU time 16.86 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:27:43 AM PST 24
Peak memory 195684 kb
Host smart-009a7b07-a26d-47d5-afef-7393396bffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862376246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3862376246
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1827579672
Short name T834
Test name
Test status
Simulation time 777991736 ps
CPU time 1.39 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:27:28 AM PST 24
Peak memory 198104 kb
Host smart-63af7de9-42a0-4563-b9f5-b66d5a79d1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827579672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1827579672
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2527800293
Short name T874
Test name
Test status
Simulation time 70842592377 ps
CPU time 191.55 seconds
Started Jan 25 04:13:15 AM PST 24
Finished Jan 25 04:16:28 AM PST 24
Peak memory 210584 kb
Host smart-c48dcc01-c817-4ec6-baed-99d9c761cf19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527800293 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2527800293
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1454702652
Short name T732
Test name
Test status
Simulation time 12491560360 ps
CPU time 7.03 seconds
Started Jan 25 02:27:24 AM PST 24
Finished Jan 25 02:27:32 AM PST 24
Peak memory 199592 kb
Host smart-a131897e-d914-4d37-afcb-bba6e19064b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454702652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1454702652
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4051079860
Short name T705
Test name
Test status
Simulation time 26225188660 ps
CPU time 14.32 seconds
Started Jan 25 02:27:25 AM PST 24
Finished Jan 25 02:27:40 AM PST 24
Peak memory 200068 kb
Host smart-32eebf19-44ce-4230-af11-c0205e881f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051079860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4051079860
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2259873426
Short name T531
Test name
Test status
Simulation time 36218922 ps
CPU time 0.58 seconds
Started Jan 25 02:31:59 AM PST 24
Finished Jan 25 02:32:01 AM PST 24
Peak memory 194624 kb
Host smart-fae81eb6-ca88-4017-bcdd-109545d740bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259873426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2259873426
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1564689332
Short name T433
Test name
Test status
Simulation time 257323651360 ps
CPU time 123.44 seconds
Started Jan 25 02:31:55 AM PST 24
Finished Jan 25 02:33:59 AM PST 24
Peak memory 200104 kb
Host smart-93fdc477-703d-49ce-a438-478d41ee3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564689332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1564689332
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.80419793
Short name T981
Test name
Test status
Simulation time 36575453465 ps
CPU time 16.39 seconds
Started Jan 25 02:31:51 AM PST 24
Finished Jan 25 02:32:09 AM PST 24
Peak memory 198984 kb
Host smart-4cb1edbd-9a31-4946-b63b-1cd16ae42580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80419793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.80419793
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1484524453
Short name T303
Test name
Test status
Simulation time 28889125808 ps
CPU time 45.92 seconds
Started Jan 25 03:07:28 AM PST 24
Finished Jan 25 03:08:15 AM PST 24
Peak memory 200096 kb
Host smart-669529d1-7244-471e-92ac-296886561d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484524453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1484524453
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1777681368
Short name T893
Test name
Test status
Simulation time 1716971446900 ps
CPU time 2705.59 seconds
Started Jan 25 07:08:14 AM PST 24
Finished Jan 25 07:53:21 AM PST 24
Peak memory 199456 kb
Host smart-80a76b2d-4655-4bcd-b44c-c14245318dd6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777681368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1777681368
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1413550778
Short name T987
Test name
Test status
Simulation time 190205175913 ps
CPU time 407.27 seconds
Started Jan 25 03:14:45 AM PST 24
Finished Jan 25 03:21:33 AM PST 24
Peak memory 200144 kb
Host smart-5db5e8a4-f0d6-4819-ae89-5bde0a45638a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413550778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1413550778
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3886947357
Short name T544
Test name
Test status
Simulation time 5334586761 ps
CPU time 3.75 seconds
Started Jan 25 02:31:55 AM PST 24
Finished Jan 25 02:32:00 AM PST 24
Peak memory 198132 kb
Host smart-2c679e6f-a52b-41f7-8548-572a91de557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886947357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3886947357
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3683576718
Short name T927
Test name
Test status
Simulation time 90293805884 ps
CPU time 197.29 seconds
Started Jan 25 02:31:59 AM PST 24
Finished Jan 25 02:35:18 AM PST 24
Peak memory 200304 kb
Host smart-00149d2c-bfc9-4a66-b2cd-21d01d8115d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683576718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3683576718
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1415696080
Short name T281
Test name
Test status
Simulation time 16066425280 ps
CPU time 1056.25 seconds
Started Jan 25 03:12:30 AM PST 24
Finished Jan 25 03:30:10 AM PST 24
Peak memory 200080 kb
Host smart-e0149556-050c-47a1-95c5-e11667e67509
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415696080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1415696080
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.174502437
Short name T587
Test name
Test status
Simulation time 4118210136 ps
CPU time 34.45 seconds
Started Jan 25 02:57:14 AM PST 24
Finished Jan 25 02:57:50 AM PST 24
Peak memory 198404 kb
Host smart-f43d5ee2-9a0f-41ca-bae5-e24f868b580c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174502437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.174502437
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1179119887
Short name T1077
Test name
Test status
Simulation time 23210306099 ps
CPU time 19.22 seconds
Started Jan 25 02:31:56 AM PST 24
Finished Jan 25 02:32:17 AM PST 24
Peak memory 199116 kb
Host smart-48245222-37b7-4a64-8721-44726153557a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179119887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1179119887
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.393495713
Short name T1144
Test name
Test status
Simulation time 587194184 ps
CPU time 1.71 seconds
Started Jan 25 03:28:39 AM PST 24
Finished Jan 25 03:28:42 AM PST 24
Peak memory 195576 kb
Host smart-a5d80bb7-16be-4bc9-954a-635c560fb4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393495713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.393495713
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3350202461
Short name T814
Test name
Test status
Simulation time 709680331 ps
CPU time 1.93 seconds
Started Jan 25 02:52:51 AM PST 24
Finished Jan 25 02:52:54 AM PST 24
Peak memory 197828 kb
Host smart-5f85543a-e894-427c-ab9a-a2350d8d0eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350202461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3350202461
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2800642992
Short name T259
Test name
Test status
Simulation time 2208753738627 ps
CPU time 1322.81 seconds
Started Jan 25 02:32:00 AM PST 24
Finished Jan 25 02:54:04 AM PST 24
Peak memory 208468 kb
Host smart-2099da5c-ca66-42e2-9664-2743398537a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800642992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2800642992
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.134914070
Short name T942
Test name
Test status
Simulation time 64366034350 ps
CPU time 651.15 seconds
Started Jan 25 02:31:54 AM PST 24
Finished Jan 25 02:42:46 AM PST 24
Peak memory 214796 kb
Host smart-a8063cf9-8665-482d-8cbe-99b9db6ff45a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134914070 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.134914070
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1231742514
Short name T768
Test name
Test status
Simulation time 1389071811 ps
CPU time 2.99 seconds
Started Jan 25 03:56:51 AM PST 24
Finished Jan 25 03:56:56 AM PST 24
Peak memory 198560 kb
Host smart-72dd01a2-612c-41a0-83c0-34d5ce1c5998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231742514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1231742514
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.843133493
Short name T697
Test name
Test status
Simulation time 11299484401 ps
CPU time 19.83 seconds
Started Jan 25 02:32:00 AM PST 24
Finished Jan 25 02:32:21 AM PST 24
Peak memory 199888 kb
Host smart-b095c8a1-f59c-4be5-b3d7-8c42ca2bae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843133493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.843133493
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.132851912
Short name T1180
Test name
Test status
Simulation time 14268061 ps
CPU time 0.59 seconds
Started Jan 25 02:32:22 AM PST 24
Finished Jan 25 02:32:24 AM PST 24
Peak memory 195716 kb
Host smart-8ce395f4-b63c-4f25-962d-a7b5563aa1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132851912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.132851912
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2581490119
Short name T569
Test name
Test status
Simulation time 114587353790 ps
CPU time 51.05 seconds
Started Jan 25 03:57:21 AM PST 24
Finished Jan 25 03:58:12 AM PST 24
Peak memory 200048 kb
Host smart-1cbb71ed-98b8-4a6a-adb2-e419d33ddfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581490119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2581490119
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.154513344
Short name T343
Test name
Test status
Simulation time 73719792800 ps
CPU time 15.46 seconds
Started Jan 25 02:32:00 AM PST 24
Finished Jan 25 02:32:16 AM PST 24
Peak memory 199984 kb
Host smart-ddd91447-d030-4e04-b741-e8d3e350f71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154513344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.154513344
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.4107825244
Short name T448
Test name
Test status
Simulation time 811253214955 ps
CPU time 301.81 seconds
Started Jan 25 02:32:21 AM PST 24
Finished Jan 25 02:37:24 AM PST 24
Peak memory 198996 kb
Host smart-03fad84f-8093-4372-872b-c296dd4e627a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107825244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4107825244
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4139152419
Short name T974
Test name
Test status
Simulation time 46628022924 ps
CPU time 213.99 seconds
Started Jan 25 02:32:21 AM PST 24
Finished Jan 25 02:35:56 AM PST 24
Peak memory 200092 kb
Host smart-134224c3-7e76-42ab-80e2-430c538bb745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139152419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4139152419
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.706820758
Short name T1030
Test name
Test status
Simulation time 8329561794 ps
CPU time 17.09 seconds
Started Jan 25 02:32:27 AM PST 24
Finished Jan 25 02:32:46 AM PST 24
Peak memory 199220 kb
Host smart-3f5fc9f2-2ff2-4c10-82b9-3309a9c549bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706820758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.706820758
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.757229386
Short name T914
Test name
Test status
Simulation time 65717554346 ps
CPU time 100.59 seconds
Started Jan 25 02:32:21 AM PST 24
Finished Jan 25 02:34:03 AM PST 24
Peak memory 200208 kb
Host smart-064cd26a-6c01-405a-acf5-1755ab15e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757229386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.757229386
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2641177264
Short name T767
Test name
Test status
Simulation time 14807027069 ps
CPU time 177.78 seconds
Started Jan 25 02:32:22 AM PST 24
Finished Jan 25 02:35:21 AM PST 24
Peak memory 200060 kb
Host smart-7721a6dc-f4cd-421c-9848-ff1c0391e0cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641177264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2641177264
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1309754767
Short name T1100
Test name
Test status
Simulation time 202446275 ps
CPU time 1.31 seconds
Started Jan 25 03:54:49 AM PST 24
Finished Jan 25 03:54:51 AM PST 24
Peak memory 197780 kb
Host smart-fb2ad67e-479e-4e07-8475-3cd63e5b6ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1309754767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1309754767
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2347021287
Short name T816
Test name
Test status
Simulation time 119797574316 ps
CPU time 43.89 seconds
Started Jan 25 02:32:24 AM PST 24
Finished Jan 25 02:33:09 AM PST 24
Peak memory 199056 kb
Host smart-18e6a1c0-38f1-4bb9-bd6a-00c482d7bb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347021287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2347021287
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.28525871
Short name T1117
Test name
Test status
Simulation time 32012489086 ps
CPU time 49.16 seconds
Started Jan 25 02:32:22 AM PST 24
Finished Jan 25 02:33:13 AM PST 24
Peak memory 195684 kb
Host smart-90bfc6d4-dae0-4abd-ad05-f47f1a88ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28525871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.28525871
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2014171652
Short name T1014
Test name
Test status
Simulation time 5859303301 ps
CPU time 14.93 seconds
Started Jan 25 05:56:35 AM PST 24
Finished Jan 25 05:56:51 AM PST 24
Peak memory 198864 kb
Host smart-bbd2584d-6a1e-4ce2-b15b-de037cc53fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014171652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2014171652
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3991145654
Short name T1111
Test name
Test status
Simulation time 24900688518 ps
CPU time 122.68 seconds
Started Jan 25 02:32:21 AM PST 24
Finished Jan 25 02:34:25 AM PST 24
Peak memory 216100 kb
Host smart-30cc615c-1530-4662-9fa1-8cc32fcb9d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991145654 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3991145654
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2387655139
Short name T572
Test name
Test status
Simulation time 7611963522 ps
CPU time 1.88 seconds
Started Jan 25 02:32:26 AM PST 24
Finished Jan 25 02:32:29 AM PST 24
Peak memory 198664 kb
Host smart-6c8793af-db76-4995-8fe4-3e0cf4b2c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387655139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2387655139
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3423312607
Short name T1172
Test name
Test status
Simulation time 64349942106 ps
CPU time 146.56 seconds
Started Jan 25 02:31:56 AM PST 24
Finished Jan 25 02:34:24 AM PST 24
Peak memory 200072 kb
Host smart-1ef1b80f-36ed-4c93-91c9-4d6cf2decad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423312607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3423312607
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3688479662
Short name T722
Test name
Test status
Simulation time 34191672 ps
CPU time 0.64 seconds
Started Jan 25 02:04:49 AM PST 24
Finished Jan 25 02:05:00 AM PST 24
Peak memory 195728 kb
Host smart-6aadc0fb-72d7-4a72-b415-52c9caebadba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688479662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3688479662
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3991445183
Short name T437
Test name
Test status
Simulation time 74165501522 ps
CPU time 103.93 seconds
Started Jan 25 02:18:25 AM PST 24
Finished Jan 25 02:20:10 AM PST 24
Peak memory 200040 kb
Host smart-cc92920e-ca23-40b3-99a1-0df38c01d5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991445183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3991445183
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2916480291
Short name T1215
Test name
Test status
Simulation time 155513912487 ps
CPU time 75.92 seconds
Started Jan 25 02:02:56 AM PST 24
Finished Jan 25 02:04:17 AM PST 24
Peak memory 200028 kb
Host smart-bb647a9d-b36e-440d-b728-d8f8fba4f1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916480291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2916480291
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1633227601
Short name T277
Test name
Test status
Simulation time 15815279764 ps
CPU time 27.37 seconds
Started Jan 25 02:02:56 AM PST 24
Finished Jan 25 02:03:29 AM PST 24
Peak memory 199376 kb
Host smart-e1e55982-29d3-4e2a-9119-4ef5b332a480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633227601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1633227601
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.55299221
Short name T694
Test name
Test status
Simulation time 190387532381 ps
CPU time 298.13 seconds
Started Jan 25 02:04:41 AM PST 24
Finished Jan 25 02:09:47 AM PST 24
Peak memory 199560 kb
Host smart-944fad81-3f9d-4c76-a906-22af5b7a258c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55299221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.55299221
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2713679258
Short name T972
Test name
Test status
Simulation time 157090603358 ps
CPU time 329.95 seconds
Started Jan 25 02:04:49 AM PST 24
Finished Jan 25 02:10:30 AM PST 24
Peak memory 200036 kb
Host smart-493d0aae-0f63-4e76-910c-5ce7b2d4f168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713679258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2713679258
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2841581399
Short name T754
Test name
Test status
Simulation time 4778586479 ps
CPU time 8.73 seconds
Started Jan 25 02:04:40 AM PST 24
Finished Jan 25 02:04:53 AM PST 24
Peak memory 197760 kb
Host smart-b82d1d1b-e0a8-44a8-b7c4-ae2a8d4edd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841581399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2841581399
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.770438055
Short name T786
Test name
Test status
Simulation time 201923702520 ps
CPU time 69.96 seconds
Started Jan 25 02:04:47 AM PST 24
Finished Jan 25 02:06:09 AM PST 24
Peak memory 200160 kb
Host smart-af09a89e-1fe1-44cc-8ea9-9b24729d09f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770438055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.770438055
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.421623003
Short name T419
Test name
Test status
Simulation time 10798837543 ps
CPU time 135.81 seconds
Started Jan 25 02:04:43 AM PST 24
Finished Jan 25 02:07:09 AM PST 24
Peak memory 200012 kb
Host smart-b9d7129c-d3d8-4c64-a85c-3bbf9b218fe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421623003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.421623003
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.795961548
Short name T775
Test name
Test status
Simulation time 480067591 ps
CPU time 1.21 seconds
Started Jan 25 02:37:14 AM PST 24
Finished Jan 25 02:37:17 AM PST 24
Peak memory 197856 kb
Host smart-4712c95a-de94-4884-bfe6-71e40d49e2fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=795961548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.795961548
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2488216650
Short name T341
Test name
Test status
Simulation time 34102214185 ps
CPU time 89.39 seconds
Started Jan 25 02:04:42 AM PST 24
Finished Jan 25 02:06:22 AM PST 24
Peak memory 199908 kb
Host smart-7939240a-4c34-4a46-8275-2c84af511fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488216650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2488216650
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1387553255
Short name T429
Test name
Test status
Simulation time 6468315335 ps
CPU time 11.74 seconds
Started Jan 25 02:04:41 AM PST 24
Finished Jan 25 02:05:03 AM PST 24
Peak memory 195628 kb
Host smart-2ae019ce-8432-4731-a5b6-7e37d73649ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387553255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1387553255
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.32774099
Short name T83
Test name
Test status
Simulation time 587084481 ps
CPU time 1.21 seconds
Started Jan 25 02:04:46 AM PST 24
Finished Jan 25 02:05:01 AM PST 24
Peak memory 217260 kb
Host smart-382ebc6e-d388-4911-b0a1-8f7bb6a2e4c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32774099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.32774099
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3854580932
Short name T830
Test name
Test status
Simulation time 298793300 ps
CPU time 1.19 seconds
Started Jan 25 02:02:52 AM PST 24
Finished Jan 25 02:03:00 AM PST 24
Peak memory 197760 kb
Host smart-87a5394b-1460-4189-9e29-5b3e957655f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854580932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3854580932
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3218644248
Short name T1155
Test name
Test status
Simulation time 1163738913931 ps
CPU time 1648.56 seconds
Started Jan 25 02:04:44 AM PST 24
Finished Jan 25 02:32:27 AM PST 24
Peak memory 208472 kb
Host smart-36fc986e-c188-48b9-9fb6-bd3cd3cb01fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218644248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3218644248
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1804884143
Short name T895
Test name
Test status
Simulation time 211006252174 ps
CPU time 625.94 seconds
Started Jan 25 02:04:43 AM PST 24
Finished Jan 25 02:15:20 AM PST 24
Peak memory 230440 kb
Host smart-2009d475-b208-4ef2-8300-964592477d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804884143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1804884143
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2458747386
Short name T730
Test name
Test status
Simulation time 1197925243 ps
CPU time 4.75 seconds
Started Jan 25 02:04:43 AM PST 24
Finished Jan 25 02:04:59 AM PST 24
Peak memory 198424 kb
Host smart-3d7751ba-7dbf-41e7-b104-6d8efb1a9c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458747386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2458747386
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.62230414
Short name T1146
Test name
Test status
Simulation time 98278422218 ps
CPU time 16.89 seconds
Started Jan 25 03:40:00 AM PST 24
Finished Jan 25 03:40:18 AM PST 24
Peak memory 200096 kb
Host smart-b2c0b14a-09a6-485d-8c0b-5fe9e5d8b6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62230414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.62230414
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.254099194
Short name T777
Test name
Test status
Simulation time 29048989 ps
CPU time 0.55 seconds
Started Jan 25 02:32:40 AM PST 24
Finished Jan 25 02:32:43 AM PST 24
Peak memory 195656 kb
Host smart-1117ad15-97d1-4a58-b962-ea86e93c6975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254099194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.254099194
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1934870402
Short name T399
Test name
Test status
Simulation time 23041992821 ps
CPU time 20.17 seconds
Started Jan 25 02:32:35 AM PST 24
Finished Jan 25 02:32:56 AM PST 24
Peak memory 199552 kb
Host smart-24c36733-a0b4-49dc-8c9c-1459cba8a54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934870402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1934870402
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3113466431
Short name T604
Test name
Test status
Simulation time 50073460901 ps
CPU time 40.44 seconds
Started Jan 25 02:32:40 AM PST 24
Finished Jan 25 02:33:22 AM PST 24
Peak memory 199992 kb
Host smart-8ffaa74c-d6cd-40ff-a62a-85b3902581c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113466431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3113466431
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3298558198
Short name T11
Test name
Test status
Simulation time 75154579702 ps
CPU time 129.47 seconds
Started Jan 25 02:32:38 AM PST 24
Finished Jan 25 02:34:49 AM PST 24
Peak memory 200092 kb
Host smart-2d0d9c64-8dc5-4457-b490-8a91e3dd3258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298558198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3298558198
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1156458812
Short name T771
Test name
Test status
Simulation time 27777070232 ps
CPU time 17.25 seconds
Started Jan 25 02:32:36 AM PST 24
Finished Jan 25 02:32:54 AM PST 24
Peak memory 198912 kb
Host smart-8c3d9e4e-bbb2-45e8-8f73-c5f351171186
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156458812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1156458812
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3666059512
Short name T728
Test name
Test status
Simulation time 95723275784 ps
CPU time 1065.5 seconds
Started Jan 25 02:32:30 AM PST 24
Finished Jan 25 02:50:17 AM PST 24
Peak memory 200036 kb
Host smart-1c089fb0-fb01-47e8-8f83-77654bdaf8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666059512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3666059512
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2509585895
Short name T600
Test name
Test status
Simulation time 6163455407 ps
CPU time 4.09 seconds
Started Jan 25 02:32:37 AM PST 24
Finished Jan 25 02:32:42 AM PST 24
Peak memory 198168 kb
Host smart-7fef8e5d-b566-46eb-b29a-c9867d1df898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509585895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2509585895
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.2311349438
Short name T832
Test name
Test status
Simulation time 35642543266 ps
CPU time 100.14 seconds
Started Jan 25 02:32:41 AM PST 24
Finished Jan 25 02:34:23 AM PST 24
Peak memory 200072 kb
Host smart-b61965e2-61f0-4600-b984-bce5285ebf1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311349438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2311349438
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2227822586
Short name T869
Test name
Test status
Simulation time 147494867 ps
CPU time 0.65 seconds
Started Jan 25 02:32:39 AM PST 24
Finished Jan 25 02:32:42 AM PST 24
Peak memory 195560 kb
Host smart-8bf08533-8cd6-4ad2-b1f8-752770d6cc3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227822586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2227822586
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3387966220
Short name T752
Test name
Test status
Simulation time 24611817742 ps
CPU time 30.7 seconds
Started Jan 25 02:32:38 AM PST 24
Finished Jan 25 02:33:09 AM PST 24
Peak memory 199824 kb
Host smart-31c0a2b5-7c7f-4fca-bd78-0a1f51461104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387966220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3387966220
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1531188876
Short name T858
Test name
Test status
Simulation time 29485068815 ps
CPU time 12.5 seconds
Started Jan 25 02:32:41 AM PST 24
Finished Jan 25 02:32:57 AM PST 24
Peak memory 195588 kb
Host smart-d2aff02a-ef5a-45cf-8c9d-2f83e667a8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531188876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1531188876
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3718751117
Short name T670
Test name
Test status
Simulation time 932478403 ps
CPU time 3.52 seconds
Started Jan 25 02:32:25 AM PST 24
Finished Jan 25 02:32:30 AM PST 24
Peak memory 197836 kb
Host smart-233c753f-f9dd-4e21-a64c-fdde1331ff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718751117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3718751117
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1815632270
Short name T1211
Test name
Test status
Simulation time 188243713193 ps
CPU time 2065.53 seconds
Started Jan 25 02:32:42 AM PST 24
Finished Jan 25 03:07:11 AM PST 24
Peak memory 208520 kb
Host smart-e7dcd400-9727-4c8a-9085-aa75e3f0d66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815632270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1815632270
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.458076938
Short name T1128
Test name
Test status
Simulation time 114435950907 ps
CPU time 655.41 seconds
Started Jan 25 02:32:39 AM PST 24
Finished Jan 25 02:43:35 AM PST 24
Peak memory 216736 kb
Host smart-684d43d6-f371-49f0-bb5d-f2b5de169468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458076938 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.458076938
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3437919609
Short name T820
Test name
Test status
Simulation time 910469754 ps
CPU time 3.23 seconds
Started Jan 25 02:32:40 AM PST 24
Finished Jan 25 02:32:44 AM PST 24
Peak memory 198452 kb
Host smart-0ae66f4a-d6df-4216-a0d8-73d3746c5851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437919609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3437919609
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3172739815
Short name T939
Test name
Test status
Simulation time 42975028741 ps
CPU time 73.33 seconds
Started Jan 25 02:32:37 AM PST 24
Finished Jan 25 02:33:52 AM PST 24
Peak memory 200056 kb
Host smart-a04a38dd-d4a3-4f9b-9749-7095adecc05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172739815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3172739815
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.473404902
Short name T897
Test name
Test status
Simulation time 18386127 ps
CPU time 0.57 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:32:52 AM PST 24
Peak memory 194684 kb
Host smart-f8ddff09-e912-4411-9e90-3c34c280706a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473404902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.473404902
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4116524051
Short name T539
Test name
Test status
Simulation time 33172262324 ps
CPU time 102.17 seconds
Started Jan 25 02:32:42 AM PST 24
Finished Jan 25 02:34:28 AM PST 24
Peak memory 200096 kb
Host smart-8d6fe4be-15cf-4780-9a12-87d243596112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116524051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4116524051
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2279570019
Short name T677
Test name
Test status
Simulation time 141979507647 ps
CPU time 120.38 seconds
Started Jan 25 02:32:41 AM PST 24
Finished Jan 25 02:34:43 AM PST 24
Peak memory 200040 kb
Host smart-a91c2e8c-2444-462d-8e42-b6b2f527f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279570019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2279570019
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2928324460
Short name T222
Test name
Test status
Simulation time 261546290205 ps
CPU time 55.75 seconds
Started Jan 25 02:32:42 AM PST 24
Finished Jan 25 02:33:41 AM PST 24
Peak memory 200112 kb
Host smart-538ca868-54c9-4f44-8105-e9a9c77a5f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928324460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2928324460
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1805769313
Short name T941
Test name
Test status
Simulation time 8035409633 ps
CPU time 13.13 seconds
Started Jan 25 02:32:43 AM PST 24
Finished Jan 25 02:32:59 AM PST 24
Peak memory 195688 kb
Host smart-735cc154-1946-4608-ba51-fad0ff9212ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805769313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1805769313
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.901533523
Short name T1174
Test name
Test status
Simulation time 114388012465 ps
CPU time 330.96 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:38:21 AM PST 24
Peak memory 200048 kb
Host smart-d277bd94-2401-452b-bc68-2001846a9f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=901533523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.901533523
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2193950623
Short name T489
Test name
Test status
Simulation time 190228831 ps
CPU time 0.85 seconds
Started Jan 25 02:32:43 AM PST 24
Finished Jan 25 02:32:47 AM PST 24
Peak memory 195560 kb
Host smart-227cced7-a444-40e3-8c82-4682f6fed4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193950623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2193950623
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3738665211
Short name T148
Test name
Test status
Simulation time 27771741404 ps
CPU time 34.6 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:33:25 AM PST 24
Peak memory 197276 kb
Host smart-ca2d0afd-c463-4ac3-85f7-84219cfb9bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738665211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3738665211
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.382528053
Short name T424
Test name
Test status
Simulation time 22964915746 ps
CPU time 1403.54 seconds
Started Jan 25 02:32:43 AM PST 24
Finished Jan 25 02:56:10 AM PST 24
Peak memory 200084 kb
Host smart-491be641-5244-4cc5-9c47-64a5dc2f8265
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382528053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.382528053
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2273006823
Short name T920
Test name
Test status
Simulation time 472134375 ps
CPU time 0.88 seconds
Started Jan 25 02:32:42 AM PST 24
Finished Jan 25 02:32:46 AM PST 24
Peak memory 196604 kb
Host smart-fbd5a2c5-5371-4ba1-a159-9b59056cb20e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273006823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2273006823
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1861447525
Short name T810
Test name
Test status
Simulation time 29744274343 ps
CPU time 14.89 seconds
Started Jan 25 02:32:43 AM PST 24
Finished Jan 25 02:33:01 AM PST 24
Peak memory 199132 kb
Host smart-7e9dc8c9-e02f-4e33-8a2a-3ce191a4d3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861447525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1861447525
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1483972161
Short name T985
Test name
Test status
Simulation time 2194432778 ps
CPU time 2.49 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:32:53 AM PST 24
Peak memory 195640 kb
Host smart-ca70989f-ca81-4c03-b07b-bfb6d3b889ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483972161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1483972161
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.960761085
Short name T710
Test name
Test status
Simulation time 887199198 ps
CPU time 2.1 seconds
Started Jan 25 02:32:39 AM PST 24
Finished Jan 25 02:32:42 AM PST 24
Peak memory 198312 kb
Host smart-70d6fb16-4f0a-4ec4-860d-eb9e9d08d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960761085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.960761085
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2736498390
Short name T1029
Test name
Test status
Simulation time 1617940450 ps
CPU time 2.04 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:32:53 AM PST 24
Peak memory 198256 kb
Host smart-f96aba11-4951-4301-8368-05a7463b0b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736498390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2736498390
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.842308438
Short name T214
Test name
Test status
Simulation time 98548632716 ps
CPU time 192.44 seconds
Started Jan 25 02:32:43 AM PST 24
Finished Jan 25 02:35:59 AM PST 24
Peak memory 200080 kb
Host smart-c7e36dcb-2a98-424c-9bb1-419bb7557360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842308438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.842308438
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.71603196
Short name T1025
Test name
Test status
Simulation time 11763554 ps
CPU time 0.55 seconds
Started Jan 25 02:33:15 AM PST 24
Finished Jan 25 02:33:22 AM PST 24
Peak memory 194636 kb
Host smart-863450f8-5c96-4b39-bce9-c8fbdddca0b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71603196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.71603196
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.784472239
Short name T1101
Test name
Test status
Simulation time 70026385182 ps
CPU time 104.91 seconds
Started Jan 25 02:32:45 AM PST 24
Finished Jan 25 02:34:34 AM PST 24
Peak memory 200044 kb
Host smart-ac9e5f04-b78b-4465-a5b2-e6835a2475e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784472239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.784472239
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2645532230
Short name T386
Test name
Test status
Simulation time 48878386239 ps
CPU time 76.81 seconds
Started Jan 25 02:32:48 AM PST 24
Finished Jan 25 02:34:09 AM PST 24
Peak memory 198988 kb
Host smart-453eaf9f-7638-46c9-b254-ac1b8bb30c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645532230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2645532230
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3266654491
Short name T225
Test name
Test status
Simulation time 22739138039 ps
CPU time 36.12 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:33:27 AM PST 24
Peak memory 199940 kb
Host smart-8ad1e4f4-af47-4ada-946c-5499dcb26b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266654491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3266654491
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1761105860
Short name T586
Test name
Test status
Simulation time 47771555204 ps
CPU time 86.17 seconds
Started Jan 25 02:32:46 AM PST 24
Finished Jan 25 02:34:16 AM PST 24
Peak memory 200080 kb
Host smart-b13d0c1f-92a9-4321-b4e9-1a78a0a389b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761105860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1761105860
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.349049746
Short name T398
Test name
Test status
Simulation time 91116403259 ps
CPU time 514.85 seconds
Started Jan 25 02:32:57 AM PST 24
Finished Jan 25 02:41:34 AM PST 24
Peak memory 200072 kb
Host smart-b32abd45-1880-4468-883e-c258fa9d1113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349049746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.349049746
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3438883114
Short name T28
Test name
Test status
Simulation time 8666896796 ps
CPU time 17.82 seconds
Started Jan 25 02:33:00 AM PST 24
Finished Jan 25 02:33:19 AM PST 24
Peak memory 199656 kb
Host smart-01ca2e44-d4cd-4e88-a10b-2a40a877a8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438883114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3438883114
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3666472740
Short name T650
Test name
Test status
Simulation time 110896533912 ps
CPU time 47.41 seconds
Started Jan 25 02:32:46 AM PST 24
Finished Jan 25 02:33:37 AM PST 24
Peak memory 198444 kb
Host smart-368231a7-3f67-48b4-bb52-406a63f7e708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666472740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3666472740
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3874826360
Short name T511
Test name
Test status
Simulation time 11897154785 ps
CPU time 662.48 seconds
Started Jan 25 04:35:39 AM PST 24
Finished Jan 25 04:46:44 AM PST 24
Peak memory 200148 kb
Host smart-2d42d0d9-09ef-4f0b-aeb8-14357e4dd312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874826360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3874826360
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.351214287
Short name T88
Test name
Test status
Simulation time 2280309043 ps
CPU time 5.52 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:32:55 AM PST 24
Peak memory 198284 kb
Host smart-d7f85911-8291-493a-b699-3f16ef332f2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351214287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.351214287
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.318082063
Short name T1212
Test name
Test status
Simulation time 110691432419 ps
CPU time 89.39 seconds
Started Jan 25 02:32:48 AM PST 24
Finished Jan 25 02:34:22 AM PST 24
Peak memory 199872 kb
Host smart-3091bcc1-6077-44d0-88b5-7f18778c315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318082063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.318082063
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3083270200
Short name T1214
Test name
Test status
Simulation time 33369761433 ps
CPU time 55.86 seconds
Started Jan 25 02:32:48 AM PST 24
Finished Jan 25 02:33:49 AM PST 24
Peak memory 195484 kb
Host smart-7eafffef-c436-454e-baa9-765d1c60c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083270200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3083270200
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2459023947
Short name T1109
Test name
Test status
Simulation time 757080483 ps
CPU time 1.6 seconds
Started Jan 25 02:32:48 AM PST 24
Finished Jan 25 02:32:54 AM PST 24
Peak memory 199252 kb
Host smart-10469053-6ca2-43dc-9cc7-aa0de0030224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459023947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2459023947
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2274402871
Short name T755
Test name
Test status
Simulation time 118674610047 ps
CPU time 58.56 seconds
Started Jan 25 02:33:14 AM PST 24
Finished Jan 25 02:34:20 AM PST 24
Peak memory 200128 kb
Host smart-d525f196-2a89-4e31-a8bc-78e550649547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274402871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2274402871
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2834049524
Short name T105
Test name
Test status
Simulation time 71993686028 ps
CPU time 429.43 seconds
Started Jan 25 03:32:02 AM PST 24
Finished Jan 25 03:39:13 AM PST 24
Peak memory 208816 kb
Host smart-9e85e646-475c-4fc3-b9d3-2f08ba51ef55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834049524 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2834049524
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.145165035
Short name T970
Test name
Test status
Simulation time 6709777286 ps
CPU time 9.51 seconds
Started Jan 25 02:33:05 AM PST 24
Finished Jan 25 02:33:18 AM PST 24
Peak memory 199384 kb
Host smart-186afb76-3a5d-40fb-b78c-1dfba605a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145165035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.145165035
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3606571644
Short name T1003
Test name
Test status
Simulation time 68500200693 ps
CPU time 50.43 seconds
Started Jan 25 02:32:47 AM PST 24
Finished Jan 25 02:33:40 AM PST 24
Peak memory 200064 kb
Host smart-62836e21-d110-452b-8e47-4cb3d76dc395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606571644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3606571644
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2418059385
Short name T818
Test name
Test status
Simulation time 152892359 ps
CPU time 0.57 seconds
Started Jan 25 02:33:30 AM PST 24
Finished Jan 25 02:33:32 AM PST 24
Peak memory 195708 kb
Host smart-08e984b2-65c8-44a9-aa6f-74fbc8070bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418059385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2418059385
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3359128641
Short name T402
Test name
Test status
Simulation time 39822936781 ps
CPU time 34.91 seconds
Started Jan 25 02:33:15 AM PST 24
Finished Jan 25 02:33:57 AM PST 24
Peak memory 199844 kb
Host smart-4138d01e-a1c9-4ed4-b5ff-669380351632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359128641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3359128641
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1284449122
Short name T868
Test name
Test status
Simulation time 22699532534 ps
CPU time 14.55 seconds
Started Jan 25 02:33:19 AM PST 24
Finished Jan 25 02:33:39 AM PST 24
Peak memory 199468 kb
Host smart-7eaa5809-cb74-406a-927d-766d8ad2af55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284449122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1284449122
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3150011989
Short name T1213
Test name
Test status
Simulation time 1966118581123 ps
CPU time 3140.82 seconds
Started Jan 25 02:33:19 AM PST 24
Finished Jan 25 03:25:46 AM PST 24
Peak memory 200068 kb
Host smart-fda7e455-2b2c-47ed-89f5-b90bde0ae45a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150011989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3150011989
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.375981791
Short name T1011
Test name
Test status
Simulation time 91617002558 ps
CPU time 212.87 seconds
Started Jan 25 02:33:32 AM PST 24
Finished Jan 25 02:37:07 AM PST 24
Peak memory 200140 kb
Host smart-b2227c3b-a57c-485e-98a9-954781536ee4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375981791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.375981791
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1060327310
Short name T1096
Test name
Test status
Simulation time 1521278083 ps
CPU time 1.33 seconds
Started Jan 25 02:33:29 AM PST 24
Finished Jan 25 02:33:32 AM PST 24
Peak memory 195540 kb
Host smart-69414a9b-e5c9-49bd-a0d9-a30fc4867294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060327310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1060327310
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.678672583
Short name T1127
Test name
Test status
Simulation time 22583550705 ps
CPU time 21.99 seconds
Started Jan 25 02:33:16 AM PST 24
Finished Jan 25 02:33:45 AM PST 24
Peak memory 198132 kb
Host smart-d08423da-379f-4a2a-a96c-0225c9100fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678672583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.678672583
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2686407705
Short name T918
Test name
Test status
Simulation time 15407396144 ps
CPU time 209.92 seconds
Started Jan 25 02:33:32 AM PST 24
Finished Jan 25 02:37:04 AM PST 24
Peak memory 200020 kb
Host smart-489938fc-6554-41a5-b577-36cae090f016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686407705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2686407705
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.4117514358
Short name T930
Test name
Test status
Simulation time 3287251640 ps
CPU time 35.24 seconds
Started Jan 25 02:33:16 AM PST 24
Finished Jan 25 02:33:58 AM PST 24
Peak memory 198904 kb
Host smart-753437da-af99-48cc-92a2-4831789cc7a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117514358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.4117514358
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2687132984
Short name T244
Test name
Test status
Simulation time 107223806419 ps
CPU time 47.78 seconds
Started Jan 25 02:33:15 AM PST 24
Finished Jan 25 02:34:10 AM PST 24
Peak memory 199956 kb
Host smart-67b92010-615e-410d-bbcb-46fb335403bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687132984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2687132984
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4010217369
Short name T543
Test name
Test status
Simulation time 4052777426 ps
CPU time 7.23 seconds
Started Jan 25 02:33:17 AM PST 24
Finished Jan 25 02:33:31 AM PST 24
Peak memory 195904 kb
Host smart-435a20be-df11-4868-868a-12bc46102756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010217369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4010217369
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.527912826
Short name T1071
Test name
Test status
Simulation time 243272125 ps
CPU time 2.52 seconds
Started Jan 25 02:33:17 AM PST 24
Finished Jan 25 02:33:26 AM PST 24
Peak memory 197784 kb
Host smart-a5a5a4cd-4b60-4deb-93fd-2d485d7df03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527912826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.527912826
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1400011864
Short name T715
Test name
Test status
Simulation time 1296356781244 ps
CPU time 1207.61 seconds
Started Jan 25 02:33:32 AM PST 24
Finished Jan 25 02:53:42 AM PST 24
Peak memory 208496 kb
Host smart-3bb7ff99-65ea-4e69-85d8-3986880125e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400011864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1400011864
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3259920098
Short name T764
Test name
Test status
Simulation time 117775079138 ps
CPU time 370.71 seconds
Started Jan 25 02:33:29 AM PST 24
Finished Jan 25 02:39:42 AM PST 24
Peak memory 208448 kb
Host smart-6f3eb7cc-c835-45d1-94d7-88f9772f7af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259920098 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3259920098
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3908983523
Short name T1181
Test name
Test status
Simulation time 7022623963 ps
CPU time 9.07 seconds
Started Jan 25 02:33:30 AM PST 24
Finished Jan 25 02:33:40 AM PST 24
Peak memory 199084 kb
Host smart-bca5b299-f0c8-4d9d-ab8d-a480a48d36d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908983523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3908983523
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1905414954
Short name T1046
Test name
Test status
Simulation time 63868918954 ps
CPU time 122.19 seconds
Started Jan 25 02:33:17 AM PST 24
Finished Jan 25 02:35:26 AM PST 24
Peak memory 200072 kb
Host smart-b8a55c42-9252-4f35-9955-c4da5f26344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905414954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1905414954
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2514775334
Short name T96
Test name
Test status
Simulation time 40546921 ps
CPU time 0.58 seconds
Started Jan 25 02:34:19 AM PST 24
Finished Jan 25 02:34:28 AM PST 24
Peak memory 195676 kb
Host smart-7b614444-3dc6-4636-b67f-a252f0b2dae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514775334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2514775334
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1616611823
Short name T646
Test name
Test status
Simulation time 99099980340 ps
CPU time 85.83 seconds
Started Jan 25 02:33:56 AM PST 24
Finished Jan 25 02:35:32 AM PST 24
Peak memory 200052 kb
Host smart-5d934e49-ee8a-43c3-a793-ead1f47db697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616611823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1616611823
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.103653499
Short name T1063
Test name
Test status
Simulation time 21399646998 ps
CPU time 17.91 seconds
Started Jan 25 02:33:51 AM PST 24
Finished Jan 25 02:34:22 AM PST 24
Peak memory 197212 kb
Host smart-8f8f5e32-2491-4265-b9fa-60b224d527e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103653499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.103653499
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2741919416
Short name T1106
Test name
Test status
Simulation time 91768504301 ps
CPU time 37.97 seconds
Started Jan 25 02:33:56 AM PST 24
Finished Jan 25 02:34:44 AM PST 24
Peak memory 199988 kb
Host smart-96f2c24f-02a7-44c2-acff-271d9bd15d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741919416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2741919416
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2355577260
Short name T411
Test name
Test status
Simulation time 2198933793900 ps
CPU time 2799.2 seconds
Started Jan 25 02:33:51 AM PST 24
Finished Jan 25 03:20:44 AM PST 24
Peak memory 200068 kb
Host smart-7c05b448-3648-4f00-914f-14d13c602596
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355577260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2355577260
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2517216375
Short name T890
Test name
Test status
Simulation time 105837567501 ps
CPU time 152.22 seconds
Started Jan 25 02:34:18 AM PST 24
Finished Jan 25 02:36:53 AM PST 24
Peak memory 200096 kb
Host smart-306cec93-03f4-4430-8584-079d374f43b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517216375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2517216375
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1418991021
Short name T1099
Test name
Test status
Simulation time 2408602025 ps
CPU time 1.69 seconds
Started Jan 25 02:34:22 AM PST 24
Finished Jan 25 02:34:32 AM PST 24
Peak memory 197152 kb
Host smart-359d72fd-dd90-4bb8-9a05-b3869a6f1bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418991021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1418991021
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2556436988
Short name T801
Test name
Test status
Simulation time 131412053765 ps
CPU time 75.69 seconds
Started Jan 25 02:33:52 AM PST 24
Finished Jan 25 02:35:20 AM PST 24
Peak memory 200056 kb
Host smart-c97a38ec-350a-46ea-b0b6-7dc83bafaf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556436988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2556436988
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1231151511
Short name T1064
Test name
Test status
Simulation time 42456429560 ps
CPU time 564.08 seconds
Started Jan 25 02:34:21 AM PST 24
Finished Jan 25 02:43:53 AM PST 24
Peak memory 200148 kb
Host smart-cd3b9b06-2d7c-40f6-959d-6f11d9a312f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231151511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1231151511
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1157761367
Short name T446
Test name
Test status
Simulation time 2280154135 ps
CPU time 6.75 seconds
Started Jan 25 02:33:54 AM PST 24
Finished Jan 25 02:34:13 AM PST 24
Peak memory 198080 kb
Host smart-268eac29-ae2f-4153-be7d-bd6b43d2ece6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157761367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1157761367
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2645315260
Short name T238
Test name
Test status
Simulation time 14624566807 ps
CPU time 25.36 seconds
Started Jan 25 02:33:49 AM PST 24
Finished Jan 25 02:34:27 AM PST 24
Peak memory 198788 kb
Host smart-0abfea47-c4e4-4d41-b788-2721bd8abc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645315260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2645315260
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1617829764
Short name T1195
Test name
Test status
Simulation time 37045302396 ps
CPU time 61.32 seconds
Started Jan 25 02:33:54 AM PST 24
Finished Jan 25 02:35:07 AM PST 24
Peak memory 195716 kb
Host smart-d3b86cf5-ed64-4ad4-a794-bd878322b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617829764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1617829764
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1691756527
Short name T1110
Test name
Test status
Simulation time 449251743 ps
CPU time 1.05 seconds
Started Jan 25 02:33:33 AM PST 24
Finished Jan 25 02:33:36 AM PST 24
Peak memory 198128 kb
Host smart-5769f15a-48ef-4228-91b7-7ae29b13607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691756527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1691756527
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1308705113
Short name T1151
Test name
Test status
Simulation time 84981981397 ps
CPU time 108.64 seconds
Started Jan 25 02:34:21 AM PST 24
Finished Jan 25 02:36:19 AM PST 24
Peak memory 200012 kb
Host smart-124fcf72-678b-4788-8d2a-eae47625e30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308705113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1308705113
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2859830932
Short name T107
Test name
Test status
Simulation time 267416533911 ps
CPU time 1225.95 seconds
Started Jan 25 02:34:20 AM PST 24
Finished Jan 25 02:54:53 AM PST 24
Peak memory 233148 kb
Host smart-9cbf3f04-0ae7-4d49-89b6-660a206ce37b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859830932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2859830932
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.80099120
Short name T682
Test name
Test status
Simulation time 3044339512 ps
CPU time 2.98 seconds
Started Jan 25 02:34:23 AM PST 24
Finished Jan 25 02:34:33 AM PST 24
Peak memory 198084 kb
Host smart-a334a662-c951-4a71-a2df-5a94c5417c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80099120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.80099120
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2047359103
Short name T19
Test name
Test status
Simulation time 35088502244 ps
CPU time 30.52 seconds
Started Jan 25 02:33:32 AM PST 24
Finished Jan 25 02:34:05 AM PST 24
Peak memory 200052 kb
Host smart-e0ac27fd-03c7-4556-9acf-ae3f775df987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047359103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2047359103
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1324802826
Short name T735
Test name
Test status
Simulation time 41097720 ps
CPU time 0.57 seconds
Started Jan 25 02:34:37 AM PST 24
Finished Jan 25 02:34:41 AM PST 24
Peak memory 195716 kb
Host smart-0ca8427c-2699-4711-8287-6db85a568981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324802826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1324802826
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3509804547
Short name T704
Test name
Test status
Simulation time 281280887057 ps
CPU time 52.86 seconds
Started Jan 25 02:34:18 AM PST 24
Finished Jan 25 02:35:14 AM PST 24
Peak memory 200092 kb
Host smart-379f5926-3ca7-4c9c-b116-fbb631d0101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509804547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3509804547
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3137937652
Short name T575
Test name
Test status
Simulation time 165119544831 ps
CPU time 231.4 seconds
Started Jan 25 02:34:20 AM PST 24
Finished Jan 25 02:38:19 AM PST 24
Peak memory 199328 kb
Host smart-6bd9c3ba-21fe-4376-adcc-e3a348f20b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137937652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3137937652
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2737355084
Short name T110
Test name
Test status
Simulation time 44042790158 ps
CPU time 39.28 seconds
Started Jan 25 02:34:21 AM PST 24
Finished Jan 25 02:35:10 AM PST 24
Peak memory 199704 kb
Host smart-f935cfeb-21e4-4f44-b1c3-cad700556fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737355084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2737355084
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4274844784
Short name T615
Test name
Test status
Simulation time 277358078975 ps
CPU time 189.24 seconds
Started Jan 25 02:34:36 AM PST 24
Finished Jan 25 02:37:49 AM PST 24
Peak memory 200096 kb
Host smart-8d17d040-0548-4b01-9baf-17dada7540af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274844784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4274844784
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.273707845
Short name T505
Test name
Test status
Simulation time 2196098822 ps
CPU time 2.74 seconds
Started Jan 25 02:34:39 AM PST 24
Finished Jan 25 02:34:44 AM PST 24
Peak memory 197152 kb
Host smart-4202e0c0-3603-41fe-b694-4223bf267f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273707845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.273707845
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1428573662
Short name T907
Test name
Test status
Simulation time 61711302111 ps
CPU time 183.67 seconds
Started Jan 25 02:34:21 AM PST 24
Finished Jan 25 02:37:34 AM PST 24
Peak memory 199152 kb
Host smart-930da011-2b8b-4133-9221-b73b6fb7c42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428573662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1428573662
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2628337966
Short name T916
Test name
Test status
Simulation time 16962689404 ps
CPU time 506.63 seconds
Started Jan 25 02:34:36 AM PST 24
Finished Jan 25 02:43:06 AM PST 24
Peak memory 200072 kb
Host smart-41911534-4d9b-4612-8f75-7b1653194e06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628337966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2628337966
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.37781172
Short name T545
Test name
Test status
Simulation time 3093440363 ps
CPU time 24.66 seconds
Started Jan 25 02:34:19 AM PST 24
Finished Jan 25 02:34:51 AM PST 24
Peak memory 198576 kb
Host smart-564ded39-dbce-4369-a037-4a0ebad5c025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37781172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.37781172
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3994197135
Short name T627
Test name
Test status
Simulation time 19589538648 ps
CPU time 36.13 seconds
Started Jan 25 02:34:37 AM PST 24
Finished Jan 25 02:35:16 AM PST 24
Peak memory 200048 kb
Host smart-e77ec397-b91a-4457-b0dc-faccfc7a75aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994197135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3994197135
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3282817637
Short name T422
Test name
Test status
Simulation time 5685128766 ps
CPU time 9.26 seconds
Started Jan 25 02:34:19 AM PST 24
Finished Jan 25 02:34:37 AM PST 24
Peak memory 195508 kb
Host smart-d865fcf5-7b1e-478a-8696-fe78a38fc879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282817637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3282817637
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2593162652
Short name T417
Test name
Test status
Simulation time 431171735 ps
CPU time 1.94 seconds
Started Jan 25 02:34:21 AM PST 24
Finished Jan 25 02:34:31 AM PST 24
Peak memory 198088 kb
Host smart-fe563627-2179-4661-a922-4a64eca13c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593162652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2593162652
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.4271363350
Short name T790
Test name
Test status
Simulation time 217865184191 ps
CPU time 619.87 seconds
Started Jan 25 02:34:37 AM PST 24
Finished Jan 25 02:45:00 AM PST 24
Peak memory 200076 kb
Host smart-766e81f0-8521-4e95-8995-d8d10e4f1054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271363350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.4271363350
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.4129813472
Short name T900
Test name
Test status
Simulation time 339025833960 ps
CPU time 591.03 seconds
Started Jan 25 02:34:39 AM PST 24
Finished Jan 25 02:44:34 AM PST 24
Peak memory 224828 kb
Host smart-5605ff34-f81c-4cd8-86d4-732678903688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129813472 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.4129813472
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.945183734
Short name T783
Test name
Test status
Simulation time 743717897 ps
CPU time 2.4 seconds
Started Jan 25 02:34:39 AM PST 24
Finished Jan 25 02:34:44 AM PST 24
Peak memory 198444 kb
Host smart-fcb1706a-7fb7-43e2-9f6d-b9a781b9cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945183734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.945183734
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_alert_test.520342493
Short name T698
Test name
Test status
Simulation time 24135106 ps
CPU time 0.65 seconds
Started Jan 25 02:34:59 AM PST 24
Finished Jan 25 02:35:03 AM PST 24
Peak memory 195708 kb
Host smart-7d839037-fa90-4e1c-91e6-d4bd856480c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520342493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.520342493
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1628139288
Short name T1033
Test name
Test status
Simulation time 15995698983 ps
CPU time 26.87 seconds
Started Jan 25 02:34:37 AM PST 24
Finished Jan 25 02:35:07 AM PST 24
Peak memory 199864 kb
Host smart-cdf7481b-7289-47f8-88f1-a30f274597a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628139288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1628139288
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.4228644701
Short name T1230
Test name
Test status
Simulation time 156717983434 ps
CPU time 201.58 seconds
Started Jan 25 03:07:07 AM PST 24
Finished Jan 25 03:10:30 AM PST 24
Peak memory 199188 kb
Host smart-5936eea5-804a-4636-8a53-7f829634c25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228644701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4228644701
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3140128577
Short name T1171
Test name
Test status
Simulation time 22675305143 ps
CPU time 19.77 seconds
Started Jan 25 02:34:37 AM PST 24
Finished Jan 25 02:35:00 AM PST 24
Peak memory 199812 kb
Host smart-f8ee3fd6-a8ca-4794-826b-82914fa6f331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140128577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3140128577
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1279937849
Short name T699
Test name
Test status
Simulation time 14760304658 ps
CPU time 3.3 seconds
Started Jan 25 02:34:37 AM PST 24
Finished Jan 25 02:34:43 AM PST 24
Peak memory 199268 kb
Host smart-1be60957-b47f-461f-80b8-891ef44a0551
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279937849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1279937849
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.996519984
Short name T998
Test name
Test status
Simulation time 139260417291 ps
CPU time 326.41 seconds
Started Jan 25 02:34:52 AM PST 24
Finished Jan 25 02:40:22 AM PST 24
Peak memory 200028 kb
Host smart-a9ce92ad-09d6-4fa3-9f26-56302368cf63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996519984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.996519984
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3707937575
Short name T643
Test name
Test status
Simulation time 7286904795 ps
CPU time 4.39 seconds
Started Jan 25 02:34:38 AM PST 24
Finished Jan 25 02:34:45 AM PST 24
Peak memory 199868 kb
Host smart-fc971418-4e0a-4886-901a-7d64569585e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707937575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3707937575
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3352516322
Short name T641
Test name
Test status
Simulation time 109910850744 ps
CPU time 52.39 seconds
Started Jan 25 02:34:36 AM PST 24
Finished Jan 25 02:35:32 AM PST 24
Peak memory 200244 kb
Host smart-56bc8e05-c7df-43ec-8bca-d3396c433c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352516322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3352516322
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1886598101
Short name T591
Test name
Test status
Simulation time 33332077847 ps
CPU time 204.94 seconds
Started Jan 25 02:34:34 AM PST 24
Finished Jan 25 02:38:03 AM PST 24
Peak memory 200036 kb
Host smart-6f4b1d96-9f3c-4826-9370-115a238d0694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886598101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1886598101
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2058875866
Short name T1037
Test name
Test status
Simulation time 1463428094 ps
CPU time 3.86 seconds
Started Jan 25 02:34:36 AM PST 24
Finished Jan 25 02:34:43 AM PST 24
Peak memory 198160 kb
Host smart-165a9dcf-680a-4347-a5a9-17752b9821a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2058875866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2058875866
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1591616607
Short name T241
Test name
Test status
Simulation time 7052696594 ps
CPU time 12.27 seconds
Started Jan 25 02:34:34 AM PST 24
Finished Jan 25 02:34:50 AM PST 24
Peak memory 197660 kb
Host smart-7fc90cd4-b1ec-4d77-b3ca-b5d512aff9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591616607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1591616607
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1162321114
Short name T605
Test name
Test status
Simulation time 4075153365 ps
CPU time 2.33 seconds
Started Jan 25 02:34:36 AM PST 24
Finished Jan 25 02:34:42 AM PST 24
Peak memory 195708 kb
Host smart-2e1a7c8c-18bd-470f-87e4-ede79342a9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162321114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1162321114
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3098224115
Short name T556
Test name
Test status
Simulation time 581454849 ps
CPU time 1.27 seconds
Started Jan 25 05:09:33 AM PST 24
Finished Jan 25 05:09:35 AM PST 24
Peak memory 198148 kb
Host smart-49d7d4e5-2635-4478-be70-24ee0eb903d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098224115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3098224115
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.580296179
Short name T296
Test name
Test status
Simulation time 107727330264 ps
CPU time 446.64 seconds
Started Jan 25 02:34:56 AM PST 24
Finished Jan 25 02:42:25 AM PST 24
Peak memory 200124 kb
Host smart-f771ee2a-3709-48f4-bf99-9bb745cd149f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580296179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.580296179
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.518946931
Short name T1039
Test name
Test status
Simulation time 207688702405 ps
CPU time 493.25 seconds
Started Jan 25 02:34:59 AM PST 24
Finished Jan 25 02:43:17 AM PST 24
Peak memory 215824 kb
Host smart-e5c4a139-77ec-4091-aeb7-ee19172617e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518946931 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.518946931
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1551062182
Short name T603
Test name
Test status
Simulation time 6615235378 ps
CPU time 21.72 seconds
Started Jan 25 02:34:39 AM PST 24
Finished Jan 25 02:35:04 AM PST 24
Peak memory 198880 kb
Host smart-65477b01-2dc9-4a5c-9f7c-75967458a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551062182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1551062182
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1447438275
Short name T843
Test name
Test status
Simulation time 16075166140 ps
CPU time 27.46 seconds
Started Jan 25 02:34:35 AM PST 24
Finished Jan 25 02:35:06 AM PST 24
Peak memory 198164 kb
Host smart-1ab50d15-cf03-4b72-877b-1565b11ed555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447438275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1447438275
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3705443474
Short name T751
Test name
Test status
Simulation time 20401909 ps
CPU time 0.57 seconds
Started Jan 25 02:35:13 AM PST 24
Finished Jan 25 02:35:17 AM PST 24
Peak memory 195724 kb
Host smart-6d6806d3-cac2-43a6-9632-6206494b2ced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705443474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3705443474
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2542836351
Short name T731
Test name
Test status
Simulation time 193012640382 ps
CPU time 164.18 seconds
Started Jan 25 02:34:58 AM PST 24
Finished Jan 25 02:37:46 AM PST 24
Peak memory 199880 kb
Host smart-f712bf49-51f7-4f63-a21c-cda608485c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542836351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2542836351
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1988706656
Short name T878
Test name
Test status
Simulation time 168052652291 ps
CPU time 153.62 seconds
Started Jan 25 02:34:57 AM PST 24
Finished Jan 25 02:37:34 AM PST 24
Peak memory 199148 kb
Host smart-a20b29f6-81c1-42a4-8d4b-0aaab5c264d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988706656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1988706656
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.4044948077
Short name T330
Test name
Test status
Simulation time 55824396476 ps
CPU time 25.55 seconds
Started Jan 25 02:34:51 AM PST 24
Finished Jan 25 02:35:21 AM PST 24
Peak memory 200092 kb
Host smart-4df60846-fda3-443a-bc68-387c93827a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044948077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4044948077
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.818049348
Short name T25
Test name
Test status
Simulation time 307846379732 ps
CPU time 434.88 seconds
Started Jan 25 02:35:14 AM PST 24
Finished Jan 25 02:42:32 AM PST 24
Peak memory 199360 kb
Host smart-c9dabdf9-d2b5-4666-9ff2-1a0b6eda70d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818049348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.818049348
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3310439583
Short name T514
Test name
Test status
Simulation time 73138485983 ps
CPU time 260.92 seconds
Started Jan 25 02:35:16 AM PST 24
Finished Jan 25 02:39:38 AM PST 24
Peak memory 200036 kb
Host smart-b3a784b1-529c-47f2-adbd-a8f3c2409e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3310439583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3310439583
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3026390448
Short name T485
Test name
Test status
Simulation time 6937256918 ps
CPU time 14.46 seconds
Started Jan 25 02:35:15 AM PST 24
Finished Jan 25 02:35:32 AM PST 24
Peak memory 198004 kb
Host smart-cd1f43e8-fc47-4eff-8a5d-c251de9a9900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026390448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3026390448
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3114747330
Short name T418
Test name
Test status
Simulation time 53753566571 ps
CPU time 23.72 seconds
Started Jan 25 02:35:16 AM PST 24
Finished Jan 25 02:35:41 AM PST 24
Peak memory 200188 kb
Host smart-386c62b3-512f-423f-9f04-d0974756b3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114747330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3114747330
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1237954353
Short name T265
Test name
Test status
Simulation time 30126424216 ps
CPU time 403.16 seconds
Started Jan 25 02:35:13 AM PST 24
Finished Jan 25 02:41:59 AM PST 24
Peak memory 200080 kb
Host smart-06b7bf66-b99a-4ed3-9357-b59cf2242412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237954353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1237954353
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4241493127
Short name T1087
Test name
Test status
Simulation time 3070198656 ps
CPU time 3.04 seconds
Started Jan 25 02:35:19 AM PST 24
Finished Jan 25 02:35:24 AM PST 24
Peak memory 198420 kb
Host smart-f46ca6ce-d184-48a0-9a4b-fbebb9473ba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4241493127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4241493127
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3806465291
Short name T240
Test name
Test status
Simulation time 163939454144 ps
CPU time 21.76 seconds
Started Jan 25 02:35:14 AM PST 24
Finished Jan 25 02:35:38 AM PST 24
Peak memory 200032 kb
Host smart-759eaaf1-8e4d-41db-b5d7-46cc0b7b81e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806465291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3806465291
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.260158059
Short name T852
Test name
Test status
Simulation time 2985116439 ps
CPU time 5.48 seconds
Started Jan 25 02:35:12 AM PST 24
Finished Jan 25 02:35:19 AM PST 24
Peak memory 195900 kb
Host smart-76d37b73-5379-439c-8e0c-cd8cbfaad8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260158059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.260158059
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1716630843
Short name T1182
Test name
Test status
Simulation time 697378115 ps
CPU time 1.9 seconds
Started Jan 25 02:34:56 AM PST 24
Finished Jan 25 02:35:00 AM PST 24
Peak memory 198444 kb
Host smart-fad5090c-e28b-4cea-b8e8-ce74a0ae95b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716630843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1716630843
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.416204200
Short name T903
Test name
Test status
Simulation time 88291683303 ps
CPU time 1600.93 seconds
Started Jan 25 02:35:16 AM PST 24
Finished Jan 25 03:01:59 AM PST 24
Peak memory 225024 kb
Host smart-41abb02f-c846-448b-b84c-2156378edf7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416204200 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.416204200
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.4207039777
Short name T626
Test name
Test status
Simulation time 382260881 ps
CPU time 1.54 seconds
Started Jan 25 02:35:19 AM PST 24
Finished Jan 25 02:35:23 AM PST 24
Peak memory 198256 kb
Host smart-039e4f66-7efe-496b-b6b2-8d5ae35da162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207039777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.4207039777
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.193151986
Short name T787
Test name
Test status
Simulation time 9653309927 ps
CPU time 15.19 seconds
Started Jan 25 02:34:53 AM PST 24
Finished Jan 25 02:35:11 AM PST 24
Peak memory 198740 kb
Host smart-2d0ad6de-fa63-49fb-ad4e-7919bb928b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193151986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.193151986
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3464163378
Short name T1093
Test name
Test status
Simulation time 42821580 ps
CPU time 0.6 seconds
Started Jan 25 02:35:36 AM PST 24
Finished Jan 25 02:35:45 AM PST 24
Peak memory 195736 kb
Host smart-fa641d3b-6ad9-41ef-a7c8-a6600ad896a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464163378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3464163378
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3658640878
Short name T311
Test name
Test status
Simulation time 286902371142 ps
CPU time 446 seconds
Started Jan 25 02:35:14 AM PST 24
Finished Jan 25 02:42:43 AM PST 24
Peak memory 199784 kb
Host smart-f6a48582-46d9-4902-9f0b-dce4de213e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658640878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3658640878
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.12079952
Short name T358
Test name
Test status
Simulation time 5004583797 ps
CPU time 8.83 seconds
Started Jan 25 02:49:14 AM PST 24
Finished Jan 25 02:49:24 AM PST 24
Peak memory 197120 kb
Host smart-7b3ffb65-98d5-4c93-b5cd-8ef69aeedb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12079952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.12079952
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2933026267
Short name T608
Test name
Test status
Simulation time 15833940240 ps
CPU time 28.49 seconds
Started Jan 25 02:35:40 AM PST 24
Finished Jan 25 02:36:13 AM PST 24
Peak memory 199996 kb
Host smart-43e04668-9a07-480d-a20d-2554e57e60bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933026267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2933026267
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2385588433
Short name T533
Test name
Test status
Simulation time 18813611101 ps
CPU time 28.05 seconds
Started Jan 25 02:35:36 AM PST 24
Finished Jan 25 02:36:12 AM PST 24
Peak memory 196448 kb
Host smart-64cbe302-a380-46f4-84ff-b124c1ab28e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385588433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2385588433
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1900178025
Short name T301
Test name
Test status
Simulation time 53066803212 ps
CPU time 320.51 seconds
Started Jan 25 02:35:37 AM PST 24
Finished Jan 25 02:41:05 AM PST 24
Peak memory 200124 kb
Host smart-28eb09b8-bb65-4021-8278-1517d9a9d7ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900178025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1900178025
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3038488615
Short name T528
Test name
Test status
Simulation time 6545161423 ps
CPU time 3.98 seconds
Started Jan 25 03:49:08 AM PST 24
Finished Jan 25 03:49:18 AM PST 24
Peak memory 198196 kb
Host smart-46c64c13-9001-4ed7-8b5a-bb193b15976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038488615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3038488615
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.2015422700
Short name T693
Test name
Test status
Simulation time 360595375363 ps
CPU time 66.88 seconds
Started Jan 25 02:35:36 AM PST 24
Finished Jan 25 02:36:51 AM PST 24
Peak memory 208524 kb
Host smart-51f40ba5-774b-466c-a0b1-5f7244459966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015422700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2015422700
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2006546772
Short name T1090
Test name
Test status
Simulation time 15445438497 ps
CPU time 176.39 seconds
Started Jan 25 02:35:39 AM PST 24
Finished Jan 25 02:38:41 AM PST 24
Peak memory 200096 kb
Host smart-b16441fa-f216-4206-a989-2d1cf4d20ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006546772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2006546772
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2696207829
Short name T996
Test name
Test status
Simulation time 14020171758 ps
CPU time 26.5 seconds
Started Jan 25 02:35:36 AM PST 24
Finished Jan 25 02:36:11 AM PST 24
Peak memory 200104 kb
Host smart-3bd63563-062c-44a4-bf1d-3b8065cab0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696207829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2696207829
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1236997424
Short name T836
Test name
Test status
Simulation time 3249489383 ps
CPU time 1.97 seconds
Started Jan 25 02:35:36 AM PST 24
Finished Jan 25 02:35:46 AM PST 24
Peak memory 195876 kb
Host smart-64104941-30d2-4bfe-958d-1f368ea53a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236997424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1236997424
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.44140728
Short name T660
Test name
Test status
Simulation time 5731076297 ps
CPU time 13.66 seconds
Started Jan 25 02:35:13 AM PST 24
Finished Jan 25 02:35:30 AM PST 24
Peak memory 199512 kb
Host smart-2def84cc-5875-4d1c-ad1d-2606618453c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44140728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.44140728
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2529139190
Short name T175
Test name
Test status
Simulation time 321389640579 ps
CPU time 1755.07 seconds
Started Jan 25 02:35:39 AM PST 24
Finished Jan 25 03:05:00 AM PST 24
Peak memory 208540 kb
Host smart-510edcf8-9d60-4344-a403-6f10ac4ebabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529139190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2529139190
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2203162252
Short name T1216
Test name
Test status
Simulation time 465779832 ps
CPU time 1.55 seconds
Started Jan 25 02:35:34 AM PST 24
Finished Jan 25 02:35:42 AM PST 24
Peak memory 197416 kb
Host smart-9a150679-8d27-404a-9644-aa3e1ab8716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203162252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2203162252
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1666609026
Short name T210
Test name
Test status
Simulation time 53717692130 ps
CPU time 17.42 seconds
Started Jan 25 02:35:13 AM PST 24
Finished Jan 25 02:35:34 AM PST 24
Peak memory 200068 kb
Host smart-0675a54b-ca59-49d5-9b30-807a0bcf6a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666609026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1666609026
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3690568254
Short name T860
Test name
Test status
Simulation time 49367438 ps
CPU time 0.56 seconds
Started Jan 25 02:36:28 AM PST 24
Finished Jan 25 02:36:30 AM PST 24
Peak memory 195668 kb
Host smart-0117ba35-b6c2-49e0-9dd9-91a37e53e070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690568254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3690568254
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2779383109
Short name T104
Test name
Test status
Simulation time 194111704004 ps
CPU time 36.84 seconds
Started Jan 25 02:55:11 AM PST 24
Finished Jan 25 02:55:49 AM PST 24
Peak memory 200024 kb
Host smart-265eb103-b887-4122-b464-8950962d7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779383109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2779383109
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2233819896
Short name T1196
Test name
Test status
Simulation time 37538533077 ps
CPU time 16.63 seconds
Started Jan 25 02:36:31 AM PST 24
Finished Jan 25 02:36:49 AM PST 24
Peak memory 199064 kb
Host smart-d5aa5b03-1f08-426c-bb18-0615281850e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233819896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2233819896
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3509840870
Short name T256
Test name
Test status
Simulation time 117916199634 ps
CPU time 51.88 seconds
Started Jan 25 03:17:52 AM PST 24
Finished Jan 25 03:18:45 AM PST 24
Peak memory 200040 kb
Host smart-d0666323-8501-4a48-9b45-a6005367ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509840870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3509840870
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.296248747
Short name T657
Test name
Test status
Simulation time 36824040845 ps
CPU time 13.39 seconds
Started Jan 25 02:45:45 AM PST 24
Finished Jan 25 02:46:00 AM PST 24
Peak memory 197228 kb
Host smart-2e27e4a0-120d-4a1b-a242-dd3fff5dba64
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296248747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.296248747
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4003949083
Short name T1153
Test name
Test status
Simulation time 210984285794 ps
CPU time 203.47 seconds
Started Jan 25 03:01:02 AM PST 24
Finished Jan 25 03:04:38 AM PST 24
Peak memory 200048 kb
Host smart-1326ecc6-4604-4e98-9b88-08467cdc90ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003949083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4003949083
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1614364371
Short name T546
Test name
Test status
Simulation time 4674056269 ps
CPU time 6.06 seconds
Started Jan 25 02:36:32 AM PST 24
Finished Jan 25 02:36:39 AM PST 24
Peak memory 198576 kb
Host smart-30650bbb-da48-4ad9-bd16-966537a7c5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614364371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1614364371
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3776947500
Short name T622
Test name
Test status
Simulation time 158514830301 ps
CPU time 68.06 seconds
Started Jan 25 02:36:28 AM PST 24
Finished Jan 25 02:37:37 AM PST 24
Peak memory 200244 kb
Host smart-a5f14146-56d9-4c9d-a93d-2f3fcb27ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776947500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3776947500
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2736415650
Short name T829
Test name
Test status
Simulation time 20726897767 ps
CPU time 59.58 seconds
Started Jan 25 02:36:36 AM PST 24
Finished Jan 25 02:37:36 AM PST 24
Peak memory 200104 kb
Host smart-a28e68d0-cc3c-4603-a642-4823aacd3f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736415650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2736415650
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1940458030
Short name T548
Test name
Test status
Simulation time 1571470089 ps
CPU time 2.13 seconds
Started Jan 25 02:36:31 AM PST 24
Finished Jan 25 02:36:35 AM PST 24
Peak memory 198068 kb
Host smart-a46985e1-3465-4f59-828a-019525ac3f1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1940458030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1940458030
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.304372373
Short name T1075
Test name
Test status
Simulation time 1777982396 ps
CPU time 3.55 seconds
Started Jan 25 02:36:28 AM PST 24
Finished Jan 25 02:36:32 AM PST 24
Peak memory 195556 kb
Host smart-0e2355e2-2832-47d7-b808-e8879e3dee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304372373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.304372373
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1504862329
Short name T568
Test name
Test status
Simulation time 129008546 ps
CPU time 0.96 seconds
Started Jan 25 02:35:39 AM PST 24
Finished Jan 25 02:35:45 AM PST 24
Peak memory 196692 kb
Host smart-070a6552-2c02-4195-8294-7ebf63508eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504862329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1504862329
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3314043927
Short name T685
Test name
Test status
Simulation time 90789542708 ps
CPU time 138.58 seconds
Started Jan 25 02:36:32 AM PST 24
Finished Jan 25 02:38:51 AM PST 24
Peak memory 200356 kb
Host smart-7d866451-c9d1-4ccf-9c62-4e5893bf943b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314043927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3314043927
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1054904792
Short name T922
Test name
Test status
Simulation time 39948602789 ps
CPU time 264.78 seconds
Started Jan 25 02:36:32 AM PST 24
Finished Jan 25 02:40:58 AM PST 24
Peak memory 210660 kb
Host smart-bd1493cb-5bfc-447e-8f8d-8381ae0bd863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054904792 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1054904792
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2927590600
Short name T1049
Test name
Test status
Simulation time 5213833111 ps
CPU time 2.51 seconds
Started Jan 25 02:36:33 AM PST 24
Finished Jan 25 02:36:36 AM PST 24
Peak memory 198168 kb
Host smart-554279c6-13e5-49c6-8923-20eeb6773824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927590600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2927590600
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2878274792
Short name T875
Test name
Test status
Simulation time 137571882637 ps
CPU time 223.71 seconds
Started Jan 25 03:19:00 AM PST 24
Finished Jan 25 03:22:45 AM PST 24
Peak memory 200136 kb
Host smart-370626a7-6877-4e15-8b7f-d90716e40431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878274792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2878274792
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1015383072
Short name T1036
Test name
Test status
Simulation time 10945473 ps
CPU time 0.59 seconds
Started Jan 25 02:05:05 AM PST 24
Finished Jan 25 02:05:13 AM PST 24
Peak memory 194756 kb
Host smart-2df8d514-c503-4a90-b857-847ab01f5bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015383072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1015383072
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.709974937
Short name T1209
Test name
Test status
Simulation time 56030932785 ps
CPU time 31.36 seconds
Started Jan 25 02:04:43 AM PST 24
Finished Jan 25 02:05:25 AM PST 24
Peak memory 200064 kb
Host smart-4d71487f-a769-4b20-b59f-69368f580237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709974937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.709974937
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1266109031
Short name T1226
Test name
Test status
Simulation time 99121466828 ps
CPU time 32.52 seconds
Started Jan 25 02:04:44 AM PST 24
Finished Jan 25 02:05:30 AM PST 24
Peak memory 200040 kb
Host smart-fe22c58d-b555-45db-9171-e97bf72e41d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266109031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1266109031
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2511963920
Short name T114
Test name
Test status
Simulation time 17941616566 ps
CPU time 28.16 seconds
Started Jan 25 04:27:39 AM PST 24
Finished Jan 25 04:28:10 AM PST 24
Peak memory 200120 kb
Host smart-1bd87386-a121-4974-baeb-34608d3dc775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511963920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2511963920
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3231340961
Short name T405
Test name
Test status
Simulation time 663552210268 ps
CPU time 1122.53 seconds
Started Jan 25 02:04:38 AM PST 24
Finished Jan 25 02:23:23 AM PST 24
Peak memory 199888 kb
Host smart-51e396e7-cf02-47d6-9422-aa92080655ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231340961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3231340961
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2139373680
Short name T826
Test name
Test status
Simulation time 313707874823 ps
CPU time 271.76 seconds
Started Jan 25 02:05:05 AM PST 24
Finished Jan 25 02:09:44 AM PST 24
Peak memory 200076 kb
Host smart-35209346-4a4c-4256-b128-2d8e43b931c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139373680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2139373680
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.418703515
Short name T519
Test name
Test status
Simulation time 6732859196 ps
CPU time 3.5 seconds
Started Jan 25 02:05:05 AM PST 24
Finished Jan 25 02:05:16 AM PST 24
Peak memory 196908 kb
Host smart-f438c64a-66aa-4e6d-a431-0c466d8dacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418703515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.418703515
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.490612600
Short name T581
Test name
Test status
Simulation time 63240154222 ps
CPU time 63.19 seconds
Started Jan 25 02:04:43 AM PST 24
Finished Jan 25 02:05:56 AM PST 24
Peak memory 200268 kb
Host smart-26e935fa-63c8-4375-a7ff-104b9d7f29f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490612600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.490612600
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3004924707
Short name T527
Test name
Test status
Simulation time 8525771412 ps
CPU time 258.33 seconds
Started Jan 25 02:05:07 AM PST 24
Finished Jan 25 02:09:33 AM PST 24
Peak memory 200068 kb
Host smart-3e936eee-7725-4c80-ab01-cc5d5ed72ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004924707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3004924707
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1450469185
Short name T696
Test name
Test status
Simulation time 4975622579 ps
CPU time 21.63 seconds
Started Jan 25 02:04:43 AM PST 24
Finished Jan 25 02:05:15 AM PST 24
Peak memory 198504 kb
Host smart-ef58fdef-4f4d-4f1c-b114-baa1e42bf1d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450469185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1450469185
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1705733584
Short name T684
Test name
Test status
Simulation time 77652426791 ps
CPU time 118.64 seconds
Started Jan 25 02:04:53 AM PST 24
Finished Jan 25 02:07:02 AM PST 24
Peak memory 200064 kb
Host smart-db13223f-8021-434e-84ad-376b48cd5992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705733584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1705733584
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3546843200
Short name T547
Test name
Test status
Simulation time 1660489120 ps
CPU time 1.77 seconds
Started Jan 25 02:04:44 AM PST 24
Finished Jan 25 02:05:00 AM PST 24
Peak memory 195556 kb
Host smart-051914d6-f6c0-4cd9-9398-1bdf3e0bbfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546843200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3546843200
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3125310872
Short name T440
Test name
Test status
Simulation time 6024283826 ps
CPU time 7.79 seconds
Started Jan 25 02:04:42 AM PST 24
Finished Jan 25 02:04:59 AM PST 24
Peak memory 198780 kb
Host smart-55e4e8d5-aec6-453f-b1c4-05b293db4d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125310872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3125310872
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.775882213
Short name T383
Test name
Test status
Simulation time 225089661657 ps
CPU time 78.98 seconds
Started Jan 25 07:06:43 AM PST 24
Finished Jan 25 07:08:03 AM PST 24
Peak memory 200432 kb
Host smart-6ba887fb-46ef-42f8-880b-27375caedc1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775882213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.775882213
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2238678795
Short name T796
Test name
Test status
Simulation time 118299586258 ps
CPU time 1433.44 seconds
Started Jan 25 02:05:08 AM PST 24
Finished Jan 25 02:29:10 AM PST 24
Peak memory 216644 kb
Host smart-b8cb694a-71a3-44a4-8279-a5e97d9fd5c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238678795 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2238678795
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3874647902
Short name T1183
Test name
Test status
Simulation time 822410647 ps
CPU time 3.18 seconds
Started Jan 25 02:04:41 AM PST 24
Finished Jan 25 02:04:47 AM PST 24
Peak memory 198280 kb
Host smart-c870cb83-df65-4af5-a157-82f1c2cd77b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874647902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3874647902
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.35071800
Short name T1053
Test name
Test status
Simulation time 140855901729 ps
CPU time 87.04 seconds
Started Jan 25 02:04:44 AM PST 24
Finished Jan 25 02:06:26 AM PST 24
Peak memory 199940 kb
Host smart-8a0d6fc0-f0ea-4d7b-b303-2f4c7735f185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35071800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.35071800
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1881243941
Short name T314
Test name
Test status
Simulation time 11537322280 ps
CPU time 22.82 seconds
Started Jan 25 02:36:36 AM PST 24
Finished Jan 25 02:37:00 AM PST 24
Peak memory 200104 kb
Host smart-abc3cec6-6175-4be5-9d75-ac4b6ddcef43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881243941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1881243941
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3971896867
Short name T1017
Test name
Test status
Simulation time 165599584839 ps
CPU time 421.88 seconds
Started Jan 25 02:36:34 AM PST 24
Finished Jan 25 02:43:37 AM PST 24
Peak memory 216824 kb
Host smart-0c6ddf5d-e172-441a-ae0a-083e20d3a740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971896867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3971896867
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1253878765
Short name T252
Test name
Test status
Simulation time 39150429034 ps
CPU time 17.95 seconds
Started Jan 25 02:36:33 AM PST 24
Finished Jan 25 02:36:52 AM PST 24
Peak memory 199856 kb
Host smart-0288eb51-95c7-4f64-abb4-08d0fe7e1fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253878765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1253878765
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.213561368
Short name T1059
Test name
Test status
Simulation time 86274468782 ps
CPU time 1494.49 seconds
Started Jan 25 02:36:55 AM PST 24
Finished Jan 25 03:01:51 AM PST 24
Peak memory 216136 kb
Host smart-373df6ee-da21-4ce1-a639-dbe0cfaceac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213561368 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.213561368
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.334384347
Short name T315
Test name
Test status
Simulation time 60413133752 ps
CPU time 28.05 seconds
Started Jan 25 02:36:50 AM PST 24
Finished Jan 25 02:37:21 AM PST 24
Peak memory 199908 kb
Host smart-cbab728c-31d6-4cbb-a6b1-fb8e7df3998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334384347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.334384347
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.569864731
Short name T1143
Test name
Test status
Simulation time 157689422342 ps
CPU time 429.55 seconds
Started Jan 25 02:36:48 AM PST 24
Finished Jan 25 02:44:00 AM PST 24
Peak memory 208628 kb
Host smart-88be9a5f-160d-4f0a-8fe6-184f2d82f7b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569864731 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.569864731
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2505585334
Short name T122
Test name
Test status
Simulation time 18926813985 ps
CPU time 22.47 seconds
Started Jan 25 02:36:55 AM PST 24
Finished Jan 25 02:37:19 AM PST 24
Peak memory 199552 kb
Host smart-662acac5-b24b-4960-a56e-ac7765889086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505585334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2505585334
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2782093792
Short name T420
Test name
Test status
Simulation time 24822959837 ps
CPU time 296.4 seconds
Started Jan 25 04:48:48 AM PST 24
Finished Jan 25 04:53:53 AM PST 24
Peak memory 211744 kb
Host smart-bb1cb411-46b4-4c05-a89a-d83892f1c4d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782093792 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2782093792
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1569234432
Short name T980
Test name
Test status
Simulation time 15390008914 ps
CPU time 23.88 seconds
Started Jan 25 03:48:01 AM PST 24
Finished Jan 25 03:48:25 AM PST 24
Peak memory 200024 kb
Host smart-08b0ad51-d39b-4108-b26b-60b770d2a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569234432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1569234432
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3834865608
Short name T250
Test name
Test status
Simulation time 163795005402 ps
CPU time 35.06 seconds
Started Jan 25 04:13:54 AM PST 24
Finished Jan 25 04:14:37 AM PST 24
Peak memory 199696 kb
Host smart-a983e46f-4228-434d-a666-ab0fe0ae2174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834865608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3834865608
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1015412299
Short name T251
Test name
Test status
Simulation time 118440010559 ps
CPU time 178.96 seconds
Started Jan 25 02:36:53 AM PST 24
Finished Jan 25 02:39:53 AM PST 24
Peak memory 199288 kb
Host smart-eb4e862e-f9f0-4adc-8503-18806be1e1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015412299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1015412299
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3865533391
Short name T876
Test name
Test status
Simulation time 1047191581347 ps
CPU time 970.68 seconds
Started Jan 25 06:41:10 AM PST 24
Finished Jan 25 06:57:22 AM PST 24
Peak memory 225076 kb
Host smart-5a0a8ab4-50ad-4dd1-ace3-1ca0be6b5e60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865533391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3865533391
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.4108543065
Short name T884
Test name
Test status
Simulation time 20848446393 ps
CPU time 369.1 seconds
Started Jan 25 03:48:40 AM PST 24
Finished Jan 25 03:54:50 AM PST 24
Peak memory 210656 kb
Host smart-1a8b8698-54df-4542-bf79-57439a3f5494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108543065 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.4108543065
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2508217325
Short name T937
Test name
Test status
Simulation time 37456125259 ps
CPU time 36.72 seconds
Started Jan 25 02:36:50 AM PST 24
Finished Jan 25 02:37:28 AM PST 24
Peak memory 200112 kb
Host smart-0f28a95d-46ee-4536-8035-a998be39f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508217325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2508217325
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1642711314
Short name T444
Test name
Test status
Simulation time 26248377422 ps
CPU time 728.47 seconds
Started Jan 25 02:36:46 AM PST 24
Finished Jan 25 02:48:56 AM PST 24
Peak memory 215744 kb
Host smart-c8599209-054f-46dd-8ecb-4e990c2a0ae4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642711314 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1642711314
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1465069481
Short name T234
Test name
Test status
Simulation time 16993939232 ps
CPU time 17.49 seconds
Started Jan 25 02:36:48 AM PST 24
Finished Jan 25 02:37:07 AM PST 24
Peak memory 199952 kb
Host smart-930e764d-c0a7-45c8-b177-c52206cef0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465069481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1465069481
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.4258076682
Short name T1104
Test name
Test status
Simulation time 53772455684 ps
CPU time 367.55 seconds
Started Jan 25 02:37:01 AM PST 24
Finished Jan 25 02:43:10 AM PST 24
Peak memory 215300 kb
Host smart-4f4a1aed-668e-4f34-8a2e-6dd630fa478e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258076682 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.4258076682
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.478898978
Short name T654
Test name
Test status
Simulation time 13851522 ps
CPU time 0.6 seconds
Started Jan 25 05:11:25 AM PST 24
Finished Jan 25 05:11:29 AM PST 24
Peak memory 194776 kb
Host smart-4298d974-480c-4c14-b084-51c1230b8742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478898978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.478898978
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2049631892
Short name T781
Test name
Test status
Simulation time 29599966353 ps
CPU time 47.29 seconds
Started Jan 25 02:05:06 AM PST 24
Finished Jan 25 02:06:01 AM PST 24
Peak memory 199928 kb
Host smart-fa6e5643-dceb-4fb4-b3c2-e6fadd1e3d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049631892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2049631892
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2817753751
Short name T381
Test name
Test status
Simulation time 62952275817 ps
CPU time 14.35 seconds
Started Jan 25 02:05:05 AM PST 24
Finished Jan 25 02:05:27 AM PST 24
Peak memory 199780 kb
Host smart-b96aa44c-0b14-4a70-8e58-42d46649a7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817753751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2817753751
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.3502692160
Short name T664
Test name
Test status
Simulation time 9093402132 ps
CPU time 17.94 seconds
Started Jan 25 02:05:38 AM PST 24
Finished Jan 25 02:06:11 AM PST 24
Peak memory 199084 kb
Host smart-730c1c6c-bfc7-4b91-8b4c-dc0dbb585f14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502692160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3502692160
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4182954964
Short name T408
Test name
Test status
Simulation time 59117585982 ps
CPU time 136.56 seconds
Started Jan 25 04:10:24 AM PST 24
Finished Jan 25 04:12:46 AM PST 24
Peak memory 200092 kb
Host smart-77a72b18-f928-4a79-908c-b7814eb17c4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182954964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4182954964
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3323360796
Short name T828
Test name
Test status
Simulation time 58606384077 ps
CPU time 115.46 seconds
Started Jan 25 02:05:32 AM PST 24
Finished Jan 25 02:07:30 AM PST 24
Peak memory 208448 kb
Host smart-c16fc219-db57-4fde-9ef2-2b6b13150cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323360796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3323360796
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.902396010
Short name T1055
Test name
Test status
Simulation time 8921998009 ps
CPU time 103.54 seconds
Started Jan 25 02:35:54 AM PST 24
Finished Jan 25 02:37:38 AM PST 24
Peak memory 200120 kb
Host smart-509af2fd-f276-41b3-804e-8a0b0f0f606f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902396010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.902396010
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.865307205
Short name T1124
Test name
Test status
Simulation time 4626729501 ps
CPU time 12.85 seconds
Started Jan 25 02:05:31 AM PST 24
Finished Jan 25 02:05:47 AM PST 24
Peak memory 198736 kb
Host smart-437d755c-e4ac-44c2-94ae-2dc69b3512c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865307205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.865307205
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3761405487
Short name T351
Test name
Test status
Simulation time 80912484259 ps
CPU time 34.93 seconds
Started Jan 25 02:05:30 AM PST 24
Finished Jan 25 02:06:08 AM PST 24
Peak memory 199292 kb
Host smart-26b5a23d-260b-4048-badd-ee0c8ecad35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761405487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3761405487
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1846286938
Short name T1179
Test name
Test status
Simulation time 1617598339 ps
CPU time 1.35 seconds
Started Jan 25 02:30:18 AM PST 24
Finished Jan 25 02:30:23 AM PST 24
Peak memory 195600 kb
Host smart-e8d65f97-b661-4019-97fb-6c1f9cdcf462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846286938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1846286938
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4105552208
Short name T549
Test name
Test status
Simulation time 309747637 ps
CPU time 1.02 seconds
Started Jan 25 02:40:40 AM PST 24
Finished Jan 25 02:40:47 AM PST 24
Peak memory 197912 kb
Host smart-5c6186e4-e3c7-4bb4-a43f-7699e6c5fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105552208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4105552208
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2083005441
Short name T349
Test name
Test status
Simulation time 671158529859 ps
CPU time 305.28 seconds
Started Jan 25 02:06:59 AM PST 24
Finished Jan 25 02:12:08 AM PST 24
Peak memory 200044 kb
Host smart-aadd8f80-b486-4dd9-84a3-f5e4eea8e3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083005441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2083005441
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3328151755
Short name T261
Test name
Test status
Simulation time 105170954806 ps
CPU time 642.44 seconds
Started Jan 25 03:18:30 AM PST 24
Finished Jan 25 03:29:14 AM PST 24
Peak memory 225000 kb
Host smart-88eb4d95-2f87-49b0-b198-de14bc75cdee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328151755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3328151755
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2840369902
Short name T688
Test name
Test status
Simulation time 3919107400 ps
CPU time 2.98 seconds
Started Jan 25 02:33:19 AM PST 24
Finished Jan 25 02:33:27 AM PST 24
Peak memory 198700 kb
Host smart-0120e455-473a-4b0e-ba85-c96ed5e105e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840369902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2840369902
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3645469391
Short name T441
Test name
Test status
Simulation time 105208784397 ps
CPU time 23 seconds
Started Jan 25 02:05:01 AM PST 24
Finished Jan 25 02:05:34 AM PST 24
Peak memory 200016 kb
Host smart-c78c1bd5-65e2-49bd-9c88-b0558799fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645469391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3645469391
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1020775230
Short name T118
Test name
Test status
Simulation time 128195390813 ps
CPU time 55.56 seconds
Started Jan 25 02:37:05 AM PST 24
Finished Jan 25 02:38:02 AM PST 24
Peak memory 200056 kb
Host smart-4fc697a7-6cf0-43fb-8f0f-e1a8f052ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020775230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1020775230
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3699451250
Short name T325
Test name
Test status
Simulation time 162441242095 ps
CPU time 585.62 seconds
Started Jan 25 02:37:05 AM PST 24
Finished Jan 25 02:46:52 AM PST 24
Peak memory 219752 kb
Host smart-41f07859-7431-4626-b2a0-3c7b0dc1e7e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699451250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3699451250
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3629679040
Short name T166
Test name
Test status
Simulation time 53768932059 ps
CPU time 26.61 seconds
Started Jan 25 02:37:05 AM PST 24
Finished Jan 25 02:37:33 AM PST 24
Peak memory 199964 kb
Host smart-5c58489f-f011-4e58-aaec-6e9af937363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629679040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3629679040
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2080394498
Short name T590
Test name
Test status
Simulation time 75394058340 ps
CPU time 257.44 seconds
Started Jan 25 02:38:48 AM PST 24
Finished Jan 25 02:43:20 AM PST 24
Peak memory 208460 kb
Host smart-0b461811-ab7b-40ca-9538-9bd349455a3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080394498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2080394498
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.724751361
Short name T1202
Test name
Test status
Simulation time 43597488686 ps
CPU time 27.02 seconds
Started Jan 25 02:38:38 AM PST 24
Finished Jan 25 02:39:08 AM PST 24
Peak memory 199916 kb
Host smart-64575b83-2d61-45c6-9bc8-2efaa681eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724751361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.724751361
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2629300237
Short name T537
Test name
Test status
Simulation time 18823418953 ps
CPU time 260.12 seconds
Started Jan 25 02:38:38 AM PST 24
Finished Jan 25 02:43:00 AM PST 24
Peak memory 208924 kb
Host smart-986323f0-01ad-47ed-9297-4fa0fd95ce6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629300237 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2629300237
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2767652868
Short name T1026
Test name
Test status
Simulation time 17658037715 ps
CPU time 16.08 seconds
Started Jan 25 02:38:35 AM PST 24
Finished Jan 25 02:38:53 AM PST 24
Peak memory 199092 kb
Host smart-c52f7cc8-f71b-4b28-9e2b-7f3360693c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767652868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2767652868
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.967415917
Short name T888
Test name
Test status
Simulation time 27514960469 ps
CPU time 729.92 seconds
Started Jan 25 02:38:40 AM PST 24
Finished Jan 25 02:50:54 AM PST 24
Peak memory 208460 kb
Host smart-82868a29-1ddd-4317-8f24-f03825033eb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967415917 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.967415917
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.429058608
Short name T237
Test name
Test status
Simulation time 136962404010 ps
CPU time 109.21 seconds
Started Jan 25 02:38:35 AM PST 24
Finished Jan 25 02:40:25 AM PST 24
Peak memory 199928 kb
Host smart-b161a03d-06fe-45f6-b109-ceeb95015209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429058608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.429058608
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3091761936
Short name T719
Test name
Test status
Simulation time 110332010629 ps
CPU time 46.67 seconds
Started Jan 25 02:38:35 AM PST 24
Finished Jan 25 02:39:24 AM PST 24
Peak memory 199912 kb
Host smart-d18cf5f9-596c-4191-b5cf-732b73d9a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091761936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3091761936
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1769940279
Short name T339
Test name
Test status
Simulation time 100964524314 ps
CPU time 650.88 seconds
Started Jan 25 02:38:36 AM PST 24
Finished Jan 25 02:49:28 AM PST 24
Peak memory 216820 kb
Host smart-e92809a3-920f-4ef9-8c3b-79ec3f2f6c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769940279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1769940279
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3543609137
Short name T310
Test name
Test status
Simulation time 140710959180 ps
CPU time 89.38 seconds
Started Jan 25 02:38:48 AM PST 24
Finished Jan 25 02:40:32 AM PST 24
Peak memory 200064 kb
Host smart-13077d75-b718-43e1-b9aa-be9d2e66a414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543609137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3543609137
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3916889226
Short name T1232
Test name
Test status
Simulation time 44405210236 ps
CPU time 390.14 seconds
Started Jan 25 02:38:48 AM PST 24
Finished Jan 25 02:45:32 AM PST 24
Peak memory 214272 kb
Host smart-5e28338c-01eb-45fe-816c-214181d36138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916889226 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3916889226
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.85681321
Short name T367
Test name
Test status
Simulation time 67338688970 ps
CPU time 33.26 seconds
Started Jan 25 02:38:38 AM PST 24
Finished Jan 25 02:39:14 AM PST 24
Peak memory 200000 kb
Host smart-75d9b3e4-edf4-4c8c-a8c6-952651f51562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85681321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.85681321
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3454096804
Short name T951
Test name
Test status
Simulation time 270992537885 ps
CPU time 446.85 seconds
Started Jan 25 02:38:55 AM PST 24
Finished Jan 25 02:46:29 AM PST 24
Peak memory 216796 kb
Host smart-bb9e5ca8-649a-428c-8834-56d8ef4146cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454096804 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3454096804
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1340924662
Short name T723
Test name
Test status
Simulation time 11555688120 ps
CPU time 10.64 seconds
Started Jan 25 02:38:55 AM PST 24
Finished Jan 25 02:39:13 AM PST 24
Peak memory 200024 kb
Host smart-914a656f-d84a-429c-842f-dc65251ac78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340924662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1340924662
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3751271514
Short name T323
Test name
Test status
Simulation time 93452318860 ps
CPU time 1299.35 seconds
Started Jan 25 02:38:53 AM PST 24
Finished Jan 25 03:00:42 AM PST 24
Peak memory 220444 kb
Host smart-586920bd-4b1e-45b8-a600-34855cd6092c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751271514 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3751271514
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3991675522
Short name T856
Test name
Test status
Simulation time 12903959 ps
CPU time 0.64 seconds
Started Jan 25 02:07:32 AM PST 24
Finished Jan 25 02:07:34 AM PST 24
Peak memory 195668 kb
Host smart-4e0cedac-53e4-41b0-ac27-e39f2114dc12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991675522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3991675522
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2844062490
Short name T515
Test name
Test status
Simulation time 31536590068 ps
CPU time 45.4 seconds
Started Jan 25 02:07:03 AM PST 24
Finished Jan 25 02:07:52 AM PST 24
Peak memory 199624 kb
Host smart-e501109a-f800-42ed-aa07-eb391c7ffa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844062490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2844062490
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2653371918
Short name T373
Test name
Test status
Simulation time 145764029838 ps
CPU time 245.78 seconds
Started Jan 25 02:32:24 AM PST 24
Finished Jan 25 02:36:31 AM PST 24
Peak memory 200036 kb
Host smart-07c0ace4-ba42-4440-970a-30a3efd687f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653371918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2653371918
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1114199135
Short name T1061
Test name
Test status
Simulation time 29569481321 ps
CPU time 60.16 seconds
Started Jan 25 02:07:00 AM PST 24
Finished Jan 25 02:08:03 AM PST 24
Peak memory 200016 kb
Host smart-dab63e00-cc5b-43b9-b0b5-e73945402994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114199135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1114199135
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1202183696
Short name T793
Test name
Test status
Simulation time 227571693353 ps
CPU time 326.82 seconds
Started Jan 25 04:29:21 AM PST 24
Finished Jan 25 04:35:01 AM PST 24
Peak memory 199996 kb
Host smart-de572dd5-275f-455c-9df4-08743ad6a96e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202183696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1202183696
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1817614012
Short name T642
Test name
Test status
Simulation time 53260807913 ps
CPU time 179.04 seconds
Started Jan 25 02:07:00 AM PST 24
Finished Jan 25 02:10:03 AM PST 24
Peak memory 199964 kb
Host smart-8fab7190-b01a-48bf-b55b-87d474ec594b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817614012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1817614012
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3825384133
Short name T737
Test name
Test status
Simulation time 11217735124 ps
CPU time 10.85 seconds
Started Jan 25 02:07:00 AM PST 24
Finished Jan 25 02:07:15 AM PST 24
Peak memory 198368 kb
Host smart-539fdaca-a85c-4aed-bea7-858debf00403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825384133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3825384133
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3611734814
Short name T416
Test name
Test status
Simulation time 266849973138 ps
CPU time 279.88 seconds
Started Jan 25 02:07:00 AM PST 24
Finished Jan 25 02:11:43 AM PST 24
Peak memory 200052 kb
Host smart-750400e2-717e-4aea-a79a-e05dc98727a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611734814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3611734814
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.1385874143
Short name T1062
Test name
Test status
Simulation time 16716720173 ps
CPU time 861.82 seconds
Started Jan 25 02:07:02 AM PST 24
Finished Jan 25 02:21:27 AM PST 24
Peak memory 200048 kb
Host smart-b82b42d4-bd43-4882-8a02-0502c53547f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385874143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1385874143
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2271902307
Short name T774
Test name
Test status
Simulation time 3021949240 ps
CPU time 9.74 seconds
Started Jan 25 02:07:01 AM PST 24
Finished Jan 25 02:07:14 AM PST 24
Peak memory 198520 kb
Host smart-b9a3e4f7-d458-44a4-af54-62d965cc2f11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271902307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2271902307
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1996986762
Short name T824
Test name
Test status
Simulation time 25278626989 ps
CPU time 7.29 seconds
Started Jan 25 03:18:30 AM PST 24
Finished Jan 25 03:18:38 AM PST 24
Peak memory 198316 kb
Host smart-6a61dc48-8520-43ae-a216-f0767e041382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996986762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1996986762
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2517090173
Short name T919
Test name
Test status
Simulation time 3359456548 ps
CPU time 2.45 seconds
Started Jan 25 03:47:00 AM PST 24
Finished Jan 25 03:47:09 AM PST 24
Peak memory 195900 kb
Host smart-d3e26494-528a-427c-8d79-f77709f78751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517090173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2517090173
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2446054663
Short name T870
Test name
Test status
Simulation time 11054225790 ps
CPU time 26.89 seconds
Started Jan 25 03:10:42 AM PST 24
Finished Jan 25 03:11:10 AM PST 24
Peak memory 199880 kb
Host smart-0b517a87-c465-4ce0-b761-d7dca9405538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446054663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2446054663
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.733124168
Short name T1069
Test name
Test status
Simulation time 158202586663 ps
CPU time 909.83 seconds
Started Jan 25 02:07:35 AM PST 24
Finished Jan 25 02:22:47 AM PST 24
Peak memory 200068 kb
Host smart-08df5f9e-69e7-4335-9549-eb095cd26979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733124168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.733124168
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.4257436678
Short name T565
Test name
Test status
Simulation time 36150537026 ps
CPU time 403.58 seconds
Started Jan 25 02:57:50 AM PST 24
Finished Jan 25 03:04:36 AM PST 24
Peak memory 214080 kb
Host smart-0672bf49-940b-4edd-aa82-acf149cdacef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257436678 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.4257436678
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3718766370
Short name T609
Test name
Test status
Simulation time 1449779451 ps
CPU time 3.2 seconds
Started Jan 25 02:07:04 AM PST 24
Finished Jan 25 02:07:10 AM PST 24
Peak memory 198900 kb
Host smart-b5ee62e4-b0b4-45b4-9a04-9450592baba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718766370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3718766370
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.240127483
Short name T1206
Test name
Test status
Simulation time 230108877352 ps
CPU time 39.15 seconds
Started Jan 25 02:07:01 AM PST 24
Finished Jan 25 02:07:44 AM PST 24
Peak memory 200076 kb
Host smart-b4bd23e1-afca-4d62-8330-23f8cd1028f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240127483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.240127483
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2515331059
Short name T945
Test name
Test status
Simulation time 32979173671 ps
CPU time 60.8 seconds
Started Jan 25 02:38:55 AM PST 24
Finished Jan 25 02:40:03 AM PST 24
Peak memory 200116 kb
Host smart-c6d56a37-b461-41eb-b33d-5cd551753aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515331059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2515331059
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3161453249
Short name T517
Test name
Test status
Simulation time 87596670830 ps
CPU time 502.74 seconds
Started Jan 25 02:39:05 AM PST 24
Finished Jan 25 02:47:33 AM PST 24
Peak memory 216788 kb
Host smart-b0dce7e2-d397-425b-a81a-0b91e46ec3bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161453249 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3161453249
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3087744472
Short name T99
Test name
Test status
Simulation time 100042948774 ps
CPU time 158.88 seconds
Started Jan 25 02:38:56 AM PST 24
Finished Jan 25 02:41:42 AM PST 24
Peak memory 200076 kb
Host smart-d07bccd7-90c9-4253-898a-30289084fb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087744472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3087744472
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2328873880
Short name T583
Test name
Test status
Simulation time 95189183380 ps
CPU time 896.65 seconds
Started Jan 25 02:38:59 AM PST 24
Finished Jan 25 02:54:02 AM PST 24
Peak memory 224980 kb
Host smart-76581cd8-62f0-4df6-bdf7-a7c500711617
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328873880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2328873880
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3332852743
Short name T1190
Test name
Test status
Simulation time 53336645334 ps
CPU time 21.53 seconds
Started Jan 25 04:48:40 AM PST 24
Finished Jan 25 04:49:05 AM PST 24
Peak memory 200080 kb
Host smart-4d136655-1ae9-43f9-a173-962deb86acf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332852743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3332852743
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2616140325
Short name T345
Test name
Test status
Simulation time 97002739648 ps
CPU time 872.84 seconds
Started Jan 25 02:38:53 AM PST 24
Finished Jan 25 02:53:35 AM PST 24
Peak memory 225020 kb
Host smart-52fb56e2-6448-423c-abd6-ba7e4cebbf56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616140325 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2616140325
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3334057775
Short name T862
Test name
Test status
Simulation time 82242573794 ps
CPU time 36.78 seconds
Started Jan 25 02:38:54 AM PST 24
Finished Jan 25 02:39:39 AM PST 24
Peak memory 200076 kb
Host smart-08dc4c25-8635-476b-8835-369743a309ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334057775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3334057775
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.758285167
Short name T763
Test name
Test status
Simulation time 37284951908 ps
CPU time 586.9 seconds
Started Jan 25 02:38:53 AM PST 24
Finished Jan 25 02:48:49 AM PST 24
Peak memory 209932 kb
Host smart-a3758f00-97a6-4862-9ba8-0d4eb0a45a5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758285167 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.758285167
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.54607919
Short name T185
Test name
Test status
Simulation time 57990618087 ps
CPU time 46.13 seconds
Started Jan 25 03:20:08 AM PST 24
Finished Jan 25 03:20:56 AM PST 24
Peak memory 199164 kb
Host smart-3ced109b-0957-40c7-bd53-0e4f3f64ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54607919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.54607919
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.4047416611
Short name T1227
Test name
Test status
Simulation time 7459389008 ps
CPU time 13.71 seconds
Started Jan 25 02:38:53 AM PST 24
Finished Jan 25 02:39:16 AM PST 24
Peak memory 199040 kb
Host smart-c18c00e9-e1d6-4968-a57a-7520fef00f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047416611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.4047416611
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2953452572
Short name T401
Test name
Test status
Simulation time 63700286542 ps
CPU time 866.02 seconds
Started Jan 25 02:39:12 AM PST 24
Finished Jan 25 02:53:41 AM PST 24
Peak memory 216744 kb
Host smart-2238b70a-9de3-4a2f-a262-698f17471c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953452572 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2953452572
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3223440666
Short name T320
Test name
Test status
Simulation time 79223017914 ps
CPU time 33.08 seconds
Started Jan 25 02:39:12 AM PST 24
Finished Jan 25 02:39:47 AM PST 24
Peak memory 200100 kb
Host smart-8f62445f-4698-4a03-b245-f08da6239b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223440666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3223440666
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2758135170
Short name T800
Test name
Test status
Simulation time 36031644311 ps
CPU time 565.01 seconds
Started Jan 25 04:21:41 AM PST 24
Finished Jan 25 04:31:07 AM PST 24
Peak memory 211200 kb
Host smart-7e383141-fcad-4da8-b0b3-5b66d116b9fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758135170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2758135170
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1966929582
Short name T305
Test name
Test status
Simulation time 128344787595 ps
CPU time 94.01 seconds
Started Jan 25 02:39:11 AM PST 24
Finished Jan 25 02:40:48 AM PST 24
Peak memory 200084 kb
Host smart-e63b3d00-747f-48d3-8028-6a84d1d502c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966929582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1966929582
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1770949871
Short name T522
Test name
Test status
Simulation time 20939065545 ps
CPU time 496.62 seconds
Started Jan 25 04:21:35 AM PST 24
Finished Jan 25 04:29:53 AM PST 24
Peak memory 208416 kb
Host smart-349bd9ff-02ca-40d3-bb6c-c2c873fac474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770949871 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1770949871
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3177285644
Short name T551
Test name
Test status
Simulation time 77180899328 ps
CPU time 31.42 seconds
Started Jan 25 02:39:12 AM PST 24
Finished Jan 25 02:39:46 AM PST 24
Peak memory 199264 kb
Host smart-aef90a13-acd6-4070-a982-60437d78bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177285644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3177285644
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2703099307
Short name T662
Test name
Test status
Simulation time 88280703891 ps
CPU time 371.38 seconds
Started Jan 25 02:39:08 AM PST 24
Finished Jan 25 02:45:23 AM PST 24
Peak memory 212700 kb
Host smart-2516b538-df04-48df-ae12-2e32d87d2a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703099307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2703099307
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2860256961
Short name T1205
Test name
Test status
Simulation time 20070116 ps
CPU time 0.56 seconds
Started Jan 25 02:08:05 AM PST 24
Finished Jan 25 02:08:07 AM PST 24
Peak memory 194644 kb
Host smart-b0c16ac4-7b3e-4182-8a44-14a1cb0451cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860256961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2860256961
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1285933945
Short name T552
Test name
Test status
Simulation time 185513924976 ps
CPU time 69.21 seconds
Started Jan 25 02:50:52 AM PST 24
Finished Jan 25 02:52:05 AM PST 24
Peak memory 200052 kb
Host smart-c5a452ba-d9cd-4f2b-9d10-fd67854d186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285933945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1285933945
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3064918518
Short name T377
Test name
Test status
Simulation time 257691996835 ps
CPU time 121.82 seconds
Started Jan 25 02:07:35 AM PST 24
Finished Jan 25 02:09:38 AM PST 24
Peak memory 200080 kb
Host smart-0eaa09ce-8761-4eb5-8627-6ab99334dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064918518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3064918518
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3369326217
Short name T286
Test name
Test status
Simulation time 173627464347 ps
CPU time 166.34 seconds
Started Jan 25 02:07:32 AM PST 24
Finished Jan 25 02:10:20 AM PST 24
Peak memory 199400 kb
Host smart-bc0c750e-6bba-4276-aa0b-b2e7afc810eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369326217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3369326217
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4213513753
Short name T838
Test name
Test status
Simulation time 273865614824 ps
CPU time 81.82 seconds
Started Jan 25 02:07:32 AM PST 24
Finished Jan 25 02:08:55 AM PST 24
Peak memory 200060 kb
Host smart-a69873de-22e2-4da1-86db-d5f86caa3f96
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213513753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4213513753
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.4205564593
Short name T827
Test name
Test status
Simulation time 53879289795 ps
CPU time 334.13 seconds
Started Jan 25 02:08:02 AM PST 24
Finished Jan 25 02:13:37 AM PST 24
Peak memory 200072 kb
Host smart-6a85d144-2be1-46e2-a29d-868250436392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205564593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4205564593
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2924977795
Short name T1175
Test name
Test status
Simulation time 151675717 ps
CPU time 0.82 seconds
Started Jan 25 02:07:32 AM PST 24
Finished Jan 25 02:07:33 AM PST 24
Peak memory 196580 kb
Host smart-a8cef507-de91-43d7-b699-0a3c20a9e80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924977795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2924977795
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2134925704
Short name T1070
Test name
Test status
Simulation time 39306283839 ps
CPU time 61.43 seconds
Started Jan 25 04:34:12 AM PST 24
Finished Jan 25 04:35:18 AM PST 24
Peak memory 200068 kb
Host smart-5d1b94cd-1bf9-44d2-a6c8-899a06e996e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134925704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2134925704
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3893817463
Short name T409
Test name
Test status
Simulation time 7037697681 ps
CPU time 392.65 seconds
Started Jan 25 02:08:03 AM PST 24
Finished Jan 25 02:14:37 AM PST 24
Peak memory 200068 kb
Host smart-5473fa84-44f0-4f40-aaf8-8d3e22e8afc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893817463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3893817463
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1320276513
Short name T1221
Test name
Test status
Simulation time 630441614 ps
CPU time 3.36 seconds
Started Jan 25 03:56:25 AM PST 24
Finished Jan 25 03:56:33 AM PST 24
Peak memory 198100 kb
Host smart-e2b0d40d-db26-4ca3-8e3b-cc78720afd78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320276513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1320276513
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2598106560
Short name T946
Test name
Test status
Simulation time 133003807261 ps
CPU time 109 seconds
Started Jan 25 02:07:36 AM PST 24
Finished Jan 25 02:09:26 AM PST 24
Peak memory 199708 kb
Host smart-086cea42-ca3d-4f0f-8b82-266445e54856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598106560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2598106560
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1809167870
Short name T1074
Test name
Test status
Simulation time 45262577961 ps
CPU time 77.84 seconds
Started Jan 25 02:07:32 AM PST 24
Finished Jan 25 02:08:51 AM PST 24
Peak memory 195624 kb
Host smart-4dd5c36a-5a4c-4e42-baf2-6cbecb48db9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809167870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1809167870
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1842243159
Short name T973
Test name
Test status
Simulation time 6200137214 ps
CPU time 9.63 seconds
Started Jan 25 06:01:55 AM PST 24
Finished Jan 25 06:02:07 AM PST 24
Peak memory 200024 kb
Host smart-3551e0cd-eff0-4203-b170-dd4512020060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842243159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1842243159
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2631154266
Short name T867
Test name
Test status
Simulation time 177290237842 ps
CPU time 903.87 seconds
Started Jan 25 02:08:03 AM PST 24
Finished Jan 25 02:23:08 AM PST 24
Peak memory 200068 kb
Host smart-2cddf2de-5739-45bd-aa47-fa35bd5b1a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631154266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2631154266
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.412301734
Short name T536
Test name
Test status
Simulation time 6586823387 ps
CPU time 24.14 seconds
Started Jan 25 02:07:33 AM PST 24
Finished Jan 25 02:07:58 AM PST 24
Peak memory 199952 kb
Host smart-7d16c7d9-582d-477c-a4c8-c06aaf03db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412301734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.412301734
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3598352340
Short name T194
Test name
Test status
Simulation time 18922434894 ps
CPU time 15.8 seconds
Started Jan 25 02:07:34 AM PST 24
Finished Jan 25 02:07:52 AM PST 24
Peak memory 199176 kb
Host smart-b55630a6-2732-4c15-a0fd-0ff43536e8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598352340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3598352340
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.452142351
Short name T689
Test name
Test status
Simulation time 83069633357 ps
CPU time 30.29 seconds
Started Jan 25 03:05:23 AM PST 24
Finished Jan 25 03:05:54 AM PST 24
Peak memory 200068 kb
Host smart-502f2e24-4549-405c-af55-984bf9daa988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452142351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.452142351
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1170148243
Short name T348
Test name
Test status
Simulation time 179176503077 ps
CPU time 1581.01 seconds
Started Jan 25 02:39:13 AM PST 24
Finished Jan 25 03:05:36 AM PST 24
Peak memory 225028 kb
Host smart-2afa5b01-0418-4365-952e-dcf3f7f89de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170148243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1170148243
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2333960105
Short name T112
Test name
Test status
Simulation time 127173605625 ps
CPU time 160.37 seconds
Started Jan 25 05:16:17 AM PST 24
Finished Jan 25 05:19:04 AM PST 24
Peak memory 200128 kb
Host smart-c36978bf-09a4-4f43-ac61-391fe8c6aacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333960105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2333960105
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2964980073
Short name T361
Test name
Test status
Simulation time 20787888673 ps
CPU time 181.73 seconds
Started Jan 25 02:39:08 AM PST 24
Finished Jan 25 02:42:13 AM PST 24
Peak memory 209588 kb
Host smart-26afb9ed-bc71-4fcb-8675-74bbb2ccfb82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964980073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2964980073
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2271313904
Short name T906
Test name
Test status
Simulation time 85499116779 ps
CPU time 29.31 seconds
Started Jan 25 04:49:44 AM PST 24
Finished Jan 25 04:50:26 AM PST 24
Peak memory 200052 kb
Host smart-c065fcab-33c8-4e82-86e9-fc26a81fbccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271313904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2271313904
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2056274565
Short name T1225
Test name
Test status
Simulation time 87331566073 ps
CPU time 61.45 seconds
Started Jan 25 02:39:09 AM PST 24
Finished Jan 25 02:40:14 AM PST 24
Peak memory 200008 kb
Host smart-714d3876-4c57-4d00-8c24-1d036a399142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056274565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2056274565
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1379107901
Short name T359
Test name
Test status
Simulation time 9126998060 ps
CPU time 16.18 seconds
Started Jan 25 02:39:09 AM PST 24
Finished Jan 25 02:39:29 AM PST 24
Peak memory 198888 kb
Host smart-f939c287-b58c-483e-90e8-560103d5085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379107901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1379107901
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.327271724
Short name T374
Test name
Test status
Simulation time 99997609225 ps
CPU time 176.03 seconds
Started Jan 25 03:46:25 AM PST 24
Finished Jan 25 03:49:22 AM PST 24
Peak memory 208484 kb
Host smart-a5a616cb-8a33-4ef1-9d62-1249448760af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327271724 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.327271724
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3162539327
Short name T255
Test name
Test status
Simulation time 231041212695 ps
CPU time 702.1 seconds
Started Jan 25 02:39:21 AM PST 24
Finished Jan 25 02:51:09 AM PST 24
Peak memory 224924 kb
Host smart-68fa135b-f5e6-41bd-93ee-d1913e607910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162539327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3162539327
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4230317520
Short name T134
Test name
Test status
Simulation time 55268498220 ps
CPU time 43.2 seconds
Started Jan 25 02:39:23 AM PST 24
Finished Jan 25 02:40:17 AM PST 24
Peak memory 200072 kb
Host smart-5a7568ab-78df-4c64-adb1-e11c6cb7e694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230317520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4230317520
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3422051908
Short name T841
Test name
Test status
Simulation time 12170303242 ps
CPU time 22.06 seconds
Started Jan 25 02:39:20 AM PST 24
Finished Jan 25 02:39:48 AM PST 24
Peak memory 199848 kb
Host smart-6e23c919-1c4b-4dfd-88c3-5d19aeb5432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422051908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3422051908
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3324186923
Short name T990
Test name
Test status
Simulation time 143393253245 ps
CPU time 1030.69 seconds
Started Jan 25 02:39:22 AM PST 24
Finished Jan 25 02:56:43 AM PST 24
Peak memory 216540 kb
Host smart-bd09ea17-6928-4771-96e1-e486064d7192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324186923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3324186923
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1544285584
Short name T306
Test name
Test status
Simulation time 20201664405 ps
CPU time 34.56 seconds
Started Jan 25 02:39:19 AM PST 24
Finished Jan 25 02:39:59 AM PST 24
Peak memory 200068 kb
Host smart-47c0a004-8914-4c3b-9091-5fc59d4638cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544285584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1544285584
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3337108869
Short name T766
Test name
Test status
Simulation time 26110840700 ps
CPU time 340.34 seconds
Started Jan 25 02:39:22 AM PST 24
Finished Jan 25 02:45:08 AM PST 24
Peak memory 209932 kb
Host smart-0f6b6ae6-7904-469c-8335-81015b5dd5c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337108869 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3337108869
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3657727584
Short name T636
Test name
Test status
Simulation time 48154747 ps
CPU time 0.57 seconds
Started Jan 25 02:09:11 AM PST 24
Finished Jan 25 02:09:14 AM PST 24
Peak memory 194588 kb
Host smart-55710767-7f2a-4831-a48e-d54bae29b9f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657727584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3657727584
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2737726659
Short name T634
Test name
Test status
Simulation time 181493772375 ps
CPU time 297.15 seconds
Started Jan 25 02:08:02 AM PST 24
Finished Jan 25 02:13:00 AM PST 24
Peak memory 200096 kb
Host smart-91cbde18-e206-421f-b1ef-6d18297980bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737726659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2737726659
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2041601596
Short name T1043
Test name
Test status
Simulation time 33924757985 ps
CPU time 56.44 seconds
Started Jan 25 02:08:53 AM PST 24
Finished Jan 25 02:09:50 AM PST 24
Peak memory 199584 kb
Host smart-75cc6438-fef8-4bbc-b277-42bf39379206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041601596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2041601596
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1537104702
Short name T262
Test name
Test status
Simulation time 91048561105 ps
CPU time 71.29 seconds
Started Jan 25 02:48:36 AM PST 24
Finished Jan 25 02:49:49 AM PST 24
Peak memory 200064 kb
Host smart-02445fc9-c4a0-499e-8106-ba04a6dc35fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537104702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1537104702
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1496899239
Short name T950
Test name
Test status
Simulation time 683069760771 ps
CPU time 608.64 seconds
Started Jan 25 02:08:52 AM PST 24
Finished Jan 25 02:19:02 AM PST 24
Peak memory 200072 kb
Host smart-ba1d081b-e4b7-4214-bc41-fc971949ffde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496899239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1496899239
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.36530661
Short name T898
Test name
Test status
Simulation time 88136774145 ps
CPU time 341.72 seconds
Started Jan 25 02:08:54 AM PST 24
Finished Jan 25 02:14:37 AM PST 24
Peak memory 200076 kb
Host smart-b8f06f68-14e3-4d23-9cd4-2b393fe47c67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36530661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.36530661
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.933159744
Short name T550
Test name
Test status
Simulation time 4474902247 ps
CPU time 2.92 seconds
Started Jan 25 02:08:52 AM PST 24
Finished Jan 25 02:08:56 AM PST 24
Peak memory 198892 kb
Host smart-7123e3cc-c2d7-4588-b3f3-4fb9ac1c17f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933159744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.933159744
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1716510487
Short name T1145
Test name
Test status
Simulation time 60736086533 ps
CPU time 106.24 seconds
Started Jan 25 02:08:54 AM PST 24
Finished Jan 25 02:10:41 AM PST 24
Peak memory 197896 kb
Host smart-f29db750-1a15-4bdf-a604-0f5921ca541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716510487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1716510487
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4207452883
Short name T13
Test name
Test status
Simulation time 979370154 ps
CPU time 2.74 seconds
Started Jan 25 02:08:53 AM PST 24
Finished Jan 25 02:08:57 AM PST 24
Peak memory 198088 kb
Host smart-b8776cd9-62d1-4ad1-9166-f4ad4ffaea53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207452883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4207452883
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2855823502
Short name T992
Test name
Test status
Simulation time 41210482328 ps
CPU time 16.97 seconds
Started Jan 25 02:08:51 AM PST 24
Finished Jan 25 02:09:09 AM PST 24
Peak memory 199032 kb
Host smart-0ab46bb6-8691-4fe7-93ac-d2d803f2f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855823502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2855823502
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2693410698
Short name T532
Test name
Test status
Simulation time 4756505364 ps
CPU time 9.06 seconds
Started Jan 25 02:08:55 AM PST 24
Finished Jan 25 02:09:07 AM PST 24
Peak memory 195664 kb
Host smart-0b94c747-a319-445f-bfc8-5a386d0bd7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693410698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2693410698
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3195066894
Short name T831
Test name
Test status
Simulation time 11065847946 ps
CPU time 32.46 seconds
Started Jan 25 02:08:02 AM PST 24
Finished Jan 25 02:08:35 AM PST 24
Peak memory 199080 kb
Host smart-12265c80-9cf2-4762-b008-c3aa64ab4d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195066894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3195066894
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4080467532
Short name T896
Test name
Test status
Simulation time 12053011964 ps
CPU time 20.87 seconds
Started Jan 25 02:08:51 AM PST 24
Finished Jan 25 02:09:13 AM PST 24
Peak memory 200128 kb
Host smart-8e3c4055-b68a-4564-b464-45bdfad11e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080467532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4080467532
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3931371090
Short name T905
Test name
Test status
Simulation time 62844004632 ps
CPU time 360.3 seconds
Started Jan 25 02:08:52 AM PST 24
Finished Jan 25 02:14:54 AM PST 24
Peak memory 208464 kb
Host smart-8bfaaee7-cbed-4f89-b1a7-1c83d71577b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931371090 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3931371090
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3105434974
Short name T598
Test name
Test status
Simulation time 780532156 ps
CPU time 2.11 seconds
Started Jan 25 02:08:51 AM PST 24
Finished Jan 25 02:08:55 AM PST 24
Peak memory 198436 kb
Host smart-28fd9461-b220-4e25-ae5a-0591b6671b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105434974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3105434974
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.909581593
Short name T103
Test name
Test status
Simulation time 85256102282 ps
CPU time 26.95 seconds
Started Jan 25 02:08:01 AM PST 24
Finished Jan 25 02:08:29 AM PST 24
Peak memory 199888 kb
Host smart-3a479af7-eb17-40a1-90e3-5cbd32f37cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909581593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.909581593
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2219258081
Short name T152
Test name
Test status
Simulation time 57070230305 ps
CPU time 13.63 seconds
Started Jan 25 02:39:40 AM PST 24
Finished Jan 25 02:40:07 AM PST 24
Peak memory 199948 kb
Host smart-ed8c0a8a-505a-48f0-b50a-7816fb3cb5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219258081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2219258081
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.494043777
Short name T1018
Test name
Test status
Simulation time 52992336788 ps
CPU time 505.96 seconds
Started Jan 25 02:39:40 AM PST 24
Finished Jan 25 02:48:19 AM PST 24
Peak memory 216444 kb
Host smart-34478fdd-ec9a-4140-9774-0605b5382531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494043777 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.494043777
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2889435065
Short name T962
Test name
Test status
Simulation time 131261410543 ps
CPU time 204.43 seconds
Started Jan 25 02:39:36 AM PST 24
Finished Jan 25 02:43:14 AM PST 24
Peak memory 199824 kb
Host smart-ea3e480d-b0e7-459b-bc49-23fe4c927697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889435065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2889435065
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3025703085
Short name T313
Test name
Test status
Simulation time 21752612663 ps
CPU time 301.52 seconds
Started Jan 25 02:39:40 AM PST 24
Finished Jan 25 02:44:55 AM PST 24
Peak memory 210840 kb
Host smart-6a252d69-bbad-4fbc-9f84-852548d230c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025703085 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3025703085
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.802855641
Short name T124
Test name
Test status
Simulation time 37595251902 ps
CPU time 18.31 seconds
Started Jan 25 02:39:36 AM PST 24
Finished Jan 25 02:40:08 AM PST 24
Peak memory 200080 kb
Host smart-8e2280ea-5db9-492d-88a6-c3058356412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802855641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.802855641
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.558733787
Short name T901
Test name
Test status
Simulation time 263285992507 ps
CPU time 761.01 seconds
Started Jan 25 02:39:37 AM PST 24
Finished Jan 25 02:52:32 AM PST 24
Peak memory 216788 kb
Host smart-84f2a5f9-05f4-4f52-8da4-62bd55a345bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558733787 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.558733787
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1629083231
Short name T1158
Test name
Test status
Simulation time 45313521100 ps
CPU time 538.08 seconds
Started Jan 25 02:39:48 AM PST 24
Finished Jan 25 02:48:53 AM PST 24
Peak memory 210220 kb
Host smart-2ccc7116-25a1-4010-a045-14bd334cadc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629083231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1629083231
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.4085011314
Short name T1016
Test name
Test status
Simulation time 128928196370 ps
CPU time 140.19 seconds
Started Jan 25 02:39:50 AM PST 24
Finished Jan 25 02:42:16 AM PST 24
Peak memory 200020 kb
Host smart-963eb31c-d5e7-4cd1-947b-be605dad7d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085011314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.4085011314
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3723532296
Short name T249
Test name
Test status
Simulation time 34752395222 ps
CPU time 48.55 seconds
Started Jan 25 02:39:56 AM PST 24
Finished Jan 25 02:40:47 AM PST 24
Peak memory 200000 kb
Host smart-029532a0-9f43-4ce1-9199-5dec7607cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723532296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3723532296
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2254248439
Short name T322
Test name
Test status
Simulation time 24712016492 ps
CPU time 262.96 seconds
Started Jan 25 02:39:55 AM PST 24
Finished Jan 25 02:44:21 AM PST 24
Peak memory 216596 kb
Host smart-bb0f4224-3fc0-4e5e-87b6-5a0f7210d68f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254248439 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2254248439
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3287617218
Short name T1083
Test name
Test status
Simulation time 97773014886 ps
CPU time 25.63 seconds
Started Jan 25 02:40:04 AM PST 24
Finished Jan 25 02:40:32 AM PST 24
Peak memory 198960 kb
Host smart-a62b538f-b148-4687-8cf6-1d4e5a25b752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287617218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3287617218
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3950528826
Short name T940
Test name
Test status
Simulation time 29692798117 ps
CPU time 193.63 seconds
Started Jan 25 02:40:23 AM PST 24
Finished Jan 25 02:43:47 AM PST 24
Peak memory 215784 kb
Host smart-feeab146-d35f-4211-b42a-fe95b97f3749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950528826 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3950528826
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3716304911
Short name T932
Test name
Test status
Simulation time 36535586721 ps
CPU time 13.2 seconds
Started Jan 25 02:40:22 AM PST 24
Finished Jan 25 02:40:45 AM PST 24
Peak memory 200052 kb
Host smart-fb2a098d-46e0-4b69-83d6-78e580ea1964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716304911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3716304911
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4034700827
Short name T1165
Test name
Test status
Simulation time 97746104522 ps
CPU time 44.38 seconds
Started Jan 25 02:40:18 AM PST 24
Finished Jan 25 02:41:12 AM PST 24
Peak memory 200060 kb
Host smart-a489db04-13a3-4323-bb3d-25f1f45d0dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034700827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4034700827
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.888589479
Short name T968
Test name
Test status
Simulation time 31013114656 ps
CPU time 434.97 seconds
Started Jan 25 02:40:25 AM PST 24
Finished Jan 25 02:47:50 AM PST 24
Peak memory 216444 kb
Host smart-4c59ca12-ffb7-4e2d-9153-126a171ddf89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888589479 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.888589479
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2731654723
Short name T192
Test name
Test status
Simulation time 6493191672 ps
CPU time 12.13 seconds
Started Jan 25 02:40:24 AM PST 24
Finished Jan 25 02:40:46 AM PST 24
Peak memory 199344 kb
Host smart-9e453c3b-9975-4899-8131-4cb417ce1151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731654723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2731654723
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2865580408
Short name T538
Test name
Test status
Simulation time 42260640613 ps
CPU time 576.47 seconds
Started Jan 25 02:40:35 AM PST 24
Finished Jan 25 02:50:21 AM PST 24
Peak memory 211128 kb
Host smart-7b82211d-a6d9-45dc-847f-d249f9d932d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865580408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2865580408
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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