Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	132376	1			T4	8		T6	5		T7	8
all_values[1]	132376	1			T4	8		T6	5		T7	8
all_values[2]	132376	1			T4	8		T6	5		T7	8
all_values[3]	132376	1			T4	8		T6	5		T7	8
all_values[4]	132376	1			T4	8		T6	5		T7	8
all_values[5]	132376	1			T4	8		T6	5		T7	8
all_values[6]	132376	1			T4	8		T6	5		T7	8
all_values[7]	132376	1			T4	8		T6	5		T7	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

524580

1

T4

36

T6

25

T7

24

auto[1]

534428

1

T4

28

T6

15

T7

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040707

1

T4

40

T6

23

T7

44

auto[1]

18301

1

T4

24

T6

17

T7

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	62040	1			T4	4		T6	3		T10	1
all_values[0]	auto[0]	auto[1]	2675	1			T4	1		T6	2		T7	1
all_values[0]	auto[1]	auto[0]	65342	1			T4	3		T7	5		T10	3
all_values[0]	auto[1]	auto[1]	2319	1			T7	2		T10	3		T49	2
all_values[1]	auto[0]	auto[0]	65178	1			T4	1		T6	3		T7	1
all_values[1]	auto[0]	auto[1]	2610	1			T4	1		T6	2		T7	1
all_values[1]	auto[1]	auto[0]	62028	1			T4	5		T7	2		T49	5
all_values[1]	auto[1]	auto[1]	2560	1			T4	1		T7	4		T10	3
all_values[2]	auto[0]	auto[0]	62918	1			T6	1		T7	6		T10	2
all_values[2]	auto[0]	auto[1]	2658	1			T4	4		T6	2		T7	1
all_values[2]	auto[1]	auto[0]	64462	1			T4	1		T10	2		T50	1
all_values[2]	auto[1]	auto[1]	2338	1			T4	3		T6	2		T7	1
all_values[3]	auto[0]	auto[0]	63137	1			T4	2		T6	3		T7	3
all_values[3]	auto[0]	auto[1]	239	1			T4	5		T10	4		T49	5
all_values[3]	auto[1]	auto[0]	68753	1			T4	1		T6	1		T7	3
all_values[3]	auto[1]	auto[1]	247	1			T6	1		T7	2		T10	3
all_values[4]	auto[0]	auto[0]	61247	1			T4	2		T7	2		T10	2
all_values[4]	auto[0]	auto[1]	514	1			T7	3		T10	3		T49	6
all_values[4]	auto[1]	auto[0]	70105	1			T4	6		T6	5		T7	3
all_values[4]	auto[1]	auto[1]	510	1			T10	2		T49	1		T81	3
all_values[5]	auto[0]	auto[0]	65072	1			T4	5		T6	1		T7	2
all_values[5]	auto[0]	auto[1]	220	1			T4	1		T6	2		T10	2
all_values[5]	auto[1]	auto[0]	66881	1			T4	2		T7	5		T10	2
all_values[5]	auto[1]	auto[1]	203	1			T6	2		T7	1		T10	2
all_values[6]	auto[0]	auto[0]	68272	1			T4	3		T6	4		T7	1
all_values[6]	auto[0]	auto[1]	184	1			T4	2		T6	1		T10	1
all_values[6]	auto[1]	auto[0]	63711	1			T4	1		T7	3		T10	1
all_values[6]	auto[1]	auto[1]	209	1			T4	2		T7	4		T10	1
all_values[7]	auto[0]	auto[0]	67186	1			T4	3		T7	3		T10	3
all_values[7]	auto[0]	auto[1]	430	1			T4	2		T6	1		T10	3
all_values[7]	auto[1]	auto[0]	64375	1			T4	1		T6	2		T7	5
all_values[7]	auto[1]	auto[1]	385	1			T4	2		T6	2		T81	1