Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2557

1

T1

1

T2

2

T3

3

auto[UartRx]

2557

1

T1

1

T2

2

T3

3

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4518	1			T1	2		T2	4		T3	6
values[1]	45	1			T26	1		T65	1		T150	1
values[2]	55	1			T20	2		T33	1		T155	1
values[3]	70	1			T14	3		T26	1		T65	1
values[4]	55	1			T14	1		T33	1		T321	1
values[5]	44	1			T20	1		T368	1		T26	1
values[6]	63	1			T26	2		T319	1		T321	1
values[7]	61	1			T368	1		T65	1		T319	2
values[8]	53	1			T368	1		T26	1		T419	1
values[9]	63	1			T218	2		T155	2		T419	1
values[10]	68	1			T26	1		T65	2		T319	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2354	1			T1	1		T2	2		T3	3
auto[UartTx]	values[1]	13	1			T150	1		T445	1		T102	2
auto[UartTx]	values[2]	21	1			T20	1		T173	1		T136	1
auto[UartTx]	values[3]	10	1			T292	1		T346	1		T446	1
auto[UartTx]	values[4]	29	1			T33	1		T403	1		T447	1
auto[UartTx]	values[5]	15	1			T20	1		T26	1		T136	1
auto[UartTx]	values[6]	26	1			T26	1		T150	1		T447	1
auto[UartTx]	values[7]	23	1			T319	1		T321	1		T155	1
auto[UartTx]	values[8]	19	1			T26	1		T403	1		T117	1
auto[UartTx]	values[9]	16	1			T155	1		T419	1		T403	1
auto[UartTx]	values[10]	26	1			T65	1		T319	1		T321	2
auto[UartRx]	values[0]	2164	1			T1	1		T2	2		T3	3
auto[UartRx]	values[1]	32	1			T26	1		T65	1		T233	1
auto[UartRx]	values[2]	34	1			T20	1		T33	1		T155	1
auto[UartRx]	values[3]	60	1			T14	3		T26	1		T65	1
auto[UartRx]	values[4]	26	1			T14	1		T321	1		T419	1
auto[UartRx]	values[5]	29	1			T368	1		T65	1		T403	2
auto[UartRx]	values[6]	37	1			T26	1		T319	1		T321	1
auto[UartRx]	values[7]	38	1			T368	1		T65	1		T319	1
auto[UartRx]	values[8]	34	1			T368	1		T419	1		T403	1
auto[UartRx]	values[9]	47	1			T218	2		T155	1		T404	1
auto[UartRx]	values[10]	42	1			T26	1		T65	1		T218	1