Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1848	1			T11	2		T13	2		T19	1
auto[BaudRate115200]	2175	1			T11	4		T12	1		T13	2
auto[BaudRate230400]	1984	1			T11	1		T12	1		T20	3
auto[BaudRate128Kbps]	1887	1			T11	1		T12	3		T20	4
auto[BaudRate256Kbps]	2190	1			T12	1		T20	3		T21	3
auto[BaudRate1Mbps]	1619	1			T11	1		T19	2		T20	2
auto[BaudRate1p5Mbps]	1161	1			T20	1		T14	3		T17	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1707	1			T15	10		T25	24		T147	7
freqs[25]	1176	1			T20	19		T23	6		T444	6
freqs[48]	566	1			T175	6		T422	2		T266	6
freqs[50]	444	1			T14	26		T16	9		T34	9
freqs[100]	1248	1			T423	2		T426	2		T125	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	217	1			T25	2		T147	1		T123	1
auto[BaudRate9600]	freqs[25]	152	1			T20	6		T160	2		T415	2
auto[BaudRate9600]	freqs[48]	70	1			T175	1		T112	1		T324	2
auto[BaudRate9600]	freqs[50]	68	1			T14	2		T368	1		T448	4
auto[BaudRate9600]	freqs[100]	161	1			T426	1		T191	1		T33	9
auto[BaudRate115200]	freqs[24]	298	1			T25	3		T147	1		T305	2
auto[BaudRate115200]	freqs[25]	202	1			T444	1		T428	1		T160	1
auto[BaudRate115200]	freqs[48]	87	1			T449	1		T324	1		T450	1
auto[BaudRate115200]	freqs[50]	62	1			T14	2		T16	2		T34	2
auto[BaudRate115200]	freqs[100]	229	1			T423	1		T125	1		T441	1
auto[BaudRate230400]	freqs[24]	227	1			T25	5		T147	1		T123	1
auto[BaudRate230400]	freqs[25]	192	1			T20	3		T23	2		T444	1
auto[BaudRate230400]	freqs[48]	81	1			T266	2		T112	1		T324	1
auto[BaudRate230400]	freqs[50]	54	1			T14	3		T16	3		T34	3
auto[BaudRate230400]	freqs[100]	198	1			T423	1		T125	2		T191	2
auto[BaudRate128Kbps]	freqs[24]	284	1			T25	9		T147	2		T123	2
auto[BaudRate128Kbps]	freqs[25]	190	1			T20	4		T23	2		T415	1
auto[BaudRate128Kbps]	freqs[48]	75	1			T175	2		T422	2		T324	4
auto[BaudRate128Kbps]	freqs[50]	56	1			T14	5		T16	1		T368	3
auto[BaudRate128Kbps]	freqs[100]	165	1			T125	2		T157	2		T33	6
auto[BaudRate256Kbps]	freqs[24]	269	1			T15	4		T25	2		T305	2
auto[BaudRate256Kbps]	freqs[25]	190	1			T20	3		T23	1		T444	1
auto[BaudRate256Kbps]	freqs[48]	86	1			T175	1		T266	1		T112	3
auto[BaudRate256Kbps]	freqs[50]	66	1			T14	5		T16	1		T368	3
auto[BaudRate256Kbps]	freqs[100]	170	1			T125	2		T157	1		T191	1
auto[BaudRate1Mbps]	freqs[24]	263	1			T15	2		T25	2		T123	1
auto[BaudRate1Mbps]	freqs[25]	155	1			T20	2		T23	1		T444	2
auto[BaudRate1Mbps]	freqs[48]	84	1			T175	1		T266	1		T324	1
auto[BaudRate1Mbps]	freqs[50]	64	1			T14	6		T16	1		T34	2
auto[BaudRate1Mbps]	freqs[100]	157	1			T125	2		T441	1		T157	1
auto[BaudRate1p5Mbps]	freqs[25]	95	1			T20	1		T444	1		T428	1
auto[BaudRate1p5Mbps]	freqs[48]	83	1			T175	1		T266	2		T450	1
auto[BaudRate1p5Mbps]	freqs[50]	74	1			T14	3		T16	1		T34	2
auto[BaudRate1p5Mbps]	freqs[100]	168	1			T426	1		T125	1		T157	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded