Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	132376	1			T4	8		T6	5		T7	8
all_pins[1]	132376	1			T4	8		T6	5		T7	8
all_pins[2]	132376	1			T4	8		T6	5		T7	8
all_pins[3]	132376	1			T4	8		T6	5		T7	8
all_pins[4]	132376	1			T4	8		T6	5		T7	8
all_pins[5]	132376	1			T4	8		T6	5		T7	8
all_pins[6]	132376	1			T4	8		T6	5		T7	8
all_pins[7]	132376	1			T4	8		T6	5		T7	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1049381	1			T4	56		T6	33		T7	50
values[0x1]	9627	1			T4	8		T6	7		T7	14
transitions[0x0=>0x1]	8704	1			T4	7		T6	6		T7	9
transitions[0x1=>0x0]	8716	1			T4	7		T6	6		T7	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	129977	1			T4	8		T6	5		T7	6
all_pins[0]	values[0x1]	2399	1			T7	2		T10	3		T49	2
all_pins[0]	transitions[0x0=>0x1]	2102	1			T10	2		T49	2		T50	1
all_pins[0]	transitions[0x1=>0x0]	2259	1			T4	1		T7	2		T10	2
all_pins[1]	values[0x0]	129820	1			T4	7		T6	5		T7	4
all_pins[1]	values[0x1]	2556	1			T4	1		T7	4		T10	3
all_pins[1]	transitions[0x0=>0x1]	2277	1			T4	1		T7	3		T10	3
all_pins[1]	transitions[0x1=>0x0]	2138	1			T4	3		T6	2		T10	2
all_pins[2]	values[0x0]	129959	1			T4	5		T6	3		T7	7
all_pins[2]	values[0x1]	2417	1			T4	3		T6	2		T7	1
all_pins[2]	transitions[0x0=>0x1]	2366	1			T4	3		T6	1		T10	2
all_pins[2]	transitions[0x1=>0x0]	196	1			T7	1		T10	3		T49	1
all_pins[3]	values[0x0]	132129	1			T4	8		T6	4		T7	6
all_pins[3]	values[0x1]	247	1			T6	1		T7	2		T10	3
all_pins[3]	transitions[0x0=>0x1]	189	1			T6	1		T7	2		T10	1
all_pins[3]	transitions[0x1=>0x0]	452	1			T49	1		T81	3		T397	4
all_pins[4]	values[0x0]	131866	1			T4	8		T6	5		T7	8
all_pins[4]	values[0x1]	510	1			T10	2		T49	1		T81	3
all_pins[4]	transitions[0x0=>0x1]	433	1			T10	2		T49	1		T81	3
all_pins[4]	transitions[0x1=>0x0]	194	1			T6	2		T7	1		T10	2
all_pins[5]	values[0x0]	132105	1			T4	8		T6	3		T7	7
all_pins[5]	values[0x1]	271	1			T6	2		T7	1		T10	2
all_pins[5]	transitions[0x0=>0x1]	220	1			T6	2		T10	1		T49	1
all_pins[5]	transitions[0x1=>0x0]	791	1			T4	2		T7	3		T49	3
all_pins[6]	values[0x0]	131534	1			T4	6		T6	5		T7	4
all_pins[6]	values[0x1]	842	1			T4	2		T7	4		T10	1
all_pins[6]	transitions[0x0=>0x1]	786	1			T4	1		T7	4		T10	1
all_pins[6]	transitions[0x1=>0x0]	329	1			T4	1		T6	2		T81	1
all_pins[7]	values[0x0]	131991	1			T4	6		T6	3		T7	8
all_pins[7]	values[0x1]	385	1			T4	2		T6	2		T81	1
all_pins[7]	transitions[0x0=>0x1]	331	1			T4	2		T6	2		T81	1
all_pins[7]	transitions[0x1=>0x0]	2357	1			T7	2		T10	3		T49	2