Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	877	1			T4	7		T6	4		T7	7
all_values[1]	877	1			T4	7		T6	4		T7	7
all_values[2]	877	1			T4	7		T6	4		T7	7
all_values[3]	877	1			T4	7		T6	4		T7	7
all_values[4]	877	1			T4	7		T6	4		T7	7
all_values[5]	877	1			T4	7		T6	4		T7	7
all_values[6]	877	1			T4	7		T6	4		T7	7
all_values[7]	877	1			T4	7		T6	4		T7	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3846

1

T4

33

T6

17

T7

28

auto[1]

3170

1

T4

23

T6

15

T7

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2792

1

T4

27

T6

10

T7

25

auto[1]

4224

1

T4

29

T6

22

T7

31

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4176

1

T4

38

T6

16

T7

35

auto[1]

2840

1

T4

18

T6

16

T7

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	193	1			T4	4		T6	1		T7	1
all_values[0]	auto[0]	auto[0]	auto[1]	81	1			T6	1		T10	1		T81	1
all_values[0]	auto[0]	auto[1]	auto[0]	146	1			T4	1		T7	2		T10	1
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T7	2		T10	1		T49	1
all_values[0]	auto[1]	auto[0]	auto[1]	179	1			T4	1		T6	2		T7	1
all_values[0]	auto[1]	auto[1]	auto[1]	184	1			T4	1		T7	1		T10	3
all_values[1]	auto[0]	auto[0]	auto[0]	184	1			T4	1		T6	1		T10	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T10	3		T81	2		T72	1
all_values[1]	auto[0]	auto[1]	auto[0]	175	1			T4	2		T49	2		T397	2
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T7	2		T10	1		T50	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T4	2		T6	3		T7	3
all_values[1]	auto[1]	auto[1]	auto[1]	162	1			T4	2		T7	2		T10	1
all_values[2]	auto[0]	auto[0]	auto[0]	229	1			T7	5		T10	2		T49	1
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T4	1		T6	1		T7	1
all_values[2]	auto[0]	auto[1]	auto[0]	163	1			T50	1		T397	2		T109	1
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T4	2		T6	1		T10	2
all_values[2]	auto[1]	auto[0]	auto[1]	174	1			T4	2		T10	2		T49	4
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T4	2		T6	2		T7	1
all_values[3]	auto[0]	auto[0]	auto[0]	185	1			T4	1		T6	1		T7	2
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T4	2		T10	1		T49	3
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T4	1		T6	1		T7	2
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T6	1		T10	1		T49	1
all_values[3]	auto[1]	auto[0]	auto[1]	203	1			T4	3		T10	2		T49	2
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T6	1		T7	3		T10	3
all_values[4]	auto[0]	auto[0]	auto[0]	200	1			T4	4		T7	1		T10	1
all_values[4]	auto[0]	auto[0]	auto[1]	98	1			T7	1		T10	2		T49	4
all_values[4]	auto[0]	auto[1]	auto[0]	158	1			T4	3		T6	3		T7	2
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T10	1		T81	2		T397	1
all_values[4]	auto[1]	auto[0]	auto[1]	187	1			T7	2		T10	1		T49	2
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T6	1		T7	1		T10	1
all_values[5]	auto[0]	auto[0]	auto[0]	189	1			T4	3		T7	2		T10	1
all_values[5]	auto[0]	auto[0]	auto[1]	102	1			T4	1		T6	1		T10	2
all_values[5]	auto[0]	auto[1]	auto[0]	131	1			T4	2		T7	2		T10	2
all_values[5]	auto[0]	auto[1]	auto[1]	87	1			T7	1		T50	1		T397	1
all_values[5]	auto[1]	auto[0]	auto[1]	209	1			T7	1		T49	3		T50	1
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T4	1		T6	3		T7	1
all_values[6]	auto[0]	auto[0]	auto[0]	203	1			T4	1		T6	2		T7	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T4	2		T7	1		T49	1
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T4	1		T10	2		T397	1
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T4	1		T7	2		T49	1
all_values[6]	auto[1]	auto[0]	auto[1]	206	1			T4	1		T6	2		T7	1
all_values[6]	auto[1]	auto[1]	auto[1]	154	1			T4	1		T7	2		T49	2
all_values[7]	auto[0]	auto[0]	auto[0]	188	1			T4	2		T7	3		T10	2
all_values[7]	auto[0]	auto[0]	auto[1]	99	1			T4	2		T10	2		T81	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T4	1		T6	1		T7	2
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T6	1		T397	1		T398	1
all_values[7]	auto[1]	auto[0]	auto[1]	215	1			T6	2		T7	2		T10	1
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T4	2		T81	2		T397	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal