Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.79 98.45 100.00 99.76 100.00 97.48


Total test records in report: 1297
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T1252 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.157963580 Feb 04 12:45:54 PM PST 24 Feb 04 12:45:57 PM PST 24 19471730 ps
T1253 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3249222273 Feb 04 12:46:01 PM PST 24 Feb 04 12:46:08 PM PST 24 48371922 ps
T1254 /workspace/coverage/cover_reg_top/41.uart_intr_test.2866554341 Feb 04 12:46:33 PM PST 24 Feb 04 12:46:34 PM PST 24 15073730 ps
T1255 /workspace/coverage/cover_reg_top/19.uart_intr_test.548012783 Feb 04 12:46:32 PM PST 24 Feb 04 12:46:33 PM PST 24 38935545 ps
T1256 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3936066299 Feb 04 12:46:11 PM PST 24 Feb 04 12:46:13 PM PST 24 94862304 ps
T1257 /workspace/coverage/cover_reg_top/25.uart_intr_test.1385018495 Feb 04 12:46:33 PM PST 24 Feb 04 12:46:35 PM PST 24 23183420 ps
T1258 /workspace/coverage/cover_reg_top/12.uart_intr_test.211139599 Feb 04 12:46:12 PM PST 24 Feb 04 12:46:15 PM PST 24 65679514 ps
T1259 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1546514341 Feb 04 12:46:39 PM PST 24 Feb 04 12:46:43 PM PST 24 25631691 ps
T1260 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1719177806 Feb 04 12:46:14 PM PST 24 Feb 04 12:46:16 PM PST 24 41719054 ps
T1261 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2486164586 Feb 04 12:46:09 PM PST 24 Feb 04 12:46:13 PM PST 24 194984733 ps
T1262 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3468172380 Feb 04 12:46:11 PM PST 24 Feb 04 12:46:13 PM PST 24 19576031 ps
T1263 /workspace/coverage/cover_reg_top/29.uart_intr_test.875410968 Feb 04 12:46:30 PM PST 24 Feb 04 12:46:31 PM PST 24 14560387 ps
T1264 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1740458226 Feb 04 12:46:32 PM PST 24 Feb 04 12:46:33 PM PST 24 13437805 ps
T1265 /workspace/coverage/cover_reg_top/47.uart_intr_test.3487860771 Feb 04 12:46:29 PM PST 24 Feb 04 12:46:31 PM PST 24 43649524 ps
T1266 /workspace/coverage/cover_reg_top/24.uart_intr_test.2617549563 Feb 04 12:46:34 PM PST 24 Feb 04 12:46:35 PM PST 24 31987026 ps
T1267 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3388942529 Feb 04 12:46:10 PM PST 24 Feb 04 12:46:13 PM PST 24 227911849 ps
T1268 /workspace/coverage/cover_reg_top/19.uart_tl_errors.32343454 Feb 04 12:46:45 PM PST 24 Feb 04 12:46:51 PM PST 24 37134956 ps
T77 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1714334808 Feb 04 12:46:14 PM PST 24 Feb 04 12:46:17 PM PST 24 57667059 ps
T1269 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4087432095 Feb 04 12:46:00 PM PST 24 Feb 04 12:46:06 PM PST 24 79624108 ps
T1270 /workspace/coverage/cover_reg_top/33.uart_intr_test.4254125688 Feb 04 12:46:45 PM PST 24 Feb 04 12:46:50 PM PST 24 10526333 ps
T1271 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3750845765 Feb 04 12:45:59 PM PST 24 Feb 04 12:46:08 PM PST 24 399443651 ps
T1272 /workspace/coverage/cover_reg_top/5.uart_intr_test.900117042 Feb 04 12:46:03 PM PST 24 Feb 04 12:46:09 PM PST 24 186107121 ps
T1273 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.390614900 Feb 04 12:46:00 PM PST 24 Feb 04 12:46:06 PM PST 24 333656362 ps
T1274 /workspace/coverage/cover_reg_top/32.uart_intr_test.4227600065 Feb 04 12:46:39 PM PST 24 Feb 04 12:46:43 PM PST 24 39002057 ps
T1275 /workspace/coverage/cover_reg_top/4.uart_intr_test.3430568757 Feb 04 12:45:58 PM PST 24 Feb 04 12:46:06 PM PST 24 55290937 ps
T1276 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3275173354 Feb 04 12:45:54 PM PST 24 Feb 04 12:46:02 PM PST 24 94163740 ps
T1277 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.4249880315 Feb 04 12:46:13 PM PST 24 Feb 04 12:46:16 PM PST 24 75039521 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2552695260 Feb 04 12:46:06 PM PST 24 Feb 04 12:46:11 PM PST 24 319541768 ps
T1279 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2453257481 Feb 04 12:46:02 PM PST 24 Feb 04 12:46:08 PM PST 24 102164288 ps
T1280 /workspace/coverage/cover_reg_top/15.uart_intr_test.342101162 Feb 04 12:46:09 PM PST 24 Feb 04 12:46:12 PM PST 24 29741327 ps
T1281 /workspace/coverage/cover_reg_top/11.uart_tl_errors.926651741 Feb 04 12:46:10 PM PST 24 Feb 04 12:46:13 PM PST 24 57829416 ps
T1282 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3741965847 Feb 04 12:46:07 PM PST 24 Feb 04 12:46:11 PM PST 24 63623147 ps
T1283 /workspace/coverage/cover_reg_top/18.uart_csr_rw.2229948536 Feb 04 12:46:34 PM PST 24 Feb 04 12:46:35 PM PST 24 13304054 ps
T1284 /workspace/coverage/cover_reg_top/6.uart_intr_test.2967596701 Feb 04 12:46:08 PM PST 24 Feb 04 12:46:11 PM PST 24 207949591 ps
T1285 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2556630042 Feb 04 12:46:11 PM PST 24 Feb 04 12:46:14 PM PST 24 57386552 ps
T1286 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3975596620 Feb 04 12:46:00 PM PST 24 Feb 04 12:46:07 PM PST 24 341869296 ps
T1287 /workspace/coverage/cover_reg_top/0.uart_csr_rw.425250522 Feb 04 12:46:01 PM PST 24 Feb 04 12:46:06 PM PST 24 13914001 ps
T1288 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2237300115 Feb 04 12:46:01 PM PST 24 Feb 04 12:46:08 PM PST 24 303198489 ps
T1289 /workspace/coverage/cover_reg_top/2.uart_intr_test.855580850 Feb 04 12:45:55 PM PST 24 Feb 04 12:46:04 PM PST 24 34640350 ps
T1290 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1455459814 Feb 04 12:46:07 PM PST 24 Feb 04 12:46:11 PM PST 24 134143226 ps
T1291 /workspace/coverage/cover_reg_top/18.uart_intr_test.1238534508 Feb 04 12:46:37 PM PST 24 Feb 04 12:46:42 PM PST 24 29943519 ps
T1292 /workspace/coverage/cover_reg_top/13.uart_tl_errors.135433046 Feb 04 12:46:13 PM PST 24 Feb 04 12:46:17 PM PST 24 111201457 ps
T1293 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3280418856 Feb 04 12:46:14 PM PST 24 Feb 04 12:46:18 PM PST 24 114810556 ps
T1294 /workspace/coverage/cover_reg_top/45.uart_intr_test.1625524230 Feb 04 12:46:44 PM PST 24 Feb 04 12:46:50 PM PST 24 40092958 ps
T1295 /workspace/coverage/cover_reg_top/37.uart_intr_test.1287328673 Feb 04 12:46:33 PM PST 24 Feb 04 12:46:34 PM PST 24 43896887 ps
T1296 /workspace/coverage/cover_reg_top/8.uart_intr_test.2311152657 Feb 04 12:46:12 PM PST 24 Feb 04 12:46:15 PM PST 24 42269633 ps
T1297 /workspace/coverage/cover_reg_top/36.uart_intr_test.4133325354 Feb 04 12:46:32 PM PST 24 Feb 04 12:46:33 PM PST 24 15119571 ps

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4248533235
Short name T8
Test name
Test status
Simulation time 140227947 ps
CPU time 1.36 seconds
Started Feb 04 12:46:32 PM PST 24
Finished Feb 04 12:46:34 PM PST 24
Peak memory 199248 kb
Host smart-cc21bdea-c6d8-4116-a37a-5824b73e72d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248533235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4248533235
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2222142598
Short name T14
Test name
Test status
Simulation time 149048970133 ps
CPU time 928.98 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:44:02 PM PST 24
Peak memory 216344 kb
Host smart-2c8288c5-a09f-45b5-8fbf-c5f1376d36fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222142598 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2222142598
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3927326388
Short name T321
Test name
Test status
Simulation time 351473626572 ps
CPU time 946.8 seconds
Started Feb 04 12:29:40 PM PST 24
Finished Feb 04 12:45:39 PM PST 24
Peak memory 224712 kb
Host smart-14b7ded8-c83e-471a-beaa-215e277a3047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927326388 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3927326388
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.195708648
Short name T81
Test name
Test status
Simulation time 18221869 ps
CPU time 0.6 seconds
Started Feb 04 12:46:42 PM PST 24
Finished Feb 04 12:46:49 PM PST 24
Peak memory 194552 kb
Host smart-dcec2984-5820-4cce-8a11-a5116d3a6fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195708648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.195708648
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/default/31.uart_stress_all.1250593153
Short name T25
Test name
Test status
Simulation time 2162339009011 ps
CPU time 1319.25 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:52:04 PM PST 24
Peak memory 199816 kb
Host smart-627adc9b-2353-4b52-abff-fc7293da2bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250593153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1250593153
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.524844801
Short name T44
Test name
Test status
Simulation time 117988944 ps
CPU time 1.29 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 200080 kb
Host smart-93720a65-6415-4d11-be44-71eb9954013a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524844801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.524844801
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/default/45.uart_stress_all.231005944
Short name T241
Test name
Test status
Simulation time 163739093244 ps
CPU time 1721.55 seconds
Started Feb 04 12:30:34 PM PST 24
Finished Feb 04 12:59:19 PM PST 24
Peak memory 216040 kb
Host smart-a34eec38-81e9-4cfe-9572-bb510c1f8df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231005944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.231005944
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3230105483
Short name T65
Test name
Test status
Simulation time 516571591841 ps
CPU time 866.16 seconds
Started Feb 04 12:29:47 PM PST 24
Finished Feb 04 12:44:20 PM PST 24
Peak memory 227472 kb
Host smart-b6e79c25-0b0e-4b7f-a8e2-f63a892fcc66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230105483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3230105483
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1715089074
Short name T404
Test name
Test status
Simulation time 195196512262 ps
CPU time 658.34 seconds
Started Feb 04 12:31:10 PM PST 24
Finished Feb 04 12:42:10 PM PST 24
Peak memory 224824 kb
Host smart-de7b86f5-cbd0-4664-ad67-68ab30ed2307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715089074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1715089074
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.2120006056
Short name T421
Test name
Test status
Simulation time 761962444048 ps
CPU time 991.04 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:45:24 PM PST 24
Peak memory 216024 kb
Host smart-14fa343e-64de-4928-99a8-209ad447ff82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120006056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2120006056
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all.164585388
Short name T27
Test name
Test status
Simulation time 4276615006474 ps
CPU time 5618.38 seconds
Started Feb 04 12:30:07 PM PST 24
Finished Feb 04 02:03:52 PM PST 24
Peak memory 208260 kb
Host smart-68040d9e-0260-4706-b0b8-c3c5bc8bec80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164585388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.164585388
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3014100942
Short name T1
Test name
Test status
Simulation time 25843166 ps
CPU time 0.8 seconds
Started Feb 04 12:45:58 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 196448 kb
Host smart-58d1841c-b9de-4a4a-aafe-e460932f7773
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014100942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3014100942
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.711193395
Short name T24
Test name
Test status
Simulation time 37785725128 ps
CPU time 62.16 seconds
Started Feb 04 12:29:59 PM PST 24
Finished Feb 04 12:31:10 PM PST 24
Peak memory 199836 kb
Host smart-298553ce-c776-49ee-a492-29640b686c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711193395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.711193395
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.906370880
Short name T403
Test name
Test status
Simulation time 85427087363 ps
CPU time 841.33 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:44:01 PM PST 24
Peak memory 216456 kb
Host smart-db0372c2-8cca-4833-8fa7-877bb8d3807e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906370880 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.906370880
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.492760902
Short name T36
Test name
Test status
Simulation time 54401148 ps
CPU time 2.53 seconds
Started Feb 04 12:46:08 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 200124 kb
Host smart-883798f0-9051-4959-a41a-a525db6eef60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492760902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.492760902
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3127356279
Short name T178
Test name
Test status
Simulation time 186078554500 ps
CPU time 131.81 seconds
Started Feb 04 12:31:48 PM PST 24
Finished Feb 04 12:34:04 PM PST 24
Peak memory 199652 kb
Host smart-bafa5bb0-7f54-4fa7-82d1-36791ac39c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127356279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3127356279
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1391090576
Short name T89
Test name
Test status
Simulation time 1027319910 ps
CPU time 0.89 seconds
Started Feb 04 12:28:10 PM PST 24
Finished Feb 04 12:28:15 PM PST 24
Peak memory 217076 kb
Host smart-db636b42-8d9e-4284-8045-210c244783bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391090576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1391090576
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3603679559
Short name T66
Test name
Test status
Simulation time 244506413546 ps
CPU time 1017.73 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:48:07 PM PST 24
Peak memory 213804 kb
Host smart-685393b6-58b4-4ad1-bd69-e7b3a9275405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603679559 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3603679559
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3252893104
Short name T138
Test name
Test status
Simulation time 164335839338 ps
CPU time 62.06 seconds
Started Feb 04 12:31:33 PM PST 24
Finished Feb 04 12:32:39 PM PST 24
Peak memory 199788 kb
Host smart-bb92c489-51f6-48a0-9e14-c83b9353b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252893104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3252893104
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3386338936
Short name T96
Test name
Test status
Simulation time 13417232 ps
CPU time 0.54 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:29:18 PM PST 24
Peak memory 195204 kb
Host smart-be854d9a-709b-4fab-a7a0-411834dcc75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386338936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3386338936
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2894302217
Short name T150
Test name
Test status
Simulation time 582045331514 ps
CPU time 516.73 seconds
Started Feb 04 12:30:00 PM PST 24
Finished Feb 04 12:38:44 PM PST 24
Peak memory 216340 kb
Host smart-240f91ff-c5d1-46f8-b201-26e3843b15b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894302217 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2894302217
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.932749181
Short name T42
Test name
Test status
Simulation time 109908326 ps
CPU time 1.41 seconds
Started Feb 04 12:46:06 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 199248 kb
Host smart-61773264-9f27-4b43-9a93-9baba8df5b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932749181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.932749181
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3798619472
Short name T152
Test name
Test status
Simulation time 81642854016 ps
CPU time 15.07 seconds
Started Feb 04 12:31:46 PM PST 24
Finished Feb 04 12:32:03 PM PST 24
Peak memory 199832 kb
Host smart-bd2e2b0d-8d64-4b11-b6a4-46ac2d1fba87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798619472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3798619472
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1575724712
Short name T33
Test name
Test status
Simulation time 54481620333 ps
CPU time 578.95 seconds
Started Feb 04 12:28:41 PM PST 24
Finished Feb 04 12:38:27 PM PST 24
Peak memory 216544 kb
Host smart-d9df85d0-6dda-43d3-bd61-b52576ba1d7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575724712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1575724712
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3952665061
Short name T58
Test name
Test status
Simulation time 14627749 ps
CPU time 0.65 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:12 PM PST 24
Peak memory 195420 kb
Host smart-964c036f-e78e-43fe-bad8-16814a421dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952665061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3952665061
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1714334808
Short name T77
Test name
Test status
Simulation time 57667059 ps
CPU time 0.59 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:17 PM PST 24
Peak memory 195416 kb
Host smart-86e08ff5-7432-4a0c-af2b-e504a6491334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714334808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1714334808
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3389510837
Short name T4
Test name
Test status
Simulation time 24503689 ps
CPU time 0.59 seconds
Started Feb 04 12:46:39 PM PST 24
Finished Feb 04 12:46:43 PM PST 24
Peak memory 194388 kb
Host smart-0dc8ec61-1fbb-430d-97f5-d2f24ce10e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389510837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3389510837
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/default/32.uart_stress_all.3270754267
Short name T600
Test name
Test status
Simulation time 95457086083 ps
CPU time 277.92 seconds
Started Feb 04 12:29:43 PM PST 24
Finished Feb 04 12:34:31 PM PST 24
Peak memory 208288 kb
Host smart-59c1be34-7e5c-487a-af12-e281a7b9450e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270754267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3270754267
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3916066062
Short name T121
Test name
Test status
Simulation time 98129671202 ps
CPU time 36.05 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:32:03 PM PST 24
Peak memory 199748 kb
Host smart-dbe85b5e-cb5f-4084-ba1b-051db3b562b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916066062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3916066062
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.726284524
Short name T146
Test name
Test status
Simulation time 68336444612 ps
CPU time 33.51 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199824 kb
Host smart-74fe5fda-2b06-45fc-a175-ef948c32bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726284524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.726284524
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1346617132
Short name T129
Test name
Test status
Simulation time 77643688679 ps
CPU time 30.7 seconds
Started Feb 04 12:31:35 PM PST 24
Finished Feb 04 12:32:08 PM PST 24
Peak memory 199740 kb
Host smart-5a267c2b-7d9f-4e01-8939-f0329005b48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346617132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1346617132
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2959200757
Short name T71
Test name
Test status
Simulation time 472287286008 ps
CPU time 853.08 seconds
Started Feb 04 12:28:53 PM PST 24
Finished Feb 04 12:43:08 PM PST 24
Peak memory 224904 kb
Host smart-7f49e2a8-0d9b-4e8e-ac27-ff7eb584baa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959200757 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2959200757
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3584864023
Short name T340
Test name
Test status
Simulation time 445335860497 ps
CPU time 1301.97 seconds
Started Feb 04 12:29:31 PM PST 24
Finished Feb 04 12:51:18 PM PST 24
Peak memory 224764 kb
Host smart-d793b22c-de1e-4186-8d28-11d8256239c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584864023 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3584864023
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.292010505
Short name T328
Test name
Test status
Simulation time 113734862449 ps
CPU time 46.33 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:30:03 PM PST 24
Peak memory 199776 kb
Host smart-a90c16cc-2da9-4cdb-9da3-2c42a830589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292010505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.292010505
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.2995870140
Short name T169
Test name
Test status
Simulation time 319925138756 ps
CPU time 788.69 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:43:32 PM PST 24
Peak memory 215960 kb
Host smart-800620ab-879d-4864-a212-0f5582048fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995870140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2995870140
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1102115033
Short name T232
Test name
Test status
Simulation time 173914907163 ps
CPU time 49.9 seconds
Started Feb 04 12:30:54 PM PST 24
Finished Feb 04 12:31:48 PM PST 24
Peak memory 199860 kb
Host smart-766fdb7e-912c-40bb-b467-226ef8e84507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102115033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1102115033
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2184468375
Short name T316
Test name
Test status
Simulation time 48349373551 ps
CPU time 34.56 seconds
Started Feb 04 12:31:33 PM PST 24
Finished Feb 04 12:32:11 PM PST 24
Peak memory 199016 kb
Host smart-72753d1b-a51f-434a-96d8-de08419ec08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184468375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2184468375
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.3812053122
Short name T172
Test name
Test status
Simulation time 34197745803 ps
CPU time 42.13 seconds
Started Feb 04 12:28:56 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 199864 kb
Host smart-4949259d-4d14-4e42-97e8-249b1bd40962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812053122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3812053122
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3225247469
Short name T188
Test name
Test status
Simulation time 83021938699 ps
CPU time 53.62 seconds
Started Feb 04 12:31:52 PM PST 24
Finished Feb 04 12:32:49 PM PST 24
Peak memory 199708 kb
Host smart-e4840522-e89a-44d6-b692-2529cab96c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225247469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3225247469
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.4178325130
Short name T367
Test name
Test status
Simulation time 2547554513441 ps
CPU time 955.95 seconds
Started Feb 04 12:29:45 PM PST 24
Finished Feb 04 12:45:49 PM PST 24
Peak memory 199732 kb
Host smart-04a200ff-8237-425a-a78b-ba5c7a841235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178325130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.4178325130
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2850788896
Short name T132
Test name
Test status
Simulation time 17166596303 ps
CPU time 62.45 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:32:36 PM PST 24
Peak memory 199908 kb
Host smart-9d380ec5-618d-402c-9750-5e99faa09977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850788896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2850788896
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.702627195
Short name T135
Test name
Test status
Simulation time 152155904189 ps
CPU time 28.2 seconds
Started Feb 04 12:31:32 PM PST 24
Finished Feb 04 12:32:04 PM PST 24
Peak memory 199472 kb
Host smart-92328cb6-412e-4a75-85b8-f95431952ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702627195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.702627195
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2208109960
Short name T130
Test name
Test status
Simulation time 16627029002 ps
CPU time 29.02 seconds
Started Feb 04 12:31:24 PM PST 24
Finished Feb 04 12:31:55 PM PST 24
Peak memory 199848 kb
Host smart-1b5fafb5-e4ac-4974-9f33-1aec21bf6ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208109960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2208109960
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.381845065
Short name T194
Test name
Test status
Simulation time 20116381449 ps
CPU time 34.13 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:29:33 PM PST 24
Peak memory 199972 kb
Host smart-87d3f697-deb5-4c44-9cd9-f3597cba7401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381845065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.381845065
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2502285575
Short name T207
Test name
Test status
Simulation time 93650898735 ps
CPU time 19.76 seconds
Started Feb 04 12:31:45 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199788 kb
Host smart-6ea9a643-7c3d-4b5e-a467-acd7c1f40f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502285575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2502285575
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2668682076
Short name T11
Test name
Test status
Simulation time 133905760361 ps
CPU time 49.07 seconds
Started Feb 04 12:31:44 PM PST 24
Finished Feb 04 12:32:34 PM PST 24
Peak memory 199396 kb
Host smart-19d3abec-286e-4d09-a8f3-710b2a1bab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668682076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2668682076
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1919386769
Short name T239
Test name
Test status
Simulation time 41451770254 ps
CPU time 39.27 seconds
Started Feb 04 12:31:54 PM PST 24
Finished Feb 04 12:32:36 PM PST 24
Peak memory 199720 kb
Host smart-db87390c-f54d-4c4a-a243-9fc3ebe6029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919386769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1919386769
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.657170450
Short name T293
Test name
Test status
Simulation time 375038484428 ps
CPU time 127.07 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:32:00 PM PST 24
Peak memory 199808 kb
Host smart-ddcc4c5f-09c4-4e2e-876a-8eafec26644f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657170450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.657170450
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1232687883
Short name T330
Test name
Test status
Simulation time 80441621407 ps
CPU time 184.56 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:34:13 PM PST 24
Peak memory 215620 kb
Host smart-0bd94fa8-4059-4fd1-b164-be5fd41127c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232687883 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1232687883
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.929504182
Short name T457
Test name
Test status
Simulation time 12534485 ps
CPU time 0.54 seconds
Started Feb 04 12:46:32 PM PST 24
Finished Feb 04 12:46:33 PM PST 24
Peak memory 194312 kb
Host smart-99975d27-c75b-4b62-afb5-6223f5fcd574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929504182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.929504182
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3734313248
Short name T384
Test name
Test status
Simulation time 23865312120 ps
CPU time 36.13 seconds
Started Feb 04 12:31:35 PM PST 24
Finished Feb 04 12:32:13 PM PST 24
Peak memory 199524 kb
Host smart-eddf992b-d7fa-4036-bcd0-798b73b8352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734313248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3734313248
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2269295548
Short name T382
Test name
Test status
Simulation time 50316504950 ps
CPU time 6.67 seconds
Started Feb 04 12:31:30 PM PST 24
Finished Feb 04 12:31:42 PM PST 24
Peak memory 198572 kb
Host smart-bda0de10-52e5-4438-b4e1-fbd7df31e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269295548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2269295548
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1483695096
Short name T246
Test name
Test status
Simulation time 44937543863 ps
CPU time 45.75 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:30:03 PM PST 24
Peak memory 199612 kb
Host smart-a564d37a-519c-41b2-a142-33a72e070901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483695096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1483695096
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.152065440
Short name T371
Test name
Test status
Simulation time 328013028541 ps
CPU time 293.58 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:34:53 PM PST 24
Peak memory 216168 kb
Host smart-4d89cfa5-db06-408e-8233-c7186b1f5636
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152065440 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.152065440
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3937211116
Short name T206
Test name
Test status
Simulation time 139034267891 ps
CPU time 27.11 seconds
Started Feb 04 12:31:49 PM PST 24
Finished Feb 04 12:32:19 PM PST 24
Peak memory 199728 kb
Host smart-167479d0-65ba-4b05-9417-7af988544cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937211116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3937211116
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.864388819
Short name T361
Test name
Test status
Simulation time 71286786823 ps
CPU time 60.08 seconds
Started Feb 04 12:31:24 PM PST 24
Finished Feb 04 12:32:25 PM PST 24
Peak memory 199792 kb
Host smart-031b8b10-940d-494b-b2da-bfc489d723ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864388819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.864388819
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.621089188
Short name T184
Test name
Test status
Simulation time 127583915255 ps
CPU time 26.97 seconds
Started Feb 04 12:31:25 PM PST 24
Finished Feb 04 12:31:53 PM PST 24
Peak memory 199804 kb
Host smart-15038467-abdc-4cb4-8938-1811a4a6939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621089188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.621089188
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1930434791
Short name T323
Test name
Test status
Simulation time 166564781929 ps
CPU time 128.72 seconds
Started Feb 04 12:31:25 PM PST 24
Finished Feb 04 12:33:35 PM PST 24
Peak memory 199680 kb
Host smart-dc6094bb-79b6-4c08-b067-8686bf31c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930434791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1930434791
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3534555319
Short name T1068
Test name
Test status
Simulation time 24705571593 ps
CPU time 22.18 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:31:50 PM PST 24
Peak memory 199812 kb
Host smart-ca6d2620-f488-4390-b30f-6f185cceabdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534555319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3534555319
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.519902145
Short name T120
Test name
Test status
Simulation time 9276402941 ps
CPU time 13.99 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:31:50 PM PST 24
Peak memory 199460 kb
Host smart-63769ecb-616e-4461-a50e-6418d1eaf87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519902145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.519902145
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.151011604
Short name T1120
Test name
Test status
Simulation time 389940304071 ps
CPU time 458.36 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:36:55 PM PST 24
Peak memory 199780 kb
Host smart-e78c84e9-8cb4-4944-bd23-5f2b271c226b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151011604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.151011604
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3722700292
Short name T392
Test name
Test status
Simulation time 185090536361 ps
CPU time 619.36 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:39:37 PM PST 24
Peak memory 224804 kb
Host smart-f54d9e0e-da55-4917-9bd4-9d02348c41a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722700292 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3722700292
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4132274243
Short name T312
Test name
Test status
Simulation time 14956805416 ps
CPU time 23.12 seconds
Started Feb 04 12:31:39 PM PST 24
Finished Feb 04 12:32:04 PM PST 24
Peak memory 199716 kb
Host smart-bd53e66a-43de-4143-88c8-e998ff09eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132274243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4132274243
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.731775446
Short name T344
Test name
Test status
Simulation time 71686087963 ps
CPU time 32.9 seconds
Started Feb 04 12:31:52 PM PST 24
Finished Feb 04 12:32:29 PM PST 24
Peak memory 199448 kb
Host smart-855bcbf8-5348-4338-a3a1-6a545dfe2ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731775446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.731775446
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.439378106
Short name T385
Test name
Test status
Simulation time 91898045378 ps
CPU time 11.83 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:29:33 PM PST 24
Peak memory 199764 kb
Host smart-f5114321-8317-4736-86fd-5014682ddb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439378106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.439378106
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2086378020
Short name T220
Test name
Test status
Simulation time 79573656378 ps
CPU time 28.45 seconds
Started Feb 04 12:32:19 PM PST 24
Finished Feb 04 12:32:50 PM PST 24
Peak memory 199788 kb
Host smart-e2982c29-f087-45e0-9103-68b27c798eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086378020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2086378020
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2988937983
Short name T329
Test name
Test status
Simulation time 127433762980 ps
CPU time 60.22 seconds
Started Feb 04 12:32:19 PM PST 24
Finished Feb 04 12:33:21 PM PST 24
Peak memory 199688 kb
Host smart-e210fb41-c425-49fc-8c33-41efa5b122c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988937983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2988937983
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.451026033
Short name T215
Test name
Test status
Simulation time 12756029149 ps
CPU time 17.75 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:32:38 PM PST 24
Peak memory 199684 kb
Host smart-c38ecddc-f451-42ff-a71a-e7eb7db75e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451026033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.451026033
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.4080164233
Short name T197
Test name
Test status
Simulation time 347652947392 ps
CPU time 39.15 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:33:00 PM PST 24
Peak memory 199744 kb
Host smart-7cd4aaa0-2959-4568-910f-b3728f59bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080164233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.4080164233
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2274626636
Short name T224
Test name
Test status
Simulation time 125553501970 ps
CPU time 67.78 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:33:29 PM PST 24
Peak memory 199640 kb
Host smart-41e5eccd-9b68-42f6-850b-548ce9b34141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274626636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2274626636
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all.2385150962
Short name T28
Test name
Test status
Simulation time 187499454022 ps
CPU time 189.72 seconds
Started Feb 04 12:29:49 PM PST 24
Finished Feb 04 12:33:05 PM PST 24
Peak memory 199916 kb
Host smart-d34a10db-d5a4-4513-b9f5-075b2d0c6788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385150962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2385150962
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all.1335925487
Short name T394
Test name
Test status
Simulation time 76550363418 ps
CPU time 36.79 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:39 PM PST 24
Peak memory 199768 kb
Host smart-3f79fa8c-6d7e-4cec-b1cc-1035ae5ff01c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335925487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1335925487
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1131718183
Short name T230
Test name
Test status
Simulation time 215700047505 ps
CPU time 643.14 seconds
Started Feb 04 12:30:45 PM PST 24
Finished Feb 04 12:41:32 PM PST 24
Peak memory 228512 kb
Host smart-018d9d75-ae25-4564-b4c4-615fbca8e661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131718183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1131718183
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.729392825
Short name T17
Test name
Test status
Simulation time 81927539672 ps
CPU time 38.34 seconds
Started Feb 04 12:30:59 PM PST 24
Finished Feb 04 12:31:45 PM PST 24
Peak memory 199340 kb
Host smart-8b79f26e-28fd-4148-b1b6-ff7294b2ffcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729392825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.729392825
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1373088571
Short name T341
Test name
Test status
Simulation time 61012458552 ps
CPU time 28.47 seconds
Started Feb 04 12:28:34 PM PST 24
Finished Feb 04 12:29:09 PM PST 24
Peak memory 199516 kb
Host smart-6dbc11d1-dd01-43fa-b60f-a0596f2eb9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373088571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1373088571
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2733242220
Short name T47
Test name
Test status
Simulation time 172418939 ps
CPU time 1.28 seconds
Started Feb 04 12:45:52 PM PST 24
Finished Feb 04 12:45:56 PM PST 24
Peak memory 199112 kb
Host smart-cc439950-c84b-4207-bcff-5d7b489e4b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733242220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2733242220
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.435761601
Short name T235
Test name
Test status
Simulation time 357790990397 ps
CPU time 1050.47 seconds
Started Feb 04 12:28:10 PM PST 24
Finished Feb 04 12:45:44 PM PST 24
Peak memory 216220 kb
Host smart-5d1b4b31-ed78-437d-9090-58de4f6e7828
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435761601 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.435761601
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2868337016
Short name T1165
Test name
Test status
Simulation time 96807161320 ps
CPU time 69.27 seconds
Started Feb 04 12:28:05 PM PST 24
Finished Feb 04 12:29:16 PM PST 24
Peak memory 199748 kb
Host smart-f2e34884-e308-4b50-8b88-0287b9bc217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868337016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2868337016
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3085833354
Short name T395
Test name
Test status
Simulation time 386287630413 ps
CPU time 94.01 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:30:16 PM PST 24
Peak memory 199684 kb
Host smart-424fee0b-0eeb-4f36-bc60-846d79e4fe9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085833354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3085833354
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.936858263
Short name T251
Test name
Test status
Simulation time 52127993069 ps
CPU time 19.82 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:31:55 PM PST 24
Peak memory 199852 kb
Host smart-c6104167-f92f-4f75-8b14-22d9b5046a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936858263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.936858263
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.839854881
Short name T268
Test name
Test status
Simulation time 11617442001 ps
CPU time 20.15 seconds
Started Feb 04 12:31:24 PM PST 24
Finished Feb 04 12:31:46 PM PST 24
Peak memory 199800 kb
Host smart-23e81868-d063-4b18-9f1c-ff82087955c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839854881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.839854881
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1126307181
Short name T351
Test name
Test status
Simulation time 37171019721 ps
CPU time 49.45 seconds
Started Feb 04 12:31:23 PM PST 24
Finished Feb 04 12:32:14 PM PST 24
Peak memory 199320 kb
Host smart-45c48d06-580f-4238-bab4-af7dab246545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126307181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1126307181
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2799659894
Short name T311
Test name
Test status
Simulation time 33699362807 ps
CPU time 20.93 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:31:57 PM PST 24
Peak memory 199532 kb
Host smart-8c669be5-f64d-4eb0-b360-04a2edc0d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799659894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2799659894
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3434723013
Short name T277
Test name
Test status
Simulation time 31588895817 ps
CPU time 50.51 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:32:26 PM PST 24
Peak memory 199748 kb
Host smart-89c51d40-8894-45cb-98de-cb2b30fafc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434723013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3434723013
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.4137145911
Short name T339
Test name
Test status
Simulation time 32444821051 ps
CPU time 14.53 seconds
Started Feb 04 12:31:35 PM PST 24
Finished Feb 04 12:31:52 PM PST 24
Peak memory 199748 kb
Host smart-f095272e-09a1-45ca-b1db-1e752081d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137145911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.4137145911
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4102554321
Short name T228
Test name
Test status
Simulation time 323641508149 ps
CPU time 286.26 seconds
Started Feb 04 12:31:35 PM PST 24
Finished Feb 04 12:36:24 PM PST 24
Peak memory 199792 kb
Host smart-9ab0a2da-ced4-4b00-9bec-2f77fe1a6391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102554321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4102554321
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1166186596
Short name T336
Test name
Test status
Simulation time 28523030478 ps
CPU time 43.68 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:32:19 PM PST 24
Peak memory 199532 kb
Host smart-335c32ae-70ff-47a8-8523-7c267c8a8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166186596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1166186596
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2097040280
Short name T359
Test name
Test status
Simulation time 27411992332 ps
CPU time 20.19 seconds
Started Feb 04 12:31:43 PM PST 24
Finished Feb 04 12:32:04 PM PST 24
Peak memory 199888 kb
Host smart-195c31a0-eda3-450d-962f-e4a6b432f0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097040280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2097040280
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1303478814
Short name T302
Test name
Test status
Simulation time 64607152974 ps
CPU time 25.45 seconds
Started Feb 04 12:31:39 PM PST 24
Finished Feb 04 12:32:06 PM PST 24
Peak memory 199212 kb
Host smart-eef35aa6-b2da-443d-a3fd-ca2a2d366d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303478814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1303478814
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_full.42662800
Short name T301
Test name
Test status
Simulation time 28881102230 ps
CPU time 12.83 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:29:30 PM PST 24
Peak memory 199652 kb
Host smart-143d9121-7d0a-496c-8601-ae7df32a5e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42662800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.42662800
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.961984574
Short name T282
Test name
Test status
Simulation time 49455848033 ps
CPU time 15.82 seconds
Started Feb 04 12:31:39 PM PST 24
Finished Feb 04 12:31:56 PM PST 24
Peak memory 199576 kb
Host smart-d3426bd9-f79f-4be5-95ff-b83be7356687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961984574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.961984574
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3337421543
Short name T369
Test name
Test status
Simulation time 37410180956 ps
CPU time 53.63 seconds
Started Feb 04 12:31:39 PM PST 24
Finished Feb 04 12:32:34 PM PST 24
Peak memory 199240 kb
Host smart-2d014af7-cafb-4c4c-869d-985bf7fcb072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337421543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3337421543
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3193558292
Short name T1127
Test name
Test status
Simulation time 46034322070 ps
CPU time 123.31 seconds
Started Feb 04 12:31:38 PM PST 24
Finished Feb 04 12:33:43 PM PST 24
Peak memory 199804 kb
Host smart-6f1c72f7-2f34-4afd-aa09-d64936df0180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193558292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3193558292
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.692544224
Short name T287
Test name
Test status
Simulation time 164440422239 ps
CPU time 22.61 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:32:04 PM PST 24
Peak memory 199428 kb
Host smart-c098eb70-6309-4ffe-8d7a-6b5df73e0281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692544224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.692544224
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3395186382
Short name T273
Test name
Test status
Simulation time 69678630916 ps
CPU time 36.72 seconds
Started Feb 04 12:31:40 PM PST 24
Finished Feb 04 12:32:18 PM PST 24
Peak memory 199580 kb
Host smart-9cf5ea7f-9472-4be0-894a-47495670511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395186382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3395186382
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.613378156
Short name T166
Test name
Test status
Simulation time 181610616514 ps
CPU time 121.93 seconds
Started Feb 04 12:31:51 PM PST 24
Finished Feb 04 12:33:57 PM PST 24
Peak memory 199692 kb
Host smart-5e6744e8-1c72-4645-9fa1-c79e6f0adda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613378156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.613378156
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.659878478
Short name T148
Test name
Test status
Simulation time 115587727724 ps
CPU time 173.85 seconds
Started Feb 04 12:31:54 PM PST 24
Finished Feb 04 12:34:51 PM PST 24
Peak memory 199744 kb
Host smart-481f48b3-9a39-4c0c-9982-8f68e9d55450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659878478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.659878478
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_perf.2163790631
Short name T299
Test name
Test status
Simulation time 9995404115 ps
CPU time 589.99 seconds
Started Feb 04 12:29:24 PM PST 24
Finished Feb 04 12:39:17 PM PST 24
Peak memory 199732 kb
Host smart-fc68a6a3-4f8f-42ed-aef6-fb5aa9d02e19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163790631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2163790631
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.454744140
Short name T389
Test name
Test status
Simulation time 34597426946 ps
CPU time 52 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:30:51 PM PST 24
Peak memory 199748 kb
Host smart-4c07dc76-d896-4304-96a5-2e0cf1326185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454744140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.454744140
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3868254631
Short name T248
Test name
Test status
Simulation time 129931701784 ps
CPU time 52.24 seconds
Started Feb 04 12:31:45 PM PST 24
Finished Feb 04 12:32:39 PM PST 24
Peak memory 199788 kb
Host smart-9d58c997-b9e2-449b-b6ce-7bea7b88bd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868254631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3868254631
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.4198257615
Short name T260
Test name
Test status
Simulation time 35808985856 ps
CPU time 56.17 seconds
Started Feb 04 12:32:36 PM PST 24
Finished Feb 04 12:33:34 PM PST 24
Peak memory 199752 kb
Host smart-3c766b5b-f888-4967-be6e-7c311ea5a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198257615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.4198257615
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2358514577
Short name T343
Test name
Test status
Simulation time 118738974935 ps
CPU time 202.25 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:33:22 PM PST 24
Peak memory 199896 kb
Host smart-3bbc1216-6e5d-4785-8783-e7e2052ab1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358514577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2358514577
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_full.867627888
Short name T300
Test name
Test status
Simulation time 7644235525 ps
CPU time 11.96 seconds
Started Feb 04 12:30:30 PM PST 24
Finished Feb 04 12:30:43 PM PST 24
Peak memory 197720 kb
Host smart-816b112c-02dd-4724-8d3b-edb8bbb899be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867627888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.867627888
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1900586641
Short name T377
Test name
Test status
Simulation time 51939765095 ps
CPU time 11.82 seconds
Started Feb 04 12:30:35 PM PST 24
Finished Feb 04 12:30:50 PM PST 24
Peak memory 199724 kb
Host smart-88adf8cb-d27a-4ca6-af09-cc905c65d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900586641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1900586641
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3548589187
Short name T298
Test name
Test status
Simulation time 172849084077 ps
CPU time 224.69 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:34:31 PM PST 24
Peak memory 199848 kb
Host smart-35f6e42c-364b-43b7-816b-8a6df732b361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548589187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3548589187
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.502007080
Short name T210
Test name
Test status
Simulation time 30329410302 ps
CPU time 76.86 seconds
Started Feb 04 12:28:28 PM PST 24
Finished Feb 04 12:29:52 PM PST 24
Peak memory 199700 kb
Host smart-e4b5d73b-4383-4c99-af33-72b92190190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502007080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.502007080
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.711658328
Short name T357
Test name
Test status
Simulation time 104213204536 ps
CPU time 14.07 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:31:12 PM PST 24
Peak memory 199644 kb
Host smart-ba3892d8-f69e-419f-9c50-d67aa58be3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711658328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.711658328
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2235816913
Short name T136
Test name
Test status
Simulation time 422968280622 ps
CPU time 255.42 seconds
Started Feb 04 12:30:49 PM PST 24
Finished Feb 04 12:35:06 PM PST 24
Peak memory 216092 kb
Host smart-902be2cd-23f4-40b7-9f7c-3da868c052f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235816913 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2235816913
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1191965627
Short name T337
Test name
Test status
Simulation time 106007951906 ps
CPU time 151.09 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:33:29 PM PST 24
Peak memory 199784 kb
Host smart-92562d79-a1d1-4440-b4b8-85f567fc0432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191965627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1191965627
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1954550300
Short name T378
Test name
Test status
Simulation time 180709012009 ps
CPU time 63.75 seconds
Started Feb 04 12:31:05 PM PST 24
Finished Feb 04 12:32:11 PM PST 24
Peak memory 199860 kb
Host smart-5c261da4-d1d3-4de7-84d9-2483a423bf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954550300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1954550300
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.242773495
Short name T390
Test name
Test status
Simulation time 59158056050 ps
CPU time 43.5 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:29:26 PM PST 24
Peak memory 199660 kb
Host smart-539bdd24-da31-47d1-9f76-b7050f12838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242773495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.242773495
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2585384389
Short name T291
Test name
Test status
Simulation time 140992296262 ps
CPU time 780.35 seconds
Started Feb 04 12:31:14 PM PST 24
Finished Feb 04 12:44:15 PM PST 24
Peak memory 216288 kb
Host smart-88125b9f-f9aa-4eff-88ac-7ec880b89786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585384389 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2585384389
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3950943069
Short name T84
Test name
Test status
Simulation time 95934469 ps
CPU time 1.57 seconds
Started Feb 04 12:45:56 PM PST 24
Finished Feb 04 12:46:05 PM PST 24
Peak memory 197808 kb
Host smart-0a90f062-be65-4aa0-9665-69a97913a899
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950943069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3950943069
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2670584250
Short name T1235
Test name
Test status
Simulation time 63510804 ps
CPU time 0.64 seconds
Started Feb 04 12:45:51 PM PST 24
Finished Feb 04 12:45:55 PM PST 24
Peak memory 195420 kb
Host smart-ca8a2e5c-6436-484e-a1db-eeb5e2750027
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670584250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2670584250
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1097047584
Short name T454
Test name
Test status
Simulation time 26493153 ps
CPU time 1.24 seconds
Started Feb 04 12:46:08 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 200076 kb
Host smart-6ba06947-31c2-4917-9010-0f718e0507da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097047584 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1097047584
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.425250522
Short name T1287
Test name
Test status
Simulation time 13914001 ps
CPU time 0.65 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 195396 kb
Host smart-47abafc5-629d-4aef-84cc-de11913c3d76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425250522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.425250522
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3886994526
Short name T6
Test name
Test status
Simulation time 17910522 ps
CPU time 0.56 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 194368 kb
Host smart-1ac44070-1ed1-42f2-91da-ccb4aac91a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886994526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3886994526
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3786152596
Short name T464
Test name
Test status
Simulation time 22129544 ps
CPU time 0.74 seconds
Started Feb 04 12:45:59 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 196984 kb
Host smart-314b0d86-f6cd-48fc-aefe-8a067d7778d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786152596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3786152596
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1625173968
Short name T63
Test name
Test status
Simulation time 53910931 ps
CPU time 0.78 seconds
Started Feb 04 12:46:03 PM PST 24
Finished Feb 04 12:46:09 PM PST 24
Peak memory 195992 kb
Host smart-2f37aabd-473e-447f-904b-e6aed3ef3d21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625173968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1625173968
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2941681176
Short name T1242
Test name
Test status
Simulation time 239262494 ps
CPU time 2.27 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 197612 kb
Host smart-562a661e-f389-4a16-a6c6-d61ccb93538f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941681176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2941681176
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2935593162
Short name T40
Test name
Test status
Simulation time 141822948 ps
CPU time 0.63 seconds
Started Feb 04 12:46:03 PM PST 24
Finished Feb 04 12:46:09 PM PST 24
Peak memory 195316 kb
Host smart-7246aa61-7c04-419f-b3e5-e73f1d9d9b4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935593162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2935593162
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2453257481
Short name T1279
Test name
Test status
Simulation time 102164288 ps
CPU time 1.48 seconds
Started Feb 04 12:46:02 PM PST 24
Finished Feb 04 12:46:08 PM PST 24
Peak memory 200096 kb
Host smart-84e0bb7c-733f-4a1b-a6a8-733ec20df31e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453257481 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2453257481
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.4002268057
Short name T82
Test name
Test status
Simulation time 13708671 ps
CPU time 0.56 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 195388 kb
Host smart-2e659c9b-2ecb-4d1d-a3d2-e5277fa41fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002268057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.4002268057
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1675983188
Short name T1250
Test name
Test status
Simulation time 28608121 ps
CPU time 0.61 seconds
Started Feb 04 12:46:02 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 194300 kb
Host smart-addc523a-e77a-4428-9313-1fb52fcb0ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675983188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1675983188
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1463307402
Short name T61
Test name
Test status
Simulation time 272985784 ps
CPU time 0.72 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 196796 kb
Host smart-96be4f64-133f-4765-a35b-4d1cc91b09bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463307402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1463307402
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3104319891
Short name T48
Test name
Test status
Simulation time 273839184 ps
CPU time 2.06 seconds
Started Feb 04 12:45:59 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 200120 kb
Host smart-c31b9332-3d9b-4b9d-b7f8-4680cbd0f5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104319891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3104319891
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.802641624
Short name T396
Test name
Test status
Simulation time 603352221 ps
CPU time 0.93 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 198568 kb
Host smart-0c73eafd-ff94-4b1a-a6e3-63dcad9bbcca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802641624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.802641624
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.38201592
Short name T108
Test name
Test status
Simulation time 65093402 ps
CPU time 0.77 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 199128 kb
Host smart-b678392a-2891-4ef0-ba07-5424c2f5dae3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38201592 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.38201592
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1458118654
Short name T1249
Test name
Test status
Simulation time 35782642 ps
CPU time 0.56 seconds
Started Feb 04 12:46:03 PM PST 24
Finished Feb 04 12:46:09 PM PST 24
Peak memory 194304 kb
Host smart-719303bc-1865-44e7-814d-b4f78f2c9af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458118654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1458118654
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1449639742
Short name T479
Test name
Test status
Simulation time 22572460 ps
CPU time 0.7 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 195580 kb
Host smart-070c8113-a533-4dc0-94af-3fabfdd70649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449639742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1449639742
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3672831913
Short name T53
Test name
Test status
Simulation time 65215589 ps
CPU time 1.31 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:17 PM PST 24
Peak memory 200164 kb
Host smart-81a4ce6a-ea32-4739-9a21-1559c6569600
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672831913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3672831913
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3232266877
Short name T468
Test name
Test status
Simulation time 90942468 ps
CPU time 0.95 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 199088 kb
Host smart-780507f9-6401-41bb-bc54-cdc076c0c7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232266877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3232266877
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3400633603
Short name T474
Test name
Test status
Simulation time 27213468 ps
CPU time 1.25 seconds
Started Feb 04 12:46:04 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 200144 kb
Host smart-bca5ab72-3a4e-42f6-9f57-686c917252cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400633603 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3400633603
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2725670807
Short name T59
Test name
Test status
Simulation time 12920866 ps
CPU time 0.6 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 195340 kb
Host smart-416be277-a357-4cb8-8519-56bfff3d645c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725670807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2725670807
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1942385772
Short name T1237
Test name
Test status
Simulation time 53876560 ps
CPU time 0.67 seconds
Started Feb 04 12:46:15 PM PST 24
Finished Feb 04 12:46:17 PM PST 24
Peak memory 194380 kb
Host smart-120d1f79-5084-49e3-9e8b-acac50a98c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942385772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1942385772
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.723518067
Short name T76
Test name
Test status
Simulation time 25522717 ps
CPU time 0.76 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 197016 kb
Host smart-6f7c1f41-78b0-443a-8c30-d0aa6b9bbad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723518067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.723518067
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.926651741
Short name T1281
Test name
Test status
Simulation time 57829416 ps
CPU time 1.25 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 200124 kb
Host smart-ffc59975-7574-4643-9e6c-f6232c840f98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926651741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.926651741
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2307514142
Short name T478
Test name
Test status
Simulation time 424916793 ps
CPU time 1.29 seconds
Started Feb 04 12:46:08 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 199336 kb
Host smart-2631e7d8-90f6-4139-b5f2-14ef02d7d025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307514142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2307514142
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1842057846
Short name T1251
Test name
Test status
Simulation time 26683602 ps
CPU time 0.77 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 199344 kb
Host smart-3af552a3-e7ab-4000-aed1-dd1ff55d1490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842057846 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1842057846
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2050842935
Short name T55
Test name
Test status
Simulation time 14364935 ps
CPU time 0.59 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:15 PM PST 24
Peak memory 195456 kb
Host smart-e7cb210d-8d29-4538-bac6-47d9192788af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050842935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2050842935
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.211139599
Short name T1258
Test name
Test status
Simulation time 65679514 ps
CPU time 0.61 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:15 PM PST 24
Peak memory 194376 kb
Host smart-5d519332-9d71-4772-b9e2-230780280e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211139599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.211139599
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1220197561
Short name T452
Test name
Test status
Simulation time 68903985 ps
CPU time 0.7 seconds
Started Feb 04 12:46:07 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 195920 kb
Host smart-3eaddd71-b33a-4592-a13d-1978fb2340d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220197561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1220197561
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3970537991
Short name T1238
Test name
Test status
Simulation time 51692149 ps
CPU time 1.28 seconds
Started Feb 04 12:46:21 PM PST 24
Finished Feb 04 12:46:24 PM PST 24
Peak memory 199904 kb
Host smart-52b74f8f-be17-4866-9d7b-0b074807ad00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970537991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3970537991
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3414138650
Short name T51
Test name
Test status
Simulation time 186160612 ps
CPU time 0.97 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:15 PM PST 24
Peak memory 198964 kb
Host smart-3a5310fb-b45e-4047-b726-6c545c43b6cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414138650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3414138650
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1719177806
Short name T1260
Test name
Test status
Simulation time 41719054 ps
CPU time 0.81 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 199880 kb
Host smart-f5e35d61-bd93-467d-b064-8aaef0808247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719177806 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1719177806
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3480425000
Short name T1234
Test name
Test status
Simulation time 19098888 ps
CPU time 0.58 seconds
Started Feb 04 12:46:17 PM PST 24
Finished Feb 04 12:46:19 PM PST 24
Peak memory 195372 kb
Host smart-c4e65e45-d2d7-4996-af0c-1c99bda74905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480425000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3480425000
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.601592728
Short name T397
Test name
Test status
Simulation time 11801101 ps
CPU time 0.61 seconds
Started Feb 04 12:46:17 PM PST 24
Finished Feb 04 12:46:20 PM PST 24
Peak memory 194376 kb
Host smart-3d619407-26e3-4170-a1cb-43c0aa7402df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601592728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.601592728
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2064875295
Short name T470
Test name
Test status
Simulation time 13431125 ps
CPU time 0.68 seconds
Started Feb 04 12:46:18 PM PST 24
Finished Feb 04 12:46:21 PM PST 24
Peak memory 194888 kb
Host smart-f33e2249-d6a3-4b01-b913-c77153c62d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064875295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2064875295
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.135433046
Short name T1292
Test name
Test status
Simulation time 111201457 ps
CPU time 1.28 seconds
Started Feb 04 12:46:13 PM PST 24
Finished Feb 04 12:46:17 PM PST 24
Peak memory 200080 kb
Host smart-d45b465a-d016-4725-8868-55f29a3612c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135433046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.135433046
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3357361198
Short name T475
Test name
Test status
Simulation time 190159765 ps
CPU time 0.97 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 199044 kb
Host smart-7ce08ddd-f5e4-4ae9-9334-b1ec2bb171af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357361198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3357361198
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.961426107
Short name T400
Test name
Test status
Simulation time 25691396 ps
CPU time 0.81 seconds
Started Feb 04 12:46:18 PM PST 24
Finished Feb 04 12:46:21 PM PST 24
Peak memory 199916 kb
Host smart-cfdde365-3adb-4695-b79c-a9419b634548
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961426107 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.961426107
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2083119707
Short name T70
Test name
Test status
Simulation time 55391177 ps
CPU time 0.63 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 195608 kb
Host smart-da8bbfbd-dbbf-466c-bfeb-09bd0925031d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083119707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2083119707
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1991657948
Short name T460
Test name
Test status
Simulation time 140762931 ps
CPU time 0.63 seconds
Started Feb 04 12:46:09 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 194400 kb
Host smart-a3418a88-6e84-442f-af5c-59a6be5c3710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991657948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1991657948
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1131819506
Short name T54
Test name
Test status
Simulation time 16010452 ps
CPU time 0.72 seconds
Started Feb 04 12:46:04 PM PST 24
Finished Feb 04 12:46:10 PM PST 24
Peak memory 196860 kb
Host smart-c48d1fcb-9c7f-4b33-887e-cfefc136bc8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131819506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1131819506
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3936066299
Short name T1256
Test name
Test status
Simulation time 94862304 ps
CPU time 0.87 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 198772 kb
Host smart-34e7fa81-ddd5-498c-bc36-81a3158d221b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936066299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3936066299
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2262280039
Short name T399
Test name
Test status
Simulation time 25113137 ps
CPU time 0.8 seconds
Started Feb 04 12:46:06 PM PST 24
Finished Feb 04 12:46:10 PM PST 24
Peak memory 198504 kb
Host smart-0714e0c9-6648-4fca-a0f5-6c3a0ac0c6bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262280039 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2262280039
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.342101162
Short name T1280
Test name
Test status
Simulation time 29741327 ps
CPU time 0.57 seconds
Started Feb 04 12:46:09 PM PST 24
Finished Feb 04 12:46:12 PM PST 24
Peak memory 194396 kb
Host smart-f06a006c-20c1-42db-a031-02a76a5f263d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342101162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.342101162
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3450794090
Short name T456
Test name
Test status
Simulation time 59736743 ps
CPU time 0.72 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 196876 kb
Host smart-9a5b0144-8a95-4b79-a214-fbd7439bb8ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450794090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3450794090
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2977176887
Short name T469
Test name
Test status
Simulation time 227923904 ps
CPU time 1.29 seconds
Started Feb 04 12:46:21 PM PST 24
Finished Feb 04 12:46:24 PM PST 24
Peak memory 200128 kb
Host smart-288c10dd-3070-49a5-8952-807e6a21ec5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977176887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2977176887
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2349222606
Short name T93
Test name
Test status
Simulation time 45491856 ps
CPU time 0.98 seconds
Started Feb 04 12:46:05 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 198912 kb
Host smart-6b46e9ea-2bfe-42f6-bace-0538c71f2a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349222606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2349222606
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.77941208
Short name T83
Test name
Test status
Simulation time 20092339 ps
CPU time 0.97 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:14 PM PST 24
Peak memory 199972 kb
Host smart-ec68120a-0dbe-4a67-8864-5ddc7c01d94d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77941208 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.77941208
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3475409386
Short name T62
Test name
Test status
Simulation time 35575025 ps
CPU time 0.6 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:15 PM PST 24
Peak memory 195440 kb
Host smart-0382ba9b-cf03-414e-b62d-8724bfeef76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475409386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3475409386
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2398460685
Short name T1248
Test name
Test status
Simulation time 32188998 ps
CPU time 0.57 seconds
Started Feb 04 12:46:06 PM PST 24
Finished Feb 04 12:46:10 PM PST 24
Peak memory 194352 kb
Host smart-0eeaa6e1-8c6d-49ab-b756-dc68ad293829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398460685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2398460685
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.4249880315
Short name T1277
Test name
Test status
Simulation time 75039521 ps
CPU time 0.68 seconds
Started Feb 04 12:46:13 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 194872 kb
Host smart-d55a262f-d510-44ad-8d2f-15ced98b4cda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249880315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.4249880315
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2556630042
Short name T1285
Test name
Test status
Simulation time 57386552 ps
CPU time 1.27 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:14 PM PST 24
Peak memory 200152 kb
Host smart-8abb4105-a8db-40cc-aad2-73a4bb739789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556630042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2556630042
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1924645257
Short name T92
Test name
Test status
Simulation time 186365807 ps
CPU time 1.31 seconds
Started Feb 04 12:46:09 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 199296 kb
Host smart-aa8604ce-f1e0-47fb-a2a1-ef49a88bdb96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924645257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1924645257
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4286186661
Short name T2
Test name
Test status
Simulation time 102928631 ps
CPU time 0.94 seconds
Started Feb 04 12:46:35 PM PST 24
Finished Feb 04 12:46:38 PM PST 24
Peak memory 199984 kb
Host smart-871cbc6b-c6b1-4c86-a6fa-eedaa6286dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286186661 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4286186661
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.661247392
Short name T86
Test name
Test status
Simulation time 21803933 ps
CPU time 0.63 seconds
Started Feb 04 12:46:39 PM PST 24
Finished Feb 04 12:46:43 PM PST 24
Peak memory 195392 kb
Host smart-66b90555-0ec6-49a1-9e70-9a830b95cdcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661247392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.661247392
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2215242291
Short name T10
Test name
Test status
Simulation time 52118221 ps
CPU time 0.6 seconds
Started Feb 04 12:46:29 PM PST 24
Finished Feb 04 12:46:31 PM PST 24
Peak memory 194380 kb
Host smart-c8390d93-473c-4156-b30c-b88b0eb6c6b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215242291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2215242291
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3886332022
Short name T9
Test name
Test status
Simulation time 65195601 ps
CPU time 0.72 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:34 PM PST 24
Peak memory 195748 kb
Host smart-6941c3e0-463a-4103-83bf-97fe3cb4db68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886332022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3886332022
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2486164586
Short name T1261
Test name
Test status
Simulation time 194984733 ps
CPU time 1.36 seconds
Started Feb 04 12:46:09 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 200172 kb
Host smart-d8a32390-965d-4c8a-a334-800744bb5a40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486164586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2486164586
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3021225870
Short name T41
Test name
Test status
Simulation time 48752913 ps
CPU time 0.97 seconds
Started Feb 04 12:46:16 PM PST 24
Finished Feb 04 12:46:18 PM PST 24
Peak memory 199100 kb
Host smart-bc289ab8-4308-4ca2-a75a-6836acbd2668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021225870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3021225870
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.589939341
Short name T3
Test name
Test status
Simulation time 271528862 ps
CPU time 0.83 seconds
Started Feb 04 12:46:45 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 199964 kb
Host smart-c6c29de6-5dcb-4d48-9f95-3276aad53c6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589939341 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.589939341
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2229948536
Short name T1283
Test name
Test status
Simulation time 13304054 ps
CPU time 0.58 seconds
Started Feb 04 12:46:34 PM PST 24
Finished Feb 04 12:46:35 PM PST 24
Peak memory 195104 kb
Host smart-bdb9fe4f-4892-41c5-80e9-e6b7370f29a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229948536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2229948536
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1238534508
Short name T1291
Test name
Test status
Simulation time 29943519 ps
CPU time 0.6 seconds
Started Feb 04 12:46:37 PM PST 24
Finished Feb 04 12:46:42 PM PST 24
Peak memory 194304 kb
Host smart-8e431d49-d168-43e2-af4c-9ba86690f36f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238534508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1238534508
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1830829751
Short name T453
Test name
Test status
Simulation time 22040328 ps
CPU time 0.63 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:34 PM PST 24
Peak memory 195608 kb
Host smart-82418f4e-cee0-491e-9810-f5df88e84a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830829751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1830829751
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1537919758
Short name T451
Test name
Test status
Simulation time 43864334 ps
CPU time 2.12 seconds
Started Feb 04 12:46:28 PM PST 24
Finished Feb 04 12:46:31 PM PST 24
Peak memory 200140 kb
Host smart-e41e5e4e-e250-49e5-95d1-4b966f67bdbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537919758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1537919758
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3399418085
Short name T91
Test name
Test status
Simulation time 172696826 ps
CPU time 1.3 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:36 PM PST 24
Peak memory 199192 kb
Host smart-92257f50-85fb-43dc-8517-c812f7a7c6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399418085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3399418085
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1546514341
Short name T1259
Test name
Test status
Simulation time 25631691 ps
CPU time 0.64 seconds
Started Feb 04 12:46:39 PM PST 24
Finished Feb 04 12:46:43 PM PST 24
Peak memory 197308 kb
Host smart-caddb8bd-8b8e-4cd9-a0c7-7d2eaabfaa1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546514341 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1546514341
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1740458226
Short name T1264
Test name
Test status
Simulation time 13437805 ps
CPU time 0.56 seconds
Started Feb 04 12:46:32 PM PST 24
Finished Feb 04 12:46:33 PM PST 24
Peak memory 195372 kb
Host smart-880cb092-d0c4-4edd-8689-bcd884cb2878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740458226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1740458226
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.548012783
Short name T1255
Test name
Test status
Simulation time 38935545 ps
CPU time 0.59 seconds
Started Feb 04 12:46:32 PM PST 24
Finished Feb 04 12:46:33 PM PST 24
Peak memory 194412 kb
Host smart-5e7a2461-6687-4ec6-b5ea-dfc8e2fa627b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548012783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.548012783
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3505919991
Short name T1239
Test name
Test status
Simulation time 91655531 ps
CPU time 0.72 seconds
Started Feb 04 12:46:34 PM PST 24
Finished Feb 04 12:46:36 PM PST 24
Peak memory 196776 kb
Host smart-144d8809-499a-4b1f-9c9a-8764d8a69df3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505919991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3505919991
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.32343454
Short name T1268
Test name
Test status
Simulation time 37134956 ps
CPU time 1.67 seconds
Started Feb 04 12:46:45 PM PST 24
Finished Feb 04 12:46:51 PM PST 24
Peak memory 200100 kb
Host smart-8a0ec006-76b6-4c36-b7b0-ea1594f098eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32343454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.32343454
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2459809008
Short name T455
Test name
Test status
Simulation time 26973784 ps
CPU time 0.66 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 194672 kb
Host smart-ee4e4963-2c47-42c6-a80d-ab6b275de79f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459809008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2459809008
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.488846679
Short name T462
Test name
Test status
Simulation time 58053870 ps
CPU time 2.29 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:08 PM PST 24
Peak memory 197432 kb
Host smart-28c872bd-81f3-43cc-bd9c-d733dbbec892
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488846679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.488846679
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3229569320
Short name T80
Test name
Test status
Simulation time 51513588 ps
CPU time 0.59 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 195300 kb
Host smart-50c48931-c638-4d04-8f42-ffdec92e333b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229569320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3229569320
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.157963580
Short name T1252
Test name
Test status
Simulation time 19471730 ps
CPU time 0.94 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 199964 kb
Host smart-50e075cd-328a-4227-bb02-0de8a2d3e7ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157963580 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.157963580
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1880992096
Short name T476
Test name
Test status
Simulation time 39076712 ps
CPU time 0.58 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 195392 kb
Host smart-283eddc4-71aa-4b21-94b0-8a48e2a4cc70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880992096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1880992096
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.855580850
Short name T1289
Test name
Test status
Simulation time 34640350 ps
CPU time 0.56 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 194380 kb
Host smart-907732e4-47eb-41e0-a401-7dd740238446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855580850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.855580850
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3275173354
Short name T1276
Test name
Test status
Simulation time 94163740 ps
CPU time 0.62 seconds
Started Feb 04 12:45:54 PM PST 24
Finished Feb 04 12:46:02 PM PST 24
Peak memory 195812 kb
Host smart-8addc0c2-b7fc-401c-9786-d7d7f53c6c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275173354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3275173354
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1673289596
Short name T461
Test name
Test status
Simulation time 71032444 ps
CPU time 1.39 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 200092 kb
Host smart-10d6957e-2db8-4982-a99d-ef1743f4689b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673289596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1673289596
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.902885215
Short name T1240
Test name
Test status
Simulation time 95163426 ps
CPU time 1.37 seconds
Started Feb 04 12:45:53 PM PST 24
Finished Feb 04 12:45:57 PM PST 24
Peak memory 199232 kb
Host smart-a783c1d5-766a-489f-83c0-ad9ae74fb39d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902885215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.902885215
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3615093680
Short name T484
Test name
Test status
Simulation time 25108689 ps
CPU time 0.55 seconds
Started Feb 04 12:46:42 PM PST 24
Finished Feb 04 12:46:49 PM PST 24
Peak memory 194520 kb
Host smart-3351bf6a-fd36-4c0b-abdd-e90886a515e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615093680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3615093680
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3998475533
Short name T483
Test name
Test status
Simulation time 34899965 ps
CPU time 0.58 seconds
Started Feb 04 12:46:31 PM PST 24
Finished Feb 04 12:46:32 PM PST 24
Peak memory 194312 kb
Host smart-2f82899e-5d64-40f1-92a2-3f74b14cd4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998475533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3998475533
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1231444602
Short name T1243
Test name
Test status
Simulation time 18361632 ps
CPU time 0.64 seconds
Started Feb 04 12:46:28 PM PST 24
Finished Feb 04 12:46:30 PM PST 24
Peak memory 194424 kb
Host smart-88c24306-d2ec-47cb-9c9c-fc9f1b32b6fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231444602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1231444602
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3909989552
Short name T1241
Test name
Test status
Simulation time 43618483 ps
CPU time 0.61 seconds
Started Feb 04 12:46:38 PM PST 24
Finished Feb 04 12:46:42 PM PST 24
Peak memory 194348 kb
Host smart-6d4ad07c-7e58-4e3b-9873-3e80227c8db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909989552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3909989552
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2617549563
Short name T1266
Test name
Test status
Simulation time 31987026 ps
CPU time 0.55 seconds
Started Feb 04 12:46:34 PM PST 24
Finished Feb 04 12:46:35 PM PST 24
Peak memory 194068 kb
Host smart-9acf4614-1a5f-4b30-b318-426dd89a895d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617549563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2617549563
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1385018495
Short name T1257
Test name
Test status
Simulation time 23183420 ps
CPU time 0.6 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:35 PM PST 24
Peak memory 194372 kb
Host smart-1c15fa17-3f28-4353-ab6a-b032cb47949f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385018495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1385018495
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.760460713
Short name T473
Test name
Test status
Simulation time 20876187 ps
CPU time 0.59 seconds
Started Feb 04 12:46:41 PM PST 24
Finished Feb 04 12:46:44 PM PST 24
Peak memory 194400 kb
Host smart-8d0ff78b-530c-4820-aeaf-053d1dd47924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760460713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.760460713
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2289102337
Short name T49
Test name
Test status
Simulation time 47365120 ps
CPU time 0.58 seconds
Started Feb 04 12:46:28 PM PST 24
Finished Feb 04 12:46:30 PM PST 24
Peak memory 194404 kb
Host smart-5e1a49a3-9c71-4e33-b890-2024729d6647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289102337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2289102337
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.875410968
Short name T1263
Test name
Test status
Simulation time 14560387 ps
CPU time 0.59 seconds
Started Feb 04 12:46:30 PM PST 24
Finished Feb 04 12:46:31 PM PST 24
Peak memory 194468 kb
Host smart-2983159f-bd74-45e7-8fb0-1c591853e1c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875410968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.875410968
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1324640723
Short name T56
Test name
Test status
Simulation time 61791734 ps
CPU time 0.81 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 196428 kb
Host smart-fe78ccf2-ea02-4f02-b87d-99de93269298
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324640723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1324640723
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3965412492
Short name T68
Test name
Test status
Simulation time 262728776 ps
CPU time 2.6 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 197468 kb
Host smart-b4bc9c1d-c9a5-47ee-a3ec-92e3b836e937
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965412492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3965412492
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.785323764
Short name T39
Test name
Test status
Simulation time 92921918 ps
CPU time 0.66 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 195336 kb
Host smart-7ab1e206-c525-4007-94e2-761fa3650d2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785323764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.785323764
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2980123997
Short name T480
Test name
Test status
Simulation time 94308185 ps
CPU time 0.86 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 199964 kb
Host smart-7898d008-404a-442f-9b7d-30a94690d5d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980123997 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2980123997
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1967456801
Short name T64
Test name
Test status
Simulation time 48901777 ps
CPU time 0.6 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:03 PM PST 24
Peak memory 195416 kb
Host smart-418ec077-895f-48be-ab1b-6065b499021f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967456801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1967456801
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3587759149
Short name T481
Test name
Test status
Simulation time 113337185 ps
CPU time 0.6 seconds
Started Feb 04 12:45:57 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 194340 kb
Host smart-a4b24a5e-5e0b-4b08-9b8f-4b5e80e2c53d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587759149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3587759149
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.771643559
Short name T471
Test name
Test status
Simulation time 19095911 ps
CPU time 0.66 seconds
Started Feb 04 12:45:58 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 195748 kb
Host smart-b5ba86df-d7ad-4231-9bc0-d788227d4366
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771643559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.771643559
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3249222273
Short name T1253
Test name
Test status
Simulation time 48371922 ps
CPU time 2.12 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:08 PM PST 24
Peak memory 200168 kb
Host smart-a84bcc55-ab01-466a-bb12-6974d84650fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249222273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3249222273
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2552695260
Short name T1278
Test name
Test status
Simulation time 319541768 ps
CPU time 1.4 seconds
Started Feb 04 12:46:06 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 199124 kb
Host smart-bd564eae-6b7c-4e8e-a05f-af7e8cf75a88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552695260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2552695260
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.261353754
Short name T1245
Test name
Test status
Simulation time 14933190 ps
CPU time 0.61 seconds
Started Feb 04 12:46:41 PM PST 24
Finished Feb 04 12:46:44 PM PST 24
Peak memory 194400 kb
Host smart-c6ef0793-df98-43b1-80fd-af21ded84cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261353754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.261353754
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3372550793
Short name T75
Test name
Test status
Simulation time 24477960 ps
CPU time 0.54 seconds
Started Feb 04 12:46:34 PM PST 24
Finished Feb 04 12:46:36 PM PST 24
Peak memory 194380 kb
Host smart-f12565f6-4ad8-43cd-b1ea-823cdf344b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372550793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3372550793
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4227600065
Short name T1274
Test name
Test status
Simulation time 39002057 ps
CPU time 0.56 seconds
Started Feb 04 12:46:39 PM PST 24
Finished Feb 04 12:46:43 PM PST 24
Peak memory 194376 kb
Host smart-2aecf66b-3fdf-4cfe-886e-10e9c8bcc31b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227600065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4227600065
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4254125688
Short name T1270
Test name
Test status
Simulation time 10526333 ps
CPU time 0.57 seconds
Started Feb 04 12:46:45 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 194268 kb
Host smart-7e5608cd-e837-42ef-a208-ab10e07e0b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254125688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4254125688
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.193276135
Short name T7
Test name
Test status
Simulation time 16762546 ps
CPU time 0.6 seconds
Started Feb 04 12:46:44 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 194464 kb
Host smart-ead01a6a-45fd-4417-8121-49e9fea8056f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193276135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.193276135
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.4133325354
Short name T1297
Test name
Test status
Simulation time 15119571 ps
CPU time 0.58 seconds
Started Feb 04 12:46:32 PM PST 24
Finished Feb 04 12:46:33 PM PST 24
Peak memory 194308 kb
Host smart-2630bfa7-151f-4c6c-a930-c2fcef4e8af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133325354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4133325354
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1287328673
Short name T1295
Test name
Test status
Simulation time 43896887 ps
CPU time 0.56 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:34 PM PST 24
Peak memory 194352 kb
Host smart-0e2c407a-1b31-4580-8466-af19d92b231f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287328673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1287328673
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.131530590
Short name T50
Test name
Test status
Simulation time 14032470 ps
CPU time 0.55 seconds
Started Feb 04 12:46:29 PM PST 24
Finished Feb 04 12:46:30 PM PST 24
Peak memory 194344 kb
Host smart-4cea87e7-a97a-4cf1-8112-d12227671d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131530590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.131530590
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.862681184
Short name T459
Test name
Test status
Simulation time 12177735 ps
CPU time 0.57 seconds
Started Feb 04 12:46:35 PM PST 24
Finished Feb 04 12:46:37 PM PST 24
Peak memory 194552 kb
Host smart-eb44b14a-64c3-4d5d-888c-35a720290983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862681184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.862681184
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4087432095
Short name T1269
Test name
Test status
Simulation time 79624108 ps
CPU time 0.64 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 194528 kb
Host smart-03020493-6679-4a86-a0d5-7d1b3f1dfb18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087432095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.4087432095
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2237300115
Short name T1288
Test name
Test status
Simulation time 303198489 ps
CPU time 2.2 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:08 PM PST 24
Peak memory 197580 kb
Host smart-c6ff43ee-ef55-4bc8-bf67-cbde29f6283b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237300115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2237300115
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1812499687
Short name T38
Test name
Test status
Simulation time 12797786 ps
CPU time 0.56 seconds
Started Feb 04 12:46:03 PM PST 24
Finished Feb 04 12:46:09 PM PST 24
Peak memory 195356 kb
Host smart-056e3498-3c57-4b91-bd6c-aae4d9e48220
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812499687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1812499687
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1419078156
Short name T43
Test name
Test status
Simulation time 73021179 ps
CPU time 1.04 seconds
Started Feb 04 12:45:58 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 199948 kb
Host smart-dddb7306-c01c-409a-ac94-c427ac26a302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419078156 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1419078156
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2417672479
Short name T85
Test name
Test status
Simulation time 75463925 ps
CPU time 0.65 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 195428 kb
Host smart-98f71a44-37dc-4f96-ab97-0252fd325c1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417672479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2417672479
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3430568757
Short name T1275
Test name
Test status
Simulation time 55290937 ps
CPU time 0.59 seconds
Started Feb 04 12:45:58 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 194360 kb
Host smart-c101db40-47eb-4f6c-a7d6-4379bf8c0057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430568757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3430568757
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.468826600
Short name T467
Test name
Test status
Simulation time 12944792 ps
CPU time 0.62 seconds
Started Feb 04 12:46:01 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 195592 kb
Host smart-de4dd4e6-015f-4d32-bc11-b9b11171ad59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468826600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.468826600
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1318404891
Short name T463
Test name
Test status
Simulation time 32348295 ps
CPU time 1.63 seconds
Started Feb 04 12:45:55 PM PST 24
Finished Feb 04 12:46:04 PM PST 24
Peak memory 200132 kb
Host smart-3360cb1c-bb65-4fd3-8c79-5c7fef368232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318404891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1318404891
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.390614900
Short name T1273
Test name
Test status
Simulation time 333656362 ps
CPU time 1 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:06 PM PST 24
Peak memory 198824 kb
Host smart-08197f53-9070-47a5-b46c-ea46cee571a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390614900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.390614900
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.536471924
Short name T72
Test name
Test status
Simulation time 24019786 ps
CPU time 0.58 seconds
Started Feb 04 12:46:35 PM PST 24
Finished Feb 04 12:46:37 PM PST 24
Peak memory 194400 kb
Host smart-a1c4e609-e226-43f6-b96a-c07360dee79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536471924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.536471924
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2866554341
Short name T1254
Test name
Test status
Simulation time 15073730 ps
CPU time 0.63 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:34 PM PST 24
Peak memory 194392 kb
Host smart-97895526-2712-490b-8da9-8acfd7f0540d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866554341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2866554341
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.114530604
Short name T109
Test name
Test status
Simulation time 27783683 ps
CPU time 0.58 seconds
Started Feb 04 12:46:39 PM PST 24
Finished Feb 04 12:46:43 PM PST 24
Peak memory 194388 kb
Host smart-f10038c2-3f7c-41ad-a97d-4c300cf7effa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114530604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.114530604
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3143750586
Short name T466
Test name
Test status
Simulation time 16896911 ps
CPU time 0.58 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:35 PM PST 24
Peak memory 194356 kb
Host smart-530e7cf0-4546-4b44-9f4a-8712d096128e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143750586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3143750586
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1451977391
Short name T465
Test name
Test status
Simulation time 12653163 ps
CPU time 0.61 seconds
Started Feb 04 12:46:37 PM PST 24
Finished Feb 04 12:46:42 PM PST 24
Peak memory 194304 kb
Host smart-1c269908-32e5-487b-9cfa-2be3456ccb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451977391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1451977391
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1625524230
Short name T1294
Test name
Test status
Simulation time 40092958 ps
CPU time 0.59 seconds
Started Feb 04 12:46:44 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 194404 kb
Host smart-a53c0ca6-03c9-4e66-b2df-f77e7f35e568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625524230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1625524230
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.4159691649
Short name T482
Test name
Test status
Simulation time 14665308 ps
CPU time 0.58 seconds
Started Feb 04 12:46:42 PM PST 24
Finished Feb 04 12:46:44 PM PST 24
Peak memory 194388 kb
Host smart-97f7696c-7a6c-4ae7-a3d4-81cf40ea7691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159691649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4159691649
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3487860771
Short name T1265
Test name
Test status
Simulation time 43649524 ps
CPU time 0.59 seconds
Started Feb 04 12:46:29 PM PST 24
Finished Feb 04 12:46:31 PM PST 24
Peak memory 194380 kb
Host smart-5abb0011-8bc1-4c73-aed0-bba9d83932b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487860771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3487860771
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2076966880
Short name T485
Test name
Test status
Simulation time 38698128 ps
CPU time 0.59 seconds
Started Feb 04 12:46:33 PM PST 24
Finished Feb 04 12:46:35 PM PST 24
Peak memory 194368 kb
Host smart-3a33b9c0-f0b5-4672-a00c-f94595a6cc2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076966880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2076966880
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.603599809
Short name T1236
Test name
Test status
Simulation time 381316357 ps
CPU time 1.2 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 199968 kb
Host smart-fe46d990-1436-4a5e-b6bf-f08b2a5cdc85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603599809 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.603599809
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.498545540
Short name T69
Test name
Test status
Simulation time 15974502 ps
CPU time 0.6 seconds
Started Feb 04 12:46:08 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 195404 kb
Host smart-113a1031-d665-4a10-93d0-89b46ba65713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498545540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.498545540
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.900117042
Short name T1272
Test name
Test status
Simulation time 186107121 ps
CPU time 0.57 seconds
Started Feb 04 12:46:03 PM PST 24
Finished Feb 04 12:46:09 PM PST 24
Peak memory 194336 kb
Host smart-b8fb5fde-f525-4084-b81c-fddf5823ceca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900117042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.900117042
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3690556332
Short name T1246
Test name
Test status
Simulation time 22612671 ps
CPU time 0.64 seconds
Started Feb 04 12:46:02 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 196504 kb
Host smart-d216256d-935a-421f-b359-defb301b8333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690556332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3690556332
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1072989969
Short name T37
Test name
Test status
Simulation time 102838517 ps
CPU time 2.2 seconds
Started Feb 04 12:45:59 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 200100 kb
Host smart-bf77f1e4-fefd-417d-85ff-45badc9c2788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072989969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1072989969
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3975596620
Short name T1286
Test name
Test status
Simulation time 341869296 ps
CPU time 1.34 seconds
Started Feb 04 12:46:00 PM PST 24
Finished Feb 04 12:46:07 PM PST 24
Peak memory 199276 kb
Host smart-6d4a2987-6ea6-4e02-835d-14ed01b7b549
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975596620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3975596620
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.875134056
Short name T74
Test name
Test status
Simulation time 168253660 ps
CPU time 0.87 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:14 PM PST 24
Peak memory 199952 kb
Host smart-00325c48-68bc-4d81-a683-d01982b0dc9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875134056 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.875134056
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1436052491
Short name T60
Test name
Test status
Simulation time 19420877 ps
CPU time 0.62 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 195400 kb
Host smart-1cf74c17-4a97-4725-9b6f-3b566369ffa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436052491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1436052491
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2967596701
Short name T1284
Test name
Test status
Simulation time 207949591 ps
CPU time 0.58 seconds
Started Feb 04 12:46:08 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 194400 kb
Host smart-e78bf46b-6d03-4f34-8c55-95f2a32b734c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967596701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2967596701
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3468172380
Short name T1262
Test name
Test status
Simulation time 19576031 ps
CPU time 0.75 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 197080 kb
Host smart-4ff06a28-b58e-4fb7-9705-ae47c7622fa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468172380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3468172380
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3750845765
Short name T1271
Test name
Test status
Simulation time 399443651 ps
CPU time 2.39 seconds
Started Feb 04 12:45:59 PM PST 24
Finished Feb 04 12:46:08 PM PST 24
Peak memory 200120 kb
Host smart-f98b5480-8a47-46f3-bc4e-e88e9a69de16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750845765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3750845765
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2100766993
Short name T52
Test name
Test status
Simulation time 46524637 ps
CPU time 0.97 seconds
Started Feb 04 12:46:08 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 198704 kb
Host smart-fde2f067-3369-4753-ad0b-ca5e6e39df94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100766993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2100766993
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1455459814
Short name T1290
Test name
Test status
Simulation time 134143226 ps
CPU time 0.85 seconds
Started Feb 04 12:46:07 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 199980 kb
Host smart-bd0889b2-c412-452d-8fe1-ed04aeaddcb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455459814 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1455459814
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3276796696
Short name T1247
Test name
Test status
Simulation time 19561315 ps
CPU time 0.63 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 195336 kb
Host smart-0f5fc259-c030-48cd-af91-4779d45630e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276796696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3276796696
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2825403369
Short name T472
Test name
Test status
Simulation time 50089593 ps
CPU time 0.58 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:14 PM PST 24
Peak memory 194384 kb
Host smart-d2b04703-8f97-4d0c-abf1-20a8d3f10f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825403369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2825403369
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.4068104105
Short name T477
Test name
Test status
Simulation time 29926684 ps
CPU time 0.72 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 197728 kb
Host smart-0023ddf0-96ba-42bc-9790-cbbb741f9d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068104105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.4068104105
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2257352598
Short name T45
Test name
Test status
Simulation time 620003090 ps
CPU time 2.78 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:19 PM PST 24
Peak memory 200152 kb
Host smart-52545e73-449c-4412-a3e4-1b490e181443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257352598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2257352598
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3388942529
Short name T1267
Test name
Test status
Simulation time 227911849 ps
CPU time 1.19 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 198580 kb
Host smart-1b7f0654-c8f4-463e-9d16-e0df99afe916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388942529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3388942529
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3595693035
Short name T90
Test name
Test status
Simulation time 40613377 ps
CPU time 0.79 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:14 PM PST 24
Peak memory 199908 kb
Host smart-cf695157-f41b-4a3a-b0a8-c1d0721f981f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595693035 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3595693035
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.724677638
Short name T5
Test name
Test status
Simulation time 35219751 ps
CPU time 0.58 seconds
Started Feb 04 12:46:10 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 195344 kb
Host smart-950d0f24-8ff2-47e1-995c-e75c9e5fe256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724677638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.724677638
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2311152657
Short name T1296
Test name
Test status
Simulation time 42269633 ps
CPU time 0.63 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:15 PM PST 24
Peak memory 194420 kb
Host smart-ea02ce50-e3e2-4665-bb0b-8c188e58aafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311152657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2311152657
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1623740344
Short name T57
Test name
Test status
Simulation time 36707740 ps
CPU time 0.71 seconds
Started Feb 04 12:46:09 PM PST 24
Finished Feb 04 12:46:12 PM PST 24
Peak memory 195548 kb
Host smart-7166a56c-496d-434a-8ca9-cc1f10b70407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623740344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1623740344
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3280418856
Short name T1293
Test name
Test status
Simulation time 114810556 ps
CPU time 2.03 seconds
Started Feb 04 12:46:14 PM PST 24
Finished Feb 04 12:46:18 PM PST 24
Peak memory 200088 kb
Host smart-b00f80e9-c896-444d-b21d-5b50a5684a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280418856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3280418856
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3741965847
Short name T1282
Test name
Test status
Simulation time 63623147 ps
CPU time 1.01 seconds
Started Feb 04 12:46:07 PM PST 24
Finished Feb 04 12:46:11 PM PST 24
Peak memory 198944 kb
Host smart-1112353d-4e0f-498b-8877-d8481eb12a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741965847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3741965847
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3628953921
Short name T1244
Test name
Test status
Simulation time 29667800 ps
CPU time 0.66 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:14 PM PST 24
Peak memory 197448 kb
Host smart-a2405222-eae0-47c1-94c1-bae4116bb82b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628953921 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3628953921
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2134516210
Short name T458
Test name
Test status
Simulation time 38415485 ps
CPU time 0.57 seconds
Started Feb 04 12:46:11 PM PST 24
Finished Feb 04 12:46:13 PM PST 24
Peak memory 195400 kb
Host smart-14f81174-17bb-490e-a83a-2083d305d188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134516210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2134516210
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.328347916
Short name T398
Test name
Test status
Simulation time 60841911 ps
CPU time 0.57 seconds
Started Feb 04 12:46:12 PM PST 24
Finished Feb 04 12:46:15 PM PST 24
Peak memory 194380 kb
Host smart-43066238-c945-42a3-bd31-42fad76c735d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328347916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.328347916
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.535797688
Short name T73
Test name
Test status
Simulation time 49948127 ps
CPU time 0.81 seconds
Started Feb 04 12:46:06 PM PST 24
Finished Feb 04 12:46:10 PM PST 24
Peak memory 197012 kb
Host smart-b401c26a-c5d9-4fc0-82b8-2b6a864b8126
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535797688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.535797688
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3713370369
Short name T46
Test name
Test status
Simulation time 94114513 ps
CPU time 2.1 seconds
Started Feb 04 12:46:06 PM PST 24
Finished Feb 04 12:46:12 PM PST 24
Peak memory 200152 kb
Host smart-84c89429-4060-4fdc-8bf0-3a216e97fd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713370369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3713370369
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/default/0.uart_alert_test.528501571
Short name T796
Test name
Test status
Simulation time 32064598 ps
CPU time 0.54 seconds
Started Feb 04 12:28:10 PM PST 24
Finished Feb 04 12:28:14 PM PST 24
Peak memory 194116 kb
Host smart-c55ee9c7-a3a0-457b-b851-9f49c8df1a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528501571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.528501571
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2130175398
Short name T933
Test name
Test status
Simulation time 110598151433 ps
CPU time 35.11 seconds
Started Feb 04 12:52:27 PM PST 24
Finished Feb 04 12:53:07 PM PST 24
Peak memory 199892 kb
Host smart-a09bffc2-bf2a-409c-b7aa-0ae747d26a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130175398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2130175398
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.440179324
Short name T858
Test name
Test status
Simulation time 86696925773 ps
CPU time 112.76 seconds
Started Feb 04 12:23:43 PM PST 24
Finished Feb 04 12:25:39 PM PST 24
Peak memory 199752 kb
Host smart-d7bbfd1f-632b-40fa-b16e-7247bcb95db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440179324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.440179324
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1434290239
Short name T156
Test name
Test status
Simulation time 13569218565 ps
CPU time 19.71 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:03 PM PST 24
Peak memory 199072 kb
Host smart-6c76e7aa-93ef-44ef-9875-2783191d9e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434290239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1434290239
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.33483787
Short name T225
Test name
Test status
Simulation time 109593187153 ps
CPU time 174.92 seconds
Started Feb 04 12:27:39 PM PST 24
Finished Feb 04 12:30:37 PM PST 24
Peak memory 198320 kb
Host smart-574276d2-54ca-45b4-a8df-b9d1313fcd5d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.33483787
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.4119161799
Short name T903
Test name
Test status
Simulation time 88887718127 ps
CPU time 377.91 seconds
Started Feb 04 12:28:05 PM PST 24
Finished Feb 04 12:34:25 PM PST 24
Peak memory 199220 kb
Host smart-93d54244-1fa6-41cf-8711-9699f721dd9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119161799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.4119161799
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3173041929
Short name T1047
Test name
Test status
Simulation time 6104924418 ps
CPU time 14.67 seconds
Started Feb 04 12:28:08 PM PST 24
Finished Feb 04 12:28:26 PM PST 24
Peak memory 198312 kb
Host smart-ddf32d0b-18d3-4778-977a-943ea9ee3abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173041929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3173041929
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.797401024
Short name T884
Test name
Test status
Simulation time 114481885261 ps
CPU time 49.89 seconds
Started Feb 04 12:28:00 PM PST 24
Finished Feb 04 12:28:52 PM PST 24
Peak memory 197908 kb
Host smart-b4f194b3-6675-48a6-97ed-3f459e10e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797401024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.797401024
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1508647612
Short name T732
Test name
Test status
Simulation time 15391402733 ps
CPU time 183.87 seconds
Started Feb 04 12:28:05 PM PST 24
Finished Feb 04 12:31:12 PM PST 24
Peak memory 199772 kb
Host smart-9f8669de-79be-4f6b-9d6d-e14e6adea9d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508647612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1508647612
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3608071645
Short name T655
Test name
Test status
Simulation time 1760555277 ps
CPU time 8.89 seconds
Started Feb 04 12:23:16 PM PST 24
Finished Feb 04 12:23:26 PM PST 24
Peak memory 197440 kb
Host smart-2c93694f-8168-48ce-be82-01b31fde56e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3608071645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3608071645
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3322341770
Short name T1110
Test name
Test status
Simulation time 75302121796 ps
CPU time 125.39 seconds
Started Feb 04 12:28:06 PM PST 24
Finished Feb 04 12:30:15 PM PST 24
Peak memory 199680 kb
Host smart-60c9c83a-d146-4082-b975-ebc2a713dcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322341770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3322341770
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3333616329
Short name T422
Test name
Test status
Simulation time 4830825679 ps
CPU time 4.48 seconds
Started Feb 04 12:28:05 PM PST 24
Finished Feb 04 12:28:11 PM PST 24
Peak memory 195508 kb
Host smart-db4e2d81-3674-43ec-a2e4-cdd90791471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333616329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3333616329
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3159210548
Short name T952
Test name
Test status
Simulation time 506489804 ps
CPU time 2.89 seconds
Started Feb 04 12:26:26 PM PST 24
Finished Feb 04 12:26:34 PM PST 24
Peak memory 198092 kb
Host smart-df43db62-dabe-4ac0-a3bf-22ba9dbd4334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159210548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3159210548
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.325881459
Short name T795
Test name
Test status
Simulation time 115143633183 ps
CPU time 219.22 seconds
Started Feb 04 12:28:06 PM PST 24
Finished Feb 04 12:31:49 PM PST 24
Peak memory 215492 kb
Host smart-a7989013-1b47-4831-a034-850b16a01330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325881459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.325881459
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.796786720
Short name T104
Test name
Test status
Simulation time 4469593591 ps
CPU time 1.23 seconds
Started Feb 04 12:28:08 PM PST 24
Finished Feb 04 12:28:12 PM PST 24
Peak memory 199480 kb
Host smart-c34cc6e0-3432-426e-bee9-1a30a1d167c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796786720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.796786720
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2739059071
Short name T604
Test name
Test status
Simulation time 58513080945 ps
CPU time 23.93 seconds
Started Feb 04 12:23:16 PM PST 24
Finished Feb 04 12:23:42 PM PST 24
Peak memory 199940 kb
Host smart-5cb84425-7c59-41a8-8f29-7946ecec986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739059071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2739059071
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3318999608
Short name T523
Test name
Test status
Simulation time 17927534 ps
CPU time 0.57 seconds
Started Feb 04 12:28:16 PM PST 24
Finished Feb 04 12:28:24 PM PST 24
Peak memory 195108 kb
Host smart-d337ba23-a30c-40bd-81cc-f4ca9f8babb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318999608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3318999608
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.259437838
Short name T1135
Test name
Test status
Simulation time 159304194132 ps
CPU time 265.35 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:32:36 PM PST 24
Peak memory 199728 kb
Host smart-12acd381-6d48-422f-b212-422a4e2576e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259437838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.259437838
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3344175812
Short name T1099
Test name
Test status
Simulation time 41902530285 ps
CPU time 32.22 seconds
Started Feb 04 12:28:10 PM PST 24
Finished Feb 04 12:28:46 PM PST 24
Peak memory 199384 kb
Host smart-afae9d0c-c92c-4ec2-a0f8-96d9f0eb5597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344175812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3344175812
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.483197568
Short name T637
Test name
Test status
Simulation time 122887082483 ps
CPU time 54.64 seconds
Started Feb 04 12:28:04 PM PST 24
Finished Feb 04 12:29:01 PM PST 24
Peak memory 199724 kb
Host smart-f4fb2afa-22f5-4e5c-8d93-04307430e719
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483197568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.483197568
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2467028297
Short name T725
Test name
Test status
Simulation time 51835315182 ps
CPU time 145.33 seconds
Started Feb 04 12:27:57 PM PST 24
Finished Feb 04 12:30:27 PM PST 24
Peak memory 199820 kb
Host smart-5359a61a-712f-4054-931b-36670752dccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467028297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2467028297
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3635719681
Short name T809
Test name
Test status
Simulation time 3307388263 ps
CPU time 5.4 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:28:16 PM PST 24
Peak memory 197264 kb
Host smart-26a279df-7b4c-47ba-9eab-38f01add3828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635719681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3635719681
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2132324795
Short name T1108
Test name
Test status
Simulation time 73288656669 ps
CPU time 108.68 seconds
Started Feb 04 12:28:01 PM PST 24
Finished Feb 04 12:29:52 PM PST 24
Peak memory 199588 kb
Host smart-136b8800-ff08-4ec6-be66-2e6ef9ce0aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132324795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2132324795
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2396007618
Short name T610
Test name
Test status
Simulation time 11027378241 ps
CPU time 486.39 seconds
Started Feb 04 12:28:01 PM PST 24
Finished Feb 04 12:36:10 PM PST 24
Peak memory 199680 kb
Host smart-c29f0a75-8e8e-4717-ab6a-07f61930456b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396007618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2396007618
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3881868142
Short name T825
Test name
Test status
Simulation time 250523428 ps
CPU time 2.01 seconds
Started Feb 04 12:28:10 PM PST 24
Finished Feb 04 12:28:16 PM PST 24
Peak memory 197576 kb
Host smart-d6ba6b7d-15ca-40d5-8f20-4de9f26940ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881868142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3881868142
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3769337957
Short name T961
Test name
Test status
Simulation time 96896392374 ps
CPU time 17.45 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:28:28 PM PST 24
Peak memory 199508 kb
Host smart-9773a0fd-68fa-4c74-83e8-17b66bf7c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769337957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3769337957
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1384634131
Short name T953
Test name
Test status
Simulation time 6741266744 ps
CPU time 6.07 seconds
Started Feb 04 12:27:55 PM PST 24
Finished Feb 04 12:28:04 PM PST 24
Peak memory 195516 kb
Host smart-da1082de-e091-4d3c-9ad7-ed6cba478160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384634131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1384634131
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3773539104
Short name T97
Test name
Test status
Simulation time 438462210 ps
CPU time 0.77 seconds
Started Feb 04 12:28:15 PM PST 24
Finished Feb 04 12:28:25 PM PST 24
Peak memory 217156 kb
Host smart-b9ac5a45-cf52-4cb9-9479-01e955d5faba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773539104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3773539104
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1812105947
Short name T440
Test name
Test status
Simulation time 6052810020 ps
CPU time 12.66 seconds
Started Feb 04 12:28:05 PM PST 24
Finished Feb 04 12:28:20 PM PST 24
Peak memory 198368 kb
Host smart-2d73f093-f30c-40c5-9a57-e7d30fe44440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812105947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1812105947
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1123284434
Short name T1195
Test name
Test status
Simulation time 67509287369 ps
CPU time 35.78 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:28:47 PM PST 24
Peak memory 199772 kb
Host smart-5200fa71-6b85-439f-bfc3-0259198c9311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123284434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1123284434
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3971140119
Short name T67
Test name
Test status
Simulation time 61645006346 ps
CPU time 572.26 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:37:43 PM PST 24
Peak memory 216536 kb
Host smart-3c8702b9-c6a3-4bdf-a921-c6cc6e529da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971140119 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3971140119
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2239273936
Short name T408
Test name
Test status
Simulation time 12980932705 ps
CPU time 40.57 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:28:52 PM PST 24
Peak memory 199604 kb
Host smart-23079cd4-37f8-4dfd-b234-5924acbeef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239273936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2239273936
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4181087830
Short name T644
Test name
Test status
Simulation time 49589148672 ps
CPU time 85.32 seconds
Started Feb 04 12:28:10 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 199620 kb
Host smart-28cc3139-214f-47a2-ad2d-3659b81f2395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181087830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4181087830
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1881008951
Short name T1030
Test name
Test status
Simulation time 14670952 ps
CPU time 0.56 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:28:48 PM PST 24
Peak memory 195196 kb
Host smart-67740705-9fda-4b3e-bba1-1243f2589c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881008951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1881008951
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1663804053
Short name T1114
Test name
Test status
Simulation time 103397962182 ps
CPU time 49.33 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:29:41 PM PST 24
Peak memory 198936 kb
Host smart-2e6e4627-8ddd-4c69-8827-e88c30183330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663804053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1663804053
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1118282767
Short name T957
Test name
Test status
Simulation time 312855778238 ps
CPU time 379.19 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:35:02 PM PST 24
Peak memory 199764 kb
Host smart-adfe8c83-7697-446f-9163-e33c502622f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118282767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1118282767
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1010685280
Short name T672
Test name
Test status
Simulation time 2056569074729 ps
CPU time 816.63 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:42:29 PM PST 24
Peak memory 199720 kb
Host smart-2bce36bf-8ebb-4c0f-b633-557cb71d3990
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010685280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1010685280
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2675597050
Short name T609
Test name
Test status
Simulation time 35387346936 ps
CPU time 164.09 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:31:36 PM PST 24
Peak memory 199768 kb
Host smart-f37ece61-2aa4-4e47-8807-0bae6299d716
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675597050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2675597050
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.608929448
Short name T1079
Test name
Test status
Simulation time 1531161636 ps
CPU time 2.25 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:28:54 PM PST 24
Peak memory 197684 kb
Host smart-9d3a9a06-f7e7-434b-946d-2fbbc40db632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608929448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.608929448
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.497546494
Short name T1146
Test name
Test status
Simulation time 9277360319 ps
CPU time 4.68 seconds
Started Feb 04 12:28:46 PM PST 24
Finished Feb 04 12:28:54 PM PST 24
Peak memory 195384 kb
Host smart-a54695fb-72fa-4462-8637-7505c7c899c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497546494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.497546494
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2324521118
Short name T879
Test name
Test status
Simulation time 17029702833 ps
CPU time 252.88 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:32:54 PM PST 24
Peak memory 199648 kb
Host smart-c3482501-41cc-4809-b749-3d893c4858cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324521118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2324521118
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.167656373
Short name T891
Test name
Test status
Simulation time 994493704 ps
CPU time 1.48 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:44 PM PST 24
Peak memory 197736 kb
Host smart-1e78e1d5-f604-4c28-a695-ab53032d88c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167656373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.167656373
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3348760967
Short name T924
Test name
Test status
Simulation time 50029286349 ps
CPU time 18.61 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:01 PM PST 24
Peak memory 198248 kb
Host smart-876bc96c-1320-4ccb-b1d6-0353125afbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348760967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3348760967
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3353910944
Short name T495
Test name
Test status
Simulation time 5540874195 ps
CPU time 2.8 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:28:55 PM PST 24
Peak memory 195544 kb
Host smart-12236761-26cf-4d75-90b7-968282168038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353910944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3353910944
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4139680811
Short name T638
Test name
Test status
Simulation time 5992850570 ps
CPU time 16.16 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:29:06 PM PST 24
Peak memory 198584 kb
Host smart-d6afea64-5a7f-42c9-8a3a-a2678a56f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139680811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4139680811
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2477728420
Short name T812
Test name
Test status
Simulation time 98070793351 ps
CPU time 74.82 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:30:07 PM PST 24
Peak memory 199800 kb
Host smart-fb37a120-c669-4c21-a53b-237236d34d23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477728420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2477728420
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3624043718
Short name T1158
Test name
Test status
Simulation time 7559900958 ps
CPU time 16.76 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:29:10 PM PST 24
Peak memory 199160 kb
Host smart-a263757e-21fc-4d3f-86ab-46e1be3304f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624043718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3624043718
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2623723655
Short name T932
Test name
Test status
Simulation time 121505990498 ps
CPU time 143.39 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:30:59 PM PST 24
Peak memory 199820 kb
Host smart-84d7f482-4056-42ad-b01a-6328fed5b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623723655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2623723655
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2856965103
Short name T170
Test name
Test status
Simulation time 106596213102 ps
CPU time 162 seconds
Started Feb 04 12:31:24 PM PST 24
Finished Feb 04 12:34:08 PM PST 24
Peak memory 199956 kb
Host smart-84ccfb1c-92a1-4794-b02a-7e0718c330e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856965103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2856965103
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4012156602
Short name T787
Test name
Test status
Simulation time 183966543593 ps
CPU time 160.6 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:34:14 PM PST 24
Peak memory 199776 kb
Host smart-78135d38-40d2-495b-8f58-e9e4da65c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012156602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4012156602
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3649333553
Short name T1014
Test name
Test status
Simulation time 53319026630 ps
CPU time 39.39 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:32:15 PM PST 24
Peak memory 199728 kb
Host smart-9c6d6637-afa9-43bb-9c92-2c35067e548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649333553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3649333553
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1540088389
Short name T979
Test name
Test status
Simulation time 41312909179 ps
CPU time 18.77 seconds
Started Feb 04 12:31:23 PM PST 24
Finished Feb 04 12:31:43 PM PST 24
Peak memory 199560 kb
Host smart-a3dcdd35-cad5-4644-a7aa-a69d672c9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540088389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1540088389
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3603688756
Short name T310
Test name
Test status
Simulation time 18921840297 ps
CPU time 13.36 seconds
Started Feb 04 12:31:23 PM PST 24
Finished Feb 04 12:31:38 PM PST 24
Peak memory 198768 kb
Host smart-0c03b759-ea49-4a7c-93c5-3427c8c5ab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603688756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3603688756
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1774408668
Short name T236
Test name
Test status
Simulation time 101812028698 ps
CPU time 34.63 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:32:02 PM PST 24
Peak memory 199280 kb
Host smart-6f4caa8d-9b55-40a5-9728-cc9aa13cab18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774408668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1774408668
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3870307388
Short name T810
Test name
Test status
Simulation time 22818224118 ps
CPU time 30.79 seconds
Started Feb 04 12:31:32 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199564 kb
Host smart-4ebfebd0-e81a-4065-b8c7-acd6899f2c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870307388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3870307388
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.439751581
Short name T938
Test name
Test status
Simulation time 98259163090 ps
CPU time 21.76 seconds
Started Feb 04 12:31:23 PM PST 24
Finished Feb 04 12:31:46 PM PST 24
Peak memory 199796 kb
Host smart-27ff10b2-0bb9-4666-9b27-7e0899f2f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439751581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.439751581
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4088453188
Short name T909
Test name
Test status
Simulation time 88986071 ps
CPU time 0.57 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:43 PM PST 24
Peak memory 194300 kb
Host smart-ad0a9478-99bf-4c05-8ae4-ac0847ec8c87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088453188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4088453188
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.485752470
Short name T244
Test name
Test status
Simulation time 14183160616 ps
CPU time 23.45 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:06 PM PST 24
Peak memory 199772 kb
Host smart-03cbd960-c459-4771-b4ac-02ee9f42fb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485752470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.485752470
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2332399280
Short name T393
Test name
Test status
Simulation time 63281938234 ps
CPU time 22.13 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:29:10 PM PST 24
Peak memory 199764 kb
Host smart-9205b0e0-e793-4aba-8ac8-883bde026365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332399280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2332399280
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.607268582
Short name T165
Test name
Test status
Simulation time 52095623656 ps
CPU time 37.36 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:29:29 PM PST 24
Peak memory 199796 kb
Host smart-0fdba8c4-09ff-485a-a41d-33770d8145c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607268582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.607268582
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.395713319
Short name T498
Test name
Test status
Simulation time 24115043732 ps
CPU time 19.85 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:29:08 PM PST 24
Peak memory 196524 kb
Host smart-25963d6e-54c2-4660-94ad-a9f0e923fac5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395713319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.395713319
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2261142716
Short name T1170
Test name
Test status
Simulation time 68288181109 ps
CPU time 668.1 seconds
Started Feb 04 12:28:43 PM PST 24
Finished Feb 04 12:39:56 PM PST 24
Peak memory 199744 kb
Host smart-ed65fbf8-b65d-431e-981b-3a134b18e55c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261142716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2261142716
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2502748768
Short name T1083
Test name
Test status
Simulation time 1356956236 ps
CPU time 1.26 seconds
Started Feb 04 12:28:40 PM PST 24
Finished Feb 04 12:28:48 PM PST 24
Peak memory 195280 kb
Host smart-30adaae3-9081-4b2d-afc7-d50d1a1e8ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502748768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2502748768
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1309529146
Short name T684
Test name
Test status
Simulation time 25688763781 ps
CPU time 44.35 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:29:21 PM PST 24
Peak memory 198464 kb
Host smart-fcfbab14-d189-457e-a589-12c875e0185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309529146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1309529146
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1568766407
Short name T1214
Test name
Test status
Simulation time 2902212484 ps
CPU time 164.4 seconds
Started Feb 04 12:28:40 PM PST 24
Finished Feb 04 12:31:31 PM PST 24
Peak memory 199732 kb
Host smart-469aa720-2792-4120-a414-a108c34bbb15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1568766407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1568766407
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3716987774
Short name T880
Test name
Test status
Simulation time 2537907843 ps
CPU time 16.08 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:59 PM PST 24
Peak memory 198244 kb
Host smart-3adb1aae-3ff9-42e4-af3f-97651214ff8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716987774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3716987774
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3152711947
Short name T599
Test name
Test status
Simulation time 206764147542 ps
CPU time 357.02 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:34:45 PM PST 24
Peak memory 199748 kb
Host smart-95a946a0-4826-4465-b584-b36158bd5e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152711947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3152711947
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1044258711
Short name T943
Test name
Test status
Simulation time 2744500640 ps
CPU time 2.77 seconds
Started Feb 04 12:28:43 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 195164 kb
Host smart-41e3f8b9-663e-480f-b8a4-31254af43e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044258711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1044258711
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2032366030
Short name T674
Test name
Test status
Simulation time 715729747 ps
CPU time 2.48 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 198132 kb
Host smart-84ee17c7-f3fa-4b4a-9218-a59c4052d7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032366030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2032366030
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1891702559
Short name T115
Test name
Test status
Simulation time 1035290371721 ps
CPU time 560.1 seconds
Started Feb 04 12:28:40 PM PST 24
Finished Feb 04 12:38:06 PM PST 24
Peak memory 200028 kb
Host smart-f249c770-4d8f-45af-a5b6-c40b23d1b6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891702559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1891702559
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1210929963
Short name T1010
Test name
Test status
Simulation time 1489390745 ps
CPU time 3.28 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 198136 kb
Host smart-27547166-7e86-41d9-959f-47804968d2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210929963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1210929963
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.234851046
Short name T112
Test name
Test status
Simulation time 41359258218 ps
CPU time 58.56 seconds
Started Feb 04 12:28:30 PM PST 24
Finished Feb 04 12:29:37 PM PST 24
Peak memory 199720 kb
Host smart-e3e389d9-fb57-4e51-a710-8df397bbb054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234851046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.234851046
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3570857079
Short name T331
Test name
Test status
Simulation time 69156559887 ps
CPU time 42.49 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:32:18 PM PST 24
Peak memory 199832 kb
Host smart-8ab4cc7f-f7f6-4ab3-af52-dace3bb219e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570857079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3570857079
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2510225263
Short name T980
Test name
Test status
Simulation time 124614427862 ps
CPU time 22.12 seconds
Started Feb 04 12:31:30 PM PST 24
Finished Feb 04 12:31:58 PM PST 24
Peak memory 199804 kb
Host smart-937d93db-95ec-4622-84d1-1b4e041dfe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510225263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2510225263
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3716706659
Short name T595
Test name
Test status
Simulation time 173204374647 ps
CPU time 48.27 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:32:15 PM PST 24
Peak memory 199784 kb
Host smart-8d5e089f-d0b7-42cd-9d58-5148cf9ad299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716706659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3716706659
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2891596469
Short name T259
Test name
Test status
Simulation time 38120792618 ps
CPU time 59.07 seconds
Started Feb 04 12:31:29 PM PST 24
Finished Feb 04 12:32:35 PM PST 24
Peak memory 199744 kb
Host smart-0e55ffe6-a2e5-49b4-97ce-89998d7c7d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891596469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2891596469
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1608098667
Short name T1188
Test name
Test status
Simulation time 106494836817 ps
CPU time 84.65 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:33:00 PM PST 24
Peak memory 199804 kb
Host smart-60abd1f4-1a22-4a33-a670-d0031c5d3e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608098667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1608098667
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3573557834
Short name T555
Test name
Test status
Simulation time 24043433 ps
CPU time 0.54 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 195036 kb
Host smart-7be5b2c7-0714-49d3-b0ad-7fcf4190ca03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573557834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3573557834
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2388673408
Short name T345
Test name
Test status
Simulation time 85884509940 ps
CPU time 35.89 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:29:26 PM PST 24
Peak memory 199708 kb
Host smart-a8533e69-4e60-43d8-a0ee-0f31b8c55b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388673408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2388673408
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.4222933926
Short name T18
Test name
Test status
Simulation time 6271771307 ps
CPU time 10.24 seconds
Started Feb 04 12:28:40 PM PST 24
Finished Feb 04 12:28:57 PM PST 24
Peak memory 199732 kb
Host smart-03378740-c776-43ce-a932-23d54feda8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222933926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4222933926
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2177922031
Short name T1152
Test name
Test status
Simulation time 231654769901 ps
CPU time 281.25 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:33:24 PM PST 24
Peak memory 199912 kb
Host smart-087d7996-cb3c-49ff-9537-d12df5b263a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177922031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2177922031
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2747821235
Short name T1075
Test name
Test status
Simulation time 159723141029 ps
CPU time 138.11 seconds
Started Feb 04 12:28:43 PM PST 24
Finished Feb 04 12:31:06 PM PST 24
Peak memory 198348 kb
Host smart-f23cc468-bc93-47a8-96ef-3f487c731277
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747821235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2747821235
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1491731976
Short name T677
Test name
Test status
Simulation time 125076010473 ps
CPU time 683.96 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:40:17 PM PST 24
Peak memory 199760 kb
Host smart-6f7d70ee-d109-4676-8e72-6da8ed1ab1a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491731976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1491731976
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.157933381
Short name T1218
Test name
Test status
Simulation time 4955317854 ps
CPU time 10.42 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:29:01 PM PST 24
Peak memory 198892 kb
Host smart-d420fe61-52e5-44a6-9ffc-1b96b04cbef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157933381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.157933381
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2452296140
Short name T1142
Test name
Test status
Simulation time 74234392335 ps
CPU time 34.95 seconds
Started Feb 04 12:28:32 PM PST 24
Finished Feb 04 12:29:14 PM PST 24
Peak memory 199816 kb
Host smart-60dae1d0-0266-4447-8a4e-fe648762acb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452296140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2452296140
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.839971003
Short name T406
Test name
Test status
Simulation time 14199605194 ps
CPU time 794.25 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:42:05 PM PST 24
Peak memory 199628 kb
Host smart-6449bada-6652-4134-8945-03d7799a481a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839971003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.839971003
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1675218953
Short name T649
Test name
Test status
Simulation time 81048180293 ps
CPU time 33.24 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:29:26 PM PST 24
Peak memory 199736 kb
Host smart-3576bc3a-e046-4acb-9995-0e232e024960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675218953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1675218953
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2509576633
Short name T805
Test name
Test status
Simulation time 2167913236 ps
CPU time 2.47 seconds
Started Feb 04 12:28:44 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 195176 kb
Host smart-5e34a96c-231a-463b-8614-ab9e48bc165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509576633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2509576633
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.4174106769
Short name T1223
Test name
Test status
Simulation time 504270373 ps
CPU time 2.31 seconds
Started Feb 04 12:28:44 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 198136 kb
Host smart-3d0b7d70-a781-4e7d-9ef1-74950653bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174106769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4174106769
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.4219713439
Short name T1072
Test name
Test status
Simulation time 67086183760 ps
CPU time 57.03 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:29:47 PM PST 24
Peak memory 198448 kb
Host smart-8458b29f-2dd4-48b8-b743-00b3f78fd9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219713439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4219713439
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3960887625
Short name T78
Test name
Test status
Simulation time 387187410196 ps
CPU time 696.06 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:40:07 PM PST 24
Peak memory 229172 kb
Host smart-fcfa8e56-66cb-4bc4-a293-ab5205f98809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960887625 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3960887625
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3299732805
Short name T681
Test name
Test status
Simulation time 1112679139 ps
CPU time 2.76 seconds
Started Feb 04 12:28:44 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 198344 kb
Host smart-a8b4a15e-92b8-442f-a469-3ca106d2d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299732805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3299732805
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3061696518
Short name T450
Test name
Test status
Simulation time 25658750751 ps
CPU time 20.63 seconds
Started Feb 04 12:28:43 PM PST 24
Finished Feb 04 12:29:09 PM PST 24
Peak memory 199264 kb
Host smart-4f85ad97-d639-4acf-9885-0f602e2e6074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061696518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3061696518
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1364387008
Short name T125
Test name
Test status
Simulation time 28420085798 ps
CPU time 49.89 seconds
Started Feb 04 12:31:32 PM PST 24
Finished Feb 04 12:32:26 PM PST 24
Peak memory 199744 kb
Host smart-943d6cbe-0529-4c12-872f-379fbace5a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364387008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1364387008
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.508174100
Short name T119
Test name
Test status
Simulation time 28308162912 ps
CPU time 46.42 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:32:19 PM PST 24
Peak memory 199644 kb
Host smart-92202629-9587-41ff-8032-3896f82dcb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508174100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.508174100
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1660844834
Short name T1189
Test name
Test status
Simulation time 22760055979 ps
CPU time 31.95 seconds
Started Feb 04 12:31:29 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199636 kb
Host smart-0cd39c69-6d4d-43ba-8573-45888365a492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660844834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1660844834
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3255575132
Short name T234
Test name
Test status
Simulation time 31598382049 ps
CPU time 23.71 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:31:50 PM PST 24
Peak memory 198988 kb
Host smart-b4576bdd-5f69-466f-a33e-97c0f76468d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255575132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3255575132
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2560833902
Short name T444
Test name
Test status
Simulation time 23958355764 ps
CPU time 13.32 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:31:49 PM PST 24
Peak memory 199764 kb
Host smart-170aeecc-96a1-45dd-8894-120a271178e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560833902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2560833902
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1337786413
Short name T189
Test name
Test status
Simulation time 52052049483 ps
CPU time 84.12 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:33:00 PM PST 24
Peak memory 199884 kb
Host smart-d35de952-69bc-4f2c-9ce4-76ea6c3879b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337786413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1337786413
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2854836585
Short name T811
Test name
Test status
Simulation time 93367047803 ps
CPU time 17.39 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:31:53 PM PST 24
Peak memory 199788 kb
Host smart-4ef57bf0-a3e8-4a74-a113-e0a4597892e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854836585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2854836585
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2619723565
Short name T518
Test name
Test status
Simulation time 198018152980 ps
CPU time 28.99 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:32:02 PM PST 24
Peak memory 199804 kb
Host smart-980edfbe-da1d-42d4-aaa6-23ecb3778cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619723565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2619723565
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.180903200
Short name T721
Test name
Test status
Simulation time 11575830 ps
CPU time 0.6 seconds
Started Feb 04 12:28:59 PM PST 24
Finished Feb 04 12:29:04 PM PST 24
Peak memory 195216 kb
Host smart-14d9a99e-a862-4853-a655-085d60302aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180903200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.180903200
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2318286907
Short name T894
Test name
Test status
Simulation time 35999224961 ps
CPU time 28.07 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:29:18 PM PST 24
Peak memory 199424 kb
Host smart-348b5f08-496e-4643-a775-cef5e673f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318286907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2318286907
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.566554823
Short name T734
Test name
Test status
Simulation time 40196396535 ps
CPU time 16.96 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:28:58 PM PST 24
Peak memory 199132 kb
Host smart-17768fdc-c48c-4b2d-b94f-b570e32499d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566554823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.566554823
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3887234332
Short name T113
Test name
Test status
Simulation time 36663806829 ps
CPU time 61.09 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:29:53 PM PST 24
Peak memory 199680 kb
Host smart-bada03c2-c67a-4336-a221-abdd0ec0fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887234332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3887234332
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.900388858
Short name T744
Test name
Test status
Simulation time 754450494821 ps
CPU time 1067.3 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:46:39 PM PST 24
Peak memory 198576 kb
Host smart-cd8611a7-9db4-47e5-8bf0-27fb83246993
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900388858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.900388858
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3864369564
Short name T571
Test name
Test status
Simulation time 78734831652 ps
CPU time 193.22 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:32:05 PM PST 24
Peak memory 199836 kb
Host smart-d202bb69-b0b3-43d2-b231-5b68066b1c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864369564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3864369564
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1807183825
Short name T627
Test name
Test status
Simulation time 9913332506 ps
CPU time 9.75 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:53 PM PST 24
Peak memory 198576 kb
Host smart-da6f5cac-824b-4d99-b471-f4f21eb3daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807183825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1807183825
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.757642306
Short name T1198
Test name
Test status
Simulation time 35358692417 ps
CPU time 225.1 seconds
Started Feb 04 12:28:43 PM PST 24
Finished Feb 04 12:32:33 PM PST 24
Peak memory 199748 kb
Host smart-a39126d4-9a68-483d-ae37-6aaa182f6f11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757642306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.757642306
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.236814302
Short name T448
Test name
Test status
Simulation time 1584847801 ps
CPU time 7.54 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:28:55 PM PST 24
Peak memory 197684 kb
Host smart-3d1bfa30-d60b-4111-a3ba-60b2550f7d3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236814302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.236814302
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1804270225
Short name T1123
Test name
Test status
Simulation time 28244390374 ps
CPU time 42.37 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:29:30 PM PST 24
Peak memory 198636 kb
Host smart-82296158-f42a-4a8a-937f-bee73da0f1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804270225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1804270225
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3990196905
Short name T691
Test name
Test status
Simulation time 5328950910 ps
CPU time 8.63 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:29:01 PM PST 24
Peak memory 195560 kb
Host smart-8abbe8f8-7dd9-4eba-872a-ed78d0893bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990196905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3990196905
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.578611475
Short name T1049
Test name
Test status
Simulation time 5989489454 ps
CPU time 17.71 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:01 PM PST 24
Peak memory 199140 kb
Host smart-6e724ffc-45ba-4fa7-b28d-0346d43f89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578611475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.578611475
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.647966558
Short name T376
Test name
Test status
Simulation time 1577458221398 ps
CPU time 809.04 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:42:17 PM PST 24
Peak memory 208240 kb
Host smart-d05b5818-b561-46b3-8e38-787333c807ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647966558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.647966558
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1764934662
Short name T759
Test name
Test status
Simulation time 160153605248 ps
CPU time 704.29 seconds
Started Feb 04 12:28:42 PM PST 24
Finished Feb 04 12:40:32 PM PST 24
Peak memory 212524 kb
Host smart-e6703ac8-deb5-4602-9b9b-4e8d83c562d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764934662 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1764934662
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3767691740
Short name T869
Test name
Test status
Simulation time 1039156361 ps
CPU time 3.1 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:28:45 PM PST 24
Peak memory 198692 kb
Host smart-db80cf30-c80a-4d91-bb3f-16600b0d1d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767691740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3767691740
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3968511847
Short name T906
Test name
Test status
Simulation time 12080234806 ps
CPU time 9.34 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:28:52 PM PST 24
Peak memory 196800 kb
Host smart-2c09ec52-c5e3-4975-b702-62d4f4d9b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968511847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3968511847
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.4249753337
Short name T990
Test name
Test status
Simulation time 103500559170 ps
CPU time 37.6 seconds
Started Feb 04 12:31:29 PM PST 24
Finished Feb 04 12:32:13 PM PST 24
Peak memory 199788 kb
Host smart-87c92ef1-d935-4ef2-a413-3d289c2534c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249753337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.4249753337
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3113721
Short name T895
Test name
Test status
Simulation time 15089694541 ps
CPU time 25.05 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:32:01 PM PST 24
Peak memory 199816 kb
Host smart-2b9d98c0-af93-496f-ac4a-d2ed419a58cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3113721
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.4284331641
Short name T133
Test name
Test status
Simulation time 53683472700 ps
CPU time 23.31 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:31:56 PM PST 24
Peak memory 199792 kb
Host smart-eeda62aa-37d3-4864-912d-56ebaae3dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284331641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4284331641
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2054466883
Short name T245
Test name
Test status
Simulation time 102197073843 ps
CPU time 161.9 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:34:09 PM PST 24
Peak memory 199480 kb
Host smart-5ab384d0-ce94-4727-9f38-4c56877b0a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054466883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2054466883
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2181492123
Short name T1164
Test name
Test status
Simulation time 19143166587 ps
CPU time 29.18 seconds
Started Feb 04 12:31:30 PM PST 24
Finished Feb 04 12:32:05 PM PST 24
Peak memory 199756 kb
Host smart-10159f59-8b3a-4cac-a937-84dab3af7d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181492123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2181492123
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3821312618
Short name T123
Test name
Test status
Simulation time 61655042234 ps
CPU time 23.26 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:31:51 PM PST 24
Peak memory 199440 kb
Host smart-4f6b8875-6619-4b05-b25a-5b06941589b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821312618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3821312618
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3576077160
Short name T774
Test name
Test status
Simulation time 33047593137 ps
CPU time 46.15 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:32:19 PM PST 24
Peak memory 199820 kb
Host smart-a63bcfba-ddb0-47f0-a680-ff22f13d1b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576077160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3576077160
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3097539096
Short name T856
Test name
Test status
Simulation time 11011567 ps
CPU time 0.55 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:28:53 PM PST 24
Peak memory 194160 kb
Host smart-4ccb1635-43a9-4ba0-b288-859ccdb3fb1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097539096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3097539096
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2700710358
Short name T1091
Test name
Test status
Simulation time 124935964014 ps
CPU time 220.75 seconds
Started Feb 04 12:28:48 PM PST 24
Finished Feb 04 12:32:32 PM PST 24
Peak memory 199820 kb
Host smart-34698c94-ad12-4f88-b344-abcb3712a20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700710358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2700710358
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2877493054
Short name T896
Test name
Test status
Simulation time 170399383550 ps
CPU time 261.77 seconds
Started Feb 04 12:28:48 PM PST 24
Finished Feb 04 12:33:12 PM PST 24
Peak memory 199496 kb
Host smart-c3c1dba2-e67e-4aa8-b2b7-1456d2d3398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877493054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2877493054
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.2345217132
Short name T723
Test name
Test status
Simulation time 58842987875 ps
CPU time 24.86 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:29:23 PM PST 24
Peak memory 198388 kb
Host smart-2b21b239-642c-40cb-8ef6-f5a2494231b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345217132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2345217132
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.743168454
Short name T831
Test name
Test status
Simulation time 228674551055 ps
CPU time 174.65 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:31:48 PM PST 24
Peak memory 199784 kb
Host smart-36d90b72-857d-4d62-a4eb-95061f584ff8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743168454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.743168454
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.4210104369
Short name T1019
Test name
Test status
Simulation time 2099099089 ps
CPU time 1.49 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:29:08 PM PST 24
Peak memory 194468 kb
Host smart-ac647564-2f85-465f-97a8-ee42e8c8fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210104369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.4210104369
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1412532019
Short name T1080
Test name
Test status
Simulation time 74836801654 ps
CPU time 102.16 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:30:41 PM PST 24
Peak memory 199496 kb
Host smart-1d761b51-d724-4bbe-87fb-c1e1d965189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412532019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1412532019
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3488430738
Short name T409
Test name
Test status
Simulation time 30236160529 ps
CPU time 1536.23 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:54:35 PM PST 24
Peak memory 199884 kb
Host smart-d1d95539-5a46-4808-9412-cd57414749bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488430738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3488430738
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3136454393
Short name T1207
Test name
Test status
Simulation time 133443578080 ps
CPU time 224.37 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:32:35 PM PST 24
Peak memory 199888 kb
Host smart-8c4baa64-df4e-4b0f-91dc-34401d7876a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136454393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3136454393
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.955515078
Short name T947
Test name
Test status
Simulation time 4905870901 ps
CPU time 2.46 seconds
Started Feb 04 12:28:54 PM PST 24
Finished Feb 04 12:28:58 PM PST 24
Peak memory 195472 kb
Host smart-cf92cf63-701b-4957-9851-5926c604b0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955515078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.955515078
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3249701206
Short name T488
Test name
Test status
Simulation time 268533202 ps
CPU time 1.57 seconds
Started Feb 04 12:28:45 PM PST 24
Finished Feb 04 12:28:51 PM PST 24
Peak memory 198484 kb
Host smart-20b80370-d322-48b1-8385-98979de6cec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249701206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3249701206
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.100897303
Short name T1025
Test name
Test status
Simulation time 13341818227 ps
CPU time 154.04 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:31:40 PM PST 24
Peak memory 208356 kb
Host smart-76d87610-040f-46b9-a9f2-37513eea5853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100897303 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.100897303
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.74822020
Short name T425
Test name
Test status
Simulation time 1865163255 ps
CPU time 1.82 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:29:01 PM PST 24
Peak memory 199764 kb
Host smart-95dbf5ce-2b09-496f-a558-a0bb5774cd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74822020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.74822020
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1360954572
Short name T1201
Test name
Test status
Simulation time 36382584101 ps
CPU time 31.33 seconds
Started Feb 04 12:28:49 PM PST 24
Finished Feb 04 12:29:23 PM PST 24
Peak memory 199664 kb
Host smart-4002c88e-2677-4b43-b95e-3d3354fdefd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360954572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1360954572
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1354233529
Short name T143
Test name
Test status
Simulation time 11712141559 ps
CPU time 19.92 seconds
Started Feb 04 12:31:27 PM PST 24
Finished Feb 04 12:31:53 PM PST 24
Peak memory 199428 kb
Host smart-2cef9ece-891c-42e5-973e-692bd1d70b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354233529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1354233529
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2999816425
Short name T617
Test name
Test status
Simulation time 201021986916 ps
CPU time 41.83 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:32:17 PM PST 24
Peak memory 199776 kb
Host smart-0ffefd27-d125-45ad-bbfe-7048b48f2341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999816425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2999816425
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.875202838
Short name T274
Test name
Test status
Simulation time 85388321441 ps
CPU time 137.27 seconds
Started Feb 04 12:31:29 PM PST 24
Finished Feb 04 12:33:53 PM PST 24
Peak memory 199800 kb
Host smart-5abb49fb-61f8-4ba7-962f-15d1bd786680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875202838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.875202838
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1351852320
Short name T154
Test name
Test status
Simulation time 20889916366 ps
CPU time 10.24 seconds
Started Feb 04 12:31:30 PM PST 24
Finished Feb 04 12:31:46 PM PST 24
Peak memory 199116 kb
Host smart-44920aed-ef73-4470-822a-a310afc47491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351852320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1351852320
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3169206606
Short name T966
Test name
Test status
Simulation time 21457117392 ps
CPU time 23.14 seconds
Started Feb 04 12:31:35 PM PST 24
Finished Feb 04 12:32:00 PM PST 24
Peak memory 199824 kb
Host smart-f557692f-a2e6-4e0f-8b77-78d9109c3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169206606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3169206606
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4231130097
Short name T859
Test name
Test status
Simulation time 51245125822 ps
CPU time 81.4 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:32:57 PM PST 24
Peak memory 199772 kb
Host smart-bcc5367c-2c5f-433f-b5cd-4ea36490c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231130097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4231130097
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3771401589
Short name T839
Test name
Test status
Simulation time 12669337 ps
CPU time 0.56 seconds
Started Feb 04 12:28:51 PM PST 24
Finished Feb 04 12:28:54 PM PST 24
Peak memory 195104 kb
Host smart-996cf8f3-3193-4ac3-a7ad-ab752c1a742a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771401589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3771401589
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2944761216
Short name T1119
Test name
Test status
Simulation time 22094841188 ps
CPU time 46.72 seconds
Started Feb 04 12:28:53 PM PST 24
Finished Feb 04 12:29:42 PM PST 24
Peak memory 199608 kb
Host smart-cbafaf5b-d3ff-4986-99b0-cdd8922982fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944761216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2944761216
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.4226232954
Short name T917
Test name
Test status
Simulation time 85386376363 ps
CPU time 41.5 seconds
Started Feb 04 12:28:55 PM PST 24
Finished Feb 04 12:29:38 PM PST 24
Peak memory 198740 kb
Host smart-7e119e5c-500a-4d3d-84c1-12f68230c037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226232954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4226232954
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1809087256
Short name T871
Test name
Test status
Simulation time 8525789815 ps
CPU time 16.35 seconds
Started Feb 04 12:28:53 PM PST 24
Finished Feb 04 12:29:12 PM PST 24
Peak memory 199684 kb
Host smart-c8f8cdec-ebb9-4e38-82b7-231edbe16d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809087256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1809087256
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.554219359
Short name T956
Test name
Test status
Simulation time 731430093053 ps
CPU time 361.41 seconds
Started Feb 04 12:28:53 PM PST 24
Finished Feb 04 12:34:57 PM PST 24
Peak memory 200032 kb
Host smart-32857895-d4e8-411a-a68e-cbcc63c89c2a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554219359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.554219359
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3735913899
Short name T1131
Test name
Test status
Simulation time 151835131438 ps
CPU time 430.13 seconds
Started Feb 04 12:28:53 PM PST 24
Finished Feb 04 12:36:05 PM PST 24
Peak memory 199972 kb
Host smart-7f9db262-c87b-4490-be8d-9e7128c765ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3735913899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3735913899
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4223889313
Short name T666
Test name
Test status
Simulation time 8816595027 ps
CPU time 15.05 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:29:14 PM PST 24
Peak memory 198824 kb
Host smart-41aec7c1-c024-4dde-a66f-18ced48e2830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223889313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4223889313
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3609211087
Short name T1096
Test name
Test status
Simulation time 68711805148 ps
CPU time 119.4 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:31:06 PM PST 24
Peak memory 199360 kb
Host smart-102d2681-87e4-4640-98ba-2a6b8e181acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609211087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3609211087
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1464424163
Short name T264
Test name
Test status
Simulation time 13766863381 ps
CPU time 787.49 seconds
Started Feb 04 12:28:52 PM PST 24
Finished Feb 04 12:42:02 PM PST 24
Peak memory 200004 kb
Host smart-a9f271c9-4cff-4b68-b131-4817a523f6e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1464424163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1464424163
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3878399682
Short name T758
Test name
Test status
Simulation time 724765818 ps
CPU time 4.18 seconds
Started Feb 04 12:28:51 PM PST 24
Finished Feb 04 12:28:58 PM PST 24
Peak memory 197840 kb
Host smart-c28467b5-2519-4603-85c8-d23ee392a0d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878399682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3878399682
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.131975640
Short name T866
Test name
Test status
Simulation time 99729015242 ps
CPU time 24.46 seconds
Started Feb 04 12:28:58 PM PST 24
Finished Feb 04 12:29:25 PM PST 24
Peak memory 198848 kb
Host smart-56127f8b-cbce-4562-b574-846a6933c35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131975640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.131975640
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3775324341
Short name T782
Test name
Test status
Simulation time 3514556927 ps
CPU time 2.17 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:29:08 PM PST 24
Peak memory 195276 kb
Host smart-25382b2c-89db-4346-94d7-b11268aee611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775324341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3775324341
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2495217764
Short name T844
Test name
Test status
Simulation time 471479934 ps
CPU time 2.06 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:29:08 PM PST 24
Peak memory 198916 kb
Host smart-0041bd55-9aad-4c97-8b59-f2664ca721bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495217764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2495217764
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1306874597
Short name T601
Test name
Test status
Simulation time 541802055127 ps
CPU time 498.63 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:37:12 PM PST 24
Peak memory 199792 kb
Host smart-90e66f12-4b19-4722-8afc-0bc392b62716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306874597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1306874597
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2846873083
Short name T936
Test name
Test status
Simulation time 12371229413 ps
CPU time 33.97 seconds
Started Feb 04 12:28:52 PM PST 24
Finished Feb 04 12:29:29 PM PST 24
Peak memory 199580 kb
Host smart-88e5290d-8c56-4bc6-be31-70c7ff19ff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846873083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2846873083
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1610147759
Short name T658
Test name
Test status
Simulation time 29190590801 ps
CPU time 54.29 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:29:47 PM PST 24
Peak memory 199756 kb
Host smart-9fa722c6-2da4-46cf-b838-15493faea870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610147759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1610147759
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2206266368
Short name T306
Test name
Test status
Simulation time 19364712747 ps
CPU time 30.76 seconds
Started Feb 04 12:31:29 PM PST 24
Finished Feb 04 12:32:06 PM PST 24
Peak memory 199720 kb
Host smart-40f05825-eb2a-4fbb-b7bf-aa90ac9c1632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206266368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2206266368
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.875353793
Short name T144
Test name
Test status
Simulation time 182783472759 ps
CPU time 73.78 seconds
Started Feb 04 12:31:30 PM PST 24
Finished Feb 04 12:32:49 PM PST 24
Peak memory 199892 kb
Host smart-edaa0af4-84f7-4b9c-bd7e-cd8c2758e8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875353793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.875353793
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3837955292
Short name T1109
Test name
Test status
Simulation time 81239832841 ps
CPU time 35.54 seconds
Started Feb 04 12:31:36 PM PST 24
Finished Feb 04 12:32:13 PM PST 24
Peak memory 199740 kb
Host smart-b2fd71b2-7028-4b55-9f9f-a6490bec5a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837955292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3837955292
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1254873046
Short name T848
Test name
Test status
Simulation time 81279596133 ps
CPU time 18.03 seconds
Started Feb 04 12:31:34 PM PST 24
Finished Feb 04 12:31:55 PM PST 24
Peak memory 199748 kb
Host smart-adc4de03-a4e0-4f43-988e-24993e3bb337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254873046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1254873046
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3209292570
Short name T99
Test name
Test status
Simulation time 202837439490 ps
CPU time 191.99 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:34:48 PM PST 24
Peak memory 199852 kb
Host smart-101c8169-0433-4a6f-a3b2-04459509fdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209292570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3209292570
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.4270632141
Short name T205
Test name
Test status
Simulation time 22253020336 ps
CPU time 36.66 seconds
Started Feb 04 12:31:32 PM PST 24
Finished Feb 04 12:32:12 PM PST 24
Peak memory 199688 kb
Host smart-1580b3ba-2823-419e-b6f0-06b8e4ff4dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270632141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4270632141
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3795828051
Short name T698
Test name
Test status
Simulation time 10398376142 ps
CPU time 8.76 seconds
Started Feb 04 12:31:34 PM PST 24
Finished Feb 04 12:31:46 PM PST 24
Peak memory 199104 kb
Host smart-58c0432c-20ee-49ab-b24d-4e440fb5f031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795828051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3795828051
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3113913811
Short name T263
Test name
Test status
Simulation time 101381871632 ps
CPU time 89.88 seconds
Started Feb 04 12:31:30 PM PST 24
Finished Feb 04 12:33:05 PM PST 24
Peak memory 199052 kb
Host smart-48cef72b-ad51-4ed5-a965-e81176f0185f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113913811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3113913811
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.88607494
Short name T905
Test name
Test status
Simulation time 12825962 ps
CPU time 0.56 seconds
Started Feb 04 12:29:00 PM PST 24
Finished Feb 04 12:29:06 PM PST 24
Peak memory 195128 kb
Host smart-3bcc2e8e-193a-4cd1-89bd-e7a7d38fd84f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88607494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.88607494
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3777446865
Short name T729
Test name
Test status
Simulation time 88390887211 ps
CPU time 37.36 seconds
Started Feb 04 12:28:53 PM PST 24
Finished Feb 04 12:29:32 PM PST 24
Peak memory 199844 kb
Host smart-c8df3e9a-1e80-4634-9f20-3ca28df65aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777446865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3777446865
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3441792505
Short name T1006
Test name
Test status
Simulation time 116907499259 ps
CPU time 129.78 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:31:03 PM PST 24
Peak memory 199764 kb
Host smart-a2c5760c-ef53-4c4f-bfc0-642556652ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441792505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3441792505
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1442002536
Short name T731
Test name
Test status
Simulation time 91063201306 ps
CPU time 78.53 seconds
Started Feb 04 12:28:54 PM PST 24
Finished Feb 04 12:30:14 PM PST 24
Peak memory 199792 kb
Host smart-9367d837-b96f-4342-a848-d0c1c3af636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442002536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1442002536
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2310382240
Short name T1051
Test name
Test status
Simulation time 419445890627 ps
CPU time 560.12 seconds
Started Feb 04 12:28:51 PM PST 24
Finished Feb 04 12:38:14 PM PST 24
Peak memory 199552 kb
Host smart-0d089ba1-f016-459c-93d0-cb3ef40d5000
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310382240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2310382240
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.313066421
Short name T562
Test name
Test status
Simulation time 190513436298 ps
CPU time 1435 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:53:12 PM PST 24
Peak memory 199772 kb
Host smart-5e84aa9b-9cdc-441f-97fa-90d3cc3970f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313066421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.313066421
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2310377011
Short name T651
Test name
Test status
Simulation time 5340614628 ps
CPU time 3.62 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:29:21 PM PST 24
Peak memory 198080 kb
Host smart-8c3cf198-b9db-4cdf-8036-62989b764e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310377011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2310377011
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2816223973
Short name T815
Test name
Test status
Simulation time 132792407709 ps
CPU time 379.64 seconds
Started Feb 04 12:28:56 PM PST 24
Finished Feb 04 12:35:17 PM PST 24
Peak memory 198032 kb
Host smart-ec7b1ac9-140a-4ca9-9086-c3ea7a3cfd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816223973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2816223973
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.308678029
Short name T679
Test name
Test status
Simulation time 11481318241 ps
CPU time 638.23 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:39:56 PM PST 24
Peak memory 199644 kb
Host smart-acb770bc-7e71-400d-a12a-f3dc8de15201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308678029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.308678029
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.558680621
Short name T493
Test name
Test status
Simulation time 446694357 ps
CPU time 4.42 seconds
Started Feb 04 12:28:53 PM PST 24
Finished Feb 04 12:29:00 PM PST 24
Peak memory 197700 kb
Host smart-3011d131-6aab-4de0-9879-9aa5ed061556
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558680621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.558680621
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2289829884
Short name T34
Test name
Test status
Simulation time 35175140482 ps
CPU time 34.03 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:29:40 PM PST 24
Peak memory 199740 kb
Host smart-60d10086-aaec-4318-8f29-6d628b6b8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289829884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2289829884
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.855999103
Short name T434
Test name
Test status
Simulation time 2658835303 ps
CPU time 2.48 seconds
Started Feb 04 12:28:51 PM PST 24
Finished Feb 04 12:28:56 PM PST 24
Peak memory 195200 kb
Host smart-4d97e02f-adb2-466f-9bce-dc35ba15cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855999103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.855999103
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1295836324
Short name T1136
Test name
Test status
Simulation time 508001760 ps
CPU time 2.32 seconds
Started Feb 04 12:28:54 PM PST 24
Finished Feb 04 12:28:58 PM PST 24
Peak memory 197932 kb
Host smart-0c326264-7e27-45bf-99e6-b5c660c47740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295836324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1295836324
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2602471699
Short name T577
Test name
Test status
Simulation time 8476613600 ps
CPU time 1.67 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:28:59 PM PST 24
Peak memory 197972 kb
Host smart-e3bb01db-7b99-4cea-b422-147277bf345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602471699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2602471699
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.970476491
Short name T997
Test name
Test status
Simulation time 49812919154 ps
CPU time 21.81 seconds
Started Feb 04 12:28:51 PM PST 24
Finished Feb 04 12:29:16 PM PST 24
Peak memory 199952 kb
Host smart-c80d61e8-7ebf-4df5-a366-9f95e734b795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970476491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.970476491
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2610274553
Short name T229
Test name
Test status
Simulation time 3643854392 ps
CPU time 3.22 seconds
Started Feb 04 12:31:35 PM PST 24
Finished Feb 04 12:31:40 PM PST 24
Peak memory 197792 kb
Host smart-26ad9653-2c0d-453a-b8c0-fb10175c4d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610274553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2610274553
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2365677726
Short name T209
Test name
Test status
Simulation time 188909377893 ps
CPU time 77.38 seconds
Started Feb 04 12:31:34 PM PST 24
Finished Feb 04 12:32:54 PM PST 24
Peak memory 199844 kb
Host smart-57dd66d9-c862-4224-be6f-4cd800a969f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365677726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2365677726
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3788240701
Short name T1209
Test name
Test status
Simulation time 203589132493 ps
CPU time 383.09 seconds
Started Feb 04 12:31:29 PM PST 24
Finished Feb 04 12:37:59 PM PST 24
Peak memory 199756 kb
Host smart-3b085da3-feaa-453e-b08b-66f93369402d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788240701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3788240701
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1622358563
Short name T221
Test name
Test status
Simulation time 76478878978 ps
CPU time 30.2 seconds
Started Feb 04 12:31:31 PM PST 24
Finished Feb 04 12:32:06 PM PST 24
Peak memory 199748 kb
Host smart-13223cbe-8ecd-467c-83a3-906c959dae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622358563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1622358563
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3576227403
Short name T110
Test name
Test status
Simulation time 19526032460 ps
CPU time 28.65 seconds
Started Feb 04 12:31:34 PM PST 24
Finished Feb 04 12:32:06 PM PST 24
Peak memory 198516 kb
Host smart-5787924f-2a44-4844-8e1b-2d1098214d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576227403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3576227403
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1456142867
Short name T841
Test name
Test status
Simulation time 40147741464 ps
CPU time 70.25 seconds
Started Feb 04 12:31:33 PM PST 24
Finished Feb 04 12:32:46 PM PST 24
Peak memory 199788 kb
Host smart-e6be1b02-0702-4e4b-b971-0e79d3186262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456142867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1456142867
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2990883933
Short name T635
Test name
Test status
Simulation time 376757240571 ps
CPU time 779.85 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:42:17 PM PST 24
Peak memory 199800 kb
Host smart-fe4daeb7-5592-4080-940a-2a923a178cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990883933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2990883933
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.191430346
Short name T1205
Test name
Test status
Simulation time 75728122687 ps
CPU time 123.15 seconds
Started Feb 04 12:29:00 PM PST 24
Finished Feb 04 12:31:08 PM PST 24
Peak memory 199612 kb
Host smart-d138fd8a-c961-49d6-b83c-03194f4e8ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191430346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.191430346
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3813851631
Short name T237
Test name
Test status
Simulation time 69603166350 ps
CPU time 114.47 seconds
Started Feb 04 12:29:01 PM PST 24
Finished Feb 04 12:31:00 PM PST 24
Peak memory 199396 kb
Host smart-277e9fbb-ead3-4d69-8065-98a321ba46e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813851631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3813851631
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.42847241
Short name T915
Test name
Test status
Simulation time 91100606547 ps
CPU time 67.7 seconds
Started Feb 04 12:29:10 PM PST 24
Finished Feb 04 12:30:25 PM PST 24
Peak memory 199772 kb
Host smart-2aa634c2-6cb7-4db3-92fa-9cf14cdb022e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42847241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.42847241
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3569724563
Short name T1086
Test name
Test status
Simulation time 90113497087 ps
CPU time 329.92 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:34:47 PM PST 24
Peak memory 199800 kb
Host smart-c7089af6-24cb-4ba6-b910-2e78e26d4cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569724563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3569724563
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2770612241
Short name T597
Test name
Test status
Simulation time 8523847885 ps
CPU time 16.47 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 198432 kb
Host smart-94a2a2e9-f58f-450f-8496-14f111aa3755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770612241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2770612241
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3837264661
Short name T925
Test name
Test status
Simulation time 39894210307 ps
CPU time 67.36 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:30:27 PM PST 24
Peak memory 199904 kb
Host smart-a4972e29-d76e-4d0a-8644-d4f8f9892de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837264661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3837264661
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.576136425
Short name T549
Test name
Test status
Simulation time 32842821305 ps
CPU time 498.42 seconds
Started Feb 04 12:28:58 PM PST 24
Finished Feb 04 12:37:20 PM PST 24
Peak memory 199976 kb
Host smart-e9048619-3dd7-4778-ab9d-e1cea3d477b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576136425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.576136425
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1347830811
Short name T1230
Test name
Test status
Simulation time 2289788372 ps
CPU time 23.46 seconds
Started Feb 04 12:29:07 PM PST 24
Finished Feb 04 12:29:36 PM PST 24
Peak memory 197724 kb
Host smart-f02abfdc-107d-4bfa-aef9-e5d7838ca3ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347830811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1347830811
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.456956992
Short name T356
Test name
Test status
Simulation time 158659051286 ps
CPU time 67.87 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:30:25 PM PST 24
Peak memory 198940 kb
Host smart-23733ef5-0e17-421d-bc71-4f2022af0e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456956992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.456956992
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3011952727
Short name T1231
Test name
Test status
Simulation time 3936365359 ps
CPU time 7.12 seconds
Started Feb 04 12:28:54 PM PST 24
Finished Feb 04 12:29:03 PM PST 24
Peak memory 195468 kb
Host smart-07f7f4ab-0005-4ead-84cb-c4c3d6798455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011952727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3011952727
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1714524608
Short name T994
Test name
Test status
Simulation time 974537945 ps
CPU time 4.04 seconds
Started Feb 04 12:28:57 PM PST 24
Finished Feb 04 12:29:03 PM PST 24
Peak memory 198144 kb
Host smart-bca48818-2f51-4ca3-bc5f-ed81fff4d75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714524608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1714524608
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1328389431
Short name T187
Test name
Test status
Simulation time 72719479632 ps
CPU time 1084.66 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 226280 kb
Host smart-7b7b4c47-df76-4dd8-b742-22cb08f555d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328389431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1328389431
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.643986434
Short name T35
Test name
Test status
Simulation time 1720193734 ps
CPU time 1.59 seconds
Started Feb 04 12:28:58 PM PST 24
Finished Feb 04 12:29:03 PM PST 24
Peak memory 197312 kb
Host smart-f31b8f75-5666-4322-b931-ed5fd41c7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643986434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.643986434
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.15144209
Short name T1219
Test name
Test status
Simulation time 45178087152 ps
CPU time 66.5 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:30:22 PM PST 24
Peak memory 199768 kb
Host smart-e9680890-50da-48e7-a19a-bba3cde5ccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15144209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.15144209
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.562096657
Short name T140
Test name
Test status
Simulation time 39884715978 ps
CPU time 75.97 seconds
Started Feb 04 12:31:34 PM PST 24
Finished Feb 04 12:32:53 PM PST 24
Peak memory 199824 kb
Host smart-a79a1b83-2b3e-4468-8f08-f53d53767301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562096657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.562096657
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3555358452
Short name T158
Test name
Test status
Simulation time 29795976390 ps
CPU time 27.37 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:31:55 PM PST 24
Peak memory 199928 kb
Host smart-228766e2-1780-4b0d-9909-37391ccd0265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555358452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3555358452
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.799361702
Short name T214
Test name
Test status
Simulation time 77414849356 ps
CPU time 122.73 seconds
Started Feb 04 12:31:29 PM PST 24
Finished Feb 04 12:33:38 PM PST 24
Peak memory 199856 kb
Host smart-4083d288-4c19-431b-8faa-4044d8129aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799361702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.799361702
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3088222864
Short name T122
Test name
Test status
Simulation time 110226567275 ps
CPU time 158.65 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:34:20 PM PST 24
Peak memory 199448 kb
Host smart-d8c2054d-f30c-4ea9-ab54-075f9f6e04dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088222864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3088222864
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2829996235
Short name T1225
Test name
Test status
Simulation time 203527527101 ps
CPU time 18.83 seconds
Started Feb 04 12:31:44 PM PST 24
Finished Feb 04 12:32:04 PM PST 24
Peak memory 199972 kb
Host smart-542401af-c2b8-4fe0-ac76-5a08de665f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829996235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2829996235
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3135941703
Short name T948
Test name
Test status
Simulation time 10359622371 ps
CPU time 15.11 seconds
Started Feb 04 12:31:43 PM PST 24
Finished Feb 04 12:31:59 PM PST 24
Peak memory 199552 kb
Host smart-4e9616cf-8592-499a-ba0e-91f683a9787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135941703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3135941703
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3473709586
Short name T255
Test name
Test status
Simulation time 14613654231 ps
CPU time 30.23 seconds
Started Feb 04 12:31:39 PM PST 24
Finished Feb 04 12:32:10 PM PST 24
Peak memory 199304 kb
Host smart-df021c22-dbe0-410e-bd6c-945ee44191e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473709586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3473709586
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1880598501
Short name T181
Test name
Test status
Simulation time 114954712537 ps
CPU time 188.33 seconds
Started Feb 04 12:31:39 PM PST 24
Finished Feb 04 12:34:49 PM PST 24
Peak memory 199856 kb
Host smart-2223e9f8-e3c2-428a-8606-4487746cf2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880598501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1880598501
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3645644405
Short name T1073
Test name
Test status
Simulation time 11087315 ps
CPU time 0.52 seconds
Started Feb 04 12:29:07 PM PST 24
Finished Feb 04 12:29:14 PM PST 24
Peak memory 195156 kb
Host smart-09658883-a58f-4a5d-922f-208da215140a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645644405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3645644405
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.280426832
Short name T531
Test name
Test status
Simulation time 31191310302 ps
CPU time 13.95 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:29:31 PM PST 24
Peak memory 197672 kb
Host smart-28ad04dc-be83-4a68-a2fe-aee2e0c16265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280426832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.280426832
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.422210493
Short name T1067
Test name
Test status
Simulation time 609866032976 ps
CPU time 504.91 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:37:42 PM PST 24
Peak memory 199852 kb
Host smart-43611fbf-39d8-4965-ab8a-eb7953384371
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422210493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.422210493
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3516806722
Short name T822
Test name
Test status
Simulation time 88757899806 ps
CPU time 190.56 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:32:28 PM PST 24
Peak memory 199864 kb
Host smart-937d5d09-86a2-40d6-9244-b4002cdc7fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516806722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3516806722
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.443567043
Short name T983
Test name
Test status
Simulation time 2528998641 ps
CPU time 5.71 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:29:23 PM PST 24
Peak memory 198388 kb
Host smart-64d44065-d419-4793-92ef-176141f17777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443567043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.443567043
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3181515487
Short name T116
Test name
Test status
Simulation time 61054544576 ps
CPU time 32.05 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:29:49 PM PST 24
Peak memory 199700 kb
Host smart-990ad81f-4d06-42ed-a3d7-04eee9f12264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181515487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3181515487
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2521462737
Short name T726
Test name
Test status
Simulation time 19699296025 ps
CPU time 891.18 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:44:14 PM PST 24
Peak memory 199124 kb
Host smart-e9e2b3a0-6d1d-4f87-a588-70968ce265e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2521462737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2521462737
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.4251941034
Short name T353
Test name
Test status
Simulation time 31664375968 ps
CPU time 21.3 seconds
Started Feb 04 12:29:02 PM PST 24
Finished Feb 04 12:29:27 PM PST 24
Peak memory 199552 kb
Host smart-327120ee-abea-4754-8dd6-7646d008632b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251941034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.4251941034
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1699056941
Short name T532
Test name
Test status
Simulation time 3756544871 ps
CPU time 2.31 seconds
Started Feb 04 12:28:58 PM PST 24
Finished Feb 04 12:29:05 PM PST 24
Peak memory 195488 kb
Host smart-bbdd8889-b9b1-4a0f-8c23-12fce6da702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699056941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1699056941
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.241387456
Short name T598
Test name
Test status
Simulation time 468097089 ps
CPU time 1.29 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:29:19 PM PST 24
Peak memory 199492 kb
Host smart-e37d8dee-37b8-4415-8f4c-6dd7617b6a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241387456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.241387456
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2076890780
Short name T508
Test name
Test status
Simulation time 1779979472 ps
CPU time 1.97 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:29:19 PM PST 24
Peak memory 198180 kb
Host smart-cb69402d-acbe-476e-bc50-96254efe3625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076890780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2076890780
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1323080557
Short name T1058
Test name
Test status
Simulation time 73897200557 ps
CPU time 83.23 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:30:42 PM PST 24
Peak memory 199840 kb
Host smart-51faf17a-6032-47dc-b7c3-00f6fa113a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323080557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1323080557
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1228279546
Short name T951
Test name
Test status
Simulation time 3977645822 ps
CPU time 9.57 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:31:52 PM PST 24
Peak memory 199660 kb
Host smart-1e4448f4-c5e2-459d-a2df-f3514ef8c681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228279546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1228279546
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2687979266
Short name T922
Test name
Test status
Simulation time 179905992747 ps
CPU time 30.69 seconds
Started Feb 04 12:31:43 PM PST 24
Finished Feb 04 12:32:15 PM PST 24
Peak memory 199816 kb
Host smart-c50dc2bc-4aca-45bf-b752-94929b68083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687979266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2687979266
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1782771468
Short name T718
Test name
Test status
Simulation time 32009141820 ps
CPU time 40.66 seconds
Started Feb 04 12:31:44 PM PST 24
Finished Feb 04 12:32:26 PM PST 24
Peak memory 199736 kb
Host smart-11e12cb0-cc6d-476c-a9f7-3cddc20ebfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782771468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1782771468
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3548091623
Short name T1057
Test name
Test status
Simulation time 107837641271 ps
CPU time 503.22 seconds
Started Feb 04 12:31:48 PM PST 24
Finished Feb 04 12:40:15 PM PST 24
Peak memory 199656 kb
Host smart-b986a348-bcc5-44e2-afd5-b1cddb8c35ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548091623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3548091623
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.854497345
Short name T1005
Test name
Test status
Simulation time 3297612042 ps
CPU time 5.9 seconds
Started Feb 04 12:31:40 PM PST 24
Finished Feb 04 12:31:47 PM PST 24
Peak memory 198644 kb
Host smart-bbe4540c-694e-419a-8fc4-50be87fc4d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854497345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.854497345
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1784578531
Short name T19
Test name
Test status
Simulation time 95824055870 ps
CPU time 38.97 seconds
Started Feb 04 12:31:40 PM PST 24
Finished Feb 04 12:32:20 PM PST 24
Peak memory 198032 kb
Host smart-89555219-471c-4ecd-b0b3-354e860ebcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784578531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1784578531
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.689527360
Short name T95
Test name
Test status
Simulation time 15390064 ps
CPU time 0.57 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:29:20 PM PST 24
Peak memory 195204 kb
Host smart-13806349-7d8e-4605-866d-b2e440659132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689527360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.689527360
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2257502953
Short name T1095
Test name
Test status
Simulation time 292729238167 ps
CPU time 118.56 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:31:16 PM PST 24
Peak memory 199704 kb
Host smart-350b7a1f-4d49-432d-86bb-cc5de387903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257502953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2257502953
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.763781315
Short name T105
Test name
Test status
Simulation time 170208086501 ps
CPU time 62.31 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:30:19 PM PST 24
Peak memory 199316 kb
Host smart-94fcc0e6-7180-401b-a686-729ba53dd49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763781315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.763781315
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.797553319
Short name T177
Test name
Test status
Simulation time 45773596907 ps
CPU time 73.15 seconds
Started Feb 04 12:29:05 PM PST 24
Finished Feb 04 12:30:20 PM PST 24
Peak memory 199244 kb
Host smart-9dc1eb22-8ee8-456b-8929-8503e621831b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797553319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.797553319
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3212867627
Short name T680
Test name
Test status
Simulation time 331376778250 ps
CPU time 541.68 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:38:25 PM PST 24
Peak memory 199020 kb
Host smart-69fa51e2-e1c0-4d66-8afb-daff95f0acd2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212867627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3212867627
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.411820886
Short name T1172
Test name
Test status
Simulation time 86366454383 ps
CPU time 385.38 seconds
Started Feb 04 12:29:17 PM PST 24
Finished Feb 04 12:35:48 PM PST 24
Peak memory 199772 kb
Host smart-0f78750e-58f6-42f7-b275-c3661b2d261a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411820886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.411820886
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3143932484
Short name T509
Test name
Test status
Simulation time 1163847003 ps
CPU time 2.44 seconds
Started Feb 04 12:29:12 PM PST 24
Finished Feb 04 12:29:20 PM PST 24
Peak memory 196196 kb
Host smart-6aeeb5c1-8de0-4289-90cd-a66fa5abc4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143932484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3143932484
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3200558874
Short name T1039
Test name
Test status
Simulation time 43986471489 ps
CPU time 75.51 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:30:35 PM PST 24
Peak memory 198408 kb
Host smart-21ef40c1-db57-4c89-8d8b-d9b62e1f69cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200558874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3200558874
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3283233800
Short name T1203
Test name
Test status
Simulation time 23290067474 ps
CPU time 97.04 seconds
Started Feb 04 12:29:06 PM PST 24
Finished Feb 04 12:30:45 PM PST 24
Peak memory 199748 kb
Host smart-12359bed-256f-46b8-a2ab-2c39941403d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283233800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3283233800
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1267298804
Short name T767
Test name
Test status
Simulation time 28399566044 ps
CPU time 42.32 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:30:05 PM PST 24
Peak memory 198892 kb
Host smart-f64b55d3-bb13-4d74-a0f6-09b8bdcfc3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267298804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1267298804
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3448761284
Short name T683
Test name
Test status
Simulation time 28107453745 ps
CPU time 9.65 seconds
Started Feb 04 12:29:05 PM PST 24
Finished Feb 04 12:29:17 PM PST 24
Peak memory 195548 kb
Host smart-09327e32-4274-4bf0-a36d-6fb2c9d9c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448761284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3448761284
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2110551705
Short name T1081
Test name
Test status
Simulation time 100237452 ps
CPU time 0.89 seconds
Started Feb 04 12:29:07 PM PST 24
Finished Feb 04 12:29:16 PM PST 24
Peak memory 196376 kb
Host smart-033324da-6154-44ed-a334-cbc0dbbef9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110551705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2110551705
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.476841631
Short name T231
Test name
Test status
Simulation time 301361884254 ps
CPU time 427.23 seconds
Started Feb 04 12:29:05 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 199860 kb
Host smart-6294f5d2-ad75-479f-8ea9-0aed0dec691c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476841631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.476841631
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3535704461
Short name T334
Test name
Test status
Simulation time 310505760039 ps
CPU time 1245.93 seconds
Started Feb 04 12:29:12 PM PST 24
Finished Feb 04 12:50:03 PM PST 24
Peak memory 224724 kb
Host smart-bbbb81e7-4469-43c5-ae38-d1b418faedec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535704461 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3535704461
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1654369178
Short name T431
Test name
Test status
Simulation time 6659108267 ps
CPU time 20.33 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 199220 kb
Host smart-b51d17fa-231e-4fb1-b092-2f670ef11ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654369178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1654369178
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4219306858
Short name T588
Test name
Test status
Simulation time 39981156599 ps
CPU time 55.21 seconds
Started Feb 04 12:29:10 PM PST 24
Finished Feb 04 12:30:12 PM PST 24
Peak memory 199740 kb
Host smart-5c6b3738-3cbd-4584-8eca-7d0e8d569f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219306858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4219306858
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2433347575
Short name T745
Test name
Test status
Simulation time 20004747864 ps
CPU time 52.93 seconds
Started Feb 04 12:31:47 PM PST 24
Finished Feb 04 12:32:41 PM PST 24
Peak memory 199796 kb
Host smart-51db8c30-61e2-4bce-b330-b06ab6eff287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433347575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2433347575
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4081742896
Short name T326
Test name
Test status
Simulation time 34488854843 ps
CPU time 45.57 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:32:28 PM PST 24
Peak memory 199348 kb
Host smart-ce1b801c-50a7-40f9-a1bf-989522d2f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081742896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4081742896
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.619498968
Short name T262
Test name
Test status
Simulation time 106918557515 ps
CPU time 24.57 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199784 kb
Host smart-b6e42d44-ce92-48f5-8eb7-8a108fc02f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619498968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.619498968
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1124365107
Short name T411
Test name
Test status
Simulation time 178303388518 ps
CPU time 24.4 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199660 kb
Host smart-03a3e5d7-a515-454f-8f03-debc7d82825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124365107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1124365107
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1886145186
Short name T964
Test name
Test status
Simulation time 42834205139 ps
CPU time 43.7 seconds
Started Feb 04 12:31:42 PM PST 24
Finished Feb 04 12:32:27 PM PST 24
Peak memory 199896 kb
Host smart-6ff81528-bf75-4565-8f38-8fe60cc97e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886145186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1886145186
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3525234243
Short name T1033
Test name
Test status
Simulation time 31895562948 ps
CPU time 53.03 seconds
Started Feb 04 12:31:51 PM PST 24
Finished Feb 04 12:32:48 PM PST 24
Peak memory 199396 kb
Host smart-bafd82df-0e63-4375-9fb7-608f6bae4f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525234243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3525234243
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4186520819
Short name T381
Test name
Test status
Simulation time 60153225357 ps
CPU time 26.2 seconds
Started Feb 04 12:31:39 PM PST 24
Finished Feb 04 12:32:06 PM PST 24
Peak memory 199340 kb
Host smart-dab84751-b36d-4d3a-a861-d62c2262f5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186520819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4186520819
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.230774046
Short name T280
Test name
Test status
Simulation time 107756967980 ps
CPU time 63.24 seconds
Started Feb 04 12:31:51 PM PST 24
Finished Feb 04 12:32:58 PM PST 24
Peak memory 199768 kb
Host smart-73f8d99e-a388-49cf-a54c-edb501599cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230774046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.230774046
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2206958594
Short name T487
Test name
Test status
Simulation time 61252666 ps
CPU time 0.54 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:34 PM PST 24
Peak memory 195140 kb
Host smart-641f4c3f-3a63-4748-a497-00253bb6adfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206958594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2206958594
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1542254461
Short name T928
Test name
Test status
Simulation time 60651637457 ps
CPU time 52.77 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:29:04 PM PST 24
Peak memory 199560 kb
Host smart-795148f9-e8bf-46a8-aba3-a16b3397e558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542254461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1542254461
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2432892283
Short name T278
Test name
Test status
Simulation time 51978769011 ps
CPU time 87.07 seconds
Started Feb 04 12:28:15 PM PST 24
Finished Feb 04 12:29:51 PM PST 24
Peak memory 199776 kb
Host smart-2131c101-2ae2-4a83-9e2d-4d1b44822b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432892283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2432892283
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3359215170
Short name T147
Test name
Test status
Simulation time 78392925569 ps
CPU time 40.66 seconds
Started Feb 04 12:28:16 PM PST 24
Finished Feb 04 12:29:04 PM PST 24
Peak memory 199736 kb
Host smart-4cd1f3d5-43c6-462c-b0c2-8fee957c8341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359215170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3359215170
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1083886062
Short name T570
Test name
Test status
Simulation time 151218328177 ps
CPU time 68.16 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:29:19 PM PST 24
Peak memory 198272 kb
Host smart-c74b4658-7d47-4fdf-85ed-d73235df1fb8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083886062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1083886062
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1258403534
Short name T1124
Test name
Test status
Simulation time 233211712176 ps
CPU time 314.87 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:33:52 PM PST 24
Peak memory 199724 kb
Host smart-368fe163-b0e2-4151-ba6a-ae4784ee5512
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1258403534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1258403534
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.4270524437
Short name T520
Test name
Test status
Simulation time 2242836073 ps
CPU time 1.2 seconds
Started Feb 04 12:28:28 PM PST 24
Finished Feb 04 12:28:36 PM PST 24
Peak memory 195268 kb
Host smart-8a7eff27-7d82-4f58-9179-f1b152354545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270524437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.4270524437
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3258452988
Short name T623
Test name
Test status
Simulation time 44247406704 ps
CPU time 72.18 seconds
Started Feb 04 12:28:28 PM PST 24
Finished Feb 04 12:29:47 PM PST 24
Peak memory 208244 kb
Host smart-52648cf9-844b-47fb-80ff-d1559fac668c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258452988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3258452988
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.2374834208
Short name T992
Test name
Test status
Simulation time 19328964649 ps
CPU time 799.11 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:41:53 PM PST 24
Peak memory 199896 kb
Host smart-8d219fbd-7d10-4fa2-8e2a-4381dc3845ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374834208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2374834208
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.465874337
Short name T545
Test name
Test status
Simulation time 2658665186 ps
CPU time 17.18 seconds
Started Feb 04 12:28:15 PM PST 24
Finished Feb 04 12:28:41 PM PST 24
Peak memory 197672 kb
Host smart-9b524e7c-38af-404a-a79e-738ce7a496c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=465874337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.465874337
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1388308332
Short name T560
Test name
Test status
Simulation time 161556865688 ps
CPU time 146.57 seconds
Started Feb 04 12:28:28 PM PST 24
Finished Feb 04 12:31:01 PM PST 24
Peak memory 199804 kb
Host smart-15eca403-f693-4e9c-b929-c78d5fe5a1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388308332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1388308332
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.45634630
Short name T1038
Test name
Test status
Simulation time 2363674432 ps
CPU time 4.26 seconds
Started Feb 04 12:28:33 PM PST 24
Finished Feb 04 12:28:44 PM PST 24
Peak memory 195176 kb
Host smart-bfb24444-78fe-4bdc-bd41-732879753e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45634630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.45634630
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2549036246
Short name T98
Test name
Test status
Simulation time 61870249 ps
CPU time 0.85 seconds
Started Feb 04 12:28:17 PM PST 24
Finished Feb 04 12:28:26 PM PST 24
Peak memory 217248 kb
Host smart-a9c35dda-67d5-4602-9732-e834c0448f05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549036246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2549036246
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3210496878
Short name T573
Test name
Test status
Simulation time 5874500468 ps
CPU time 12.53 seconds
Started Feb 04 12:28:06 PM PST 24
Finished Feb 04 12:28:22 PM PST 24
Peak memory 199056 kb
Host smart-bc5b7191-2fca-4e81-aed2-3673f528701b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210496878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3210496878
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2164897102
Short name T728
Test name
Test status
Simulation time 49217266864 ps
CPU time 39.08 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:29:11 PM PST 24
Peak memory 199844 kb
Host smart-c7c74a22-c367-42ff-8938-65ed3ea552ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164897102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2164897102
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3564490817
Short name T867
Test name
Test status
Simulation time 24877543394 ps
CPU time 229.64 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:32:23 PM PST 24
Peak memory 212660 kb
Host smart-d4d6f15d-0da4-4040-a13a-16d41b0fc586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564490817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3564490817
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.661544598
Short name T824
Test name
Test status
Simulation time 724006286 ps
CPU time 2.46 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:28:39 PM PST 24
Peak memory 197664 kb
Host smart-a4829130-bb26-4b56-977e-e2b001b1e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661544598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.661544598
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1871062952
Short name T1138
Test name
Test status
Simulation time 39883101162 ps
CPU time 79.82 seconds
Started Feb 04 12:28:07 PM PST 24
Finished Feb 04 12:29:31 PM PST 24
Peak memory 199804 kb
Host smart-c39a1e0f-3b25-438e-a7bf-d7a867bac27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871062952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1871062952
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.4144652127
Short name T877
Test name
Test status
Simulation time 28656469 ps
CPU time 0.56 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:30:00 PM PST 24
Peak memory 195184 kb
Host smart-2c672a9a-b2d2-4262-b764-560a9e4cc102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144652127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4144652127
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.558826711
Short name T913
Test name
Test status
Simulation time 23727785616 ps
CPU time 32.27 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:29:51 PM PST 24
Peak memory 199620 kb
Host smart-30ee7647-93a9-46c3-b8d9-f2efc65727e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558826711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.558826711
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2253023142
Short name T1011
Test name
Test status
Simulation time 75960168879 ps
CPU time 26.81 seconds
Started Feb 04 12:29:11 PM PST 24
Finished Feb 04 12:29:44 PM PST 24
Peak memory 197392 kb
Host smart-60861ae1-3f08-4f4e-8d92-2c4c902324b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253023142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2253023142
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.739257658
Short name T1116
Test name
Test status
Simulation time 467311427231 ps
CPU time 879.14 seconds
Started Feb 04 12:29:06 PM PST 24
Finished Feb 04 12:43:47 PM PST 24
Peak memory 199784 kb
Host smart-f6e0ddb9-e1fe-435a-8377-09c4ca0c5907
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739257658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.739257658
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4216315769
Short name T1036
Test name
Test status
Simulation time 245366687600 ps
CPU time 250.51 seconds
Started Feb 04 12:29:12 PM PST 24
Finished Feb 04 12:33:28 PM PST 24
Peak memory 199692 kb
Host smart-d573301b-ceb4-4e5a-8df9-07e1b00486a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216315769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4216315769
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.428157048
Short name T1018
Test name
Test status
Simulation time 4670644276 ps
CPU time 5.09 seconds
Started Feb 04 12:29:11 PM PST 24
Finished Feb 04 12:29:22 PM PST 24
Peak memory 197948 kb
Host smart-0e9e0b8c-5592-42d8-a45c-eb667ff8e152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428157048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.428157048
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.151219251
Short name T517
Test name
Test status
Simulation time 46741429525 ps
CPU time 19.2 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:29:37 PM PST 24
Peak memory 198024 kb
Host smart-e52d22c0-437c-4c0d-b39e-dea2690ae4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151219251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.151219251
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.4283895103
Short name T1053
Test name
Test status
Simulation time 10885459032 ps
CPU time 325.23 seconds
Started Feb 04 12:29:11 PM PST 24
Finished Feb 04 12:34:43 PM PST 24
Peak memory 199780 kb
Host smart-ecf442e8-e5c0-47cd-b063-66308f02794f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283895103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.4283895103
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3531865525
Short name T1191
Test name
Test status
Simulation time 55240506147 ps
CPU time 84.5 seconds
Started Feb 04 12:29:07 PM PST 24
Finished Feb 04 12:30:38 PM PST 24
Peak memory 199828 kb
Host smart-9eedb6f4-64de-4762-85ae-721003757977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531865525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3531865525
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3585690040
Short name T746
Test name
Test status
Simulation time 6000135609 ps
CPU time 3.05 seconds
Started Feb 04 12:29:11 PM PST 24
Finished Feb 04 12:29:20 PM PST 24
Peak memory 195172 kb
Host smart-b564c3b7-85a7-44b7-a5a6-c70f297edb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585690040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3585690040
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.4089678125
Short name T923
Test name
Test status
Simulation time 100789287 ps
CPU time 0.94 seconds
Started Feb 04 12:29:17 PM PST 24
Finished Feb 04 12:29:24 PM PST 24
Peak memory 197328 kb
Host smart-ccb51a88-6df3-456c-94f8-b909de652e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089678125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.4089678125
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1395317847
Short name T592
Test name
Test status
Simulation time 733927177810 ps
CPU time 691.01 seconds
Started Feb 04 12:29:12 PM PST 24
Finished Feb 04 12:40:49 PM PST 24
Peak memory 200056 kb
Host smart-e7dbaeb8-9be8-491d-898e-6e6a53cccd1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395317847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1395317847
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2829951003
Short name T428
Test name
Test status
Simulation time 2000865236 ps
CPU time 2.1 seconds
Started Feb 04 12:29:11 PM PST 24
Finished Feb 04 12:29:19 PM PST 24
Peak memory 198516 kb
Host smart-b7e3fce4-bb10-4127-a89a-97017c880653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829951003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2829951003
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2946242590
Short name T735
Test name
Test status
Simulation time 11696185692 ps
CPU time 16.39 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:29:36 PM PST 24
Peak memory 199572 kb
Host smart-6864b928-5930-485f-845e-d9ba470b7dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946242590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2946242590
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1227621862
Short name T1023
Test name
Test status
Simulation time 58043073222 ps
CPU time 22.52 seconds
Started Feb 04 12:31:43 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199864 kb
Host smart-17739b6e-4ea9-4bf5-a68a-b89e18cb3c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227621862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1227621862
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3905240484
Short name T142
Test name
Test status
Simulation time 40649495266 ps
CPU time 21.37 seconds
Started Feb 04 12:31:51 PM PST 24
Finished Feb 04 12:32:17 PM PST 24
Peak memory 199800 kb
Host smart-0f739528-87c2-4e22-91e7-1ef2c04a13c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905240484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3905240484
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3280676561
Short name T1227
Test name
Test status
Simulation time 110232186859 ps
CPU time 48.01 seconds
Started Feb 04 12:31:40 PM PST 24
Finished Feb 04 12:32:29 PM PST 24
Peak memory 199768 kb
Host smart-4ec2a864-b471-41b0-b713-9b863459df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280676561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3280676561
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2863740274
Short name T945
Test name
Test status
Simulation time 18060684398 ps
CPU time 16.45 seconds
Started Feb 04 12:31:53 PM PST 24
Finished Feb 04 12:32:13 PM PST 24
Peak memory 199812 kb
Host smart-1f16c440-3453-442e-a022-fb6f4f365c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863740274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2863740274
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1888564047
Short name T327
Test name
Test status
Simulation time 39602651924 ps
CPU time 40.25 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:32:23 PM PST 24
Peak memory 199772 kb
Host smart-05b0a482-e4a3-4e6f-9266-e79a9d9601fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888564047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1888564047
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1821191393
Short name T276
Test name
Test status
Simulation time 104103601688 ps
CPU time 28.38 seconds
Started Feb 04 12:31:51 PM PST 24
Finished Feb 04 12:32:23 PM PST 24
Peak memory 199216 kb
Host smart-53f5088f-c163-4305-b111-9469f098091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821191393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1821191393
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3070120443
Short name T100
Test name
Test status
Simulation time 157337695576 ps
CPU time 70.65 seconds
Started Feb 04 12:31:49 PM PST 24
Finished Feb 04 12:33:03 PM PST 24
Peak memory 199772 kb
Host smart-35111414-9a3a-4e91-aa26-02cbd2d65e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070120443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3070120443
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4142162940
Short name T366
Test name
Test status
Simulation time 29099534198 ps
CPU time 11.58 seconds
Started Feb 04 12:31:38 PM PST 24
Finished Feb 04 12:31:51 PM PST 24
Peak memory 199412 kb
Host smart-dc0b00a0-076d-40b3-8a34-af89ffeb9a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142162940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4142162940
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2463405859
Short name T513
Test name
Test status
Simulation time 36655560 ps
CPU time 0.56 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:29:18 PM PST 24
Peak memory 194224 kb
Host smart-c757bcc6-d213-41e9-b74f-f41b3e202487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463405859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2463405859
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3080744371
Short name T606
Test name
Test status
Simulation time 42161143809 ps
CPU time 37.15 seconds
Started Feb 04 12:29:11 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 199676 kb
Host smart-b76d1143-e086-46f6-8ca5-4eaa93d58b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080744371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3080744371
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3551568906
Short name T1133
Test name
Test status
Simulation time 165907271549 ps
CPU time 348.76 seconds
Started Feb 04 12:29:11 PM PST 24
Finished Feb 04 12:35:06 PM PST 24
Peak memory 199696 kb
Host smart-c8e6d968-ba14-4b2e-b3c4-8ceba54eaadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551568906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3551568906
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1842843966
Short name T634
Test name
Test status
Simulation time 19864037826 ps
CPU time 74.5 seconds
Started Feb 04 12:29:12 PM PST 24
Finished Feb 04 12:30:32 PM PST 24
Peak memory 199384 kb
Host smart-5b9cf590-d0c5-435f-b314-b60f8a1bd76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842843966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1842843966
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.178837430
Short name T612
Test name
Test status
Simulation time 119217233971 ps
CPU time 263.85 seconds
Started Feb 04 12:29:12 PM PST 24
Finished Feb 04 12:33:41 PM PST 24
Peak memory 199632 kb
Host smart-4d8dc0ec-5634-4eea-82e5-5f68a51a8257
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178837430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.178837430
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.36447706
Short name T596
Test name
Test status
Simulation time 330475357682 ps
CPU time 337.69 seconds
Started Feb 04 12:29:04 PM PST 24
Finished Feb 04 12:34:45 PM PST 24
Peak memory 199804 kb
Host smart-4d049ebc-42f5-41c0-9d59-ac24be78e1be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36447706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.36447706
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1377575844
Short name T553
Test name
Test status
Simulation time 3500509674 ps
CPU time 6.81 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:29:26 PM PST 24
Peak memory 194396 kb
Host smart-3b097be2-aea2-48b5-bd9e-4469fbb4f88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377575844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1377575844
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.4002962386
Short name T892
Test name
Test status
Simulation time 8145755451 ps
CPU time 261.21 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:33:39 PM PST 24
Peak memory 199696 kb
Host smart-1339d2b2-50a9-40e6-93ae-ed81f0590657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002962386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4002962386
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2459915432
Short name T401
Test name
Test status
Simulation time 26776766004 ps
CPU time 14.01 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:29:33 PM PST 24
Peak memory 199756 kb
Host smart-6e76fbc3-761d-44fe-816e-c8e44554cad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459915432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2459915432
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2846407240
Short name T920
Test name
Test status
Simulation time 4925938008 ps
CPU time 8.72 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:29:26 PM PST 24
Peak memory 195480 kb
Host smart-736594c0-7f4f-4683-97e0-5ad3681c1ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846407240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2846407240
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1212970503
Short name T700
Test name
Test status
Simulation time 5752509010 ps
CPU time 12.11 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:30:11 PM PST 24
Peak memory 199116 kb
Host smart-4a996425-1d5a-415b-ac97-1e46db7a8e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212970503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1212970503
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3148493529
Short name T849
Test name
Test status
Simulation time 3050337225317 ps
CPU time 5539.39 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 02:01:39 PM PST 24
Peak memory 199848 kb
Host smart-24bf3fb3-8dfc-44db-89e7-bc9563e40c0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148493529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3148493529
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.157341491
Short name T314
Test name
Test status
Simulation time 28128783166 ps
CPU time 312.4 seconds
Started Feb 04 12:29:04 PM PST 24
Finished Feb 04 12:34:19 PM PST 24
Peak memory 216420 kb
Host smart-f8981dba-6664-4469-aaf5-42d70ae5e853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157341491 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.157341491
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4048787680
Short name T653
Test name
Test status
Simulation time 1215068054 ps
CPU time 3.27 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:29:20 PM PST 24
Peak memory 197980 kb
Host smart-d4546272-7cca-4025-82d8-35df793a1d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048787680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4048787680
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2718477285
Short name T640
Test name
Test status
Simulation time 59072555865 ps
CPU time 88.49 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:31:41 PM PST 24
Peak memory 199544 kb
Host smart-67a37d2e-620f-441a-a101-a6d93fbe7cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718477285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2718477285
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3858135930
Short name T654
Test name
Test status
Simulation time 49974538940 ps
CPU time 89.72 seconds
Started Feb 04 12:31:51 PM PST 24
Finished Feb 04 12:33:25 PM PST 24
Peak memory 199696 kb
Host smart-8d71835c-b055-4787-be7a-d310e5ede2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858135930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3858135930
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2953991374
Short name T137
Test name
Test status
Simulation time 250194330653 ps
CPU time 43.82 seconds
Started Feb 04 12:31:52 PM PST 24
Finished Feb 04 12:32:39 PM PST 24
Peak memory 199712 kb
Host smart-21baadcf-6c69-4212-b644-a418ef1bc30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953991374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2953991374
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1878256067
Short name T342
Test name
Test status
Simulation time 11488177521 ps
CPU time 18.79 seconds
Started Feb 04 12:31:47 PM PST 24
Finished Feb 04 12:32:08 PM PST 24
Peak memory 199728 kb
Host smart-1d8fe313-621f-45df-9418-1c30e3ba45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878256067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1878256067
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3324664206
Short name T160
Test name
Test status
Simulation time 37819833749 ps
CPU time 17.44 seconds
Started Feb 04 12:31:49 PM PST 24
Finished Feb 04 12:32:09 PM PST 24
Peak memory 199108 kb
Host smart-cc3218de-f61c-49ca-bdb8-5c2566ceb21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324664206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3324664206
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2295089964
Short name T192
Test name
Test status
Simulation time 76405603177 ps
CPU time 29.47 seconds
Started Feb 04 12:31:46 PM PST 24
Finished Feb 04 12:32:17 PM PST 24
Peak memory 199508 kb
Host smart-3a3db80c-6a05-44b4-8cf0-d33c1e4fcb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295089964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2295089964
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2132657382
Short name T438
Test name
Test status
Simulation time 199419929071 ps
CPU time 74.24 seconds
Started Feb 04 12:31:48 PM PST 24
Finished Feb 04 12:33:06 PM PST 24
Peak memory 199636 kb
Host smart-3443887e-3eee-483a-b596-09ee35f8d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132657382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2132657382
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3308372457
Short name T1179
Test name
Test status
Simulation time 13215986 ps
CPU time 0.57 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:29:22 PM PST 24
Peak memory 194244 kb
Host smart-dd201241-3248-4e45-bc8d-82645d6d3d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308372457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3308372457
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2191292940
Short name T1175
Test name
Test status
Simulation time 103071172358 ps
CPU time 157.45 seconds
Started Feb 04 12:29:17 PM PST 24
Finished Feb 04 12:32:00 PM PST 24
Peak memory 199676 kb
Host smart-664136e6-c0df-4f30-8dc1-47ad8280b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191292940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2191292940
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2164613936
Short name T569
Test name
Test status
Simulation time 137773057941 ps
CPU time 222.34 seconds
Started Feb 04 12:29:04 PM PST 24
Finished Feb 04 12:32:49 PM PST 24
Peak memory 199748 kb
Host smart-2907503f-3faa-4e6d-8760-7ea22476a7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164613936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2164613936
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1519628839
Short name T128
Test name
Test status
Simulation time 114573609327 ps
CPU time 22.32 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:29:45 PM PST 24
Peak memory 199200 kb
Host smart-7b9f9d39-fd55-493f-b9fb-18801d2cef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519628839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1519628839
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.453596132
Short name T1181
Test name
Test status
Simulation time 110613359384 ps
CPU time 56.91 seconds
Started Feb 04 12:29:07 PM PST 24
Finished Feb 04 12:30:12 PM PST 24
Peak memory 199760 kb
Host smart-a7a45d94-1213-4a1a-9135-2ce60b1c65e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453596132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.453596132
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.898276170
Short name T514
Test name
Test status
Simulation time 45519393450 ps
CPU time 100.96 seconds
Started Feb 04 12:29:06 PM PST 24
Finished Feb 04 12:30:49 PM PST 24
Peak memory 199832 kb
Host smart-21deb373-d022-475d-983b-24a4a9a2bdb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898276170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.898276170
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_noise_filter.4044819285
Short name T1052
Test name
Test status
Simulation time 9416317991 ps
CPU time 14.47 seconds
Started Feb 04 12:29:10 PM PST 24
Finished Feb 04 12:29:32 PM PST 24
Peak memory 194412 kb
Host smart-01286720-a11d-40e0-bd5e-57bfa4a521ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044819285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.4044819285
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.4047222237
Short name T558
Test name
Test status
Simulation time 10139166283 ps
CPU time 583.71 seconds
Started Feb 04 12:29:14 PM PST 24
Finished Feb 04 12:39:02 PM PST 24
Peak memory 199616 kb
Host smart-6ad7c8b1-047e-40b0-bfc5-a98cc180bec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047222237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4047222237
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2142182528
Short name T1167
Test name
Test status
Simulation time 2618478460 ps
CPU time 13.33 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:29:30 PM PST 24
Peak memory 198016 kb
Host smart-17010347-541b-4877-8b77-42dc3c770476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142182528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2142182528
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2095099999
Short name T196
Test name
Test status
Simulation time 97066471359 ps
CPU time 149.33 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:31:47 PM PST 24
Peak memory 199216 kb
Host smart-6707b9fd-7d12-44d3-9704-f688ee5ef508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095099999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2095099999
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4272625868
Short name T864
Test name
Test status
Simulation time 32110388928 ps
CPU time 29.67 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:29:47 PM PST 24
Peak memory 195528 kb
Host smart-79e6b54e-0ab6-4d2b-a6f3-257e9a818400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272625868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4272625868
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2002330961
Short name T418
Test name
Test status
Simulation time 119906137 ps
CPU time 0.95 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:29:24 PM PST 24
Peak memory 196936 kb
Host smart-81a1809e-d155-4fea-84e9-3bb5948dc66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002330961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2002330961
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1821053626
Short name T414
Test name
Test status
Simulation time 104631579501 ps
CPU time 590.77 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:39:13 PM PST 24
Peak memory 199768 kb
Host smart-6661dad4-c74a-4af8-b910-9147ab4f23a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821053626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1821053626
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.4030983930
Short name T1143
Test name
Test status
Simulation time 192464826078 ps
CPU time 311.8 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:34:30 PM PST 24
Peak memory 225512 kb
Host smart-89134ad6-31bf-46de-ae1a-e829167fa58b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030983930 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4030983930
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.958234173
Short name T657
Test name
Test status
Simulation time 987346366 ps
CPU time 3.19 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:29:20 PM PST 24
Peak memory 198244 kb
Host smart-c5c73eec-f51b-4f44-a45d-b5b584a464c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958234173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.958234173
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1780593085
Short name T23
Test name
Test status
Simulation time 13168279691 ps
CPU time 5.5 seconds
Started Feb 04 12:29:08 PM PST 24
Finished Feb 04 12:29:23 PM PST 24
Peak memory 197812 kb
Host smart-7172ed0b-2516-4c5e-ad51-a98c61f98513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780593085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1780593085
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.401929894
Short name T254
Test name
Test status
Simulation time 139832811631 ps
CPU time 65.05 seconds
Started Feb 04 12:31:52 PM PST 24
Finished Feb 04 12:33:01 PM PST 24
Peak memory 199740 kb
Host smart-9af7dff3-a959-472c-9f00-f98637aa55c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401929894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.401929894
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.726352953
Short name T151
Test name
Test status
Simulation time 207178370880 ps
CPU time 110.49 seconds
Started Feb 04 12:31:58 PM PST 24
Finished Feb 04 12:33:54 PM PST 24
Peak memory 199804 kb
Host smart-9ea95457-ee08-471f-8cdc-3bd6f6469595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726352953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.726352953
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1492889732
Short name T271
Test name
Test status
Simulation time 18334880945 ps
CPU time 23.85 seconds
Started Feb 04 12:31:53 PM PST 24
Finished Feb 04 12:32:21 PM PST 24
Peak memory 199792 kb
Host smart-6468c77a-4a8c-4d53-8db2-0407531dab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492889732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1492889732
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1315179553
Short name T286
Test name
Test status
Simulation time 56085030043 ps
CPU time 101.13 seconds
Started Feb 04 12:31:57 PM PST 24
Finished Feb 04 12:33:44 PM PST 24
Peak memory 199612 kb
Host smart-f8a5991d-e057-439b-91f4-929b85808eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315179553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1315179553
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2352132313
Short name T919
Test name
Test status
Simulation time 25609591008 ps
CPU time 59.68 seconds
Started Feb 04 12:31:57 PM PST 24
Finished Feb 04 12:33:01 PM PST 24
Peak memory 199792 kb
Host smart-5a4d9802-992e-4972-b61a-77b94eff68a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352132313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2352132313
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1291119563
Short name T1044
Test name
Test status
Simulation time 37671204918 ps
CPU time 16.89 seconds
Started Feb 04 12:31:55 PM PST 24
Finished Feb 04 12:32:14 PM PST 24
Peak memory 199892 kb
Host smart-650fd525-0d3f-4372-9117-87bf4229433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291119563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1291119563
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.203262243
Short name T1222
Test name
Test status
Simulation time 11489626 ps
CPU time 0.56 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:29:18 PM PST 24
Peak memory 193992 kb
Host smart-c8ed6490-515f-421b-b2cf-860b9d175d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203262243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.203262243
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2045305155
Short name T876
Test name
Test status
Simulation time 304864079240 ps
CPU time 79.61 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:30:37 PM PST 24
Peak memory 199800 kb
Host smart-3d5fd5d7-234a-4738-a0c3-ab072e216ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045305155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2045305155
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3892084804
Short name T1200
Test name
Test status
Simulation time 112512467689 ps
CPU time 43.52 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:30:07 PM PST 24
Peak memory 199284 kb
Host smart-8c04b7bb-81cb-4b9c-befe-65e34126d707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892084804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3892084804
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2839942947
Short name T243
Test name
Test status
Simulation time 33123549556 ps
CPU time 53.36 seconds
Started Feb 04 12:29:17 PM PST 24
Finished Feb 04 12:30:16 PM PST 24
Peak memory 199164 kb
Host smart-1ac33b2b-504f-4548-bbda-74cf66b939e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839942947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2839942947
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4109090034
Short name T676
Test name
Test status
Simulation time 423246662923 ps
CPU time 589.19 seconds
Started Feb 04 12:29:19 PM PST 24
Finished Feb 04 12:39:13 PM PST 24
Peak memory 199316 kb
Host smart-a1f20a65-2db4-45c7-934b-e71be522230a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109090034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4109090034
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.527132886
Short name T581
Test name
Test status
Simulation time 299907111972 ps
CPU time 267.43 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:33:50 PM PST 24
Peak memory 199816 kb
Host smart-44de6d5e-8d32-49a1-af83-c1b3318064fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=527132886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.527132886
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.743914041
Short name T790
Test name
Test status
Simulation time 2055343660 ps
CPU time 2.16 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:29:24 PM PST 24
Peak memory 197948 kb
Host smart-2e572ff6-15c7-4083-ac44-c3112a7d70f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743914041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.743914041
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3427668162
Short name T504
Test name
Test status
Simulation time 9991347913 ps
CPU time 14.63 seconds
Started Feb 04 12:29:21 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 193464 kb
Host smart-867714c8-02cc-4469-b188-ba32cfbbccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427668162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3427668162
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1242302197
Short name T13
Test name
Test status
Simulation time 802275845 ps
CPU time 7.87 seconds
Started Feb 04 12:29:23 PM PST 24
Finished Feb 04 12:29:34 PM PST 24
Peak memory 197692 kb
Host smart-ca45adb8-8c0a-471e-b931-de733b56c237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242302197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1242302197
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2303602151
Short name T1192
Test name
Test status
Simulation time 2829828651 ps
CPU time 4.87 seconds
Started Feb 04 12:29:07 PM PST 24
Finished Feb 04 12:29:19 PM PST 24
Peak memory 195160 kb
Host smart-1caaa4e9-4f2f-4169-b687-f0a3358ee7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303602151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2303602151
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2870653819
Short name T950
Test name
Test status
Simulation time 6050134745 ps
CPU time 5.13 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:29:25 PM PST 24
Peak memory 199176 kb
Host smart-1f2a526f-9795-4c9d-abb3-4e93092e5192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870653819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2870653819
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3380084033
Short name T347
Test name
Test status
Simulation time 254514850158 ps
CPU time 384.53 seconds
Started Feb 04 12:29:16 PM PST 24
Finished Feb 04 12:35:46 PM PST 24
Peak memory 208220 kb
Host smart-d4908fd7-ebbf-4912-ad0d-dbcc1c09e0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380084033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3380084033
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1611479600
Short name T1163
Test name
Test status
Simulation time 132111771197 ps
CPU time 624.77 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:39:47 PM PST 24
Peak memory 216208 kb
Host smart-44d5e359-f67b-42fc-8bd2-5fda33fdbd24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611479600 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1611479600
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3273407025
Short name T424
Test name
Test status
Simulation time 7003360001 ps
CPU time 19.05 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:29:40 PM PST 24
Peak memory 198900 kb
Host smart-acbed78c-137d-4845-990c-0873dfba1d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273407025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3273407025
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3153248033
Short name T535
Test name
Test status
Simulation time 8826440241 ps
CPU time 13.92 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:29:37 PM PST 24
Peak memory 196704 kb
Host smart-9d50ec23-941d-4484-b480-6def809a9f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153248033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3153248033
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2305522917
Short name T153
Test name
Test status
Simulation time 43597990018 ps
CPU time 33.38 seconds
Started Feb 04 12:31:57 PM PST 24
Finished Feb 04 12:32:35 PM PST 24
Peak memory 199408 kb
Host smart-fcced549-2024-4c4d-b9da-a60c503a087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305522917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2305522917
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3543058172
Short name T285
Test name
Test status
Simulation time 19106500954 ps
CPU time 27.58 seconds
Started Feb 04 12:31:58 PM PST 24
Finished Feb 04 12:32:31 PM PST 24
Peak memory 199868 kb
Host smart-7703dc80-bf97-4818-8d37-30d22d32cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543058172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3543058172
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1291311613
Short name T857
Test name
Test status
Simulation time 222563775778 ps
CPU time 61.8 seconds
Started Feb 04 12:31:45 PM PST 24
Finished Feb 04 12:32:48 PM PST 24
Peak memory 199908 kb
Host smart-5b3f09db-7bf3-4c25-a800-ac8f2afb5fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291311613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1291311613
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2370457247
Short name T1141
Test name
Test status
Simulation time 92309701984 ps
CPU time 27.6 seconds
Started Feb 04 12:31:57 PM PST 24
Finished Feb 04 12:32:30 PM PST 24
Peak memory 199564 kb
Host smart-07868243-457b-4591-9f36-5747c80127bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370457247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2370457247
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1724613090
Short name T269
Test name
Test status
Simulation time 104121699219 ps
CPU time 33.7 seconds
Started Feb 04 12:31:49 PM PST 24
Finished Feb 04 12:32:25 PM PST 24
Peak memory 199808 kb
Host smart-4a69922e-0edd-4c7b-9409-39495636b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724613090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1724613090
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1343394064
Short name T183
Test name
Test status
Simulation time 44541849756 ps
CPU time 18.75 seconds
Started Feb 04 12:31:44 PM PST 24
Finished Feb 04 12:32:05 PM PST 24
Peak memory 199828 kb
Host smart-aca47f89-fa03-4785-8cf3-e6aa80030374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343394064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1343394064
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3931512814
Short name T249
Test name
Test status
Simulation time 37307954536 ps
CPU time 11.75 seconds
Started Feb 04 12:31:45 PM PST 24
Finished Feb 04 12:31:58 PM PST 24
Peak memory 199692 kb
Host smart-1c38be16-5cba-4070-ad2e-473a0d7ac5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931512814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3931512814
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3453256950
Short name T101
Test name
Test status
Simulation time 163031330925 ps
CPU time 77.18 seconds
Started Feb 04 12:31:44 PM PST 24
Finished Feb 04 12:33:03 PM PST 24
Peak memory 199448 kb
Host smart-aedbea9c-0bbe-499e-9655-4a81393b29cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453256950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3453256950
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.890372525
Short name T219
Test name
Test status
Simulation time 49363525589 ps
CPU time 76.09 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:33:37 PM PST 24
Peak memory 199844 kb
Host smart-f6c26879-1c7a-4def-bd8c-bf63e9b5b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890372525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.890372525
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1526531152
Short name T593
Test name
Test status
Simulation time 14460620 ps
CPU time 0.54 seconds
Started Feb 04 12:29:23 PM PST 24
Finished Feb 04 12:29:27 PM PST 24
Peak memory 195144 kb
Host smart-014f4239-0001-43c2-9eb1-b4beec49b25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526531152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1526531152
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1870073764
Short name T826
Test name
Test status
Simulation time 95151615720 ps
CPU time 39.66 seconds
Started Feb 04 12:29:20 PM PST 24
Finished Feb 04 12:30:04 PM PST 24
Peak memory 199836 kb
Host smart-727c5aaf-874f-4d87-8d0e-eea42fa956a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870073764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1870073764
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2225817607
Short name T763
Test name
Test status
Simulation time 139001834587 ps
CPU time 203.3 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:32:45 PM PST 24
Peak memory 199176 kb
Host smart-f9e49c88-f443-4b7c-9644-60fb4c76f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225817607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2225817607
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.667431082
Short name T650
Test name
Test status
Simulation time 48618656978 ps
CPU time 94.85 seconds
Started Feb 04 12:29:19 PM PST 24
Finished Feb 04 12:30:58 PM PST 24
Peak memory 199840 kb
Host smart-14206926-ec3d-495f-b502-ecb3f3d01b40
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667431082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.667431082
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3556080316
Short name T547
Test name
Test status
Simulation time 105568951538 ps
CPU time 301.9 seconds
Started Feb 04 12:29:27 PM PST 24
Finished Feb 04 12:34:31 PM PST 24
Peak memory 199728 kb
Host smart-5d8dbad6-d1d1-4479-b02f-ebb4de01ad0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556080316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3556080316
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2242372224
Short name T559
Test name
Test status
Simulation time 7121296694 ps
CPU time 12.2 seconds
Started Feb 04 12:29:23 PM PST 24
Finished Feb 04 12:29:38 PM PST 24
Peak memory 198180 kb
Host smart-ff6f59fc-2e4a-4203-a24a-d2dff758cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242372224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2242372224
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2556514302
Short name T568
Test name
Test status
Simulation time 102181431638 ps
CPU time 88.27 seconds
Started Feb 04 12:29:13 PM PST 24
Finished Feb 04 12:30:46 PM PST 24
Peak memory 198380 kb
Host smart-1fb29f07-7811-40d5-bb79-5f85f5145253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556514302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2556514302
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3801629287
Short name T1100
Test name
Test status
Simulation time 14042983888 ps
CPU time 756.75 seconds
Started Feb 04 12:29:21 PM PST 24
Finished Feb 04 12:42:01 PM PST 24
Peak memory 199824 kb
Host smart-3a751470-80fb-4add-9181-6c89fac59a28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801629287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3801629287
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2311689918
Short name T816
Test name
Test status
Simulation time 3009983071 ps
CPU time 20.63 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:29:43 PM PST 24
Peak memory 197608 kb
Host smart-479a6f80-1530-4bc7-8570-118149d7a45d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2311689918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2311689918
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.386220159
Short name T1171
Test name
Test status
Simulation time 104467404440 ps
CPU time 22.32 seconds
Started Feb 04 12:29:15 PM PST 24
Finished Feb 04 12:29:43 PM PST 24
Peak memory 199216 kb
Host smart-66765288-8b84-4b16-8743-262795fba829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386220159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.386220159
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.781029251
Short name T769
Test name
Test status
Simulation time 37470035752 ps
CPU time 59 seconds
Started Feb 04 12:29:10 PM PST 24
Finished Feb 04 12:30:16 PM PST 24
Peak memory 195540 kb
Host smart-6804ef44-df7e-4c3b-8d3e-2f74686b66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781029251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.781029251
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1850851926
Short name T625
Test name
Test status
Simulation time 452227943 ps
CPU time 1.85 seconds
Started Feb 04 12:29:17 PM PST 24
Finished Feb 04 12:29:24 PM PST 24
Peak memory 197420 kb
Host smart-47198d97-285e-40e9-bcb7-3cf6b12fa6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850851926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1850851926
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.841352492
Short name T544
Test name
Test status
Simulation time 527547711425 ps
CPU time 393.59 seconds
Started Feb 04 12:29:22 PM PST 24
Finished Feb 04 12:35:59 PM PST 24
Peak memory 199788 kb
Host smart-f552f520-7708-442b-a500-ce5ed8732321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841352492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.841352492
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4275281646
Short name T1147
Test name
Test status
Simulation time 105100484440 ps
CPU time 162.18 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:32:28 PM PST 24
Peak memory 216316 kb
Host smart-afc8acfa-3885-49c8-b35c-f04d6417ffa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275281646 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4275281646
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.4196808026
Short name T1144
Test name
Test status
Simulation time 8812345728 ps
CPU time 10.58 seconds
Started Feb 04 12:29:31 PM PST 24
Finished Feb 04 12:29:47 PM PST 24
Peak memory 198880 kb
Host smart-11a4e239-31ff-49ea-9c97-23aabc413ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196808026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.4196808026
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1590439692
Short name T308
Test name
Test status
Simulation time 86881109486 ps
CPU time 142.47 seconds
Started Feb 04 12:29:09 PM PST 24
Finished Feb 04 12:31:40 PM PST 24
Peak memory 199840 kb
Host smart-b8c6507e-56f6-479d-887c-d91e62356043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590439692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1590439692
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2792985822
Short name T171
Test name
Test status
Simulation time 32700071446 ps
CPU time 30.01 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:32:50 PM PST 24
Peak memory 199612 kb
Host smart-07ed5af2-cd64-40f0-a1b6-637facc8eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792985822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2792985822
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.174307434
Short name T985
Test name
Test status
Simulation time 38126213720 ps
CPU time 61.77 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:33:22 PM PST 24
Peak memory 199640 kb
Host smart-dcd659c9-1034-46f8-a1da-248d0dcf1154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174307434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.174307434
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1268186960
Short name T1215
Test name
Test status
Simulation time 111169527225 ps
CPU time 218.24 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:35:59 PM PST 24
Peak memory 199672 kb
Host smart-d3d8f6b5-3692-47b8-a5d9-e72bc9795bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268186960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1268186960
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1170997682
Short name T1186
Test name
Test status
Simulation time 34373637392 ps
CPU time 56.22 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:33:17 PM PST 24
Peak memory 199816 kb
Host smart-22fa923f-bf57-4a52-b3d2-28fd86c9c7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170997682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1170997682
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2711556767
Short name T939
Test name
Test status
Simulation time 6052338385 ps
CPU time 12.49 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:32:33 PM PST 24
Peak memory 199588 kb
Host smart-b9bd2c66-2446-4749-aca9-6b573558d469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711556767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2711556767
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4067006476
Short name T999
Test name
Test status
Simulation time 147916593759 ps
CPU time 311.16 seconds
Started Feb 04 12:32:17 PM PST 24
Finished Feb 04 12:37:32 PM PST 24
Peak memory 199832 kb
Host smart-40debc1f-0e8f-462a-973e-7cf327126ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067006476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4067006476
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3281666409
Short name T1169
Test name
Test status
Simulation time 10128611847 ps
CPU time 17.96 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:32:37 PM PST 24
Peak memory 199156 kb
Host smart-f5d68eba-3cb1-4835-a80b-791010ea63ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281666409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3281666409
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2399413256
Short name T200
Test name
Test status
Simulation time 15997001914 ps
CPU time 23.78 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:32:44 PM PST 24
Peak memory 199668 kb
Host smart-9ff7fec8-1b19-41c8-86a0-295eb2ae724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399413256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2399413256
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4269469303
Short name T486
Test name
Test status
Simulation time 40602709 ps
CPU time 0.56 seconds
Started Feb 04 12:29:25 PM PST 24
Finished Feb 04 12:29:28 PM PST 24
Peak memory 195172 kb
Host smart-0a6e756b-b4bb-45a1-a2cb-8035951dcc8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269469303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4269469303
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1769244328
Short name T730
Test name
Test status
Simulation time 86238091422 ps
CPU time 64.03 seconds
Started Feb 04 12:29:36 PM PST 24
Finished Feb 04 12:30:43 PM PST 24
Peak memory 199656 kb
Host smart-067ea14b-be7e-440b-8cd5-ebb53a00557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769244328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1769244328
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2124756810
Short name T898
Test name
Test status
Simulation time 214281339185 ps
CPU time 335.12 seconds
Started Feb 04 12:30:04 PM PST 24
Finished Feb 04 12:35:46 PM PST 24
Peak memory 199392 kb
Host smart-d7d204cd-5892-4570-9d0e-d3dfce183e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124756810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2124756810
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1788282184
Short name T1202
Test name
Test status
Simulation time 6533584293 ps
CPU time 6.46 seconds
Started Feb 04 12:29:31 PM PST 24
Finished Feb 04 12:29:41 PM PST 24
Peak memory 199736 kb
Host smart-fdf954ef-41c2-4c68-bffe-080326861d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788282184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1788282184
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.4039405565
Short name T918
Test name
Test status
Simulation time 309602342757 ps
CPU time 481.91 seconds
Started Feb 04 12:29:20 PM PST 24
Finished Feb 04 12:37:26 PM PST 24
Peak memory 199852 kb
Host smart-b5ce7093-4670-4064-9e6f-f818d20c9146
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039405565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4039405565
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.716419108
Short name T548
Test name
Test status
Simulation time 94603605073 ps
CPU time 409.15 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:36:35 PM PST 24
Peak memory 199816 kb
Host smart-214558f2-d80d-48ae-a8cd-c3195a589397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716419108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.716419108
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3792154776
Short name T912
Test name
Test status
Simulation time 5588624749 ps
CPU time 8.77 seconds
Started Feb 04 12:29:23 PM PST 24
Finished Feb 04 12:29:35 PM PST 24
Peak memory 198104 kb
Host smart-8341131f-6717-4aaa-8783-6315966c6767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792154776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3792154776
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.891851709
Short name T583
Test name
Test status
Simulation time 248190896476 ps
CPU time 81.82 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:31:01 PM PST 24
Peak memory 208012 kb
Host smart-734bfb84-07e7-463a-8d4b-b7ef0a4636c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891851709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.891851709
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.403066510
Short name T902
Test name
Test status
Simulation time 12248684959 ps
CPU time 152.53 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:32:11 PM PST 24
Peak memory 199652 kb
Host smart-b6884f36-77af-48db-8428-3052821ddb87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403066510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.403066510
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1110481604
Short name T29
Test name
Test status
Simulation time 2892156877 ps
CPU time 10.54 seconds
Started Feb 04 12:29:20 PM PST 24
Finished Feb 04 12:29:35 PM PST 24
Peak memory 197968 kb
Host smart-2f130605-c8f7-43ed-8f32-b569e6142aed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1110481604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1110481604
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.582084450
Short name T1151
Test name
Test status
Simulation time 123652491029 ps
CPU time 193.17 seconds
Started Feb 04 12:29:36 PM PST 24
Finished Feb 04 12:32:53 PM PST 24
Peak memory 199012 kb
Host smart-649edd51-7d8a-447d-9a24-439222dd8b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582084450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.582084450
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2971499021
Short name T949
Test name
Test status
Simulation time 4100569834 ps
CPU time 2.12 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:29:41 PM PST 24
Peak memory 195472 kb
Host smart-a2bdb753-4331-440d-8ee9-3b3cdcc41a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971499021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2971499021
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.1458826156
Short name T554
Test name
Test status
Simulation time 449392142 ps
CPU time 1.71 seconds
Started Feb 04 12:29:24 PM PST 24
Finished Feb 04 12:29:29 PM PST 24
Peak memory 197892 kb
Host smart-206fc768-560e-40ff-acab-42d679a80e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458826156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1458826156
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.348755892
Short name T1061
Test name
Test status
Simulation time 75700452375 ps
CPU time 619.76 seconds
Started Feb 04 12:29:18 PM PST 24
Finished Feb 04 12:39:43 PM PST 24
Peak memory 199768 kb
Host smart-ba454741-de29-4401-8185-1fa101b2ca38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348755892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.348755892
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3350117003
Short name T751
Test name
Test status
Simulation time 84581302882 ps
CPU time 241.3 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:33:46 PM PST 24
Peak memory 215660 kb
Host smart-c209e878-8142-439a-84a0-aa10693b5b4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350117003 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3350117003
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.585101403
Short name T978
Test name
Test status
Simulation time 668455490 ps
CPU time 2.7 seconds
Started Feb 04 12:29:23 PM PST 24
Finished Feb 04 12:29:29 PM PST 24
Peak memory 198072 kb
Host smart-08331137-9f5b-4652-bc16-d652a1aa7e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585101403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.585101403
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3085638071
Short name T167
Test name
Test status
Simulation time 38889934739 ps
CPU time 65.53 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:30:44 PM PST 24
Peak memory 199756 kb
Host smart-f8b551fe-7ec5-4a08-8241-733a2db27ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085638071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3085638071
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1966003020
Short name T886
Test name
Test status
Simulation time 67096648677 ps
CPU time 42.37 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:33:03 PM PST 24
Peak memory 199540 kb
Host smart-7b3c30c9-5463-4c30-b70a-59606e7d2d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966003020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1966003020
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3431056914
Short name T139
Test name
Test status
Simulation time 78213851053 ps
CPU time 72.17 seconds
Started Feb 04 12:32:19 PM PST 24
Finished Feb 04 12:33:33 PM PST 24
Peak memory 199748 kb
Host smart-bf68bd50-e9e6-4ff2-936a-571dd944ba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431056914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3431056914
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2363360296
Short name T126
Test name
Test status
Simulation time 45566066184 ps
CPU time 28.51 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:32:49 PM PST 24
Peak memory 199864 kb
Host smart-38bf8bac-4216-4093-822f-ed13072b8504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363360296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2363360296
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3881451543
Short name T349
Test name
Test status
Simulation time 214792779621 ps
CPU time 385.01 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:38:46 PM PST 24
Peak memory 199768 kb
Host smart-bff11bf8-97e7-48d9-9b36-9247b0a91af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881451543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3881451543
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.4039361419
Short name T908
Test name
Test status
Simulation time 8092336229 ps
CPU time 21.64 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:32:42 PM PST 24
Peak memory 199656 kb
Host smart-7b07145c-6c10-421e-8bb9-913b847f3b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039361419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4039361419
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2400579370
Short name T317
Test name
Test status
Simulation time 73819693846 ps
CPU time 75.5 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:33:35 PM PST 24
Peak memory 199840 kb
Host smart-34af834a-b579-4fce-9f3d-958fe55a64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400579370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2400579370
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.902969072
Short name T788
Test name
Test status
Simulation time 52627584694 ps
CPU time 88.61 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:33:49 PM PST 24
Peak memory 199800 kb
Host smart-ea77c89f-01ba-4a72-b363-80b20b60ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902969072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.902969072
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4206975821
Short name T213
Test name
Test status
Simulation time 12660732764 ps
CPU time 23.76 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:32:44 PM PST 24
Peak memory 199872 kb
Host smart-d2a39339-a28f-4421-a7c5-f4e73e530100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206975821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4206975821
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3084668951
Short name T995
Test name
Test status
Simulation time 69072451 ps
CPU time 0.57 seconds
Started Feb 04 12:29:24 PM PST 24
Finished Feb 04 12:29:27 PM PST 24
Peak memory 195204 kb
Host smart-efd23587-abed-4ca0-b4be-71a7a9c0f3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084668951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3084668951
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1794095405
Short name T526
Test name
Test status
Simulation time 223682822626 ps
CPU time 534.11 seconds
Started Feb 04 12:29:23 PM PST 24
Finished Feb 04 12:38:20 PM PST 24
Peak memory 199832 kb
Host smart-8df541d2-4a7f-4dcd-baf5-46c31638e309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794095405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1794095405
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1374057751
Short name T789
Test name
Test status
Simulation time 57066255119 ps
CPU time 18.9 seconds
Started Feb 04 12:29:26 PM PST 24
Finished Feb 04 12:29:47 PM PST 24
Peak memory 198616 kb
Host smart-33005fb4-a82f-4538-a07a-d75628b173f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374057751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1374057751
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2029901823
Short name T987
Test name
Test status
Simulation time 168231756745 ps
CPU time 130.41 seconds
Started Feb 04 12:29:36 PM PST 24
Finished Feb 04 12:31:50 PM PST 24
Peak memory 199676 kb
Host smart-d8219b8e-b508-4cb7-847f-7e3b00ff1572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029901823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2029901823
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2164641229
Short name T106
Test name
Test status
Simulation time 286775157576 ps
CPU time 422.07 seconds
Started Feb 04 12:29:24 PM PST 24
Finished Feb 04 12:36:29 PM PST 24
Peak memory 199768 kb
Host smart-c4d8b790-3401-4d57-b781-1e883bf51657
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164641229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2164641229
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2669592610
Short name T931
Test name
Test status
Simulation time 171991547495 ps
CPU time 499.5 seconds
Started Feb 04 12:29:36 PM PST 24
Finished Feb 04 12:37:59 PM PST 24
Peak memory 199748 kb
Host smart-ae5a5667-0ae0-4348-896a-623eb6b2c856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669592610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2669592610
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3811705159
Short name T527
Test name
Test status
Simulation time 35543695673 ps
CPU time 64.73 seconds
Started Feb 04 12:29:24 PM PST 24
Finished Feb 04 12:30:32 PM PST 24
Peak memory 199596 kb
Host smart-60b92215-16b6-405e-bfeb-3a9be06c0bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811705159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3811705159
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.386337626
Short name T587
Test name
Test status
Simulation time 10483523653 ps
CPU time 99.11 seconds
Started Feb 04 12:29:23 PM PST 24
Finished Feb 04 12:31:05 PM PST 24
Peak memory 199652 kb
Host smart-d1930fc3-45bc-474b-856d-000bc7d067d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386337626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.386337626
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2141613662
Short name T970
Test name
Test status
Simulation time 582301421 ps
CPU time 1.99 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 197696 kb
Host smart-057584c6-d4b5-4cc1-8822-8f6a6a1a3913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141613662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2141613662
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.726350862
Short name T304
Test name
Test status
Simulation time 136775518411 ps
CPU time 62.13 seconds
Started Feb 04 12:29:36 PM PST 24
Finished Feb 04 12:30:42 PM PST 24
Peak memory 199792 kb
Host smart-22eb77f3-c726-4efa-ad69-83378e7eed97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726350862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.726350862
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3436667353
Short name T572
Test name
Test status
Simulation time 5214332961 ps
CPU time 5.58 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:29:50 PM PST 24
Peak memory 195512 kb
Host smart-99fdf985-8f10-4342-9f3c-650636da55f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436667353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3436667353
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.731424445
Short name T633
Test name
Test status
Simulation time 627899010 ps
CPU time 2.51 seconds
Started Feb 04 12:29:36 PM PST 24
Finished Feb 04 12:29:42 PM PST 24
Peak memory 197820 kb
Host smart-9726842c-7107-4199-b6ec-e8404119945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731424445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.731424445
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3888961741
Short name T750
Test name
Test status
Simulation time 846871883064 ps
CPU time 496.42 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:38:01 PM PST 24
Peak memory 215728 kb
Host smart-c9df02f9-6b87-4039-b00c-e23e6309b01b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888961741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3888961741
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1556439204
Short name T578
Test name
Test status
Simulation time 159088863912 ps
CPU time 652.51 seconds
Started Feb 04 12:29:26 PM PST 24
Finished Feb 04 12:40:20 PM PST 24
Peak memory 216344 kb
Host smart-8fb2c170-1a5d-47cb-8536-043146fdd088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556439204 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1556439204
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4282116041
Short name T738
Test name
Test status
Simulation time 6821872680 ps
CPU time 20.64 seconds
Started Feb 04 12:29:25 PM PST 24
Finished Feb 04 12:29:48 PM PST 24
Peak memory 198856 kb
Host smart-f340692a-72dd-4107-9cc6-2a8676e08e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282116041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4282116041
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2524198037
Short name T1027
Test name
Test status
Simulation time 45488558479 ps
CPU time 25.74 seconds
Started Feb 04 12:29:26 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 199688 kb
Host smart-4d0b46b5-3364-4bf3-96b6-90434e4b91f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524198037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2524198037
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.4112024583
Short name T853
Test name
Test status
Simulation time 14481090040 ps
CPU time 7.57 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:32:27 PM PST 24
Peak memory 199700 kb
Host smart-db272644-abbf-4c6f-961b-10f4a485de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112024583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.4112024583
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1371861688
Short name T1121
Test name
Test status
Simulation time 37506658113 ps
CPU time 27.54 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:32:48 PM PST 24
Peak memory 199824 kb
Host smart-19aedf4f-6f3e-4d75-bd6e-0ac98eb271c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371861688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1371861688
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3932442368
Short name T350
Test name
Test status
Simulation time 84214992178 ps
CPU time 18.62 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:32:39 PM PST 24
Peak memory 199584 kb
Host smart-f8faa273-5d42-4f3a-9c9c-0bd6f0a2dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932442368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3932442368
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1337569587
Short name T901
Test name
Test status
Simulation time 26107324754 ps
CPU time 43.59 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:33:03 PM PST 24
Peak memory 199420 kb
Host smart-0e8ae9fe-f172-44d6-9813-c27e020cff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337569587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1337569587
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.634642421
Short name T352
Test name
Test status
Simulation time 59369314377 ps
CPU time 26.98 seconds
Started Feb 04 12:32:17 PM PST 24
Finished Feb 04 12:32:47 PM PST 24
Peak memory 199852 kb
Host smart-0511e216-3e91-4f9f-b891-e13ca883d947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634642421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.634642421
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.715799563
Short name T1056
Test name
Test status
Simulation time 24825415908 ps
CPU time 39.69 seconds
Started Feb 04 12:32:23 PM PST 24
Finished Feb 04 12:33:03 PM PST 24
Peak memory 199724 kb
Host smart-a7ec61cd-49ce-4aeb-b489-108aaa87b4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715799563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.715799563
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1497201585
Short name T1212
Test name
Test status
Simulation time 135763493316 ps
CPU time 25.68 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:32:46 PM PST 24
Peak memory 199652 kb
Host smart-faf9b36a-3fff-4c7c-b545-e471aa0a62d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497201585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1497201585
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.63795404
Short name T1082
Test name
Test status
Simulation time 35767186666 ps
CPU time 28.35 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:32:49 PM PST 24
Peak memory 199836 kb
Host smart-3acd964e-a325-46c9-9c6b-e39ce73eeebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63795404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.63795404
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1157905115
Short name T295
Test name
Test status
Simulation time 17956643448 ps
CPU time 25.84 seconds
Started Feb 04 12:32:23 PM PST 24
Finished Feb 04 12:32:50 PM PST 24
Peak memory 199608 kb
Host smart-0bc5e1fd-e71c-4a37-b2af-597e793a7afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157905115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1157905115
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3551673331
Short name T1012
Test name
Test status
Simulation time 23631411987 ps
CPU time 48.1 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:33:09 PM PST 24
Peak memory 199736 kb
Host smart-30f98976-6312-4278-bf07-0d0be1e9b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551673331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3551673331
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1232070745
Short name T937
Test name
Test status
Simulation time 41169844 ps
CPU time 0.54 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 195188 kb
Host smart-bcee7cfe-c4e7-4b5b-8b37-c44ece955f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232070745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1232070745
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.419172284
Short name T1224
Test name
Test status
Simulation time 121865240596 ps
CPU time 49.5 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:30:34 PM PST 24
Peak memory 199748 kb
Host smart-b0ce3b28-f543-4641-ac45-ffc05bbb2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419172284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.419172284
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2035783744
Short name T958
Test name
Test status
Simulation time 98201658408 ps
CPU time 148.75 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199528 kb
Host smart-37a72cc2-24b1-4906-a20d-798d8aadfc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035783744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2035783744
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4045364349
Short name T157
Test name
Test status
Simulation time 12357530255 ps
CPU time 20.47 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:30:05 PM PST 24
Peak memory 199608 kb
Host smart-f0dea9fb-a199-411a-b25e-16a5fcc27a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045364349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4045364349
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1956485533
Short name T1016
Test name
Test status
Simulation time 809864961987 ps
CPU time 344.81 seconds
Started Feb 04 12:29:27 PM PST 24
Finished Feb 04 12:35:13 PM PST 24
Peak memory 199704 kb
Host smart-4afe962e-5108-48f2-8fd8-66ce028053dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956485533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1956485533
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.312659312
Short name T556
Test name
Test status
Simulation time 72235866356 ps
CPU time 161.96 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:32:34 PM PST 24
Peak memory 199640 kb
Host smart-0b1bc077-1ada-41de-ae7b-7ea74fa29bcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312659312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.312659312
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3102291437
Short name T768
Test name
Test status
Simulation time 5441592815 ps
CPU time 10.78 seconds
Started Feb 04 12:29:33 PM PST 24
Finished Feb 04 12:29:49 PM PST 24
Peak memory 197960 kb
Host smart-48a970fa-d1d3-4d32-a54b-ee129ea9856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102291437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3102291437
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2654775931
Short name T968
Test name
Test status
Simulation time 138632141335 ps
CPU time 68.4 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:31:01 PM PST 24
Peak memory 207896 kb
Host smart-579af0bf-fc02-432d-b024-6a0075e03370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654775931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2654775931
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3998213006
Short name T1008
Test name
Test status
Simulation time 11899274629 ps
CPU time 574.74 seconds
Started Feb 04 12:29:33 PM PST 24
Finished Feb 04 12:39:13 PM PST 24
Peak memory 199676 kb
Host smart-7e147300-14da-4a85-bf1e-9aa0e7b421c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998213006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3998213006
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.412639804
Short name T959
Test name
Test status
Simulation time 3328004852 ps
CPU time 15.5 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 198252 kb
Host smart-ade3d85a-eeef-4e4c-aed2-9676c3f715c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412639804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.412639804
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3633680984
Short name T1078
Test name
Test status
Simulation time 49884499709 ps
CPU time 77.38 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:31:02 PM PST 24
Peak memory 199740 kb
Host smart-92c499fc-e1cc-44f2-b035-836f5aab17a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633680984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3633680984
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1321155672
Short name T934
Test name
Test status
Simulation time 372093600 ps
CPU time 1.24 seconds
Started Feb 04 12:29:40 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 194988 kb
Host smart-081792b8-cc44-4777-a280-aaa2fb35b215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321155672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1321155672
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1184759352
Short name T1043
Test name
Test status
Simulation time 465360455 ps
CPU time 1.83 seconds
Started Feb 04 12:29:26 PM PST 24
Finished Feb 04 12:29:30 PM PST 24
Peak memory 198056 kb
Host smart-4cc74228-947a-4ad0-8fe4-90951515477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184759352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1184759352
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1691338642
Short name T1168
Test name
Test status
Simulation time 407871716141 ps
CPU time 620.29 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:39:59 PM PST 24
Peak memory 199756 kb
Host smart-947d4800-9fda-4023-8827-430e399b9cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691338642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1691338642
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2568034639
Short name T379
Test name
Test status
Simulation time 437146461663 ps
CPU time 281.23 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:34:34 PM PST 24
Peak memory 216208 kb
Host smart-90f41d10-2a21-4947-a3ae-b183b6e52656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568034639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2568034639
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1489094920
Short name T582
Test name
Test status
Simulation time 2901109241 ps
CPU time 2.55 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:29:41 PM PST 24
Peak memory 198668 kb
Host smart-6cc5d766-0843-4003-8a5a-279c98841299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489094920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1489094920
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4054483
Short name T1155
Test name
Test status
Simulation time 17299063140 ps
CPU time 12.87 seconds
Started Feb 04 12:29:27 PM PST 24
Finished Feb 04 12:29:41 PM PST 24
Peak memory 197404 kb
Host smart-6eeb535b-56e1-4e2b-963e-7c043599f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4054483
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3015302155
Short name T185
Test name
Test status
Simulation time 124548316135 ps
CPU time 39.27 seconds
Started Feb 04 12:32:23 PM PST 24
Finished Feb 04 12:33:03 PM PST 24
Peak memory 199836 kb
Host smart-0776bad0-33f6-4a0e-8d1d-2eae418c8eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015302155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3015302155
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3491574444
Short name T565
Test name
Test status
Simulation time 31266933799 ps
CPU time 9.54 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:32:30 PM PST 24
Peak memory 199248 kb
Host smart-4481f36f-9cf2-45e7-9901-59a98ba983aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491574444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3491574444
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1283713952
Short name T191
Test name
Test status
Simulation time 20532251743 ps
CPU time 30.14 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:32:51 PM PST 24
Peak memory 199848 kb
Host smart-6655a4c6-ca42-438e-8741-1dcb7df97d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283713952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1283713952
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.732676165
Short name T803
Test name
Test status
Simulation time 53199428665 ps
CPU time 87.76 seconds
Started Feb 04 12:32:15 PM PST 24
Finished Feb 04 12:33:48 PM PST 24
Peak memory 199336 kb
Host smart-56d75292-fb6f-451a-ba0d-8a38c0b794b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732676165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.732676165
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.4067858178
Short name T793
Test name
Test status
Simulation time 174282617076 ps
CPU time 215.9 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:35:56 PM PST 24
Peak memory 199772 kb
Host smart-feb8d322-a7db-4c27-bfce-9d11ad4db9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067858178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4067858178
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.361992601
Short name T216
Test name
Test status
Simulation time 123456527403 ps
CPU time 22.39 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:32:43 PM PST 24
Peak memory 199768 kb
Host smart-c2ab03b1-e8bf-466c-940d-1c8511d88f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361992601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.361992601
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2417726140
Short name T217
Test name
Test status
Simulation time 151040047470 ps
CPU time 228.84 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:36:10 PM PST 24
Peak memory 199908 kb
Host smart-8b9d2250-09a1-4cd6-b7aa-7a20187d805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417726140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2417726140
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.431982555
Short name T307
Test name
Test status
Simulation time 50140285065 ps
CPU time 11.51 seconds
Started Feb 04 12:32:22 PM PST 24
Finished Feb 04 12:32:34 PM PST 24
Peak memory 199752 kb
Host smart-78ec32a7-d173-40d0-8a29-50cf261b37a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431982555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.431982555
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3102375536
Short name T1009
Test name
Test status
Simulation time 57281759292 ps
CPU time 23.8 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:32:45 PM PST 24
Peak memory 199784 kb
Host smart-9f4ddd0b-2fde-4e31-8592-9d3b4e6fb43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102375536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3102375536
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.4110182279
Short name T1089
Test name
Test status
Simulation time 30741370 ps
CPU time 0.55 seconds
Started Feb 04 12:29:33 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 194296 kb
Host smart-267eef46-6de1-4288-8fa6-3ac05627c2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110182279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.4110182279
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2401171437
Short name T576
Test name
Test status
Simulation time 137867915079 ps
CPU time 40.22 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:30:19 PM PST 24
Peak memory 199808 kb
Host smart-a94ac819-0190-4d0a-b9be-b7a43dd30290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401171437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2401171437
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4038312625
Short name T227
Test name
Test status
Simulation time 18584030391 ps
CPU time 29.53 seconds
Started Feb 04 12:29:42 PM PST 24
Finished Feb 04 12:30:22 PM PST 24
Peak memory 199372 kb
Host smart-f53c6bb2-4d02-40b5-820e-e4c1651b46a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038312625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4038312625
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3060737961
Short name T145
Test name
Test status
Simulation time 24298304172 ps
CPU time 53.58 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:30:33 PM PST 24
Peak memory 199740 kb
Host smart-17b8dc1e-0420-48f0-b1cb-2ec370b2f2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060737961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3060737961
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3123297322
Short name T1050
Test name
Test status
Simulation time 200342696823 ps
CPU time 40.86 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:30:26 PM PST 24
Peak memory 199216 kb
Host smart-7911e7ca-8111-470f-9e74-4441fe12d183
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123297322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3123297322
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2943958163
Short name T624
Test name
Test status
Simulation time 262845314213 ps
CPU time 107.18 seconds
Started Feb 04 12:29:39 PM PST 24
Finished Feb 04 12:31:38 PM PST 24
Peak memory 199808 kb
Host smart-11af4512-816f-4983-8798-59bc07fef419
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943958163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2943958163
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2195670896
Short name T1060
Test name
Test status
Simulation time 9411679029 ps
CPU time 7.98 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:29:46 PM PST 24
Peak memory 198548 kb
Host smart-0ffdb47b-f22f-42cd-afbf-19b0724bdc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195670896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2195670896
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.306996032
Short name T1076
Test name
Test status
Simulation time 8702765660 ps
CPU time 10.96 seconds
Started Feb 04 12:29:33 PM PST 24
Finished Feb 04 12:29:49 PM PST 24
Peak memory 197680 kb
Host smart-e1189265-8090-4de3-a7bc-89280091b34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306996032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.306996032
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.177808737
Short name T1032
Test name
Test status
Simulation time 21294412546 ps
CPU time 291.33 seconds
Started Feb 04 12:29:31 PM PST 24
Finished Feb 04 12:34:28 PM PST 24
Peak memory 199708 kb
Host smart-1dd7bb69-c935-40d0-b4e7-ca5eeeec5d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177808737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.177808737
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.828785150
Short name T703
Test name
Test status
Simulation time 1704804738 ps
CPU time 4.68 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:29:44 PM PST 24
Peak memory 197636 kb
Host smart-7f7857b2-065d-48dd-ada2-febf3fad4d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828785150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.828785150
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1488124993
Short name T817
Test name
Test status
Simulation time 69439085487 ps
CPU time 29.88 seconds
Started Feb 04 12:29:39 PM PST 24
Finished Feb 04 12:30:20 PM PST 24
Peak memory 198648 kb
Host smart-b40f81f3-c4cb-4ea9-bbd5-9430f75b0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488124993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1488124993
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3456048746
Short name T538
Test name
Test status
Simulation time 36399211137 ps
CPU time 8.15 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:30:01 PM PST 24
Peak memory 195548 kb
Host smart-8fae80ec-9826-41df-b613-abf3092945db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456048746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3456048746
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2405188696
Short name T986
Test name
Test status
Simulation time 951038334 ps
CPU time 2.21 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:29:55 PM PST 24
Peak memory 197528 kb
Host smart-d425af9d-567e-471a-9714-c7020d27145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405188696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2405188696
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3767614173
Short name T261
Test name
Test status
Simulation time 1008949981127 ps
CPU time 141.24 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:32:14 PM PST 24
Peak memory 199620 kb
Host smart-6e627d74-b781-4073-9111-26aca2d306cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767614173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3767614173
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3426718285
Short name T711
Test name
Test status
Simulation time 1097633033 ps
CPU time 4.91 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:29:43 PM PST 24
Peak memory 198912 kb
Host smart-f0593b17-ea72-46e1-9507-4575643b5b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426718285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3426718285
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1183492330
Short name T852
Test name
Test status
Simulation time 64780109340 ps
CPU time 22.39 seconds
Started Feb 04 12:29:40 PM PST 24
Finished Feb 04 12:30:14 PM PST 24
Peak memory 199840 kb
Host smart-60325a35-0514-4033-9ea6-751a97b4e250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183492330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1183492330
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2963764314
Short name T821
Test name
Test status
Simulation time 12595331939 ps
CPU time 31.87 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:32:52 PM PST 24
Peak memory 199872 kb
Host smart-d67248a1-fee8-4174-9596-d896c43ba217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963764314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2963764314
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3503445555
Short name T775
Test name
Test status
Simulation time 13589481055 ps
CPU time 9.17 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:32:30 PM PST 24
Peak memory 199692 kb
Host smart-5f0bfc7d-fd2b-4f98-b35e-ee0d051deb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503445555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3503445555
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2107503270
Short name T850
Test name
Test status
Simulation time 61537930190 ps
CPU time 21.53 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:32:42 PM PST 24
Peak memory 199724 kb
Host smart-aefe448f-916b-4074-bce1-647126a4a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107503270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2107503270
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.817850466
Short name T240
Test name
Test status
Simulation time 104465483483 ps
CPU time 72.26 seconds
Started Feb 04 12:32:14 PM PST 24
Finished Feb 04 12:33:31 PM PST 24
Peak memory 199524 kb
Host smart-da33e828-1d14-4769-978b-cb7ec1cacfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817850466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.817850466
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3337343107
Short name T1092
Test name
Test status
Simulation time 122724977912 ps
CPU time 38.34 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:32:59 PM PST 24
Peak memory 199716 kb
Host smart-35244ada-f6a8-4137-95ce-6abee9f71368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337343107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3337343107
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3289656413
Short name T159
Test name
Test status
Simulation time 46721114708 ps
CPU time 70.86 seconds
Started Feb 04 12:32:17 PM PST 24
Finished Feb 04 12:33:31 PM PST 24
Peak memory 199560 kb
Host smart-21c134fc-301e-41b6-a59a-de9a95d3652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289656413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3289656413
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.309333840
Short name T1129
Test name
Test status
Simulation time 65332171438 ps
CPU time 50.74 seconds
Started Feb 04 12:32:17 PM PST 24
Finished Feb 04 12:33:11 PM PST 24
Peak memory 199804 kb
Host smart-5f97fab5-a49a-4a62-bef2-4bc0deb90768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309333840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.309333840
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1474926880
Short name T778
Test name
Test status
Simulation time 35123532881 ps
CPU time 13.42 seconds
Started Feb 04 12:32:17 PM PST 24
Finished Feb 04 12:32:34 PM PST 24
Peak memory 199352 kb
Host smart-cdc98160-bc58-4970-a095-4071502a7b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474926880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1474926880
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1164915540
Short name T1154
Test name
Test status
Simulation time 27096920891 ps
CPU time 17.76 seconds
Started Feb 04 12:32:18 PM PST 24
Finished Feb 04 12:32:39 PM PST 24
Peak memory 199756 kb
Host smart-7be64e21-04da-40b8-ba82-bac18a19d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164915540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1164915540
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.94373401
Short name T124
Test name
Test status
Simulation time 21092849084 ps
CPU time 28.89 seconds
Started Feb 04 12:32:17 PM PST 24
Finished Feb 04 12:32:49 PM PST 24
Peak memory 199828 kb
Host smart-ff4acf57-d970-4536-85ff-72c9987566ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94373401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.94373401
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.4088915179
Short name T965
Test name
Test status
Simulation time 76500324 ps
CPU time 0.57 seconds
Started Feb 04 12:29:39 PM PST 24
Finished Feb 04 12:29:51 PM PST 24
Peak memory 195144 kb
Host smart-94450c1f-684e-45af-9ef9-bc3e4f81e96c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088915179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4088915179
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3370934035
Short name T1157
Test name
Test status
Simulation time 179429342813 ps
CPU time 64.01 seconds
Started Feb 04 12:29:31 PM PST 24
Finished Feb 04 12:30:40 PM PST 24
Peak memory 199368 kb
Host smart-43e4ec30-5cd0-4bea-959a-3447ce8c294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370934035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3370934035
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3908172742
Short name T387
Test name
Test status
Simulation time 148657795502 ps
CPU time 69.8 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:30:49 PM PST 24
Peak memory 198836 kb
Host smart-d6b51237-4f92-4b99-9eec-3bb53dba82eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908172742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3908172742
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3568866018
Short name T252
Test name
Test status
Simulation time 28880002120 ps
CPU time 43.45 seconds
Started Feb 04 12:29:38 PM PST 24
Finished Feb 04 12:30:33 PM PST 24
Peak memory 199648 kb
Host smart-e5394dee-e66c-46ff-8bcd-e112f6fdfc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568866018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3568866018
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2602906703
Short name T1055
Test name
Test status
Simulation time 33457435864 ps
CPU time 61.95 seconds
Started Feb 04 12:29:38 PM PST 24
Finished Feb 04 12:30:51 PM PST 24
Peak memory 199728 kb
Host smart-7b303b16-7bfe-4865-9fd8-55a5c9e4962f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602906703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2602906703
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1786484280
Short name T661
Test name
Test status
Simulation time 58930642436 ps
CPU time 336.67 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:35:29 PM PST 24
Peak memory 199628 kb
Host smart-5a9047f3-2708-4e63-b58a-af2bb86f83a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1786484280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1786484280
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2065164848
Short name T563
Test name
Test status
Simulation time 9325326206 ps
CPU time 6.31 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:29:51 PM PST 24
Peak memory 198136 kb
Host smart-5041b7c6-1b4b-46a8-8068-163529a60ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065164848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2065164848
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2999469120
Short name T838
Test name
Test status
Simulation time 40156617074 ps
CPU time 16.61 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:30:10 PM PST 24
Peak memory 197108 kb
Host smart-4904b871-f4b3-411e-9b4e-4e98a222fa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999469120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2999469120
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3276190861
Short name T1004
Test name
Test status
Simulation time 32065702823 ps
CPU time 128.59 seconds
Started Feb 04 12:29:38 PM PST 24
Finished Feb 04 12:31:59 PM PST 24
Peak memory 199768 kb
Host smart-64303c32-593f-46b9-82e3-defabdc06708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276190861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3276190861
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1586605476
Short name T656
Test name
Test status
Simulation time 1906816387 ps
CPU time 6.38 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:29:46 PM PST 24
Peak memory 197716 kb
Host smart-f0f2b19c-b1a9-4a06-b044-0a016f2970ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586605476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1586605476
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.4010416771
Short name T1112
Test name
Test status
Simulation time 67204193682 ps
CPU time 25.69 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:30:12 PM PST 24
Peak memory 199636 kb
Host smart-642cf49b-6da9-4cfe-baa4-099bf4965593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010416771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4010416771
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3297756756
Short name T991
Test name
Test status
Simulation time 2770877403 ps
CPU time 1.67 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:29:41 PM PST 24
Peak memory 195140 kb
Host smart-0e27c45b-7291-4e47-82c1-a3bf5f42762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297756756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3297756756
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.797112749
Short name T566
Test name
Test status
Simulation time 693670981 ps
CPU time 2.83 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:29:42 PM PST 24
Peak memory 199124 kb
Host smart-6c556519-58c4-4596-bd7a-61ac0d394997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797112749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.797112749
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3039120806
Short name T1094
Test name
Test status
Simulation time 971169022 ps
CPU time 3.26 seconds
Started Feb 04 12:29:38 PM PST 24
Finished Feb 04 12:29:52 PM PST 24
Peak memory 199548 kb
Host smart-dda12f8d-2506-4bd0-8184-b2be66d1bbbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039120806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3039120806
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2571302928
Short name T998
Test name
Test status
Simulation time 1165298808 ps
CPU time 1.86 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 197936 kb
Host smart-d9e3a371-1009-4fbb-b32f-42198695360d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571302928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2571302928
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2209585249
Short name T510
Test name
Test status
Simulation time 5806044645 ps
CPU time 8.72 seconds
Started Feb 04 12:29:36 PM PST 24
Finished Feb 04 12:29:48 PM PST 24
Peak memory 195628 kb
Host smart-55591ba1-417e-437d-a9f9-13cfc9216d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209585249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2209585249
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2239522327
Short name T270
Test name
Test status
Simulation time 114510424717 ps
CPU time 44.77 seconds
Started Feb 04 12:32:16 PM PST 24
Finished Feb 04 12:33:05 PM PST 24
Peak memory 199720 kb
Host smart-8d484076-7e90-4868-9652-c4bf9ea5e761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239522327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2239522327
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1111449213
Short name T1029
Test name
Test status
Simulation time 48704278049 ps
CPU time 13.99 seconds
Started Feb 04 12:32:42 PM PST 24
Finished Feb 04 12:33:04 PM PST 24
Peak memory 199788 kb
Host smart-6335bc05-b5ce-45f0-8528-d6910d86765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111449213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1111449213
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1920531643
Short name T204
Test name
Test status
Simulation time 9534798468 ps
CPU time 14.16 seconds
Started Feb 04 12:32:38 PM PST 24
Finished Feb 04 12:32:54 PM PST 24
Peak memory 199540 kb
Host smart-50cacaca-5228-49d4-afc6-f436c49934d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920531643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1920531643
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4070459357
Short name T242
Test name
Test status
Simulation time 17487141096 ps
CPU time 61.18 seconds
Started Feb 04 12:32:37 PM PST 24
Finished Feb 04 12:33:40 PM PST 24
Peak memory 199768 kb
Host smart-2af14202-ec59-4abd-9fd8-1a4e8c2c2126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070459357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4070459357
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1081889187
Short name T333
Test name
Test status
Simulation time 100705780215 ps
CPU time 25.87 seconds
Started Feb 04 12:32:38 PM PST 24
Finished Feb 04 12:33:05 PM PST 24
Peak memory 199780 kb
Host smart-d2f2e08f-cec0-4af2-9849-7b423a162b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081889187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1081889187
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1358188922
Short name T288
Test name
Test status
Simulation time 110678114505 ps
CPU time 234.9 seconds
Started Feb 04 12:32:41 PM PST 24
Finished Feb 04 12:36:45 PM PST 24
Peak memory 199740 kb
Host smart-77221891-561d-4d67-8e4f-48ba384e9ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358188922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1358188922
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2263125315
Short name T766
Test name
Test status
Simulation time 9978042945 ps
CPU time 14.87 seconds
Started Feb 04 12:32:36 PM PST 24
Finished Feb 04 12:32:52 PM PST 24
Peak memory 199744 kb
Host smart-ff295b27-bf2d-4b4a-b8cf-6012948cf315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263125315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2263125315
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1745097852
Short name T118
Test name
Test status
Simulation time 110485077806 ps
CPU time 48.34 seconds
Started Feb 04 12:32:38 PM PST 24
Finished Feb 04 12:33:28 PM PST 24
Peak memory 199856 kb
Host smart-c96fe797-e236-4898-9267-e76e9189995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745097852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1745097852
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3285424971
Short name T360
Test name
Test status
Simulation time 98631928429 ps
CPU time 52.8 seconds
Started Feb 04 12:32:38 PM PST 24
Finished Feb 04 12:33:32 PM PST 24
Peak memory 199788 kb
Host smart-8373ba98-c1a4-4a66-a004-e1929f8015bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285424971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3285424971
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4040001603
Short name T713
Test name
Test status
Simulation time 38598705 ps
CPU time 0.53 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:32 PM PST 24
Peak memory 194300 kb
Host smart-dd2743aa-9904-427a-ad9c-e20e81441124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040001603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4040001603
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3533209316
Short name T702
Test name
Test status
Simulation time 20976498508 ps
CPU time 32.89 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:29:06 PM PST 24
Peak memory 199684 kb
Host smart-22c98bf2-48c5-4077-8a7a-1e8b335fac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533209316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3533209316
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.305746650
Short name T741
Test name
Test status
Simulation time 78733573311 ps
CPU time 20.26 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:54 PM PST 24
Peak memory 198892 kb
Host smart-edfbe800-af67-4da6-9b34-2a0eba964238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305746650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.305746650
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.286984409
Short name T976
Test name
Test status
Simulation time 74354685472 ps
CPU time 38.21 seconds
Started Feb 04 12:28:19 PM PST 24
Finished Feb 04 12:29:03 PM PST 24
Peak memory 199696 kb
Host smart-27227853-96f4-403d-8841-461a1673e13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286984409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.286984409
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4190929176
Short name T664
Test name
Test status
Simulation time 2216351746794 ps
CPU time 717.19 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:40:29 PM PST 24
Peak memory 199728 kb
Host smart-69555ec6-40c8-40b9-bd79-8bcfce9c2b25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190929176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4190929176
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3290352290
Short name T1059
Test name
Test status
Simulation time 77041504329 ps
CPU time 307.35 seconds
Started Feb 04 12:28:33 PM PST 24
Finished Feb 04 12:33:47 PM PST 24
Peak memory 199828 kb
Host smart-8e6ec516-45fe-4ed9-83f5-dcb22df6302a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290352290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3290352290
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3003174482
Short name T1161
Test name
Test status
Simulation time 2178877726 ps
CPU time 4.24 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:35 PM PST 24
Peak memory 195176 kb
Host smart-0d8329da-1cb1-4e96-ba5a-6b59eab350af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003174482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3003174482
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1386714028
Short name T410
Test name
Test status
Simulation time 256749884086 ps
CPU time 136.76 seconds
Started Feb 04 12:28:13 PM PST 24
Finished Feb 04 12:30:32 PM PST 24
Peak memory 199676 kb
Host smart-cdabc1ac-8346-4b42-a065-449a58b45e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386714028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1386714028
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.462939994
Short name T1204
Test name
Test status
Simulation time 11951277360 ps
CPU time 169.83 seconds
Started Feb 04 12:28:17 PM PST 24
Finished Feb 04 12:31:15 PM PST 24
Peak memory 199728 kb
Host smart-5b8e53b7-baab-4ec5-b94d-b614975572b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462939994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.462939994
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3427806949
Short name T618
Test name
Test status
Simulation time 124376277 ps
CPU time 0.73 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:34 PM PST 24
Peak memory 194968 kb
Host smart-61b6025a-ecee-4595-9d40-8ab0c5f83ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3427806949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3427806949
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3636036197
Short name T616
Test name
Test status
Simulation time 19006232982 ps
CPU time 29.34 seconds
Started Feb 04 12:28:17 PM PST 24
Finished Feb 04 12:28:54 PM PST 24
Peak memory 199852 kb
Host smart-838713e8-3fba-49ec-a172-49baa671730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636036197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3636036197
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1346225853
Short name T489
Test name
Test status
Simulation time 1538843943 ps
CPU time 3.08 seconds
Started Feb 04 12:28:24 PM PST 24
Finished Feb 04 12:28:33 PM PST 24
Peak memory 195084 kb
Host smart-896f1a54-a9a7-4d32-92c3-9d8fbec8f79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346225853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1346225853
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1594871837
Short name T88
Test name
Test status
Simulation time 35861649 ps
CPU time 0.73 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:34 PM PST 24
Peak memory 217168 kb
Host smart-728f1dd7-6a60-45ec-baa9-65d742f60bce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594871837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1594871837
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.671209089
Short name T1063
Test name
Test status
Simulation time 748206760 ps
CPU time 2.36 seconds
Started Feb 04 12:28:17 PM PST 24
Finished Feb 04 12:28:27 PM PST 24
Peak memory 198116 kb
Host smart-0362f585-1b72-4362-bd73-c688e69915c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671209089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.671209089
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1040151534
Short name T162
Test name
Test status
Simulation time 212728359555 ps
CPU time 357.19 seconds
Started Feb 04 12:28:33 PM PST 24
Finished Feb 04 12:34:37 PM PST 24
Peak memory 199748 kb
Host smart-d9d2f499-db77-47d1-8ef5-07f5c04aac03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040151534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1040151534
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3289467603
Short name T1001
Test name
Test status
Simulation time 140777855894 ps
CPU time 390.74 seconds
Started Feb 04 12:28:15 PM PST 24
Finished Feb 04 12:34:55 PM PST 24
Peak memory 210432 kb
Host smart-d73cb5b3-576d-4d97-b8dc-632fe8d9a952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289467603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3289467603
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.560979270
Short name T996
Test name
Test status
Simulation time 1038240868 ps
CPU time 1.32 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:28:37 PM PST 24
Peak memory 197840 kb
Host smart-7ea8682a-5ab6-4bb8-b6b7-b1efb1c40fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560979270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.560979270
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2472807935
Short name T591
Test name
Test status
Simulation time 82065729683 ps
CPU time 54.91 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:29:28 PM PST 24
Peak memory 199924 kb
Host smart-899c0d85-9414-468e-ab89-b61ed128a677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472807935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2472807935
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3505508779
Short name T851
Test name
Test status
Simulation time 95445425 ps
CPU time 0.51 seconds
Started Feb 04 12:29:47 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 195192 kb
Host smart-4745e7f2-d5f1-4c35-bb2b-d34e696aee62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505508779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3505508779
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2431603549
Short name T338
Test name
Test status
Simulation time 66028287021 ps
CPU time 27.78 seconds
Started Feb 04 12:29:45 PM PST 24
Finished Feb 04 12:30:20 PM PST 24
Peak memory 199736 kb
Host smart-e22e7715-dc24-4cb0-9f98-deaba4cb6ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431603549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2431603549
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.365879265
Short name T972
Test name
Test status
Simulation time 28823334881 ps
CPU time 47.51 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:30:40 PM PST 24
Peak memory 199372 kb
Host smart-78dee668-5910-42de-a260-d855816f348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365879265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.365879265
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3354982278
Short name T320
Test name
Test status
Simulation time 31675931817 ps
CPU time 12.97 seconds
Started Feb 04 12:29:47 PM PST 24
Finished Feb 04 12:30:06 PM PST 24
Peak memory 199404 kb
Host smart-7a76aaa3-efd6-4a95-8710-6f23b0d46178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354982278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3354982278
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2952552092
Short name T1097
Test name
Test status
Simulation time 245869096543 ps
CPU time 116.06 seconds
Started Feb 04 12:29:39 PM PST 24
Finished Feb 04 12:31:46 PM PST 24
Peak memory 199744 kb
Host smart-bb6dcb17-b8f6-43c3-adde-14a7e5168d26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952552092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2952552092
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2774450016
Short name T695
Test name
Test status
Simulation time 192855568207 ps
CPU time 265.19 seconds
Started Feb 04 12:29:39 PM PST 24
Finished Feb 04 12:34:15 PM PST 24
Peak memory 199860 kb
Host smart-4c74f973-f872-4f60-b922-d420d4a9799e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2774450016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2774450016
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1384674186
Short name T981
Test name
Test status
Simulation time 856145347 ps
CPU time 2.14 seconds
Started Feb 04 12:29:34 PM PST 24
Finished Feb 04 12:29:41 PM PST 24
Peak memory 195272 kb
Host smart-de77e692-d71c-4df2-9943-2f4ab33b482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384674186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1384674186
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.4178428775
Short name T1196
Test name
Test status
Simulation time 922233548 ps
CPU time 0.97 seconds
Started Feb 04 12:29:39 PM PST 24
Finished Feb 04 12:29:51 PM PST 24
Peak memory 193304 kb
Host smart-c34704e4-d35e-43bf-8ce5-5e32b7115686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178428775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.4178428775
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.974084263
Short name T1156
Test name
Test status
Simulation time 10840034179 ps
CPU time 155.34 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:32:22 PM PST 24
Peak memory 199792 kb
Host smart-5adc3b13-f2bc-4363-916a-d807d105f18d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974084263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.974084263
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2312726459
Short name T835
Test name
Test status
Simulation time 3283710712 ps
CPU time 35.08 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:30:28 PM PST 24
Peak memory 198236 kb
Host smart-391b1ee6-770b-4316-9e30-0f358ef6d17c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312726459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2312726459
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1646397945
Short name T375
Test name
Test status
Simulation time 210188427467 ps
CPU time 52.09 seconds
Started Feb 04 12:29:42 PM PST 24
Finished Feb 04 12:30:44 PM PST 24
Peak memory 199536 kb
Host smart-2a62b383-e154-43dd-a3bd-30e2bc3331b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646397945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1646397945
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3839701300
Short name T652
Test name
Test status
Simulation time 707970107 ps
CPU time 1.24 seconds
Started Feb 04 12:29:39 PM PST 24
Finished Feb 04 12:29:51 PM PST 24
Peak memory 195140 kb
Host smart-505ca205-cbdc-45a5-a095-7e1a13d6fedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839701300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3839701300
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3691492388
Short name T960
Test name
Test status
Simulation time 497704918 ps
CPU time 2.57 seconds
Started Feb 04 12:29:40 PM PST 24
Finished Feb 04 12:29:55 PM PST 24
Peak memory 198524 kb
Host smart-a2cb65f5-4d26-42b7-8ed6-5710e23f4b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691492388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3691492388
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.738175781
Short name T1132
Test name
Test status
Simulation time 399643913996 ps
CPU time 36.32 seconds
Started Feb 04 12:29:42 PM PST 24
Finished Feb 04 12:30:29 PM PST 24
Peak memory 208208 kb
Host smart-8fbbb91f-a4a9-4e9c-8b87-62e3be2aadb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738175781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.738175781
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3700914710
Short name T830
Test name
Test status
Simulation time 85001488975 ps
CPU time 328.31 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:35:21 PM PST 24
Peak memory 208216 kb
Host smart-580ad50f-e103-44d6-829a-69231051ae71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700914710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3700914710
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2143745537
Short name T1233
Test name
Test status
Simulation time 7198850673 ps
CPU time 9.14 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:29:57 PM PST 24
Peak memory 198776 kb
Host smart-1675a538-7d43-489f-b1ce-49459634eed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143745537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2143745537
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3047576896
Short name T179
Test name
Test status
Simulation time 62165880500 ps
CPU time 152.76 seconds
Started Feb 04 12:29:37 PM PST 24
Finished Feb 04 12:32:18 PM PST 24
Peak memory 199716 kb
Host smart-34ce6e27-230c-4ce1-8c26-20680aba9fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047576896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3047576896
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3585826168
Short name T94
Test name
Test status
Simulation time 63653714 ps
CPU time 0.61 seconds
Started Feb 04 12:29:47 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 195156 kb
Host smart-a2011514-7d9f-4404-8896-e9f7d7cb0318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585826168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3585826168
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2941807516
Short name T832
Test name
Test status
Simulation time 152327890465 ps
CPU time 32.44 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:30:26 PM PST 24
Peak memory 199768 kb
Host smart-78109242-ab77-4a4f-a1b2-3a41e1618fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941807516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2941807516
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1236902084
Short name T176
Test name
Test status
Simulation time 18348974673 ps
CPU time 40.39 seconds
Started Feb 04 12:29:35 PM PST 24
Finished Feb 04 12:30:20 PM PST 24
Peak memory 199764 kb
Host smart-b38f9b95-209b-4970-95c3-9cec84088f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236902084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1236902084
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.827413054
Short name T256
Test name
Test status
Simulation time 226079477431 ps
CPU time 285.87 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:34:40 PM PST 24
Peak memory 199792 kb
Host smart-faef43df-b0d7-4336-a819-4e5b05c5fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827413054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.827413054
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.826880155
Short name T567
Test name
Test status
Simulation time 114159125847 ps
CPU time 92.5 seconds
Started Feb 04 12:29:38 PM PST 24
Finished Feb 04 12:31:23 PM PST 24
Peak memory 199160 kb
Host smart-4d0b5356-066b-4434-bd8f-b7829437a54a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826880155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.826880155
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4038758270
Short name T794
Test name
Test status
Simulation time 48995134273 ps
CPU time 220.43 seconds
Started Feb 04 12:29:45 PM PST 24
Finished Feb 04 12:33:33 PM PST 24
Peak memory 199788 kb
Host smart-ea4a83c1-8c10-4aeb-b531-6ccd209bc91b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038758270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4038758270
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_noise_filter.995764777
Short name T580
Test name
Test status
Simulation time 41540872540 ps
CPU time 61.95 seconds
Started Feb 04 12:29:42 PM PST 24
Finished Feb 04 12:30:54 PM PST 24
Peak memory 199284 kb
Host smart-fce5092e-a7fe-4206-b498-948aa366f589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995764777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.995764777
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.435566443
Short name T186
Test name
Test status
Simulation time 6134330659 ps
CPU time 84.87 seconds
Started Feb 04 12:29:38 PM PST 24
Finished Feb 04 12:31:13 PM PST 24
Peak memory 199840 kb
Host smart-fd46e6af-2317-4e6a-8117-4699763c35fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435566443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.435566443
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1295362660
Short name T522
Test name
Test status
Simulation time 996773238 ps
CPU time 8.98 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:30:02 PM PST 24
Peak memory 197400 kb
Host smart-4babf41f-8ecf-46f2-8a6e-83b7aa269f45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295362660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1295362660
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2993619512
Short name T515
Test name
Test status
Simulation time 45627181475 ps
CPU time 35.87 seconds
Started Feb 04 12:29:42 PM PST 24
Finished Feb 04 12:30:28 PM PST 24
Peak memory 198728 kb
Host smart-afb7e9db-b608-4376-8474-26f4fd394754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993619512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2993619512
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1363058223
Short name T756
Test name
Test status
Simulation time 41155811364 ps
CPU time 15.5 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:30:09 PM PST 24
Peak memory 195272 kb
Host smart-6bce5f4c-f6de-48ed-88aa-c98c383c4c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363058223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1363058223
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.853009942
Short name T1194
Test name
Test status
Simulation time 5792662225 ps
CPU time 14.83 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:30:07 PM PST 24
Peak memory 199136 kb
Host smart-fb98c173-ff62-46b7-a5b3-9aadccbf84eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853009942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.853009942
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.4069854770
Short name T292
Test name
Test status
Simulation time 311407578017 ps
CPU time 698.33 seconds
Started Feb 04 12:29:56 PM PST 24
Finished Feb 04 12:41:43 PM PST 24
Peak memory 224624 kb
Host smart-ee234242-c51f-41d4-8605-2720f428ff7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069854770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.4069854770
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2565223900
Short name T512
Test name
Test status
Simulation time 7832853948 ps
CPU time 11.61 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:30:05 PM PST 24
Peak memory 199164 kb
Host smart-d3ca30ce-e743-4601-9774-993a99063d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565223900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2565223900
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1461462385
Short name T946
Test name
Test status
Simulation time 59354146465 ps
CPU time 30.67 seconds
Started Feb 04 12:29:41 PM PST 24
Finished Feb 04 12:30:23 PM PST 24
Peak memory 199816 kb
Host smart-97e5b204-4273-466a-9251-f8ba61e45112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461462385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1461462385
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1756646022
Short name T1117
Test name
Test status
Simulation time 40856894 ps
CPU time 0.55 seconds
Started Feb 04 12:29:51 PM PST 24
Finished Feb 04 12:29:58 PM PST 24
Peak memory 195308 kb
Host smart-80b0f725-4790-4d80-948c-068387469c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756646022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1756646022
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2262443294
Short name T781
Test name
Test status
Simulation time 215787157242 ps
CPU time 165.29 seconds
Started Feb 04 12:29:43 PM PST 24
Finished Feb 04 12:32:38 PM PST 24
Peak memory 199736 kb
Host smart-5faf3f51-12b7-4b6a-bf21-2a7d6fb961dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262443294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2262443294
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3728682247
Short name T1021
Test name
Test status
Simulation time 154965083943 ps
CPU time 280.59 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:34:34 PM PST 24
Peak memory 199380 kb
Host smart-4e3cec8e-6688-4c67-a252-e7e97b82ccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728682247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3728682247
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1493740621
Short name T279
Test name
Test status
Simulation time 150788869481 ps
CPU time 107.24 seconds
Started Feb 04 12:29:40 PM PST 24
Finished Feb 04 12:31:39 PM PST 24
Peak memory 199360 kb
Host smart-8e10c7e6-6d3a-4d9a-b2b6-c52a5947f866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493740621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1493740621
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.298713291
Short name T757
Test name
Test status
Simulation time 474483826584 ps
CPU time 957.41 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:45:52 PM PST 24
Peak memory 198536 kb
Host smart-e7a3a585-e35f-47e6-bd90-ecd9a05f3ce1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298713291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.298713291
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.184846171
Short name T607
Test name
Test status
Simulation time 102265340308 ps
CPU time 700.88 seconds
Started Feb 04 12:29:56 PM PST 24
Finished Feb 04 12:41:44 PM PST 24
Peak memory 199804 kb
Host smart-53ef043a-0691-4465-baf6-9b4b834d8d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184846171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.184846171
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2204138276
Short name T667
Test name
Test status
Simulation time 88935674239 ps
CPU time 70.9 seconds
Started Feb 04 12:29:44 PM PST 24
Finished Feb 04 12:31:03 PM PST 24
Peak memory 207808 kb
Host smart-dd2894c5-d662-4617-92a3-447cf8bb37b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204138276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2204138276
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1122749639
Short name T1232
Test name
Test status
Simulation time 24294329936 ps
CPU time 934.09 seconds
Started Feb 04 12:29:49 PM PST 24
Finished Feb 04 12:45:29 PM PST 24
Peak memory 199812 kb
Host smart-a29f5c46-0d87-4f02-b8a9-153f2f25b9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122749639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1122749639
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3723626764
Short name T842
Test name
Test status
Simulation time 3906504833 ps
CPU time 20.95 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:30:15 PM PST 24
Peak memory 198272 kb
Host smart-d6ed1084-cfb4-49a3-ac0e-386ae7d794da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3723626764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3723626764
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2672037197
Short name T537
Test name
Test status
Simulation time 13372161483 ps
CPU time 5.85 seconds
Started Feb 04 12:29:47 PM PST 24
Finished Feb 04 12:29:59 PM PST 24
Peak memory 197444 kb
Host smart-0afd8bbd-8857-4d66-a369-05b11df8bc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672037197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2672037197
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2775900234
Short name T551
Test name
Test status
Simulation time 2700077497 ps
CPU time 0.88 seconds
Started Feb 04 12:29:56 PM PST 24
Finished Feb 04 12:30:06 PM PST 24
Peak memory 195108 kb
Host smart-85f9a989-1242-4da6-beca-4ddc059ae973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775900234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2775900234
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2655842488
Short name T693
Test name
Test status
Simulation time 5363798107 ps
CPU time 15.05 seconds
Started Feb 04 12:29:45 PM PST 24
Finished Feb 04 12:30:08 PM PST 24
Peak memory 199164 kb
Host smart-c4d722b1-f2d3-4250-80bb-a7f4e936f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655842488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2655842488
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1615029245
Short name T1020
Test name
Test status
Simulation time 43049296341 ps
CPU time 488.14 seconds
Started Feb 04 12:29:49 PM PST 24
Finished Feb 04 12:38:04 PM PST 24
Peak memory 224808 kb
Host smart-aab1b32e-8c20-4438-8798-7cbba3ab328b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615029245 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1615029245
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.650697816
Short name T662
Test name
Test status
Simulation time 871837725 ps
CPU time 2.57 seconds
Started Feb 04 12:29:33 PM PST 24
Finished Feb 04 12:29:40 PM PST 24
Peak memory 198596 kb
Host smart-eba9f5cd-c87c-4211-a800-e59246722c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650697816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.650697816
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3262109750
Short name T1148
Test name
Test status
Simulation time 34259934259 ps
CPU time 21.49 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:30:26 PM PST 24
Peak memory 199472 kb
Host smart-b257780a-1f4a-42cd-946f-c293596d6081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262109750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3262109750
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3879526212
Short name T827
Test name
Test status
Simulation time 25338416 ps
CPU time 0.52 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:09 PM PST 24
Peak memory 195196 kb
Host smart-5a1d1bac-98a4-4281-b73b-c1d0a8244f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879526212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3879526212
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.17607308
Short name T688
Test name
Test status
Simulation time 44564013155 ps
CPU time 69.31 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:31:10 PM PST 24
Peak memory 199340 kb
Host smart-3bda9d17-c199-4736-8b97-5731659886cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17607308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.17607308
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2819005239
Short name T1150
Test name
Test status
Simulation time 24671504911 ps
CPU time 18.47 seconds
Started Feb 04 12:29:43 PM PST 24
Finished Feb 04 12:30:11 PM PST 24
Peak memory 199588 kb
Host smart-b78d69d9-95c5-449a-9fd9-a335692641af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819005239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2819005239
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2343711792
Short name T180
Test name
Test status
Simulation time 133114451674 ps
CPU time 35.58 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:30:38 PM PST 24
Peak memory 199844 kb
Host smart-063ac31a-5a73-4e3c-928d-a2086d0668a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343711792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2343711792
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2104677999
Short name T907
Test name
Test status
Simulation time 159991833432 ps
CPU time 143.24 seconds
Started Feb 04 12:29:52 PM PST 24
Finished Feb 04 12:32:22 PM PST 24
Peak memory 199824 kb
Host smart-17a87047-7b2a-4b47-b845-435997fd486e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104677999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2104677999
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.645351192
Short name T800
Test name
Test status
Simulation time 2732417159 ps
CPU time 3.42 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:29:56 PM PST 24
Peak memory 197332 kb
Host smart-a59d94e0-2523-468b-8c81-6e57bbce58da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645351192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.645351192
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2072107172
Short name T416
Test name
Test status
Simulation time 149942423138 ps
CPU time 249.08 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:34:12 PM PST 24
Peak memory 208332 kb
Host smart-52b62a30-581f-423a-a017-e2b16a641f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072107172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2072107172
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1329380333
Short name T854
Test name
Test status
Simulation time 30126949050 ps
CPU time 833.6 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:43:56 PM PST 24
Peak memory 199928 kb
Host smart-8bfd433b-3cb7-4265-9aa3-cc2d014aacc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329380333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1329380333
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3267702798
Short name T30
Test name
Test status
Simulation time 3852881302 ps
CPU time 25.99 seconds
Started Feb 04 12:29:44 PM PST 24
Finished Feb 04 12:30:19 PM PST 24
Peak memory 198076 kb
Host smart-62ed77f6-4cd7-4f72-9a50-da29adbd5f96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267702798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3267702798
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1376907639
Short name T1066
Test name
Test status
Simulation time 50659854960 ps
CPU time 87.73 seconds
Started Feb 04 12:29:42 PM PST 24
Finished Feb 04 12:31:20 PM PST 24
Peak memory 199820 kb
Host smart-277ec7f8-d9e4-4a57-8902-8d27f8e978cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376907639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1376907639
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.528683834
Short name T521
Test name
Test status
Simulation time 2983107943 ps
CPU time 5.61 seconds
Started Feb 04 12:29:42 PM PST 24
Finished Feb 04 12:29:58 PM PST 24
Peak memory 195156 kb
Host smart-6b2f2620-28b9-4dba-8125-7d4becf14df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528683834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.528683834
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.460821681
Short name T1118
Test name
Test status
Simulation time 345451026 ps
CPU time 1.11 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 197380 kb
Host smart-001147ba-c092-488f-923c-c91410d88191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460821681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.460821681
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1402763469
Short name T801
Test name
Test status
Simulation time 147916113601 ps
CPU time 922.54 seconds
Started Feb 04 12:29:49 PM PST 24
Finished Feb 04 12:45:18 PM PST 24
Peak memory 216348 kb
Host smart-33739b99-85e2-4c21-9a45-3ed458e8403f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402763469 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1402763469
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.307441478
Short name T426
Test name
Test status
Simulation time 6694687451 ps
CPU time 32.2 seconds
Started Feb 04 12:29:49 PM PST 24
Finished Feb 04 12:30:27 PM PST 24
Peak memory 198668 kb
Host smart-085b1ea7-0658-46ce-8be3-c20141013bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307441478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.307441478
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.387268561
Short name T542
Test name
Test status
Simulation time 36137314589 ps
CPU time 61.14 seconds
Started Feb 04 12:29:58 PM PST 24
Finished Feb 04 12:31:08 PM PST 24
Peak memory 199904 kb
Host smart-d1fe51fb-0a51-4417-8c51-5fe5e95a8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387268561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.387268561
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.658882779
Short name T1106
Test name
Test status
Simulation time 31722409 ps
CPU time 0.57 seconds
Started Feb 04 12:29:50 PM PST 24
Finished Feb 04 12:29:56 PM PST 24
Peak memory 195072 kb
Host smart-830a7bfe-430c-4687-8a32-1160243ea0d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658882779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.658882779
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3900797775
Short name T1183
Test name
Test status
Simulation time 39171209117 ps
CPU time 66.25 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:31:00 PM PST 24
Peak memory 199708 kb
Host smart-252ee562-507c-4cf0-8fc8-deebf7362711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900797775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3900797775
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1001787254
Short name T631
Test name
Test status
Simulation time 54314273242 ps
CPU time 91.8 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:31:34 PM PST 24
Peak memory 199880 kb
Host smart-8b88608f-108c-4bca-8461-57d72d4b1e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001787254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1001787254
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.642103555
Short name T1069
Test name
Test status
Simulation time 138335988132 ps
CPU time 39.26 seconds
Started Feb 04 12:29:49 PM PST 24
Finished Feb 04 12:30:34 PM PST 24
Peak memory 197944 kb
Host smart-ceff39f1-7982-48b7-be11-d6b8f38faf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642103555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.642103555
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2726127523
Short name T1103
Test name
Test status
Simulation time 497091749091 ps
CPU time 736.97 seconds
Started Feb 04 12:29:49 PM PST 24
Finished Feb 04 12:42:12 PM PST 24
Peak memory 199136 kb
Host smart-6a2f31dd-649d-4c3b-b0bb-f0407e7db086
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726127523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2726127523
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2640889008
Short name T1185
Test name
Test status
Simulation time 234897599210 ps
CPU time 364.07 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:36:04 PM PST 24
Peak memory 199884 kb
Host smart-88a63f5e-7b1d-4502-abfa-02ac6ad50e6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640889008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2640889008
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.690568177
Short name T507
Test name
Test status
Simulation time 6228925151 ps
CPU time 14.69 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:30:20 PM PST 24
Peak memory 198036 kb
Host smart-6d63439e-1bd0-40bf-8989-fbebe3f466bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690568177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.690568177
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1003954676
Short name T704
Test name
Test status
Simulation time 38860534827 ps
CPU time 37.57 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:30:43 PM PST 24
Peak memory 200000 kb
Host smart-8cc3f31e-0502-406d-a068-4a16366127ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003954676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1003954676
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1255906220
Short name T1022
Test name
Test status
Simulation time 18127990668 ps
CPU time 124.47 seconds
Started Feb 04 12:29:45 PM PST 24
Finished Feb 04 12:31:57 PM PST 24
Peak memory 199736 kb
Host smart-5b1d00a1-532c-4eea-9bb5-57e58f6b93f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1255906220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1255906220
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1062671612
Short name T1226
Test name
Test status
Simulation time 227986033107 ps
CPU time 69.36 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:31:09 PM PST 24
Peak memory 198036 kb
Host smart-79afcd55-e056-4072-8cf2-72620a7c54ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062671612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1062671612
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.396652730
Short name T620
Test name
Test status
Simulation time 37616688855 ps
CPU time 13.89 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:15 PM PST 24
Peak memory 195516 kb
Host smart-103ac113-6135-455a-8e72-f8d968b1a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396652730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.396652730
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3172446991
Short name T665
Test name
Test status
Simulation time 485242806 ps
CPU time 2.6 seconds
Started Feb 04 12:29:50 PM PST 24
Finished Feb 04 12:30:00 PM PST 24
Peak memory 197972 kb
Host smart-7a20bb1e-6ab9-4036-9c4e-7e44932179d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172446991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3172446991
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2037372129
Short name T669
Test name
Test status
Simulation time 7737491074 ps
CPU time 12.03 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:21 PM PST 24
Peak memory 198608 kb
Host smart-625c782f-fbc7-45e6-bb73-80585a04874e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037372129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2037372129
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.973934899
Short name T432
Test name
Test status
Simulation time 77734822170 ps
CPU time 106.66 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:31:47 PM PST 24
Peak memory 199360 kb
Host smart-cac77a92-2ef5-43d9-9afc-5d2d748bfe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973934899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.973934899
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.858672654
Short name T491
Test name
Test status
Simulation time 63100144 ps
CPU time 0.54 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:02 PM PST 24
Peak memory 195152 kb
Host smart-5886bbf4-950b-4592-bbe8-8c82f7a13873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858672654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.858672654
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1609961529
Short name T442
Test name
Test status
Simulation time 41323183967 ps
CPU time 21.24 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:30:26 PM PST 24
Peak memory 199704 kb
Host smart-6a6a9ce0-36b5-418f-b71a-5430aef3d75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609961529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1609961529
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.662818874
Short name T1024
Test name
Test status
Simulation time 22443403377 ps
CPU time 37.45 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:39 PM PST 24
Peak memory 199144 kb
Host smart-cc928ab6-116b-4e80-bff4-1c88eeba3053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662818874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.662818874
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.337199342
Short name T525
Test name
Test status
Simulation time 420219077831 ps
CPU time 177.17 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:33:00 PM PST 24
Peak memory 198856 kb
Host smart-9131298b-b9dc-4e98-a1fc-68ac046c5ce2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337199342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.337199342
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3940334608
Short name T776
Test name
Test status
Simulation time 109831362845 ps
CPU time 699.38 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:41:32 PM PST 24
Peak memory 199728 kb
Host smart-9d1079f8-a97f-46c8-b437-964ad8af02d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940334608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3940334608
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3656952758
Short name T837
Test name
Test status
Simulation time 13039971366 ps
CPU time 15.01 seconds
Started Feb 04 12:30:03 PM PST 24
Finished Feb 04 12:30:25 PM PST 24
Peak memory 199092 kb
Host smart-a25b3284-3512-4e8a-9772-dcbac790406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656952758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3656952758
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1859765484
Short name T862
Test name
Test status
Simulation time 129910220993 ps
CPU time 87.83 seconds
Started Feb 04 12:29:50 PM PST 24
Finished Feb 04 12:31:25 PM PST 24
Peak memory 198740 kb
Host smart-185f753b-1508-4425-82a2-65a1eb7c444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859765484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1859765484
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2625998842
Short name T1128
Test name
Test status
Simulation time 26550125292 ps
CPU time 69.53 seconds
Started Feb 04 12:29:52 PM PST 24
Finished Feb 04 12:31:08 PM PST 24
Peak memory 199772 kb
Host smart-6db6ea04-e221-45ab-acd6-48a88eef8ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625998842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2625998842
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3167790474
Short name T988
Test name
Test status
Simulation time 1076139619 ps
CPU time 2.73 seconds
Started Feb 04 12:29:50 PM PST 24
Finished Feb 04 12:30:00 PM PST 24
Peak memory 197340 kb
Host smart-17f1faac-4255-46b7-ac07-858afe839fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167790474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3167790474
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3811846323
Short name T324
Test name
Test status
Simulation time 218082205201 ps
CPU time 206.16 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:33:31 PM PST 24
Peak memory 199356 kb
Host smart-bb47161d-d59a-4769-a6e5-0cd5551d48c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811846323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3811846323
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3320249123
Short name T855
Test name
Test status
Simulation time 715419519 ps
CPU time 0.94 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:01 PM PST 24
Peak memory 195132 kb
Host smart-938fea2c-d915-4686-8c16-5b4bc45d6c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320249123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3320249123
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.871951998
Short name T1101
Test name
Test status
Simulation time 5970847715 ps
CPU time 19.03 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:30:22 PM PST 24
Peak memory 199412 kb
Host smart-f9dd5c6c-71c6-4628-b730-ba7228fb3248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871951998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.871951998
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3212226760
Short name T874
Test name
Test status
Simulation time 2475446687 ps
CPU time 1.72 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:30:07 PM PST 24
Peak memory 198112 kb
Host smart-bd5d5d04-5bf0-4e2c-8238-f99f98e13328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212226760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3212226760
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.320597678
Short name T899
Test name
Test status
Simulation time 63301145235 ps
CPU time 235.24 seconds
Started Feb 04 12:29:48 PM PST 24
Finished Feb 04 12:33:49 PM PST 24
Peak memory 199820 kb
Host smart-6e4dd297-7d58-457e-b194-d3c2247fcef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320597678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.320597678
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3775342707
Short name T492
Test name
Test status
Simulation time 11389359 ps
CPU time 0.52 seconds
Started Feb 04 12:30:00 PM PST 24
Finished Feb 04 12:30:08 PM PST 24
Peak memory 194344 kb
Host smart-b15ce921-8880-44bc-978c-3129fe8a49a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775342707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3775342707
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2161774041
Short name T779
Test name
Test status
Simulation time 52221608631 ps
CPU time 25.21 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:30:24 PM PST 24
Peak memory 199892 kb
Host smart-d3e9502a-2db1-49b3-8dbe-eaa94da87d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161774041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2161774041
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3094749794
Short name T861
Test name
Test status
Simulation time 46454021964 ps
CPU time 45.05 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:30:45 PM PST 24
Peak memory 199596 kb
Host smart-2cacd407-9ef4-4d2e-9b7f-16fe727dc645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094749794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3094749794
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1621684105
Short name T202
Test name
Test status
Simulation time 38678698324 ps
CPU time 60.13 seconds
Started Feb 04 12:29:44 PM PST 24
Finished Feb 04 12:30:53 PM PST 24
Peak memory 199780 kb
Host smart-43d007bb-fb09-4747-9dbb-8de2a80cd74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621684105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1621684105
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.4266007225
Short name T622
Test name
Test status
Simulation time 28337047698 ps
CPU time 12.74 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:14 PM PST 24
Peak memory 196416 kb
Host smart-2244f399-c3b4-4806-96c5-40442a256066
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266007225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.4266007225
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.870085771
Short name T303
Test name
Test status
Simulation time 145340991058 ps
CPU time 983.64 seconds
Started Feb 04 12:30:08 PM PST 24
Finished Feb 04 12:46:38 PM PST 24
Peak memory 199792 kb
Host smart-422b0d43-da07-4c04-b193-fb5d1514909d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870085771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.870085771
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3688831022
Short name T984
Test name
Test status
Simulation time 5174599955 ps
CPU time 2.64 seconds
Started Feb 04 12:30:07 PM PST 24
Finished Feb 04 12:30:16 PM PST 24
Peak memory 199832 kb
Host smart-9aa4798c-2817-4f86-bdbc-ac4383e7eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688831022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3688831022
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3271650287
Short name T536
Test name
Test status
Simulation time 44258105550 ps
CPU time 39.3 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:30:42 PM PST 24
Peak memory 199276 kb
Host smart-45035944-4451-4d7e-a2ea-bd62ccf5adca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271650287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3271650287
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1518238146
Short name T294
Test name
Test status
Simulation time 5762397670 ps
CPU time 86.86 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:31:36 PM PST 24
Peak memory 199784 kb
Host smart-11312502-20aa-4e7b-a735-dedab90269df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518238146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1518238146
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3419665453
Short name T872
Test name
Test status
Simulation time 3705946339 ps
CPU time 12.85 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:30:19 PM PST 24
Peak memory 198344 kb
Host smart-eac90be1-9631-4f17-bd41-f85b1fd989b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419665453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3419665453
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.5343653
Short name T873
Test name
Test status
Simulation time 235531306986 ps
CPU time 471.17 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:37:54 PM PST 24
Peak memory 199796 kb
Host smart-ed4bee8a-3760-4a22-9b48-4448eb2b7b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5343653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.5343653
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.683350295
Short name T585
Test name
Test status
Simulation time 2572440344 ps
CPU time 0.92 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:02 PM PST 24
Peak memory 195160 kb
Host smart-7d313b6b-c93d-44e1-89d4-4e9c15a4ff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683350295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.683350295
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1675511638
Short name T511
Test name
Test status
Simulation time 328171523 ps
CPU time 1 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:10 PM PST 24
Peak memory 197856 kb
Host smart-b64b212a-e43c-488f-ae54-c3f05087efa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675511638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1675511638
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.497140047
Short name T828
Test name
Test status
Simulation time 243403275331 ps
CPU time 744.12 seconds
Started Feb 04 12:30:04 PM PST 24
Finished Feb 04 12:42:35 PM PST 24
Peak memory 212512 kb
Host smart-afea3bfa-31f6-4f1d-b506-5831daf4a00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497140047 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.497140047
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.4141726251
Short name T575
Test name
Test status
Simulation time 12140923570 ps
CPU time 39.13 seconds
Started Feb 04 12:29:52 PM PST 24
Finished Feb 04 12:30:38 PM PST 24
Peak memory 199596 kb
Host smart-771867e3-63a3-4d5d-b3b2-ec57774b5d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141726251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.4141726251
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1788012773
Short name T1193
Test name
Test status
Simulation time 139348883359 ps
CPU time 230.4 seconds
Started Feb 04 12:29:46 PM PST 24
Finished Feb 04 12:33:43 PM PST 24
Peak memory 199708 kb
Host smart-9f70bbd5-2de1-4678-8895-52e7979e59f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788012773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1788012773
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3966283852
Short name T1070
Test name
Test status
Simulation time 24890332 ps
CPU time 0.59 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:09 PM PST 24
Peak memory 195252 kb
Host smart-345b8914-d436-4bbc-8f13-e7affaf619cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966283852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3966283852
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.530073536
Short name T1211
Test name
Test status
Simulation time 92609845216 ps
CPU time 137.44 seconds
Started Feb 04 12:29:59 PM PST 24
Finished Feb 04 12:32:25 PM PST 24
Peak memory 199740 kb
Host smart-7c6f7011-02e9-4135-b601-427bee8c3e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530073536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.530073536
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1536682853
Short name T111
Test name
Test status
Simulation time 152595506948 ps
CPU time 56.17 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:31:09 PM PST 24
Peak memory 198844 kb
Host smart-5b195c98-70d1-4d65-8cc2-128231efe2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536682853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1536682853
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3509038202
Short name T1037
Test name
Test status
Simulation time 75378600669 ps
CPU time 117.89 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199784 kb
Host smart-2fcdd187-44f1-4f40-a420-8ecb4f381de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509038202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3509038202
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.60360248
Short name T1206
Test name
Test status
Simulation time 626435539 ps
CPU time 1.67 seconds
Started Feb 04 12:29:52 PM PST 24
Finished Feb 04 12:30:00 PM PST 24
Peak memory 195020 kb
Host smart-6f8215e8-5749-44bc-9047-4e28cea20923
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60360248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.60360248
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3854715568
Short name T15
Test name
Test status
Simulation time 202284331470 ps
CPU time 546.26 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:39:05 PM PST 24
Peak memory 199776 kb
Host smart-a2616723-bb37-4423-adda-c3e614725769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854715568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3854715568
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.287066250
Short name T621
Test name
Test status
Simulation time 4871552067 ps
CPU time 8.78 seconds
Started Feb 04 12:29:59 PM PST 24
Finished Feb 04 12:30:16 PM PST 24
Peak memory 197780 kb
Host smart-cd3107a1-e74c-481d-8bbc-e0e7fbfbefe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287066250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.287066250
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.4165526087
Short name T797
Test name
Test status
Simulation time 213073109881 ps
CPU time 156.49 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:32:45 PM PST 24
Peak memory 200204 kb
Host smart-eac83f91-89a6-41bd-859f-bc4c5d7c62a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165526087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.4165526087
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2364827980
Short name T163
Test name
Test status
Simulation time 16127172006 ps
CPU time 362.91 seconds
Started Feb 04 12:29:53 PM PST 24
Finished Feb 04 12:36:02 PM PST 24
Peak memory 199792 kb
Host smart-5035f921-6ac8-4002-822f-6a546081622e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2364827980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2364827980
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.893231217
Short name T630
Test name
Test status
Simulation time 3135902904 ps
CPU time 9.6 seconds
Started Feb 04 12:30:07 PM PST 24
Finished Feb 04 12:30:23 PM PST 24
Peak memory 198532 kb
Host smart-8aaf7619-b6ad-4eac-8bf9-3703a83ced5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893231217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.893231217
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.4139844195
Short name T929
Test name
Test status
Simulation time 23941463302 ps
CPU time 40.51 seconds
Started Feb 04 12:30:07 PM PST 24
Finished Feb 04 12:30:54 PM PST 24
Peak memory 198124 kb
Host smart-3b8facf9-bbc1-4c55-bf85-e3e53707bd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139844195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.4139844195
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1176097597
Short name T710
Test name
Test status
Simulation time 5844516840 ps
CPU time 10.13 seconds
Started Feb 04 12:30:00 PM PST 24
Finished Feb 04 12:30:18 PM PST 24
Peak memory 195504 kb
Host smart-f268d868-0283-458d-9614-8b8a4cc52ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176097597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1176097597
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1459674348
Short name T1105
Test name
Test status
Simulation time 469532202 ps
CPU time 1.86 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:03 PM PST 24
Peak memory 197416 kb
Host smart-f7a1dd65-784b-4f5c-87d2-74463ed8340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459674348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1459674348
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1050446851
Short name T1177
Test name
Test status
Simulation time 3137238509140 ps
CPU time 4488.87 seconds
Started Feb 04 12:29:58 PM PST 24
Finished Feb 04 01:44:56 PM PST 24
Peak memory 208208 kb
Host smart-67c4c21a-418f-40a7-8759-6e0ccabd5111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050446851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1050446851
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.4051046969
Short name T1221
Test name
Test status
Simulation time 43195021432 ps
CPU time 514.11 seconds
Started Feb 04 12:29:58 PM PST 24
Finished Feb 04 12:38:41 PM PST 24
Peak memory 216528 kb
Host smart-55549887-2c80-4e7e-b1ce-5a86c0b5069d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051046969 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.4051046969
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2490358279
Short name T843
Test name
Test status
Simulation time 4953143769 ps
CPU time 2.04 seconds
Started Feb 04 12:31:56 PM PST 24
Finished Feb 04 12:32:00 PM PST 24
Peak memory 199344 kb
Host smart-06fec862-dbfe-43c5-a3e1-18606530b7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490358279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2490358279
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.739542583
Short name T1035
Test name
Test status
Simulation time 181938531164 ps
CPU time 46.97 seconds
Started Feb 04 12:30:02 PM PST 24
Finished Feb 04 12:30:57 PM PST 24
Peak memory 199720 kb
Host smart-e6ab52eb-706a-4c53-b6c2-8c737d62bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739542583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.739542583
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3379416745
Short name T611
Test name
Test status
Simulation time 85265546 ps
CPU time 0.54 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:30:07 PM PST 24
Peak memory 194232 kb
Host smart-836cea2d-8887-4e11-9c14-f98a1b977957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379416745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3379416745
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4291263511
Short name T198
Test name
Test status
Simulation time 38196539623 ps
CPU time 13.44 seconds
Started Feb 04 12:31:55 PM PST 24
Finished Feb 04 12:32:11 PM PST 24
Peak memory 199436 kb
Host smart-eec5eecb-85f6-4175-aaa8-2a210b32c122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291263511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4291263511
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2061662071
Short name T840
Test name
Test status
Simulation time 20048678517 ps
CPU time 28.07 seconds
Started Feb 04 12:30:07 PM PST 24
Finished Feb 04 12:30:41 PM PST 24
Peak memory 199616 kb
Host smart-6b5fafe0-e898-4e0a-8890-c1b320d19f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061662071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2061662071
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3104571746
Short name T1115
Test name
Test status
Simulation time 100691095109 ps
CPU time 12.3 seconds
Started Feb 04 12:29:52 PM PST 24
Finished Feb 04 12:30:11 PM PST 24
Peak memory 199004 kb
Host smart-87a6d342-cb22-4ffc-ab9b-3cd39adf95b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104571746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3104571746
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2436634691
Short name T114
Test name
Test status
Simulation time 2156626362060 ps
CPU time 818.97 seconds
Started Feb 04 12:29:57 PM PST 24
Finished Feb 04 12:43:45 PM PST 24
Peak memory 199028 kb
Host smart-61a05efd-426f-43dc-b16d-737116072d63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436634691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2436634691
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3323772526
Short name T708
Test name
Test status
Simulation time 39890591139 ps
CPU time 76.61 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:33:00 PM PST 24
Peak memory 198368 kb
Host smart-a0182121-ac91-4863-be3d-21d82c6916d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323772526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3323772526
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2300184029
Short name T900
Test name
Test status
Simulation time 538604681 ps
CPU time 0.9 seconds
Started Feb 04 12:29:56 PM PST 24
Finished Feb 04 12:30:05 PM PST 24
Peak memory 196724 kb
Host smart-1a71a1fb-025c-4985-9a77-3d4e3ed04d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300184029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2300184029
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.266794184
Short name T705
Test name
Test status
Simulation time 10277054375 ps
CPU time 18.56 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:27 PM PST 24
Peak memory 196784 kb
Host smart-cb85613e-9311-4628-a493-f592123062b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266794184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.266794184
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2283484863
Short name T506
Test name
Test status
Simulation time 19159146514 ps
CPU time 934.14 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:45:46 PM PST 24
Peak memory 199772 kb
Host smart-63c4311e-0d77-4e33-8e91-8c1fbf487253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283484863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2283484863
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3324844834
Short name T663
Test name
Test status
Simulation time 853794886 ps
CPU time 4.34 seconds
Started Feb 04 12:31:56 PM PST 24
Finished Feb 04 12:32:02 PM PST 24
Peak memory 197572 kb
Host smart-e4d98211-83f5-4b47-a6ba-366f2cec7acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324844834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3324844834
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1484002016
Short name T806
Test name
Test status
Simulation time 67083619557 ps
CPU time 32.5 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:30:35 PM PST 24
Peak memory 199276 kb
Host smart-701e25e8-ae9d-480d-b925-bb43c9b51dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484002016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1484002016
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1537628869
Short name T1178
Test name
Test status
Simulation time 4801938717 ps
CPU time 1.48 seconds
Started Feb 04 12:29:58 PM PST 24
Finished Feb 04 12:30:09 PM PST 24
Peak memory 195528 kb
Host smart-bff8cd1b-8272-4d7d-a7f7-43955900c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537628869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1537628869
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1385131494
Short name T1153
Test name
Test status
Simulation time 5326218957 ps
CPU time 8.29 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:17 PM PST 24
Peak memory 199064 kb
Host smart-e0481038-4b64-4cc6-b52b-f1612f9aa21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385131494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1385131494
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3828751084
Short name T761
Test name
Test status
Simulation time 1778895280 ps
CPU time 1.89 seconds
Started Feb 04 12:30:07 PM PST 24
Finished Feb 04 12:30:15 PM PST 24
Peak memory 197916 kb
Host smart-e91cba2b-7fa8-40a7-adb9-c3740084ddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828751084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3828751084
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.343354428
Short name T647
Test name
Test status
Simulation time 118867424225 ps
CPU time 60.17 seconds
Started Feb 04 12:30:02 PM PST 24
Finished Feb 04 12:31:10 PM PST 24
Peak memory 199744 kb
Host smart-426eff95-4348-4cf5-8092-ae2f4f56634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343354428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.343354428
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3649943998
Short name T524
Test name
Test status
Simulation time 39546911 ps
CPU time 0.56 seconds
Started Feb 04 12:30:08 PM PST 24
Finished Feb 04 12:30:15 PM PST 24
Peak memory 195144 kb
Host smart-4a68adb8-3053-4eb6-b18e-c8d7f9530ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649943998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3649943998
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.525078616
Short name T716
Test name
Test status
Simulation time 125319501391 ps
CPU time 89.58 seconds
Started Feb 04 12:30:00 PM PST 24
Finished Feb 04 12:31:37 PM PST 24
Peak memory 199116 kb
Host smart-ac912051-3b19-4524-b681-d134c760bf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525078616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.525078616
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3523906165
Short name T594
Test name
Test status
Simulation time 18945837227 ps
CPU time 14.15 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:23 PM PST 24
Peak memory 199756 kb
Host smart-4c94fda3-7d7f-4811-8d63-e8da0b87af6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523906165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3523906165
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.2377100141
Short name T784
Test name
Test status
Simulation time 1217321594136 ps
CPU time 2757.47 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 01:16:06 PM PST 24
Peak memory 199728 kb
Host smart-d53f2383-8d5a-4b4d-9b05-b9a3a23baa2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377100141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2377100141
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3455227904
Short name T993
Test name
Test status
Simulation time 53944761906 ps
CPU time 163.52 seconds
Started Feb 04 12:30:15 PM PST 24
Finished Feb 04 12:33:00 PM PST 24
Peak memory 199780 kb
Host smart-03c36930-1c41-4a6f-be89-349cf418de94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455227904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3455227904
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.650017992
Short name T32
Test name
Test status
Simulation time 3652505977 ps
CPU time 5.48 seconds
Started Feb 04 12:29:54 PM PST 24
Finished Feb 04 12:30:08 PM PST 24
Peak memory 198188 kb
Host smart-42f323e1-48a3-4eb9-a4c1-3ecfee900bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650017992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.650017992
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3330039779
Short name T772
Test name
Test status
Simulation time 84150716628 ps
CPU time 36.1 seconds
Started Feb 04 12:29:55 PM PST 24
Finished Feb 04 12:30:39 PM PST 24
Peak memory 198852 kb
Host smart-5da75a76-796f-44b5-a534-3c6c8a0e0991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330039779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3330039779
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.139310540
Short name T1145
Test name
Test status
Simulation time 10860664090 ps
CPU time 593.68 seconds
Started Feb 04 12:31:41 PM PST 24
Finished Feb 04 12:41:37 PM PST 24
Peak memory 198348 kb
Host smart-e70c7e02-292f-4daf-9e39-a8c6e52b7b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139310540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.139310540
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2718813935
Short name T808
Test name
Test status
Simulation time 1296762667 ps
CPU time 2.08 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:11 PM PST 24
Peak memory 197668 kb
Host smart-b2fdfa09-b9f6-4e1a-a875-69a47231ee0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718813935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2718813935
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3979568951
Short name T1064
Test name
Test status
Simulation time 36044450754 ps
CPU time 26.99 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:36 PM PST 24
Peak memory 198616 kb
Host smart-7fc9f21c-ecdc-46e6-bc5b-6a6e623cb075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979568951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3979568951
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1151351404
Short name T402
Test name
Test status
Simulation time 1971609821 ps
CPU time 2.32 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:11 PM PST 24
Peak memory 195120 kb
Host smart-41070d5d-1043-4c6f-a2f9-25a96665458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151351404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1151351404
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2452934696
Short name T764
Test name
Test status
Simulation time 5681563062 ps
CPU time 7.38 seconds
Started Feb 04 12:30:02 PM PST 24
Finished Feb 04 12:30:17 PM PST 24
Peak memory 199660 kb
Host smart-080f6d09-789d-4dc8-9001-066fdae9bab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452934696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2452934696
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1328892416
Short name T1180
Test name
Test status
Simulation time 83655418086 ps
CPU time 43.04 seconds
Started Feb 04 12:30:05 PM PST 24
Finished Feb 04 12:30:55 PM PST 24
Peak memory 199728 kb
Host smart-a9f53bf3-a638-428c-8c83-40520210e255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328892416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1328892416
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.735248549
Short name T419
Test name
Test status
Simulation time 34450510077 ps
CPU time 533.98 seconds
Started Feb 04 12:30:09 PM PST 24
Finished Feb 04 12:39:08 PM PST 24
Peak memory 216332 kb
Host smart-60962887-766d-414a-b11b-a60902bb2602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735248549 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.735248549
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.305620670
Short name T648
Test name
Test status
Simulation time 895763618 ps
CPU time 1.87 seconds
Started Feb 04 12:30:00 PM PST 24
Finished Feb 04 12:30:10 PM PST 24
Peak memory 198124 kb
Host smart-25c76af8-9bdc-410c-8034-44ee5979bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305620670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.305620670
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1201416037
Short name T942
Test name
Test status
Simulation time 81718319906 ps
CPU time 13.35 seconds
Started Feb 04 12:30:01 PM PST 24
Finished Feb 04 12:30:22 PM PST 24
Peak memory 199384 kb
Host smart-bb1cbf33-8f23-4728-ac41-dde32fc68702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201416037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1201416037
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.517419270
Short name T1077
Test name
Test status
Simulation time 14020439 ps
CPU time 0.53 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:28:36 PM PST 24
Peak memory 195128 kb
Host smart-2458f980-95b9-4fef-af95-8845aa11c4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517419270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.517419270
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1651590231
Short name T1197
Test name
Test status
Simulation time 126305448791 ps
CPU time 74.5 seconds
Started Feb 04 12:28:33 PM PST 24
Finished Feb 04 12:29:54 PM PST 24
Peak memory 199748 kb
Host smart-1d3e58fd-8864-4e13-bb75-b88a2a2612d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651590231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1651590231
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4158076097
Short name T860
Test name
Test status
Simulation time 37205646918 ps
CPU time 53.9 seconds
Started Feb 04 12:28:33 PM PST 24
Finished Feb 04 12:29:34 PM PST 24
Peak memory 198800 kb
Host smart-0fa9e5d2-b769-449b-8102-e93c4e4bfc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158076097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4158076097
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2630925610
Short name T714
Test name
Test status
Simulation time 8592979346 ps
CPU time 11.97 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:42 PM PST 24
Peak memory 199764 kb
Host smart-e0aa9178-f1bd-427e-9dda-12208822772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630925610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2630925610
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3131636934
Short name T777
Test name
Test status
Simulation time 1048879969 ps
CPU time 1.45 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:33 PM PST 24
Peak memory 195116 kb
Host smart-ed4cc3fe-55c1-462d-b761-e988c80db24d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131636934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3131636934
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2173190313
Short name T973
Test name
Test status
Simulation time 94143756377 ps
CPU time 230.32 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:32:27 PM PST 24
Peak memory 199728 kb
Host smart-2de65393-968b-452d-bbac-1f83acae3676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173190313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2173190313
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.450434926
Short name T1007
Test name
Test status
Simulation time 1217679157 ps
CPU time 2.35 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:33 PM PST 24
Peak memory 198832 kb
Host smart-f409107f-086f-4d81-bd4a-aaa41f852c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450434926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.450434926
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2264014661
Short name T1125
Test name
Test status
Simulation time 50795494995 ps
CPU time 114.1 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:30:28 PM PST 24
Peak memory 198680 kb
Host smart-4c3cb3e8-e503-49cc-a306-1a9cad0b9cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264014661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2264014661
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3407924661
Short name T579
Test name
Test status
Simulation time 27292921672 ps
CPU time 184.5 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:31:36 PM PST 24
Peak memory 199900 kb
Host smart-2e507899-6d35-486b-bb93-14fa6e1d9856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407924661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3407924661
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.212782839
Short name T1190
Test name
Test status
Simulation time 247600756 ps
CPU time 1.96 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:35 PM PST 24
Peak memory 197276 kb
Host smart-e38e1ad3-2dd8-4a30-9ef1-4ac0a06a6946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212782839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.212782839
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2156476810
Short name T1160
Test name
Test status
Simulation time 165615255312 ps
CPU time 67.83 seconds
Started Feb 04 12:28:33 PM PST 24
Finished Feb 04 12:29:48 PM PST 24
Peak memory 199732 kb
Host smart-2a306363-e3eb-45af-810d-a0e233e9a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156476810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2156476810
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.599522766
Short name T503
Test name
Test status
Simulation time 1843296615 ps
CPU time 3.74 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:37 PM PST 24
Peak memory 195208 kb
Host smart-4577aa6b-97d1-4b2d-92f7-791885fb69d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599522766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.599522766
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1560083371
Short name T87
Test name
Test status
Simulation time 52057878 ps
CPU time 0.79 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:28:37 PM PST 24
Peak memory 217136 kb
Host smart-ff63e54f-fcd0-4f47-969b-7d9ff7d90d8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560083371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1560083371
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2650952160
Short name T989
Test name
Test status
Simulation time 274927111 ps
CPU time 1.29 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:34 PM PST 24
Peak memory 197980 kb
Host smart-046ee1b7-8e37-4b80-aea2-a5ebd222ddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650952160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2650952160
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3295130178
Short name T446
Test name
Test status
Simulation time 308772845870 ps
CPU time 892.72 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:43:23 PM PST 24
Peak memory 216604 kb
Host smart-193c9847-2a01-4982-b5e9-aca926ae646f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295130178 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3295130178
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.48210199
Short name T954
Test name
Test status
Simulation time 1259188739 ps
CPU time 4.09 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:37 PM PST 24
Peak memory 199248 kb
Host smart-659f9a4a-3354-4a3d-b7e0-299acd168f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48210199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.48210199
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.855830535
Short name T415
Test name
Test status
Simulation time 62875078666 ps
CPU time 28.63 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:29:00 PM PST 24
Peak memory 199856 kb
Host smart-a4fe9f0a-5815-424c-9a23-041845754d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855830535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.855830535
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2427579111
Short name T944
Test name
Test status
Simulation time 12425659 ps
CPU time 0.58 seconds
Started Feb 04 12:30:15 PM PST 24
Finished Feb 04 12:30:17 PM PST 24
Peak memory 195176 kb
Host smart-7f4471ac-55cd-4a44-957b-7c2a1e7e6f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427579111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2427579111
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1078627268
Short name T1084
Test name
Test status
Simulation time 104179159573 ps
CPU time 35.54 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:30:48 PM PST 24
Peak memory 199808 kb
Host smart-51aa9841-6089-4608-9e90-731a299b09d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078627268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1078627268
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2794602815
Short name T355
Test name
Test status
Simulation time 36193714655 ps
CPU time 54.33 seconds
Started Feb 04 12:30:17 PM PST 24
Finished Feb 04 12:31:13 PM PST 24
Peak memory 199804 kb
Host smart-499bc48a-e5af-473b-8793-6b9f6d549258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794602815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2794602815
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3416366931
Short name T955
Test name
Test status
Simulation time 18964148137 ps
CPU time 16.89 seconds
Started Feb 04 12:30:05 PM PST 24
Finished Feb 04 12:30:29 PM PST 24
Peak memory 199424 kb
Host smart-91513d7f-5a32-45d4-9084-485b9e02d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416366931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3416366931
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1878824241
Short name T516
Test name
Test status
Simulation time 1898276295093 ps
CPU time 1401.02 seconds
Started Feb 04 12:30:13 PM PST 24
Finished Feb 04 12:53:37 PM PST 24
Peak memory 198704 kb
Host smart-4f2201d9-08b2-45ba-a79e-b6e8e49ab38c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878824241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1878824241
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3215710092
Short name T823
Test name
Test status
Simulation time 71105192991 ps
CPU time 445.3 seconds
Started Feb 04 12:30:08 PM PST 24
Finished Feb 04 12:37:39 PM PST 24
Peak memory 199924 kb
Host smart-ba57d2b3-b8e7-445a-96d0-ce053d811ca0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3215710092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3215710092
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1476831988
Short name T502
Test name
Test status
Simulation time 10243495657 ps
CPU time 18.63 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:30:32 PM PST 24
Peak memory 198576 kb
Host smart-1c6cf95b-3e25-4e0b-8d65-131dbf1d649d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476831988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1476831988
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.588659758
Short name T614
Test name
Test status
Simulation time 69395351390 ps
CPU time 255.57 seconds
Started Feb 04 12:30:03 PM PST 24
Finished Feb 04 12:34:26 PM PST 24
Peak memory 199104 kb
Host smart-c71b3606-de5d-4115-a3ad-a0504135b3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588659758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.588659758
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.585482861
Short name T1071
Test name
Test status
Simulation time 30592591327 ps
CPU time 1570.32 seconds
Started Feb 04 12:30:04 PM PST 24
Finished Feb 04 12:56:22 PM PST 24
Peak memory 199800 kb
Host smart-7670c632-fc2c-4c1d-868b-28e40c2d0abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585482861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.585482861
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2583362553
Short name T501
Test name
Test status
Simulation time 400075738 ps
CPU time 1.61 seconds
Started Feb 04 12:30:02 PM PST 24
Finished Feb 04 12:30:11 PM PST 24
Peak memory 197392 kb
Host smart-f3f472d3-b2ba-4553-836a-4265413f88e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2583362553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2583362553
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3631889547
Short name T786
Test name
Test status
Simulation time 125368783258 ps
CPU time 179.84 seconds
Started Feb 04 12:30:13 PM PST 24
Finished Feb 04 12:33:15 PM PST 24
Peak memory 199236 kb
Host smart-987c6d6b-a558-478b-ad71-ad0bfb89653d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631889547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3631889547
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2003518978
Short name T773
Test name
Test status
Simulation time 3690682267 ps
CPU time 2.15 seconds
Started Feb 04 12:30:03 PM PST 24
Finished Feb 04 12:30:12 PM PST 24
Peak memory 195472 kb
Host smart-d926d19b-de53-4b53-9522-e01a1c5863ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003518978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2003518978
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.704961020
Short name T1113
Test name
Test status
Simulation time 282016353 ps
CPU time 0.99 seconds
Started Feb 04 12:30:12 PM PST 24
Finished Feb 04 12:30:16 PM PST 24
Peak memory 197768 kb
Host smart-915e7278-ded4-440d-bad7-5f621a8ac4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704961020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.704961020
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.4118186568
Short name T388
Test name
Test status
Simulation time 178726915752 ps
CPU time 20.61 seconds
Started Feb 04 12:30:04 PM PST 24
Finished Feb 04 12:30:32 PM PST 24
Peak memory 199744 kb
Host smart-211cf61c-fa6e-435d-a419-41b1cd6f10c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118186568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.4118186568
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2854917239
Short name T383
Test name
Test status
Simulation time 112940407816 ps
CPU time 429.58 seconds
Started Feb 04 12:30:05 PM PST 24
Finished Feb 04 12:37:21 PM PST 24
Peak memory 216124 kb
Host smart-e60130ad-94fd-48aa-88be-3fce40363e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854917239 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2854917239
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2103525210
Short name T875
Test name
Test status
Simulation time 1877130367 ps
CPU time 1.72 seconds
Started Feb 04 12:30:15 PM PST 24
Finished Feb 04 12:30:18 PM PST 24
Peak memory 197468 kb
Host smart-41fbe2e5-edcb-461f-87ce-fcc2108a986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103525210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2103525210
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3593447158
Short name T1104
Test name
Test status
Simulation time 13504469676 ps
CPU time 9.05 seconds
Started Feb 04 12:30:02 PM PST 24
Finished Feb 04 12:30:19 PM PST 24
Peak memory 198004 kb
Host smart-eddd8a13-d19a-4c9e-a756-690ab77d9494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593447158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3593447158
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.95022771
Short name T798
Test name
Test status
Simulation time 12247934 ps
CPU time 0.53 seconds
Started Feb 04 12:30:15 PM PST 24
Finished Feb 04 12:30:17 PM PST 24
Peak memory 194148 kb
Host smart-e4d70761-dce4-4df6-9d71-8ff4aa5411b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95022771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.95022771
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1353061321
Short name T921
Test name
Test status
Simulation time 74270509806 ps
CPU time 54.26 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:31:07 PM PST 24
Peak memory 199808 kb
Host smart-aaa1bc75-fd16-498e-9e17-656436248bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353061321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1353061321
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1334369574
Short name T982
Test name
Test status
Simulation time 290937114710 ps
CPU time 108.28 seconds
Started Feb 04 12:30:08 PM PST 24
Finished Feb 04 12:32:03 PM PST 24
Peak memory 198796 kb
Host smart-d11ac2c7-9d5c-429a-9e52-cece0d8f1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334369574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1334369574
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.74321080
Short name T253
Test name
Test status
Simulation time 24611997637 ps
CPU time 42.52 seconds
Started Feb 04 12:30:09 PM PST 24
Finished Feb 04 12:30:57 PM PST 24
Peak memory 199100 kb
Host smart-d021fe74-2dd4-4be3-a988-3f4a1e5873bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74321080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.74321080
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2010815185
Short name T530
Test name
Test status
Simulation time 281847220616 ps
CPU time 469.23 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:38:02 PM PST 24
Peak memory 199940 kb
Host smart-59d052e4-c272-4030-b654-1cb089f42f84
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010815185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2010815185
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.164026140
Short name T1074
Test name
Test status
Simulation time 81146478243 ps
CPU time 133.42 seconds
Started Feb 04 12:30:13 PM PST 24
Finished Feb 04 12:32:29 PM PST 24
Peak memory 199768 kb
Host smart-a50a3fa5-5e35-44bd-b464-8680ca6a2ebc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164026140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.164026140
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2541117689
Short name T619
Test name
Test status
Simulation time 8688917590 ps
CPU time 16.55 seconds
Started Feb 04 12:30:10 PM PST 24
Finished Feb 04 12:30:32 PM PST 24
Peak memory 198380 kb
Host smart-7339546a-83bc-4f5b-92fb-04022048ad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541117689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2541117689
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3025493112
Short name T771
Test name
Test status
Simulation time 145800443919 ps
CPU time 274.19 seconds
Started Feb 04 12:30:13 PM PST 24
Finished Feb 04 12:34:50 PM PST 24
Peak memory 199256 kb
Host smart-38b8de6c-c00d-4ef9-aa5d-9b9cacf3133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025493112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3025493112
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1215241908
Short name T16
Test name
Test status
Simulation time 38166714256 ps
CPU time 1022.97 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:47:15 PM PST 24
Peak memory 199816 kb
Host smart-57cb87da-fced-46f1-b28b-29f272daed1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215241908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1215241908
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3085434614
Short name T971
Test name
Test status
Simulation time 570770138 ps
CPU time 4.89 seconds
Started Feb 04 12:30:10 PM PST 24
Finished Feb 04 12:30:20 PM PST 24
Peak memory 197644 kb
Host smart-d435758e-e3bd-4e9d-a4ae-fa73fd9d724d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085434614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3085434614
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.116137056
Short name T1054
Test name
Test status
Simulation time 112140726589 ps
CPU time 75.15 seconds
Started Feb 04 12:30:13 PM PST 24
Finished Feb 04 12:31:31 PM PST 24
Peak memory 199132 kb
Host smart-4bb0c621-0b4c-471c-8221-337ff792e2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116137056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.116137056
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3956108368
Short name T1122
Test name
Test status
Simulation time 4115349111 ps
CPU time 2.21 seconds
Started Feb 04 12:30:09 PM PST 24
Finished Feb 04 12:30:17 PM PST 24
Peak memory 195556 kb
Host smart-450b42b4-70a9-4298-bba1-622a873eb0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956108368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3956108368
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.469573920
Short name T586
Test name
Test status
Simulation time 6290211599 ps
CPU time 11.49 seconds
Started Feb 04 12:30:15 PM PST 24
Finished Feb 04 12:30:28 PM PST 24
Peak memory 198548 kb
Host smart-faae01cb-5641-4121-8026-150f843b7578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469573920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.469573920
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.456336830
Short name T289
Test name
Test status
Simulation time 264112281157 ps
CPU time 1068.04 seconds
Started Feb 04 12:30:04 PM PST 24
Finished Feb 04 12:47:59 PM PST 24
Peak memory 199796 kb
Host smart-41c1955c-23da-4ac2-97be-3d0fe4c070ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456336830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.456336830
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2591550140
Short name T916
Test name
Test status
Simulation time 382271617295 ps
CPU time 907.67 seconds
Started Feb 04 12:30:04 PM PST 24
Finished Feb 04 12:45:19 PM PST 24
Peak memory 216304 kb
Host smart-62db715f-9321-4543-a21e-4af0b093e0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591550140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2591550140
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.4142503350
Short name T626
Test name
Test status
Simulation time 1027848306 ps
CPU time 2.84 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:30:16 PM PST 24
Peak memory 199232 kb
Host smart-91b35686-f0e0-4444-b818-c2fd15bee9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142503350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.4142503350
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3206983624
Short name T740
Test name
Test status
Simulation time 62671248516 ps
CPU time 28.4 seconds
Started Feb 04 12:30:06 PM PST 24
Finished Feb 04 12:30:41 PM PST 24
Peak memory 199856 kb
Host smart-fa4b81f8-6f05-4c7b-a0db-9e1c67ec1d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206983624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3206983624
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.989309418
Short name T807
Test name
Test status
Simulation time 16348896 ps
CPU time 0.58 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:30:24 PM PST 24
Peak memory 195148 kb
Host smart-6c233f86-3f38-4698-8c02-545e8e0551ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989309418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.989309418
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.808737270
Short name T325
Test name
Test status
Simulation time 44666351704 ps
CPU time 49.85 seconds
Started Feb 04 12:30:10 PM PST 24
Finished Feb 04 12:31:05 PM PST 24
Peak memory 199768 kb
Host smart-05ef65b0-2001-424d-9d94-dc7a59e2798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808737270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.808737270
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1861425415
Short name T1228
Test name
Test status
Simulation time 175396308458 ps
CPU time 169.04 seconds
Started Feb 04 12:30:04 PM PST 24
Finished Feb 04 12:33:00 PM PST 24
Peak memory 199824 kb
Host smart-42c8a9c2-c578-4985-b75e-b9a3f53dce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861425415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1861425415
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2393833994
Short name T802
Test name
Test status
Simulation time 210895734213 ps
CPU time 292.27 seconds
Started Feb 04 12:30:25 PM PST 24
Finished Feb 04 12:35:19 PM PST 24
Peak memory 199876 kb
Host smart-04e05e08-bc03-4ae4-9599-da391f493c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393833994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2393833994
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.402359980
Short name T927
Test name
Test status
Simulation time 32770121942 ps
CPU time 26.2 seconds
Started Feb 04 12:30:25 PM PST 24
Finished Feb 04 12:30:53 PM PST 24
Peak memory 197468 kb
Host smart-d938c49f-bcb8-44e7-bdb7-a76c57fc7c1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402359980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.402359980
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3037168381
Short name T1017
Test name
Test status
Simulation time 84635210398 ps
CPU time 240.03 seconds
Started Feb 04 12:30:20 PM PST 24
Finished Feb 04 12:34:21 PM PST 24
Peak memory 199724 kb
Host smart-61a6995b-f869-4816-be29-3b2544666c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037168381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3037168381
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1116459879
Short name T1098
Test name
Test status
Simulation time 2232793446 ps
CPU time 4.05 seconds
Started Feb 04 12:30:25 PM PST 24
Finished Feb 04 12:30:30 PM PST 24
Peak memory 195152 kb
Host smart-1739b795-b987-49f0-ae0b-ea8d86f657ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116459879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1116459879
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.421011732
Short name T1199
Test name
Test status
Simulation time 69919989276 ps
CPU time 134.88 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:32:40 PM PST 24
Peak memory 208000 kb
Host smart-2976144d-dd14-462c-9278-1a74e165828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421011732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.421011732
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1813799822
Short name T505
Test name
Test status
Simulation time 18144756256 ps
CPU time 904.7 seconds
Started Feb 04 12:30:21 PM PST 24
Finished Feb 04 12:45:28 PM PST 24
Peak memory 199812 kb
Host smart-2ff6c5c7-9d53-4613-918a-ad5f87cf6b7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813799822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1813799822
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3404262093
Short name T715
Test name
Test status
Simulation time 127464150730 ps
CPU time 35.01 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:31:00 PM PST 24
Peak memory 199668 kb
Host smart-c3b4e97b-ca15-4b08-a528-b048aad5f6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404262093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3404262093
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1961935296
Short name T540
Test name
Test status
Simulation time 3620784771 ps
CPU time 6.82 seconds
Started Feb 04 12:30:26 PM PST 24
Finished Feb 04 12:30:34 PM PST 24
Peak memory 195428 kb
Host smart-475c88ec-c251-4c8f-b7f4-45f9293e74ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961935296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1961935296
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2142150385
Short name T834
Test name
Test status
Simulation time 459906062 ps
CPU time 1.83 seconds
Started Feb 04 12:30:15 PM PST 24
Finished Feb 04 12:30:18 PM PST 24
Peak memory 198608 kb
Host smart-fc5e2e91-339b-4960-8b40-5a416fef6097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142150385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2142150385
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2126813267
Short name T155
Test name
Test status
Simulation time 42039239857 ps
CPU time 462.74 seconds
Started Feb 04 12:30:27 PM PST 24
Finished Feb 04 12:38:11 PM PST 24
Peak memory 216624 kb
Host smart-e2a64e39-99ee-4868-b759-2ed1400161e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126813267 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2126813267
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1806132064
Short name T673
Test name
Test status
Simulation time 6496901844 ps
CPU time 17.59 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:30:43 PM PST 24
Peak memory 198504 kb
Host smart-c7e7ac64-7d94-4ea2-9270-021e66d5875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806132064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1806132064
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1965311823
Short name T1045
Test name
Test status
Simulation time 7901826796 ps
CPU time 12.21 seconds
Started Feb 04 12:30:09 PM PST 24
Finished Feb 04 12:30:27 PM PST 24
Peak memory 199804 kb
Host smart-7f43cf97-14c9-4365-9654-1399c20b30e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965311823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1965311823
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.263847918
Short name T1174
Test name
Test status
Simulation time 11353879 ps
CPU time 0.54 seconds
Started Feb 04 12:30:23 PM PST 24
Finished Feb 04 12:30:25 PM PST 24
Peak memory 195180 kb
Host smart-5f18fddf-2044-4442-9d26-b6879236eb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263847918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.263847918
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2284695002
Short name T557
Test name
Test status
Simulation time 47343724215 ps
CPU time 20.56 seconds
Started Feb 04 12:30:27 PM PST 24
Finished Feb 04 12:30:48 PM PST 24
Peak memory 199708 kb
Host smart-f43f0464-6ced-445a-bfeb-41bf49997a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284695002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2284695002
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3976791374
Short name T315
Test name
Test status
Simulation time 220716240373 ps
CPU time 26.2 seconds
Started Feb 04 12:30:31 PM PST 24
Finished Feb 04 12:31:01 PM PST 24
Peak memory 199980 kb
Host smart-3337633e-5d55-4e17-9220-04b26d3e0952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976791374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3976791374
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.572102049
Short name T433
Test name
Test status
Simulation time 68379545282 ps
CPU time 44.93 seconds
Started Feb 04 12:30:31 PM PST 24
Finished Feb 04 12:31:19 PM PST 24
Peak memory 199704 kb
Host smart-48602b1f-95ef-4013-ab4f-efcbc2c26d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572102049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.572102049
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1062088415
Short name T791
Test name
Test status
Simulation time 962521411849 ps
CPU time 347.97 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:36:14 PM PST 24
Peak memory 199564 kb
Host smart-bab2389f-4e73-409f-8112-d3cb1a0734d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062088415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1062088415
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3238000282
Short name T814
Test name
Test status
Simulation time 126426549833 ps
CPU time 342.17 seconds
Started Feb 04 12:30:33 PM PST 24
Finished Feb 04 12:36:19 PM PST 24
Peak memory 199716 kb
Host smart-25a18e4e-bedb-4185-b774-6ef67ad97ffa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238000282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3238000282
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.4121763706
Short name T1046
Test name
Test status
Simulation time 7926937853 ps
CPU time 13.4 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:30:38 PM PST 24
Peak memory 198280 kb
Host smart-6ee48d19-2548-4506-a5ad-08ce9184cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121763706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4121763706
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.4164709038
Short name T413
Test name
Test status
Simulation time 64867471965 ps
CPU time 116.07 seconds
Started Feb 04 12:30:32 PM PST 24
Finished Feb 04 12:32:31 PM PST 24
Peak memory 208204 kb
Host smart-f06f640a-d940-4b00-b98c-2837fdbeeb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164709038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.4164709038
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.482028126
Short name T12
Test name
Test status
Simulation time 24122466343 ps
CPU time 171.94 seconds
Started Feb 04 12:30:34 PM PST 24
Finished Feb 04 12:33:29 PM PST 24
Peak memory 199736 kb
Host smart-d986aff9-eaee-46d0-bbff-a18c0a80e8c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=482028126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.482028126
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2617054282
Short name T1088
Test name
Test status
Simulation time 2438391295 ps
CPU time 16.31 seconds
Started Feb 04 12:30:25 PM PST 24
Finished Feb 04 12:30:43 PM PST 24
Peak memory 198112 kb
Host smart-ad01de22-804b-4ea2-b225-cc29423f971b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617054282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2617054282
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3264888109
Short name T690
Test name
Test status
Simulation time 148416997503 ps
CPU time 100.95 seconds
Started Feb 04 12:30:23 PM PST 24
Finished Feb 04 12:32:05 PM PST 24
Peak memory 199660 kb
Host smart-0637b777-0ee2-4389-b203-4e0d683c650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264888109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3264888109
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.832595596
Short name T885
Test name
Test status
Simulation time 2222952134 ps
CPU time 4.49 seconds
Started Feb 04 12:30:21 PM PST 24
Finished Feb 04 12:30:26 PM PST 24
Peak memory 195300 kb
Host smart-b190dc13-7013-4eae-b51c-a384db08bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832595596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.832595596
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2214339241
Short name T1093
Test name
Test status
Simulation time 535845169 ps
CPU time 1.3 seconds
Started Feb 04 12:30:19 PM PST 24
Finished Feb 04 12:30:22 PM PST 24
Peak memory 198104 kb
Host smart-4eead9fe-315e-4b89-b517-68cb820692ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214339241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2214339241
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2199027359
Short name T211
Test name
Test status
Simulation time 149384536373 ps
CPU time 142.29 seconds
Started Feb 04 12:30:31 PM PST 24
Finished Feb 04 12:32:56 PM PST 24
Peak memory 200080 kb
Host smart-00db4fa4-d8aa-45c7-84c8-111342491b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199027359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2199027359
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.4233540312
Short name T368
Test name
Test status
Simulation time 41295878839 ps
CPU time 246.77 seconds
Started Feb 04 12:30:27 PM PST 24
Finished Feb 04 12:34:35 PM PST 24
Peak memory 211968 kb
Host smart-9eced525-c20d-49b8-b3a3-8b420f02e5d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233540312 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.4233540312
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3065327715
Short name T639
Test name
Test status
Simulation time 6481848399 ps
CPU time 10.54 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:30:36 PM PST 24
Peak memory 199228 kb
Host smart-291d54e3-aaee-4325-8039-3bed6b89a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065327715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3065327715
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.539488319
Short name T1003
Test name
Test status
Simulation time 55863654322 ps
CPU time 24.23 seconds
Started Feb 04 12:30:33 PM PST 24
Finished Feb 04 12:31:01 PM PST 24
Peak memory 199728 kb
Host smart-618e0505-754b-45fe-bfea-51c9000675e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539488319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.539488319
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.174703379
Short name T692
Test name
Test status
Simulation time 15910854 ps
CPU time 0.56 seconds
Started Feb 04 12:30:23 PM PST 24
Finished Feb 04 12:30:25 PM PST 24
Peak memory 195136 kb
Host smart-2bd6eb28-94cc-4c26-8c8d-930e2b337499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174703379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.174703379
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3049303186
Short name T175
Test name
Test status
Simulation time 66256572697 ps
CPU time 53.54 seconds
Started Feb 04 12:30:23 PM PST 24
Finished Feb 04 12:31:18 PM PST 24
Peak memory 198528 kb
Host smart-0f189c2a-4fa6-411c-a358-a0f1fd06d7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049303186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3049303186
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3729674989
Short name T195
Test name
Test status
Simulation time 115366065808 ps
CPU time 46.06 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:31:09 PM PST 24
Peak memory 199848 kb
Host smart-d82c522f-2928-49ac-b514-23d5aa7b9063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729674989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3729674989
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.823620058
Short name T449
Test name
Test status
Simulation time 7114822139 ps
CPU time 5.87 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:30:30 PM PST 24
Peak memory 195288 kb
Host smart-1f77b522-71e7-4226-91ab-f6a3933b9b93
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823620058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.823620058
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2588859940
Short name T407
Test name
Test status
Simulation time 132404555314 ps
CPU time 934.49 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:45:58 PM PST 24
Peak memory 199812 kb
Host smart-98cb17ec-abc3-4c57-91a4-ac901f1f699a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588859940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2588859940
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1015158398
Short name T534
Test name
Test status
Simulation time 6004732703 ps
CPU time 4.05 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:30:30 PM PST 24
Peak memory 198964 kb
Host smart-8e59424c-927e-473b-b914-2a063d719c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015158398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1015158398
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.402156312
Short name T1002
Test name
Test status
Simulation time 110642921808 ps
CPU time 241.17 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:34:25 PM PST 24
Peak memory 208272 kb
Host smart-405cb27d-e56c-4f66-b0ca-22b072826eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402156312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.402156312
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.4262383809
Short name T1085
Test name
Test status
Simulation time 24699023631 ps
CPU time 362.8 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:36:26 PM PST 24
Peak memory 199768 kb
Host smart-fab68353-d2bd-4ed2-8169-5828bb24339c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262383809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4262383809
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.671824433
Short name T1184
Test name
Test status
Simulation time 3410477303 ps
CPU time 11.13 seconds
Started Feb 04 12:30:20 PM PST 24
Finished Feb 04 12:30:32 PM PST 24
Peak memory 197672 kb
Host smart-9910a207-2758-4a05-ade7-17c4458d5fad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671824433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.671824433
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3632683924
Short name T281
Test name
Test status
Simulation time 16526134931 ps
CPU time 16.94 seconds
Started Feb 04 12:30:23 PM PST 24
Finished Feb 04 12:30:41 PM PST 24
Peak memory 198716 kb
Host smart-f24df362-6f9b-48c0-b990-56fc1c6436bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632683924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3632683924
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2832436408
Short name T914
Test name
Test status
Simulation time 4374956712 ps
CPU time 4.21 seconds
Started Feb 04 12:30:27 PM PST 24
Finished Feb 04 12:30:33 PM PST 24
Peak memory 195504 kb
Host smart-b06094c9-f080-448d-a3bf-ba5e37b52d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832436408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2832436408
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1977604428
Short name T1107
Test name
Test status
Simulation time 624934536 ps
CPU time 2.89 seconds
Started Feb 04 12:30:32 PM PST 24
Finished Feb 04 12:30:39 PM PST 24
Peak memory 197744 kb
Host smart-78f79f29-842c-4bde-8982-27cdbddf07ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977604428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1977604428
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2079094588
Short name T362
Test name
Test status
Simulation time 197215429749 ps
CPU time 89.21 seconds
Started Feb 04 12:30:26 PM PST 24
Finished Feb 04 12:31:57 PM PST 24
Peak memory 199812 kb
Host smart-5bef92ac-0da8-4b00-bd94-8b4c740c55d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079094588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2079094588
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3744928962
Short name T818
Test name
Test status
Simulation time 215459957952 ps
CPU time 464.08 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:38:10 PM PST 24
Peak memory 216704 kb
Host smart-5430914d-342c-4141-b7e4-94671add6dbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744928962 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3744928962
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1922920548
Short name T605
Test name
Test status
Simulation time 6761712580 ps
CPU time 12.44 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:30:38 PM PST 24
Peak memory 198916 kb
Host smart-30e640b6-b5ec-488d-8718-2f74a182b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922920548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1922920548
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2445504354
Short name T642
Test name
Test status
Simulation time 144761351317 ps
CPU time 57.56 seconds
Started Feb 04 12:30:22 PM PST 24
Finished Feb 04 12:31:21 PM PST 24
Peak memory 199772 kb
Host smart-1e9c2a2a-dee0-4d18-b547-0efd8a9e3a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445504354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2445504354
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1055370951
Short name T499
Test name
Test status
Simulation time 14564531 ps
CPU time 0.56 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:30:41 PM PST 24
Peak memory 195236 kb
Host smart-5fe75ffa-cef0-4988-bc9e-5164e10f289e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055370951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1055370951
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3596573947
Short name T668
Test name
Test status
Simulation time 169563851031 ps
CPU time 62.9 seconds
Started Feb 04 12:30:30 PM PST 24
Finished Feb 04 12:31:34 PM PST 24
Peak memory 199748 kb
Host smart-68b6b374-30cf-42df-90ea-67399d2b6d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596573947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3596573947
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3448826790
Short name T1176
Test name
Test status
Simulation time 89195047123 ps
CPU time 38.37 seconds
Started Feb 04 12:30:25 PM PST 24
Finished Feb 04 12:31:05 PM PST 24
Peak memory 197956 kb
Host smart-1d53ff54-dc23-45cb-a7f9-4b709d7a8f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448826790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3448826790
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.546576322
Short name T223
Test name
Test status
Simulation time 49589839991 ps
CPU time 31.44 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:30:57 PM PST 24
Peak memory 199836 kb
Host smart-1c017498-dbec-4911-bf63-d6002a3a8618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546576322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.546576322
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2442855111
Short name T543
Test name
Test status
Simulation time 2639795099398 ps
CPU time 1930.44 seconds
Started Feb 04 12:30:37 PM PST 24
Finished Feb 04 01:02:50 PM PST 24
Peak memory 199756 kb
Host smart-f9529f86-ff8a-4cf1-8f67-b1c8d4b2f9f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442855111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2442855111
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.393835363
Short name T412
Test name
Test status
Simulation time 234064174794 ps
CPU time 314.5 seconds
Started Feb 04 12:30:34 PM PST 24
Finished Feb 04 12:35:52 PM PST 24
Peak memory 199796 kb
Host smart-2d88e0ed-101f-42c8-a4ef-759ce7a7589b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=393835363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.393835363
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1138438328
Short name T833
Test name
Test status
Simulation time 1118351056 ps
CPU time 2.58 seconds
Started Feb 04 12:30:34 PM PST 24
Finished Feb 04 12:30:40 PM PST 24
Peak memory 195220 kb
Host smart-3e234e8f-4e93-4f84-bb77-960869e2a2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138438328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1138438328
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3167191591
Short name T739
Test name
Test status
Simulation time 153298653355 ps
CPU time 65.85 seconds
Started Feb 04 12:30:32 PM PST 24
Finished Feb 04 12:31:41 PM PST 24
Peak memory 208056 kb
Host smart-d5747182-0c69-4b6f-b5e3-35425c8c7322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167191591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3167191591
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2200827905
Short name T602
Test name
Test status
Simulation time 14875978026 ps
CPU time 652.81 seconds
Started Feb 04 12:30:36 PM PST 24
Finished Feb 04 12:41:31 PM PST 24
Peak memory 199760 kb
Host smart-25afc836-2c25-4dd3-bdc0-f31e41feb7b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200827905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2200827905
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.754826592
Short name T733
Test name
Test status
Simulation time 371078035 ps
CPU time 2.1 seconds
Started Feb 04 12:30:33 PM PST 24
Finished Feb 04 12:30:39 PM PST 24
Peak memory 197676 kb
Host smart-525d7658-11e4-49e1-92e7-dcd868caa7fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754826592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.754826592
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3257797915
Short name T1026
Test name
Test status
Simulation time 53248775616 ps
CPU time 43.19 seconds
Started Feb 04 12:30:33 PM PST 24
Finished Feb 04 12:31:20 PM PST 24
Peak memory 198952 kb
Host smart-3418a5c1-bba4-4db4-9899-e0f833b58a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257797915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3257797915
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.400683369
Short name T727
Test name
Test status
Simulation time 3515098568 ps
CPU time 3.59 seconds
Started Feb 04 12:30:34 PM PST 24
Finished Feb 04 12:30:41 PM PST 24
Peak memory 195432 kb
Host smart-4f5cbb75-126f-4cc6-864f-e6c272123087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400683369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.400683369
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.712868779
Short name T529
Test name
Test status
Simulation time 711747816 ps
CPU time 1.58 seconds
Started Feb 04 12:30:21 PM PST 24
Finished Feb 04 12:30:23 PM PST 24
Peak memory 197956 kb
Host smart-f5b20aac-923f-4009-8923-d178716a6082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712868779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.712868779
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.594464271
Short name T845
Test name
Test status
Simulation time 176155532743 ps
CPU time 523.57 seconds
Started Feb 04 12:30:35 PM PST 24
Finished Feb 04 12:39:22 PM PST 24
Peak memory 224792 kb
Host smart-2ff8e292-48cd-4210-8edc-d962b3e8c794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594464271 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.594464271
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3532746660
Short name T1040
Test name
Test status
Simulation time 2717573159 ps
CPU time 2.72 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:30:50 PM PST 24
Peak memory 197864 kb
Host smart-cf49be43-0a43-42cb-83cf-74b0de5f8c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532746660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3532746660
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1529449711
Short name T974
Test name
Test status
Simulation time 189064779481 ps
CPU time 95.87 seconds
Started Feb 04 12:30:24 PM PST 24
Finished Feb 04 12:32:01 PM PST 24
Peak memory 199652 kb
Host smart-1d8ef8b0-2866-4771-a495-81801c75e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529449711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1529449711
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3492221597
Short name T671
Test name
Test status
Simulation time 27077150 ps
CPU time 0.54 seconds
Started Feb 04 12:30:36 PM PST 24
Finished Feb 04 12:30:39 PM PST 24
Peak memory 195196 kb
Host smart-875a610a-7786-4d45-bc33-c26b20c640bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492221597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3492221597
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2115947551
Short name T765
Test name
Test status
Simulation time 269895327356 ps
CPU time 63.78 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:31:51 PM PST 24
Peak memory 199864 kb
Host smart-c823a204-bc32-41d5-acb0-ae6cd3bad957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115947551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2115947551
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1777208771
Short name T363
Test name
Test status
Simulation time 111473908780 ps
CPU time 188.71 seconds
Started Feb 04 12:30:35 PM PST 24
Finished Feb 04 12:33:46 PM PST 24
Peak memory 199064 kb
Host smart-fd5a2fd2-2f38-4db9-a7aa-2186de16e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777208771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1777208771
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3320818157
Short name T804
Test name
Test status
Simulation time 8086662819 ps
CPU time 15.72 seconds
Started Feb 04 12:30:37 PM PST 24
Finished Feb 04 12:30:56 PM PST 24
Peak memory 199868 kb
Host smart-815812c6-132b-4954-8cbd-74710c2b7040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320818157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3320818157
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2625501604
Short name T226
Test name
Test status
Simulation time 292199163322 ps
CPU time 502.1 seconds
Started Feb 04 12:30:35 PM PST 24
Finished Feb 04 12:39:00 PM PST 24
Peak memory 199856 kb
Host smart-53168b8f-78aa-4b57-9e9e-91bda2d96179
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625501604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2625501604
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3624321375
Short name T670
Test name
Test status
Simulation time 186564744910 ps
CPU time 536.26 seconds
Started Feb 04 12:30:40 PM PST 24
Finished Feb 04 12:39:44 PM PST 24
Peak memory 198948 kb
Host smart-fd15f743-d839-4fc8-9062-36bdc4f06832
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624321375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3624321375
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2944139313
Short name T888
Test name
Test status
Simulation time 6414294693 ps
CPU time 4.01 seconds
Started Feb 04 12:30:36 PM PST 24
Finished Feb 04 12:30:42 PM PST 24
Peak memory 198688 kb
Host smart-b9702ccb-4a70-43d5-a3a7-044bb015dd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944139313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2944139313
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1816201719
Short name T904
Test name
Test status
Simulation time 165959529983 ps
CPU time 86.79 seconds
Started Feb 04 12:30:36 PM PST 24
Finished Feb 04 12:32:05 PM PST 24
Peak memory 208240 kb
Host smart-cb91b5c5-07e7-4427-989a-d84893025e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816201719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1816201719
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2401050620
Short name T660
Test name
Test status
Simulation time 34044708474 ps
CPU time 89.17 seconds
Started Feb 04 12:30:37 PM PST 24
Finished Feb 04 12:32:08 PM PST 24
Peak memory 199788 kb
Host smart-5b382889-5f65-497f-911f-0e0da3a76256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401050620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2401050620
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.4031214918
Short name T706
Test name
Test status
Simulation time 1517746360 ps
CPU time 10.99 seconds
Started Feb 04 12:30:35 PM PST 24
Finished Feb 04 12:30:49 PM PST 24
Peak memory 197736 kb
Host smart-cfbb38c1-fe27-404f-90df-c9e037b2f0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031214918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4031214918
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2469270707
Short name T430
Test name
Test status
Simulation time 789309772 ps
CPU time 1.96 seconds
Started Feb 04 12:30:36 PM PST 24
Finished Feb 04 12:30:40 PM PST 24
Peak memory 195200 kb
Host smart-939bf861-dc42-4375-941e-baec90a0495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469270707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2469270707
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.198462174
Short name T724
Test name
Test status
Simulation time 6000461893 ps
CPU time 27.53 seconds
Started Feb 04 12:30:36 PM PST 24
Finished Feb 04 12:31:06 PM PST 24
Peak memory 199140 kb
Host smart-0abbaf68-a4eb-437e-b9ba-37b09085345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198462174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.198462174
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.817120471
Short name T675
Test name
Test status
Simulation time 160077174837 ps
CPU time 160.98 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:33:27 PM PST 24
Peak memory 208164 kb
Host smart-9b91a0e4-682e-4eeb-9220-8f0aedce58ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817120471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.817120471
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3775363099
Short name T846
Test name
Test status
Simulation time 91318622791 ps
CPU time 409.85 seconds
Started Feb 04 12:30:40 PM PST 24
Finished Feb 04 12:37:38 PM PST 24
Peak memory 215452 kb
Host smart-609eaf95-5ab6-40a3-95d9-b88b71775eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775363099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3775363099
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3545471426
Short name T519
Test name
Test status
Simulation time 13878528801 ps
CPU time 19.26 seconds
Started Feb 04 12:30:37 PM PST 24
Finished Feb 04 12:30:59 PM PST 24
Peak memory 199728 kb
Host smart-ba822e0f-f223-4bc4-82ae-50a3b8d06af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545471426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3545471426
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1257816431
Short name T1090
Test name
Test status
Simulation time 117342855546 ps
CPU time 37.61 seconds
Started Feb 04 12:30:34 PM PST 24
Finished Feb 04 12:31:15 PM PST 24
Peak memory 199704 kb
Host smart-65a861df-3f0e-48f8-96da-26f3a2b1081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257816431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1257816431
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4085610775
Short name T1041
Test name
Test status
Simulation time 23437325 ps
CPU time 0.54 seconds
Started Feb 04 12:30:40 PM PST 24
Finished Feb 04 12:30:49 PM PST 24
Peak memory 195260 kb
Host smart-0ba38394-9ae0-40d0-a7c0-245bb13e31e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085610775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4085610775
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1879961965
Short name T935
Test name
Test status
Simulation time 55111244457 ps
CPU time 84.23 seconds
Started Feb 04 12:30:43 PM PST 24
Finished Feb 04 12:32:13 PM PST 24
Peak memory 199748 kb
Host smart-f3e3ff82-333a-4d10-8c2d-9a88dbf12133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879961965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1879961965
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1815068169
Short name T820
Test name
Test status
Simulation time 53183104733 ps
CPU time 45.84 seconds
Started Feb 04 12:30:37 PM PST 24
Finished Feb 04 12:31:26 PM PST 24
Peak memory 199708 kb
Host smart-d96a4577-e28b-4936-8029-f708465532a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815068169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1815068169
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.915496065
Short name T659
Test name
Test status
Simulation time 22611995823 ps
CPU time 9.88 seconds
Started Feb 04 12:30:37 PM PST 24
Finished Feb 04 12:30:50 PM PST 24
Peak memory 199484 kb
Host smart-96bbeba7-3d53-4f76-aec6-ba6b34941af2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915496065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.915496065
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4261187502
Short name T813
Test name
Test status
Simulation time 89240221641 ps
CPU time 633.97 seconds
Started Feb 04 12:30:41 PM PST 24
Finished Feb 04 12:41:23 PM PST 24
Peak memory 199644 kb
Host smart-964ef279-52ff-450b-ae44-ca96799ccdf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261187502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4261187502
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_noise_filter.445842903
Short name T743
Test name
Test status
Simulation time 18373461121 ps
CPU time 29.51 seconds
Started Feb 04 12:30:43 PM PST 24
Finished Feb 04 12:31:19 PM PST 24
Peak memory 198448 kb
Host smart-a89357c7-ae46-4065-a2f0-5aa5c23ed794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445842903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.445842903
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.79952524
Short name T590
Test name
Test status
Simulation time 16066762509 ps
CPU time 456.52 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:38:17 PM PST 24
Peak memory 199792 kb
Host smart-67db0275-366b-4dc6-a419-7e52a7a298d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79952524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.79952524
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1833116617
Short name T496
Test name
Test status
Simulation time 4131018135 ps
CPU time 39.96 seconds
Started Feb 04 12:30:37 PM PST 24
Finished Feb 04 12:31:20 PM PST 24
Peak memory 197844 kb
Host smart-f4ba4f50-5c08-4169-ac5d-77520ff34907
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833116617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1833116617
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3775361057
Short name T868
Test name
Test status
Simulation time 33681664809 ps
CPU time 53.89 seconds
Started Feb 04 12:30:44 PM PST 24
Finished Feb 04 12:31:43 PM PST 24
Peak memory 198964 kb
Host smart-5cf1db10-257d-4321-87ef-35ed698402dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775361057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3775361057
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3899112607
Short name T1137
Test name
Test status
Simulation time 2747099976 ps
CPU time 5.02 seconds
Started Feb 04 12:30:41 PM PST 24
Finished Feb 04 12:30:54 PM PST 24
Peak memory 195176 kb
Host smart-728fc884-cfd1-4d71-a841-bab1ed9154ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899112607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3899112607
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4025271700
Short name T737
Test name
Test status
Simulation time 113200110 ps
CPU time 0.99 seconds
Started Feb 04 12:30:41 PM PST 24
Finished Feb 04 12:30:50 PM PST 24
Peak memory 197408 kb
Host smart-5edc18ad-05f9-4672-8d78-10309bbe4b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025271700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4025271700
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.974527378
Short name T107
Test name
Test status
Simulation time 711900369091 ps
CPU time 738.35 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:43:05 PM PST 24
Peak memory 199800 kb
Host smart-f732967d-373d-4855-ad1f-43b7aec1edd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974527378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.974527378
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1809178236
Short name T539
Test name
Test status
Simulation time 458065050 ps
CPU time 1.47 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:30:46 PM PST 24
Peak memory 197676 kb
Host smart-25401b73-b9f1-47da-81a4-e18153e4bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809178236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1809178236
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.815538324
Short name T1031
Test name
Test status
Simulation time 43413784411 ps
CPU time 79.17 seconds
Started Feb 04 12:30:39 PM PST 24
Finished Feb 04 12:32:07 PM PST 24
Peak memory 199864 kb
Host smart-8dbc73ac-59b0-49ad-a4e5-a06b91e3a300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815538324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.815538324
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2287775709
Short name T799
Test name
Test status
Simulation time 23345352 ps
CPU time 0.59 seconds
Started Feb 04 12:30:50 PM PST 24
Finished Feb 04 12:30:52 PM PST 24
Peak memory 194168 kb
Host smart-a6e9704e-94b3-4db8-afc8-e00260a9ff3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287775709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2287775709
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1054539669
Short name T678
Test name
Test status
Simulation time 59538538482 ps
CPU time 81.65 seconds
Started Feb 04 12:30:46 PM PST 24
Finished Feb 04 12:32:11 PM PST 24
Peak memory 199704 kb
Host smart-0238ae23-9a66-457e-859e-dfc41ebcedd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054539669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1054539669
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1255271177
Short name T203
Test name
Test status
Simulation time 26967673972 ps
CPU time 47.05 seconds
Started Feb 04 12:30:45 PM PST 24
Finished Feb 04 12:31:36 PM PST 24
Peak memory 199452 kb
Host smart-4ac83480-27af-4102-b16c-b76505aec973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255271177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1255271177
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.868362254
Short name T305
Test name
Test status
Simulation time 180459794208 ps
CPU time 75.04 seconds
Started Feb 04 12:30:45 PM PST 24
Finished Feb 04 12:32:04 PM PST 24
Peak memory 199360 kb
Host smart-0c93c476-313a-4900-b9de-a63d78bdcb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868362254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.868362254
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3348768506
Short name T1173
Test name
Test status
Simulation time 387483089782 ps
CPU time 148.94 seconds
Started Feb 04 12:30:45 PM PST 24
Finished Feb 04 12:33:18 PM PST 24
Peak memory 199608 kb
Host smart-696307b9-0c71-44d4-be27-0154d4aaf086
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348768506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3348768506
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3888742438
Short name T755
Test name
Test status
Simulation time 97576135868 ps
CPU time 232.64 seconds
Started Feb 04 12:30:43 PM PST 24
Finished Feb 04 12:34:42 PM PST 24
Peak memory 199508 kb
Host smart-cc5b59fb-a3f7-4a77-b212-ce266373e0c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888742438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3888742438
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1588239061
Short name T550
Test name
Test status
Simulation time 5670262780 ps
CPU time 13.77 seconds
Started Feb 04 12:30:43 PM PST 24
Finished Feb 04 12:31:03 PM PST 24
Peak memory 197652 kb
Host smart-bab8931b-044e-4004-89b3-44a0141a4973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588239061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1588239061
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3756059959
Short name T420
Test name
Test status
Simulation time 56251034426 ps
CPU time 57.65 seconds
Started Feb 04 12:30:45 PM PST 24
Finished Feb 04 12:31:47 PM PST 24
Peak memory 199136 kb
Host smart-2534dab6-fe8b-40a5-ae3c-4ced2231f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756059959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3756059959
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1440055010
Short name T717
Test name
Test status
Simulation time 18989826205 ps
CPU time 548.83 seconds
Started Feb 04 12:30:43 PM PST 24
Finished Feb 04 12:39:58 PM PST 24
Peak memory 199716 kb
Host smart-72267965-c919-47f9-98ca-e74f80ccf079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1440055010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1440055010
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.659147882
Short name T940
Test name
Test status
Simulation time 127738649481 ps
CPU time 185.65 seconds
Started Feb 04 12:30:46 PM PST 24
Finished Feb 04 12:33:55 PM PST 24
Peak memory 199696 kb
Host smart-5fe9a41f-8f15-4ce3-90e6-57129b756ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659147882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.659147882
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3903413219
Short name T603
Test name
Test status
Simulation time 3491715427 ps
CPU time 2.11 seconds
Started Feb 04 12:30:45 PM PST 24
Finished Feb 04 12:30:51 PM PST 24
Peak memory 194768 kb
Host smart-f6ad4fa7-8960-43b9-b3de-55bf22c3c865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903413219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3903413219
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3371166484
Short name T712
Test name
Test status
Simulation time 459602583 ps
CPU time 1.94 seconds
Started Feb 04 12:30:40 PM PST 24
Finished Feb 04 12:30:50 PM PST 24
Peak memory 197936 kb
Host smart-08e4ae8c-f855-4cbe-a8e4-bcad94e28b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371166484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3371166484
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.4219512182
Short name T893
Test name
Test status
Simulation time 1006641618884 ps
CPU time 589.05 seconds
Started Feb 04 12:30:50 PM PST 24
Finished Feb 04 12:40:40 PM PST 24
Peak memory 199972 kb
Host smart-02f7dd5d-e0d5-4a4f-8bd4-c7df292d8acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219512182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4219512182
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3577284931
Short name T218
Test name
Test status
Simulation time 241049307181 ps
CPU time 849.15 seconds
Started Feb 04 12:30:55 PM PST 24
Finished Feb 04 12:45:08 PM PST 24
Peak memory 216232 kb
Host smart-0df9a65e-8e07-4945-8ff2-4c9cbc8fb501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577284931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3577284931
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4108668179
Short name T427
Test name
Test status
Simulation time 447074339 ps
CPU time 1.49 seconds
Started Feb 04 12:30:38 PM PST 24
Finished Feb 04 12:30:42 PM PST 24
Peak memory 196240 kb
Host smart-49a7eace-828d-41fe-b043-d78ba2fd57e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108668179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4108668179
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1827914838
Short name T1213
Test name
Test status
Simulation time 3391065890 ps
CPU time 6.32 seconds
Started Feb 04 12:30:45 PM PST 24
Finished Feb 04 12:30:56 PM PST 24
Peak memory 196504 kb
Host smart-7a55aca4-e1eb-4f61-8008-d493c0e7c012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827914838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1827914838
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1130161301
Short name T561
Test name
Test status
Simulation time 10911390 ps
CPU time 0.53 seconds
Started Feb 04 12:30:50 PM PST 24
Finished Feb 04 12:30:52 PM PST 24
Peak memory 195220 kb
Host smart-52c4f260-e270-4ebc-8e7d-effddf906d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130161301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1130161301
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2147165075
Short name T707
Test name
Test status
Simulation time 99750978058 ps
CPU time 45.63 seconds
Started Feb 04 12:30:48 PM PST 24
Finished Feb 04 12:31:36 PM PST 24
Peak memory 199752 kb
Host smart-671b8913-8618-41ed-b838-1a1ffce3a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147165075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2147165075
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3242232458
Short name T969
Test name
Test status
Simulation time 281644305401 ps
CPU time 364.57 seconds
Started Feb 04 12:30:49 PM PST 24
Finished Feb 04 12:36:55 PM PST 24
Peak memory 199844 kb
Host smart-58370660-5b25-49c0-889b-4b8926c1d4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242232458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3242232458
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.813528686
Short name T250
Test name
Test status
Simulation time 33727676963 ps
CPU time 14.27 seconds
Started Feb 04 12:30:52 PM PST 24
Finished Feb 04 12:31:11 PM PST 24
Peak memory 199504 kb
Host smart-f6d8f6dc-9b25-4a59-9241-43052ed4c467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813528686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.813528686
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2667125822
Short name T753
Test name
Test status
Simulation time 37406016006 ps
CPU time 32.63 seconds
Started Feb 04 12:30:49 PM PST 24
Finished Feb 04 12:31:23 PM PST 24
Peak memory 198744 kb
Host smart-1b094ce2-ea05-4635-990b-f69607d91229
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667125822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2667125822
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2215078316
Short name T646
Test name
Test status
Simulation time 83837463095 ps
CPU time 164.41 seconds
Started Feb 04 12:30:51 PM PST 24
Finished Feb 04 12:33:37 PM PST 24
Peak memory 199900 kb
Host smart-0dcc93a6-1975-4c58-8149-a439b60fd3d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215078316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2215078316
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.541414705
Short name T31
Test name
Test status
Simulation time 6096629151 ps
CPU time 4.48 seconds
Started Feb 04 12:30:50 PM PST 24
Finished Feb 04 12:30:56 PM PST 24
Peak memory 198016 kb
Host smart-a498feac-114a-4553-a41b-67af1779a27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541414705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.541414705
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1205621748
Short name T941
Test name
Test status
Simulation time 133284302458 ps
CPU time 99.48 seconds
Started Feb 04 12:30:57 PM PST 24
Finished Feb 04 12:32:39 PM PST 24
Peak memory 199096 kb
Host smart-b6c0b081-329c-4e65-8936-396938c63df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205621748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1205621748
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.231988830
Short name T615
Test name
Test status
Simulation time 11428754383 ps
CPU time 139.83 seconds
Started Feb 04 12:30:57 PM PST 24
Finished Feb 04 12:33:20 PM PST 24
Peak memory 199760 kb
Host smart-354abe81-12d9-4952-b0b0-eee58491a8ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231988830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.231988830
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3811645457
Short name T701
Test name
Test status
Simulation time 153216135 ps
CPU time 0.99 seconds
Started Feb 04 12:30:52 PM PST 24
Finished Feb 04 12:30:56 PM PST 24
Peak memory 197472 kb
Host smart-7c5eeff4-c786-40f0-a93d-733984bbc947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3811645457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3811645457
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3768538941
Short name T380
Test name
Test status
Simulation time 15667507061 ps
CPU time 22.25 seconds
Started Feb 04 12:30:50 PM PST 24
Finished Feb 04 12:31:14 PM PST 24
Peak memory 198920 kb
Host smart-82bdcf2d-fe56-4421-9cc2-d92aa6d8f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768538941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3768538941
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2430207907
Short name T436
Test name
Test status
Simulation time 33496545374 ps
CPU time 55.02 seconds
Started Feb 04 12:30:50 PM PST 24
Finished Feb 04 12:31:47 PM PST 24
Peak memory 195644 kb
Host smart-f247b709-47e4-4596-9c13-708124fddde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430207907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2430207907
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.4110662292
Short name T443
Test name
Test status
Simulation time 498623280 ps
CPU time 1.86 seconds
Started Feb 04 12:30:56 PM PST 24
Finished Feb 04 12:31:01 PM PST 24
Peak memory 197496 kb
Host smart-9b916986-0dbf-4686-9727-1ca47d99aa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110662292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.4110662292
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.654700882
Short name T296
Test name
Test status
Simulation time 140539719957 ps
CPU time 27.77 seconds
Started Feb 04 12:30:56 PM PST 24
Finished Feb 04 12:31:27 PM PST 24
Peak memory 199776 kb
Host smart-df05e337-fbb8-4e5e-9fe9-d2f0f92dac9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654700882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.654700882
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1603584867
Short name T386
Test name
Test status
Simulation time 37871528511 ps
CPU time 216.11 seconds
Started Feb 04 12:30:50 PM PST 24
Finished Feb 04 12:34:28 PM PST 24
Peak memory 208144 kb
Host smart-437d3070-5e23-4d42-a90a-3d651df7685a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603584867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1603584867
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.321263134
Short name T1048
Test name
Test status
Simulation time 880798392 ps
CPU time 3.11 seconds
Started Feb 04 12:30:57 PM PST 24
Finished Feb 04 12:31:03 PM PST 24
Peak memory 197728 kb
Host smart-99ffbd4b-be8c-4d9a-baaf-48a5d32582e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321263134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.321263134
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2745317866
Short name T975
Test name
Test status
Simulation time 10749923586 ps
CPU time 12.5 seconds
Started Feb 04 12:30:49 PM PST 24
Finished Feb 04 12:31:03 PM PST 24
Peak memory 199436 kb
Host smart-6d980196-3c24-4777-baf0-8af18e5e2b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745317866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2745317866
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.664333693
Short name T541
Test name
Test status
Simulation time 32819786 ps
CPU time 0.53 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:28:43 PM PST 24
Peak memory 194160 kb
Host smart-6836bdcf-0c3c-45eb-a206-d7b7472a6be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664333693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.664333693
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.4234403008
Short name T636
Test name
Test status
Simulation time 35732265608 ps
CPU time 24.24 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:56 PM PST 24
Peak memory 199748 kb
Host smart-dbfdfef0-f9e5-4603-a30b-f04ae1d1e367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234403008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.4234403008
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2695438234
Short name T374
Test name
Test status
Simulation time 40092251060 ps
CPU time 56.96 seconds
Started Feb 04 12:28:27 PM PST 24
Finished Feb 04 12:29:31 PM PST 24
Peak memory 199832 kb
Host smart-98244a08-c4d0-44dc-800e-f162a944a80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695438234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2695438234
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.2636454893
Short name T1087
Test name
Test status
Simulation time 123066434733 ps
CPU time 49.19 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:29:23 PM PST 24
Peak memory 198604 kb
Host smart-ce108cf9-6c2f-482d-b263-dc1e1d154a57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636454893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2636454893
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.573085088
Short name T1130
Test name
Test status
Simulation time 129895631130 ps
CPU time 735.54 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:40:58 PM PST 24
Peak memory 199852 kb
Host smart-48c7406d-b71c-41c7-9fdd-c1e612cba03c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573085088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.573085088
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3718204988
Short name T836
Test name
Test status
Simulation time 8647214982 ps
CPU time 6.69 seconds
Started Feb 04 12:28:19 PM PST 24
Finished Feb 04 12:28:31 PM PST 24
Peak memory 198228 kb
Host smart-eda36d2f-02c6-4440-b18b-894d9cf114bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718204988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3718204988
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3093132872
Short name T685
Test name
Test status
Simulation time 71337437703 ps
CPU time 144.6 seconds
Started Feb 04 12:28:16 PM PST 24
Finished Feb 04 12:30:49 PM PST 24
Peak memory 198728 kb
Host smart-a650745c-0941-41a5-aaa6-296928884c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093132872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3093132872
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3285359789
Short name T682
Test name
Test status
Simulation time 3537021957 ps
CPU time 137.94 seconds
Started Feb 04 12:28:27 PM PST 24
Finished Feb 04 12:30:52 PM PST 24
Peak memory 199672 kb
Host smart-1ed56198-7c9c-458e-87bf-54d171f93dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285359789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3285359789
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2955270106
Short name T490
Test name
Test status
Simulation time 2039777239 ps
CPU time 3.4 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:43 PM PST 24
Peak memory 197940 kb
Host smart-88be4069-b4ba-4cd2-af2a-0e95f126f478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955270106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2955270106
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2535189801
Short name T348
Test name
Test status
Simulation time 18424795715 ps
CPU time 30.96 seconds
Started Feb 04 12:28:20 PM PST 24
Finished Feb 04 12:28:56 PM PST 24
Peak memory 199704 kb
Host smart-ca69d206-be67-4979-9a38-f66a7fed28e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535189801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2535189801
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2046081644
Short name T747
Test name
Test status
Simulation time 2965058527 ps
CPU time 1.93 seconds
Started Feb 04 12:28:20 PM PST 24
Finished Feb 04 12:28:27 PM PST 24
Peak memory 195148 kb
Host smart-7be6ad62-806a-46ad-a2d9-3f1eeab46070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046081644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2046081644
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1537325126
Short name T1013
Test name
Test status
Simulation time 459759566 ps
CPU time 1.46 seconds
Started Feb 04 12:28:28 PM PST 24
Finished Feb 04 12:28:36 PM PST 24
Peak memory 197916 kb
Host smart-5f2c8880-830c-48a3-a832-771186ac27b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537325126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1537325126
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.217535741
Short name T182
Test name
Test status
Simulation time 201725804021 ps
CPU time 554.7 seconds
Started Feb 04 12:28:28 PM PST 24
Finished Feb 04 12:37:49 PM PST 24
Peak memory 199704 kb
Host smart-00191907-9e79-4d23-8a88-1dd725a94857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217535741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.217535741
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.4109259157
Short name T437
Test name
Test status
Simulation time 7409637030 ps
CPU time 16.13 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:59 PM PST 24
Peak memory 198848 kb
Host smart-ab5e7975-0c95-488c-8e70-0f5b804f5278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109259157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4109259157
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2529820789
Short name T926
Test name
Test status
Simulation time 178329271785 ps
CPU time 28.44 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:29:00 PM PST 24
Peak memory 199768 kb
Host smart-56869f58-93e6-4d18-800e-0b9d5a3901f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529820789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2529820789
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.4168808027
Short name T589
Test name
Test status
Simulation time 79128511652 ps
CPU time 19.34 seconds
Started Feb 04 12:30:51 PM PST 24
Finished Feb 04 12:31:12 PM PST 24
Peak memory 199660 kb
Host smart-c8b0323a-7acd-44a2-874d-ceabcbf13f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168808027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.4168808027
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.889345798
Short name T117
Test name
Test status
Simulation time 111022363952 ps
CPU time 976.93 seconds
Started Feb 04 12:30:54 PM PST 24
Finished Feb 04 12:47:16 PM PST 24
Peak memory 224744 kb
Host smart-4ff01bc0-c482-40ec-90c3-73fc170a92de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889345798 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.889345798
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1877448120
Short name T174
Test name
Test status
Simulation time 144847892122 ps
CPU time 35.03 seconds
Started Feb 04 12:30:48 PM PST 24
Finished Feb 04 12:31:25 PM PST 24
Peak memory 199408 kb
Host smart-fcc6a81c-096f-4e38-9701-863a1e4e97d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877448120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1877448120
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.557832274
Short name T102
Test name
Test status
Simulation time 43584105187 ps
CPU time 649.74 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:41:48 PM PST 24
Peak memory 215696 kb
Host smart-d972f6aa-3c78-49dc-b3c0-a2f8ab91286b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557832274 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.557832274
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2244630379
Short name T258
Test name
Test status
Simulation time 8862145752 ps
CPU time 14.08 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:31:12 PM PST 24
Peak memory 199708 kb
Host smart-529ef4a6-49fd-484b-a3e8-0f1e0b832728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244630379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2244630379
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2971946233
Short name T1220
Test name
Test status
Simulation time 80296462904 ps
CPU time 1406.67 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:54:25 PM PST 24
Peak memory 224764 kb
Host smart-ddae3d9a-94eb-49a4-b7b5-071b35f8c14b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971946233 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2971946233
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.469489297
Short name T26
Test name
Test status
Simulation time 157407455697 ps
CPU time 463.53 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:38:42 PM PST 24
Peak memory 216564 kb
Host smart-cc7c600e-bab3-4b24-ae48-2608f224bf72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469489297 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.469489297
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3420690323
Short name T1187
Test name
Test status
Simulation time 208245688423 ps
CPU time 121.04 seconds
Started Feb 04 12:30:51 PM PST 24
Finished Feb 04 12:32:55 PM PST 24
Peak memory 199860 kb
Host smart-33704b79-89c7-4145-ab6c-ff4d02065c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420690323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3420690323
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1299540115
Short name T319
Test name
Test status
Simulation time 11145341763 ps
CPU time 154.95 seconds
Started Feb 04 12:30:57 PM PST 24
Finished Feb 04 12:33:35 PM PST 24
Peak memory 208476 kb
Host smart-d3c053be-918a-4a72-ad6d-def0ff3dff23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299540115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1299540115
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3837575218
Short name T783
Test name
Test status
Simulation time 54467744219 ps
CPU time 655.57 seconds
Started Feb 04 12:30:54 PM PST 24
Finished Feb 04 12:41:54 PM PST 24
Peak memory 216512 kb
Host smart-711cf91d-6296-4bc4-8b09-c62c303c524a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837575218 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3837575218
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1236772045
Short name T309
Test name
Test status
Simulation time 118358820668 ps
CPU time 35.94 seconds
Started Feb 04 12:30:52 PM PST 24
Finished Feb 04 12:31:33 PM PST 24
Peak memory 199068 kb
Host smart-52b1e07b-603a-4462-8c9e-43deee333a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236772045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1236772045
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2772669685
Short name T447
Test name
Test status
Simulation time 4483529898 ps
CPU time 57.78 seconds
Started Feb 04 12:30:52 PM PST 24
Finished Feb 04 12:31:54 PM PST 24
Peak memory 200280 kb
Host smart-e5e99cdf-5552-4161-b6f5-0bc79bd3564d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772669685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2772669685
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.941530638
Short name T762
Test name
Test status
Simulation time 89990488739 ps
CPU time 129.63 seconds
Started Feb 04 12:30:54 PM PST 24
Finished Feb 04 12:33:08 PM PST 24
Peak memory 199860 kb
Host smart-311f06f6-d6b8-491b-b045-bd79e6ad1252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941530638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.941530638
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3750909493
Short name T696
Test name
Test status
Simulation time 38908485560 ps
CPU time 308.4 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:36:06 PM PST 24
Peak memory 216552 kb
Host smart-6ffafc03-f202-4c6c-aa6d-0f8309b74baa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750909493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3750909493
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3345179
Short name T365
Test name
Test status
Simulation time 13792139408 ps
CPU time 11.89 seconds
Started Feb 04 12:30:53 PM PST 24
Finished Feb 04 12:31:10 PM PST 24
Peak memory 199788 kb
Host smart-d5927710-d68c-41da-9294-ee2a67d86a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3345179
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2554548104
Short name T564
Test name
Test status
Simulation time 23451212771 ps
CPU time 276.35 seconds
Started Feb 04 12:30:54 PM PST 24
Finished Feb 04 12:35:35 PM PST 24
Peak memory 216344 kb
Host smart-9f5d2642-47f7-4744-998f-d956539ce021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554548104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2554548104
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.4238253056
Short name T977
Test name
Test status
Simulation time 50978083 ps
CPU time 0.53 seconds
Started Feb 04 12:28:27 PM PST 24
Finished Feb 04 12:28:34 PM PST 24
Peak memory 193992 kb
Host smart-d7d540b9-8f2e-4280-aedd-3221e9628aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238253056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4238253056
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1719252658
Short name T354
Test name
Test status
Simulation time 94277067255 ps
CPU time 34.55 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:17 PM PST 24
Peak memory 199328 kb
Host smart-2f683e03-1922-4247-89fb-8b23c1c12cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719252658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1719252658
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.772597328
Short name T161
Test name
Test status
Simulation time 131016159574 ps
CPU time 218.89 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:32:22 PM PST 24
Peak memory 199740 kb
Host smart-a12d7608-2fc4-4a37-b6f8-c96e8ddc361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772597328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.772597328
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1563676577
Short name T719
Test name
Test status
Simulation time 406686029785 ps
CPU time 562.58 seconds
Started Feb 04 12:28:28 PM PST 24
Finished Feb 04 12:37:58 PM PST 24
Peak memory 199720 kb
Host smart-ce48b4ce-9922-4eff-b3a1-58c670b29d1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563676577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1563676577
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.306537974
Short name T528
Test name
Test status
Simulation time 84697823754 ps
CPU time 272.13 seconds
Started Feb 04 12:28:18 PM PST 24
Finished Feb 04 12:32:57 PM PST 24
Peak memory 199680 kb
Host smart-e94ce33d-a2de-44eb-aef1-1ea20ec009b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306537974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.306537974
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3452799808
Short name T546
Test name
Test status
Simulation time 1229152859 ps
CPU time 2.93 seconds
Started Feb 04 12:28:29 PM PST 24
Finished Feb 04 12:28:40 PM PST 24
Peak memory 197988 kb
Host smart-d82601fe-61b1-4e38-afcd-64b046afdfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452799808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3452799808
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.678639367
Short name T417
Test name
Test status
Simulation time 13480137679 ps
CPU time 20 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:03 PM PST 24
Peak memory 197108 kb
Host smart-71da7097-8f41-4fb2-90ff-e23f3164bac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678639367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.678639367
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3812063558
Short name T297
Test name
Test status
Simulation time 7867458936 ps
CPU time 186.78 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:31:50 PM PST 24
Peak memory 199012 kb
Host smart-41879bf4-c7b7-4ab2-b257-efb70f9e6360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812063558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3812063558
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.808832168
Short name T1149
Test name
Test status
Simulation time 1273359038 ps
CPU time 10.34 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:44 PM PST 24
Peak memory 197304 kb
Host smart-39e16155-cdd0-43c4-b822-322d03aa67a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808832168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.808832168
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3400932862
Short name T370
Test name
Test status
Simulation time 132384976123 ps
CPU time 213.23 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:32:05 PM PST 24
Peak memory 199760 kb
Host smart-06410e6e-8304-48ec-ba10-364b273d3f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400932862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3400932862
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2057769529
Short name T423
Test name
Test status
Simulation time 3985569081 ps
CPU time 6.51 seconds
Started Feb 04 12:28:33 PM PST 24
Finished Feb 04 12:28:46 PM PST 24
Peak memory 195452 kb
Host smart-13df544f-8c9d-4792-a62c-a4a1b2b42391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057769529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2057769529
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1882209569
Short name T760
Test name
Test status
Simulation time 449563877 ps
CPU time 2.69 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:33 PM PST 24
Peak memory 198096 kb
Host smart-71dbfcb9-1e29-4c73-bd7e-3ffd2ff872cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882209569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1882209569
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3793570440
Short name T697
Test name
Test status
Simulation time 28230613850 ps
CPU time 1374.08 seconds
Started Feb 04 12:28:34 PM PST 24
Finished Feb 04 12:51:35 PM PST 24
Peak memory 199844 kb
Host smart-c69004d5-6c6a-4278-a47e-8184bf38eea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793570440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3793570440
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.92674023
Short name T346
Test name
Test status
Simulation time 34913541429 ps
CPU time 348.23 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:34:20 PM PST 24
Peak memory 216280 kb
Host smart-1b0b5d2e-6b2b-4d14-a095-ef36d61345ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92674023 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.92674023
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2195733281
Short name T441
Test name
Test status
Simulation time 558145012 ps
CPU time 2.52 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:36 PM PST 24
Peak memory 199108 kb
Host smart-46f00a3d-556c-4487-b402-acd80c8a6e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195733281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2195733281
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2498844318
Short name T780
Test name
Test status
Simulation time 114276435493 ps
CPU time 87.16 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:30:10 PM PST 24
Peak memory 199324 kb
Host smart-b7df7727-7356-4e55-964f-4bb101be6309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498844318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2498844318
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4212352668
Short name T930
Test name
Test status
Simulation time 26077762015 ps
CPU time 37.29 seconds
Started Feb 04 12:30:54 PM PST 24
Finished Feb 04 12:31:36 PM PST 24
Peak memory 199764 kb
Host smart-a856ee64-5fa1-461d-bf23-bf66159bda90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212352668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4212352668
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3367662948
Short name T1028
Test name
Test status
Simulation time 69945402735 ps
CPU time 212.67 seconds
Started Feb 04 12:30:58 PM PST 24
Finished Feb 04 12:34:38 PM PST 24
Peak memory 215936 kb
Host smart-99f780a1-95bd-4e2e-b204-136734eaa806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367662948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3367662948
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2229931926
Short name T1102
Test name
Test status
Simulation time 111203680143 ps
CPU time 82.62 seconds
Started Feb 04 12:30:52 PM PST 24
Finished Feb 04 12:32:19 PM PST 24
Peak memory 199396 kb
Host smart-35cdde1e-3e6c-46c9-a55e-8aab3677201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229931926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2229931926
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1189877577
Short name T391
Test name
Test status
Simulation time 359091657155 ps
CPU time 641.23 seconds
Started Feb 04 12:30:56 PM PST 24
Finished Feb 04 12:41:41 PM PST 24
Peak memory 216364 kb
Host smart-4a035991-7008-43fb-8ad2-b12eef7660d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189877577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1189877577
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1834004774
Short name T722
Test name
Test status
Simulation time 24198329403 ps
CPU time 281.02 seconds
Started Feb 04 12:30:56 PM PST 24
Finished Feb 04 12:35:41 PM PST 24
Peak memory 208120 kb
Host smart-f8c80dc6-aa54-4c27-a9a2-406309d470f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834004774 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1834004774
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1788487280
Short name T168
Test name
Test status
Simulation time 118814474873 ps
CPU time 15.9 seconds
Started Feb 04 12:30:54 PM PST 24
Finished Feb 04 12:31:14 PM PST 24
Peak memory 199796 kb
Host smart-c0a32eca-20f5-4d90-9693-88e1967ae952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788487280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1788487280
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3324841997
Short name T1000
Test name
Test status
Simulation time 158650568377 ps
CPU time 491.95 seconds
Started Feb 04 12:31:15 PM PST 24
Finished Feb 04 12:39:28 PM PST 24
Peak memory 224804 kb
Host smart-bb068108-22ce-4a0c-b379-eaa972203b3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324841997 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3324841997
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3829266861
Short name T709
Test name
Test status
Simulation time 131005461826 ps
CPU time 183.99 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:34:13 PM PST 24
Peak memory 199220 kb
Host smart-e116b440-530f-4fef-af5b-99a8d9ea5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829266861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3829266861
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3668492411
Short name T79
Test name
Test status
Simulation time 175858741274 ps
CPU time 670.76 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:42:22 PM PST 24
Peak memory 227204 kb
Host smart-9b23be71-3c70-4e8d-a197-bd7a10419ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668492411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3668492411
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3112977455
Short name T435
Test name
Test status
Simulation time 12190582009 ps
CPU time 20.12 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:31:29 PM PST 24
Peak memory 199784 kb
Host smart-917ac039-9b12-4c5c-94d7-ba08403e0837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112977455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3112977455
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.147894771
Short name T882
Test name
Test status
Simulation time 314048349154 ps
CPU time 401.61 seconds
Started Feb 04 12:31:06 PM PST 24
Finished Feb 04 12:37:50 PM PST 24
Peak memory 216524 kb
Host smart-a7f0d4d0-bd4b-40dc-8d17-3896fc1932c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147894771 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.147894771
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2208638264
Short name T742
Test name
Test status
Simulation time 9138033853 ps
CPU time 9.35 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:31:20 PM PST 24
Peak memory 199668 kb
Host smart-35dc3aea-2364-453d-9e2d-85dab7d0c63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208638264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2208638264
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2359281506
Short name T372
Test name
Test status
Simulation time 116252237078 ps
CPU time 565.87 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:40:36 PM PST 24
Peak memory 228208 kb
Host smart-813d6c93-03ba-4d56-9e2a-9a2d58b9d19e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359281506 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2359281506
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.4231466489
Short name T313
Test name
Test status
Simulation time 6314709594 ps
CPU time 9.66 seconds
Started Feb 04 12:31:05 PM PST 24
Finished Feb 04 12:31:17 PM PST 24
Peak memory 197492 kb
Host smart-8049ae58-c242-400b-b4dd-0aaa150a73ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231466489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.4231466489
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.169167960
Short name T290
Test name
Test status
Simulation time 21254444266 ps
CPU time 207 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:34:38 PM PST 24
Peak memory 216216 kb
Host smart-8d0b15fa-9b21-4909-bc25-8a19282e18d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169167960 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.169167960
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.104376189
Short name T267
Test name
Test status
Simulation time 135893303299 ps
CPU time 50.53 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:32:01 PM PST 24
Peak memory 199792 kb
Host smart-24c534d6-681e-4842-8f8a-a300d3bd8470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104376189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.104376189
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1305534629
Short name T1134
Test name
Test status
Simulation time 77263220992 ps
CPU time 488.63 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:39:19 PM PST 24
Peak memory 216572 kb
Host smart-ff8a1c2c-7ea3-4fde-9aaa-adc92bb005ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305534629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1305534629
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.151727023
Short name T584
Test name
Test status
Simulation time 12708000 ps
CPU time 0.54 seconds
Started Feb 04 12:28:38 PM PST 24
Finished Feb 04 12:28:44 PM PST 24
Peak memory 195112 kb
Host smart-14b473e3-6875-473b-9fad-17310ba1dc0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151727023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.151727023
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2271602879
Short name T829
Test name
Test status
Simulation time 125098331467 ps
CPU time 26.04 seconds
Started Feb 04 12:28:34 PM PST 24
Finished Feb 04 12:29:06 PM PST 24
Peak memory 199824 kb
Host smart-978859ff-5daf-4e14-8ce1-2e1829c4a2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271602879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2271602879
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.622424684
Short name T1166
Test name
Test status
Simulation time 125095473979 ps
CPU time 99.74 seconds
Started Feb 04 12:28:34 PM PST 24
Finished Feb 04 12:30:20 PM PST 24
Peak memory 199548 kb
Host smart-1a2f1124-eb15-4c97-ab30-45af89b16ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622424684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.622424684
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.3381950238
Short name T785
Test name
Test status
Simulation time 170631618034 ps
CPU time 100.02 seconds
Started Feb 04 12:28:23 PM PST 24
Finished Feb 04 12:30:05 PM PST 24
Peak memory 198932 kb
Host smart-ef682b54-8a45-4c86-8c5a-5e8c576e9143
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381950238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3381950238
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1886537866
Short name T429
Test name
Test status
Simulation time 106271891069 ps
CPU time 290.24 seconds
Started Feb 04 12:28:34 PM PST 24
Finished Feb 04 12:33:31 PM PST 24
Peak memory 199908 kb
Host smart-784cce97-522d-4006-8a0f-c69bc5c339c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886537866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1886537866
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.938332978
Short name T1217
Test name
Test status
Simulation time 5303998984 ps
CPU time 3.62 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:37 PM PST 24
Peak memory 197412 kb
Host smart-384beb10-5062-426f-8cd0-48ed95bfce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938332978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.938332978
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1000340049
Short name T22
Test name
Test status
Simulation time 5703156929 ps
CPU time 10.04 seconds
Started Feb 04 12:28:23 PM PST 24
Finished Feb 04 12:28:37 PM PST 24
Peak memory 193464 kb
Host smart-7d9106bd-292e-4dc5-a757-0406f6588575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000340049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1000340049
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2582284760
Short name T266
Test name
Test status
Simulation time 6579212352 ps
CPU time 155.21 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:31:07 PM PST 24
Peak memory 199748 kb
Host smart-6f731576-e580-41c6-8edc-71ecf2424ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582284760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2582284760
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2520548190
Short name T1111
Test name
Test status
Simulation time 1978591279 ps
CPU time 3.32 seconds
Started Feb 04 12:28:25 PM PST 24
Finished Feb 04 12:28:35 PM PST 24
Peak memory 197324 kb
Host smart-1ba4262a-9102-49aa-9fd7-93e0f882146b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520548190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2520548190
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2912612646
Short name T699
Test name
Test status
Simulation time 32090270605 ps
CPU time 33.57 seconds
Started Feb 04 12:28:27 PM PST 24
Finished Feb 04 12:29:07 PM PST 24
Peak memory 198176 kb
Host smart-1897d66e-e7f6-4716-acb5-ca2b585a0bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912612646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2912612646
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1402064878
Short name T1042
Test name
Test status
Simulation time 413523426 ps
CPU time 1.27 seconds
Started Feb 04 12:28:26 PM PST 24
Finished Feb 04 12:28:35 PM PST 24
Peak memory 195168 kb
Host smart-4e0c720a-4a87-40dd-9ce2-5fe7c2d270fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402064878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1402064878
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.4030908084
Short name T613
Test name
Test status
Simulation time 292108717 ps
CPU time 1.49 seconds
Started Feb 04 12:28:21 PM PST 24
Finished Feb 04 12:28:26 PM PST 24
Peak memory 197336 kb
Host smart-21af18f5-4637-4d13-ba7c-158ec65eaea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030908084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4030908084
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2134069804
Short name T358
Test name
Test status
Simulation time 362206854482 ps
CPU time 52.85 seconds
Started Feb 04 12:28:23 PM PST 24
Finished Feb 04 12:29:21 PM PST 24
Peak memory 199788 kb
Host smart-bef00a95-8b15-4619-a81d-9f80acbb4700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134069804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2134069804
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.914783728
Short name T364
Test name
Test status
Simulation time 153853210478 ps
CPU time 519.95 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:37:22 PM PST 24
Peak memory 224520 kb
Host smart-e7ac11dd-07b2-4485-948c-f00f989e49b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914783728 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.914783728
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3921629255
Short name T500
Test name
Test status
Simulation time 2300215678 ps
CPU time 2.2 seconds
Started Feb 04 12:28:27 PM PST 24
Finished Feb 04 12:28:36 PM PST 24
Peak memory 197564 kb
Host smart-26e19cae-73b2-46ce-b873-424e585feb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921629255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3921629255
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1840935324
Short name T1062
Test name
Test status
Simulation time 49978497691 ps
CPU time 45.23 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:28 PM PST 24
Peak memory 199572 kb
Host smart-d84f304b-b7a4-4df4-b538-ecbaa28b3876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840935324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1840935324
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2021293601
Short name T1229
Test name
Test status
Simulation time 70240881053 ps
CPU time 54.79 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:32:06 PM PST 24
Peak memory 199748 kb
Host smart-eea15253-6704-4442-b671-a51311628ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021293601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2021293601
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3826564932
Short name T643
Test name
Test status
Simulation time 31197190236 ps
CPU time 93.83 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:32:43 PM PST 24
Peak memory 209888 kb
Host smart-caa9a771-d09e-413b-89ba-33e7554cecb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826564932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3826564932
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3176344169
Short name T632
Test name
Test status
Simulation time 116944975854 ps
CPU time 161.14 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:33:54 PM PST 24
Peak memory 198980 kb
Host smart-ee2bc9a0-1e76-4494-9a72-6e228ac400dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176344169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3176344169
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1142005025
Short name T881
Test name
Test status
Simulation time 46076093090 ps
CPU time 191.62 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:34:22 PM PST 24
Peak memory 208172 kb
Host smart-e425ae08-e399-4b94-a44d-c6dfc32900ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142005025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1142005025
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1864713801
Short name T911
Test name
Test status
Simulation time 27305119733 ps
CPU time 45.98 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:31:57 PM PST 24
Peak memory 199116 kb
Host smart-16727256-b474-4e35-90a2-a24e80238580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864713801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1864713801
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.504917637
Short name T238
Test name
Test status
Simulation time 122164859698 ps
CPU time 455.81 seconds
Started Feb 04 12:31:04 PM PST 24
Finished Feb 04 12:38:43 PM PST 24
Peak memory 216608 kb
Host smart-34fe94bf-f6e0-44b3-8760-9d4dc1a2e7db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504917637 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.504917637
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.887735804
Short name T272
Test name
Test status
Simulation time 152654660182 ps
CPU time 237.68 seconds
Started Feb 04 12:31:12 PM PST 24
Finished Feb 04 12:35:11 PM PST 24
Peak memory 199748 kb
Host smart-4ae1692a-a6b6-4013-b071-38e9289b4f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887735804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.887735804
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3382342498
Short name T533
Test name
Test status
Simulation time 44943744056 ps
CPU time 298.63 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:36:08 PM PST 24
Peak memory 215644 kb
Host smart-05b99109-90f9-4e59-ab63-a67230d922a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382342498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3382342498
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1750967971
Short name T134
Test name
Test status
Simulation time 58394230423 ps
CPU time 122.41 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:33:13 PM PST 24
Peak memory 199412 kb
Host smart-82b2c13f-acd1-40c1-a2dc-4e180a117987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750967971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1750967971
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.926048786
Short name T322
Test name
Test status
Simulation time 21551687469 ps
CPU time 36.63 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:31:49 PM PST 24
Peak memory 199072 kb
Host smart-1bfde1c9-6c04-4d7b-80e6-ae0355d1efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926048786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.926048786
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2012133509
Short name T574
Test name
Test status
Simulation time 51398624951 ps
CPU time 578.21 seconds
Started Feb 04 12:31:10 PM PST 24
Finished Feb 04 12:40:50 PM PST 24
Peak memory 216312 kb
Host smart-d3e23b17-bd5e-481d-9ba3-70603dc83a79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012133509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2012133509
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1592003913
Short name T736
Test name
Test status
Simulation time 53171625404 ps
CPU time 80.44 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:32:33 PM PST 24
Peak memory 199716 kb
Host smart-3a25ae56-bbdc-4946-9c34-ed3d6de3fe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592003913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1592003913
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.28863895
Short name T164
Test name
Test status
Simulation time 111059254199 ps
CPU time 316.15 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:36:26 PM PST 24
Peak memory 210900 kb
Host smart-36fc406d-bc59-44b7-b4b0-9f51d74e1e7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28863895 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.28863895
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3281359761
Short name T283
Test name
Test status
Simulation time 47032563233 ps
CPU time 38.21 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:31:49 PM PST 24
Peak memory 199172 kb
Host smart-e27794ed-674f-4d28-be14-3449cf383c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281359761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3281359761
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2029719295
Short name T1210
Test name
Test status
Simulation time 31884010982 ps
CPU time 293.29 seconds
Started Feb 04 12:31:15 PM PST 24
Finished Feb 04 12:36:09 PM PST 24
Peak memory 216264 kb
Host smart-1f4994f6-54d1-49ea-bd9a-de099c2469ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029719295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2029719295
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2483508134
Short name T887
Test name
Test status
Simulation time 104732376874 ps
CPU time 23.3 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:31:35 PM PST 24
Peak memory 199844 kb
Host smart-40f88356-a71a-45cf-8f1f-768259bfaa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483508134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2483508134
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1100266796
Short name T865
Test name
Test status
Simulation time 106977677083 ps
CPU time 1004.51 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:47:56 PM PST 24
Peak memory 216360 kb
Host smart-6f88f28d-a050-4194-96ff-cdde1d556863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100266796 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1100266796
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.4020219033
Short name T335
Test name
Test status
Simulation time 145205467720 ps
CPU time 104.42 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:32:53 PM PST 24
Peak memory 199928 kb
Host smart-e49f1dfe-42f1-440d-b815-c70ad750590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020219033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.4020219033
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3056942410
Short name T910
Test name
Test status
Simulation time 276938871075 ps
CPU time 704.16 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:42:55 PM PST 24
Peak memory 216308 kb
Host smart-f988b8aa-7a68-4df7-ad4d-1e77799b6591
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056942410 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3056942410
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3918430291
Short name T497
Test name
Test status
Simulation time 36036688 ps
CPU time 0.52 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:43 PM PST 24
Peak memory 193896 kb
Host smart-52b84745-3a23-46bb-8cfc-7a2c2a15b03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918430291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3918430291
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.406923248
Short name T687
Test name
Test status
Simulation time 103711645701 ps
CPU time 29.91 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:13 PM PST 24
Peak memory 199764 kb
Host smart-0c6401a8-3a89-4801-9171-b952f4cc38b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406923248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.406923248
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3278168752
Short name T284
Test name
Test status
Simulation time 57391898242 ps
CPU time 30.22 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:29:12 PM PST 24
Peak memory 199540 kb
Host smart-f95786bd-4234-4ee7-bbc6-3a017152623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278168752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3278168752
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3175465839
Short name T897
Test name
Test status
Simulation time 737169682145 ps
CPU time 639.6 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:39:23 PM PST 24
Peak memory 198952 kb
Host smart-7badf9f7-8136-44bc-9ca7-f6ee4ee65a36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175465839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3175465839
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3655515428
Short name T720
Test name
Test status
Simulation time 102596792053 ps
CPU time 622.07 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:39:04 PM PST 24
Peak memory 199536 kb
Host smart-3587c55a-4a71-4983-bf53-74c73f6d475d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655515428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3655515428
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2378886720
Short name T889
Test name
Test status
Simulation time 90347996051 ps
CPU time 151.02 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:31:14 PM PST 24
Peak memory 208296 kb
Host smart-4509bfae-487e-4c1f-911f-7a71206b6df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378886720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2378886720
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.1242042024
Short name T1065
Test name
Test status
Simulation time 29841663004 ps
CPU time 976.13 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:44:59 PM PST 24
Peak memory 199728 kb
Host smart-5a792834-6c60-41c7-9f20-f3485685168b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242042024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1242042024
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3066497162
Short name T645
Test name
Test status
Simulation time 2496459323 ps
CPU time 28.98 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:12 PM PST 24
Peak memory 197676 kb
Host smart-c205534a-b252-4264-9d12-f0f2adec2398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066497162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3066497162
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3090733325
Short name T878
Test name
Test status
Simulation time 107564310907 ps
CPU time 177.01 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:31:40 PM PST 24
Peak memory 199372 kb
Host smart-b43a0ba3-93a8-471f-884a-890df6d7de65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090733325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3090733325
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1792900862
Short name T1034
Test name
Test status
Simulation time 40666630825 ps
CPU time 17.42 seconds
Started Feb 04 12:28:36 PM PST 24
Finished Feb 04 12:29:00 PM PST 24
Peak memory 195180 kb
Host smart-20e5a7e3-c81d-40fa-8507-44ad43c05754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792900862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1792900862
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2323754676
Short name T967
Test name
Test status
Simulation time 871498250 ps
CPU time 1.94 seconds
Started Feb 04 12:28:24 PM PST 24
Finished Feb 04 12:28:32 PM PST 24
Peak memory 197636 kb
Host smart-37a8cc5e-e982-4a72-ac79-c3612729ae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323754676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2323754676
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.867134960
Short name T962
Test name
Test status
Simulation time 181313921680 ps
CPU time 328.28 seconds
Started Feb 04 12:28:44 PM PST 24
Finished Feb 04 12:34:17 PM PST 24
Peak memory 199772 kb
Host smart-07ba011b-94b6-4120-a2a4-0f89fd7037f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867134960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.867134960
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.387432438
Short name T552
Test name
Test status
Simulation time 20472888775 ps
CPU time 486.46 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:36:50 PM PST 24
Peak memory 208436 kb
Host smart-9d252692-881b-492c-a1a8-5ec2f043dc81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387432438 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.387432438
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3999459976
Short name T890
Test name
Test status
Simulation time 1232217130 ps
CPU time 1.84 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:45 PM PST 24
Peak memory 197868 kb
Host smart-4fb1f8cb-996a-450a-ac68-6f54dee3b6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999459976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3999459976
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2294112688
Short name T628
Test name
Test status
Simulation time 145477928830 ps
CPU time 41.02 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:29:24 PM PST 24
Peak memory 199544 kb
Host smart-548e0a31-4096-4ee4-9c13-0b6eef5d06f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294112688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2294112688
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1078574493
Short name T208
Test name
Test status
Simulation time 42781380613 ps
CPU time 25.08 seconds
Started Feb 04 12:31:08 PM PST 24
Finished Feb 04 12:31:35 PM PST 24
Peak memory 199820 kb
Host smart-7bdba54c-8bc1-46bc-a4ab-039919e0b42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078574493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1078574493
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.79391967
Short name T1140
Test name
Test status
Simulation time 67612009932 ps
CPU time 387.61 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:37:36 PM PST 24
Peak memory 216624 kb
Host smart-5003185a-1dc4-4862-88f3-8e9cc4acacac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79391967 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.79391967
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3970725866
Short name T190
Test name
Test status
Simulation time 83261923484 ps
CPU time 68.24 seconds
Started Feb 04 12:31:10 PM PST 24
Finished Feb 04 12:32:20 PM PST 24
Peak memory 199772 kb
Host smart-69dd605a-6254-4316-89f4-c333a0c61fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970725866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3970725866
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1008451845
Short name T445
Test name
Test status
Simulation time 38335955126 ps
CPU time 384.58 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:37:37 PM PST 24
Peak memory 216504 kb
Host smart-7e7ca0c0-91ea-4637-b387-6f83b22ff8a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008451845 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1008451845
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3834702053
Short name T149
Test name
Test status
Simulation time 31505229730 ps
CPU time 48.99 seconds
Started Feb 04 12:31:13 PM PST 24
Finished Feb 04 12:32:04 PM PST 24
Peak memory 198348 kb
Host smart-1aecd7be-d5b9-41e4-b5e3-7c01d4d75473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834702053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3834702053
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3579997465
Short name T173
Test name
Test status
Simulation time 194669399143 ps
CPU time 447.53 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:38:38 PM PST 24
Peak memory 210728 kb
Host smart-df77081b-a598-470c-832a-1ae3c314ead7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579997465 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3579997465
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3550189988
Short name T222
Test name
Test status
Simulation time 34780929739 ps
CPU time 29.83 seconds
Started Feb 04 12:31:14 PM PST 24
Finished Feb 04 12:31:45 PM PST 24
Peak memory 199748 kb
Host smart-db5ccac6-19d8-4e4e-91bd-ee8e9083a596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550189988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3550189988
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.224812679
Short name T686
Test name
Test status
Simulation time 20014191823 ps
CPU time 242.01 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:35:13 PM PST 24
Peak memory 208168 kb
Host smart-50a489fe-9e29-4b23-b88a-21fabf7ce88c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224812679 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.224812679
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3543574902
Short name T752
Test name
Test status
Simulation time 114112290613 ps
CPU time 92.97 seconds
Started Feb 04 12:31:05 PM PST 24
Finished Feb 04 12:32:40 PM PST 24
Peak memory 199652 kb
Host smart-8e8361cc-c448-43d6-8299-0dced97cfe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543574902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3543574902
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.213522711
Short name T641
Test name
Test status
Simulation time 9007279017 ps
CPU time 81.48 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:32:33 PM PST 24
Peak memory 215400 kb
Host smart-5e60f29c-f4a0-4987-8737-ac9b42bbfe86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213522711 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.213522711
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1252907387
Short name T754
Test name
Test status
Simulation time 84677937867 ps
CPU time 133.65 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:33:26 PM PST 24
Peak memory 199776 kb
Host smart-ec06b3bb-7a6b-48f0-a2d8-da79b06a50a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252907387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1252907387
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3361975827
Short name T373
Test name
Test status
Simulation time 298584898153 ps
CPU time 1003.32 seconds
Started Feb 04 12:31:10 PM PST 24
Finished Feb 04 12:47:55 PM PST 24
Peak memory 224748 kb
Host smart-56c487cc-50fc-4d02-8104-0521edb4a656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361975827 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3361975827
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2649342840
Short name T247
Test name
Test status
Simulation time 111163988420 ps
CPU time 185.21 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:34:17 PM PST 24
Peak memory 199844 kb
Host smart-24f6ea75-2b92-46fb-a841-6eb661a91146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649342840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2649342840
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3682048019
Short name T847
Test name
Test status
Simulation time 58552408196 ps
CPU time 24.18 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:31:33 PM PST 24
Peak memory 198200 kb
Host smart-2128cefc-47c9-42a0-8407-07d76964a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682048019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3682048019
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.476261622
Short name T1208
Test name
Test status
Simulation time 109194626656 ps
CPU time 288.73 seconds
Started Feb 04 12:31:10 PM PST 24
Finished Feb 04 12:36:01 PM PST 24
Peak memory 216520 kb
Host smart-c6b205eb-6c96-4956-88f0-edc1dce65f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476261622 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.476261622
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1092788614
Short name T199
Test name
Test status
Simulation time 131410302825 ps
CPU time 69.03 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:32:18 PM PST 24
Peak memory 199708 kb
Host smart-18b5514d-dd30-4a66-bd47-8b5070e249c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092788614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1092788614
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2236475461
Short name T131
Test name
Test status
Simulation time 47974669505 ps
CPU time 76.17 seconds
Started Feb 04 12:31:10 PM PST 24
Finished Feb 04 12:32:28 PM PST 24
Peak memory 199760 kb
Host smart-2d5f85c5-87d0-4c1a-b3b8-4d3c4b905cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236475461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2236475461
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3382472239
Short name T1216
Test name
Test status
Simulation time 64975906944 ps
CPU time 195.74 seconds
Started Feb 04 12:31:10 PM PST 24
Finished Feb 04 12:34:28 PM PST 24
Peak memory 216120 kb
Host smart-141daf38-f055-4c51-8516-cfb3da4f63e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382472239 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3382472239
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.17051376
Short name T1162
Test name
Test status
Simulation time 34942147 ps
CPU time 0.56 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:28:53 PM PST 24
Peak memory 194204 kb
Host smart-db72bff5-04a0-4058-8efc-c0f73cef0018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17051376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.17051376
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3965867047
Short name T770
Test name
Test status
Simulation time 142915699712 ps
CPU time 98.24 seconds
Started Feb 04 12:28:38 PM PST 24
Finished Feb 04 12:30:22 PM PST 24
Peak memory 199660 kb
Host smart-20be9415-42bc-4caf-bf09-760df3850e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965867047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3965867047
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1815430491
Short name T332
Test name
Test status
Simulation time 202025353837 ps
CPU time 71.24 seconds
Started Feb 04 12:28:34 PM PST 24
Finished Feb 04 12:29:52 PM PST 24
Peak memory 199848 kb
Host smart-cf2f2364-e29a-4118-80be-bf63417daf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815430491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1815430491
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1367137824
Short name T127
Test name
Test status
Simulation time 50772381030 ps
CPU time 47.37 seconds
Started Feb 04 12:28:44 PM PST 24
Finished Feb 04 12:29:36 PM PST 24
Peak memory 199772 kb
Host smart-5c2772e8-916f-4411-a485-e5048c432290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367137824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1367137824
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2667843416
Short name T689
Test name
Test status
Simulation time 721583959525 ps
CPU time 1108.47 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:47:12 PM PST 24
Peak memory 199084 kb
Host smart-d8bea431-2f8e-4d3e-806f-69122fbaecb0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667843416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2667843416
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1905588025
Short name T819
Test name
Test status
Simulation time 135152839961 ps
CPU time 653.28 seconds
Started Feb 04 12:28:47 PM PST 24
Finished Feb 04 12:39:44 PM PST 24
Peak memory 199728 kb
Host smart-cf769635-5f55-48cf-adf4-3677af9f64e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905588025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1905588025
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2828751463
Short name T494
Test name
Test status
Simulation time 145559929 ps
CPU time 0.83 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:28:54 PM PST 24
Peak memory 195164 kb
Host smart-8a7e39b5-b105-462c-b732-3ca1a0e292e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828751463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2828751463
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.4074107863
Short name T883
Test name
Test status
Simulation time 32043348237 ps
CPU time 55.7 seconds
Started Feb 04 12:28:38 PM PST 24
Finished Feb 04 12:29:39 PM PST 24
Peak memory 197916 kb
Host smart-35c8cc51-f614-4e5a-8729-61172ca362f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074107863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.4074107863
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1022905765
Short name T608
Test name
Test status
Simulation time 36609494904 ps
CPU time 867.57 seconds
Started Feb 04 12:28:43 PM PST 24
Finished Feb 04 12:43:16 PM PST 24
Peak memory 199748 kb
Host smart-f3b81d26-7c8f-4c85-9a88-7f10c926d4a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022905765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1022905765
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2956954297
Short name T748
Test name
Test status
Simulation time 1832770410 ps
CPU time 5.97 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:28:49 PM PST 24
Peak memory 197296 kb
Host smart-f8f7c55f-270a-4f0e-b02e-30c03ec2171e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956954297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2956954297
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.4122557557
Short name T439
Test name
Test status
Simulation time 138366695854 ps
CPU time 287.99 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:33:41 PM PST 24
Peak memory 199708 kb
Host smart-435e8acb-db08-41a5-86d1-cf220abb4ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122557557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4122557557
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3780563980
Short name T629
Test name
Test status
Simulation time 4141253992 ps
CPU time 1.48 seconds
Started Feb 04 12:28:44 PM PST 24
Finished Feb 04 12:28:50 PM PST 24
Peak memory 195468 kb
Host smart-c4ef2be8-8dfd-4d40-9142-3546fdd413a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780563980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3780563980
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2289716241
Short name T103
Test name
Test status
Simulation time 5546482972 ps
CPU time 8.18 seconds
Started Feb 04 12:28:35 PM PST 24
Finished Feb 04 12:28:49 PM PST 24
Peak memory 199464 kb
Host smart-e56c07f4-f66f-4bcf-9c5e-bed24d0724e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289716241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2289716241
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2692039538
Short name T792
Test name
Test status
Simulation time 127156568717 ps
CPU time 161.11 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:31:34 PM PST 24
Peak memory 199764 kb
Host smart-29ddfc17-9ce4-4aa4-a3cd-4a3c4000158e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692039538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2692039538
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.538599783
Short name T694
Test name
Test status
Simulation time 30748102305 ps
CPU time 762.39 seconds
Started Feb 04 12:28:44 PM PST 24
Finished Feb 04 12:41:31 PM PST 24
Peak memory 212692 kb
Host smart-37bd3404-670e-45d1-8d33-8619a1e4388d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538599783 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.538599783
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3603104285
Short name T870
Test name
Test status
Simulation time 2681347860 ps
CPU time 1.35 seconds
Started Feb 04 12:28:50 PM PST 24
Finished Feb 04 12:28:54 PM PST 24
Peak memory 198048 kb
Host smart-0345b9db-82b4-44f9-8dae-6ab9bca0b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603104285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3603104285
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1971845912
Short name T405
Test name
Test status
Simulation time 198232577928 ps
CPU time 90.78 seconds
Started Feb 04 12:28:37 PM PST 24
Finished Feb 04 12:30:14 PM PST 24
Peak memory 199764 kb
Host smart-76f1f4f5-48e9-4cdb-9ca4-a788b938fc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971845912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1971845912
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.3179932577
Short name T749
Test name
Test status
Simulation time 106638631211 ps
CPU time 38.55 seconds
Started Feb 04 12:31:09 PM PST 24
Finished Feb 04 12:31:50 PM PST 24
Peak memory 199280 kb
Host smart-ac29a705-dc26-4a8e-9d68-e8dbb3a4b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179932577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3179932577
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2305559622
Short name T1126
Test name
Test status
Simulation time 276812373932 ps
CPU time 509.5 seconds
Started Feb 04 12:31:12 PM PST 24
Finished Feb 04 12:39:43 PM PST 24
Peak memory 216364 kb
Host smart-833ce55c-94b2-4b56-83b6-529d95bdd1d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305559622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2305559622
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3273819820
Short name T265
Test name
Test status
Simulation time 344374041515 ps
CPU time 53.06 seconds
Started Feb 04 12:31:15 PM PST 24
Finished Feb 04 12:32:09 PM PST 24
Peak memory 199772 kb
Host smart-8b74aa91-6858-44da-83e6-92f90700fae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273819820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3273819820
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1446683554
Short name T1159
Test name
Test status
Simulation time 40502062793 ps
CPU time 1177.05 seconds
Started Feb 04 12:31:12 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 208824 kb
Host smart-db83d56f-1e26-4200-86ba-afe00d8d27a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446683554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1446683554
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1242278776
Short name T318
Test name
Test status
Simulation time 128711754389 ps
CPU time 75.45 seconds
Started Feb 04 12:31:14 PM PST 24
Finished Feb 04 12:32:30 PM PST 24
Peak memory 199736 kb
Host smart-8274062a-568d-4b56-ad24-f219014c4312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242278776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1242278776
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.358389722
Short name T201
Test name
Test status
Simulation time 198673241775 ps
CPU time 585.88 seconds
Started Feb 04 12:31:12 PM PST 24
Finished Feb 04 12:40:59 PM PST 24
Peak memory 216300 kb
Host smart-bbd564ae-944f-44ac-b436-f89451364a33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358389722 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.358389722
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.421054686
Short name T863
Test name
Test status
Simulation time 66646555142 ps
CPU time 764.74 seconds
Started Feb 04 12:31:12 PM PST 24
Finished Feb 04 12:43:58 PM PST 24
Peak memory 216272 kb
Host smart-fd80f833-d4da-4c69-a399-43297b2a4d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421054686 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.421054686
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3099730348
Short name T193
Test name
Test status
Simulation time 60920856066 ps
CPU time 96.11 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:32:48 PM PST 24
Peak memory 199428 kb
Host smart-5f387a90-abb8-47c1-8229-bf9366e1473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099730348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3099730348
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.4171491192
Short name T275
Test name
Test status
Simulation time 217456611894 ps
CPU time 906.31 seconds
Started Feb 04 12:31:07 PM PST 24
Finished Feb 04 12:46:16 PM PST 24
Peak memory 216416 kb
Host smart-fd061d68-1ba5-4286-8265-0b547f7c7dd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171491192 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.4171491192
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2324314083
Short name T257
Test name
Test status
Simulation time 60182280392 ps
CPU time 17.52 seconds
Started Feb 04 12:31:11 PM PST 24
Finished Feb 04 12:31:30 PM PST 24
Peak memory 199800 kb
Host smart-74681f21-abe5-4044-a3b5-3ae51e423090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324314083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2324314083
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.262455182
Short name T1182
Test name
Test status
Simulation time 603036908513 ps
CPU time 429.6 seconds
Started Feb 04 12:31:23 PM PST 24
Finished Feb 04 12:38:34 PM PST 24
Peak memory 216568 kb
Host smart-f5313841-c750-481d-bc4c-43abe5691656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262455182 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.262455182
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1052370733
Short name T212
Test name
Test status
Simulation time 302427438380 ps
CPU time 221.66 seconds
Started Feb 04 12:31:23 PM PST 24
Finished Feb 04 12:35:06 PM PST 24
Peak memory 199824 kb
Host smart-2ed574da-c028-4864-aac8-ea7096cdef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052370733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1052370733
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3937875144
Short name T233
Test name
Test status
Simulation time 141779345073 ps
CPU time 407.62 seconds
Started Feb 04 12:31:25 PM PST 24
Finished Feb 04 12:38:14 PM PST 24
Peak memory 224792 kb
Host smart-1aa3df48-ed5d-456d-bdeb-356aaf871c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937875144 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3937875144
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.486594224
Short name T1015
Test name
Test status
Simulation time 61938518505 ps
CPU time 101.16 seconds
Started Feb 04 12:31:23 PM PST 24
Finished Feb 04 12:33:06 PM PST 24
Peak memory 199848 kb
Host smart-c54f31a3-af61-4306-b82c-4922eaf20882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486594224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.486594224
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2419263613
Short name T20
Test name
Test status
Simulation time 147264014987 ps
CPU time 336.81 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:37:04 PM PST 24
Peak memory 215188 kb
Host smart-9665551b-b030-4fc7-b854-bfd7ed26312a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419263613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2419263613
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2105606994
Short name T21
Test name
Test status
Simulation time 101526861335 ps
CPU time 16.43 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:31:43 PM PST 24
Peak memory 199284 kb
Host smart-74f8ab35-49cd-4746-94f3-5191d5bffb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105606994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2105606994
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1291732521
Short name T1139
Test name
Test status
Simulation time 93003755348 ps
CPU time 485.21 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:39:32 PM PST 24
Peak memory 216584 kb
Host smart-7fe07c8b-0fcb-4980-ac7a-c703c045324a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291732521 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1291732521
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4116600677
Short name T141
Test name
Test status
Simulation time 156218854637 ps
CPU time 101.7 seconds
Started Feb 04 12:31:26 PM PST 24
Finished Feb 04 12:33:09 PM PST 24
Peak memory 199596 kb
Host smart-782cf0c6-5ec2-4900-9d31-75f24c060191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116600677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4116600677
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.764731792
Short name T963
Test name
Test status
Simulation time 99243365812 ps
CPU time 310.09 seconds
Started Feb 04 12:31:28 PM PST 24
Finished Feb 04 12:36:46 PM PST 24
Peak memory 216656 kb
Host smart-0e33ff88-a5bb-4ddf-8b85-589df2127f42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764731792 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.764731792
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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