Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	124954	1			T3	5		T4	8		T5	1
all_values[1]	124954	1			T3	5		T4	8		T5	1
all_values[2]	124954	1			T3	5		T4	8		T5	1
all_values[3]	124954	1			T3	5		T4	8		T5	1
all_values[4]	124954	1			T3	5		T4	8		T5	1
all_values[5]	124954	1			T3	5		T4	8		T5	1
all_values[6]	124954	1			T3	5		T4	8		T5	1
all_values[7]	124954	1			T3	5		T4	8		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

509464

1

T3

16

T4

30

T5

8

auto[1]

490168

1

T3

24

T4

34

T7

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981431

1

T3

31

T4

35

T5

8

auto[1]

18201

1

T3

9

T4

29

T7

21

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	60171	1			T3	1		T4	2		T5	1
all_values[0]	auto[0]	auto[1]	2678	1			T4	1		T7	1		T36	1
all_values[0]	auto[1]	auto[0]	59755	1			T3	4		T4	1		T7	4
all_values[0]	auto[1]	auto[1]	2350	1			T4	4		T7	2		T36	1
all_values[1]	auto[0]	auto[0]	59211	1			T4	2		T5	1		T8	1
all_values[1]	auto[0]	auto[1]	2786	1			T3	1		T7	3		T51	2
all_values[1]	auto[1]	auto[0]	60416	1			T3	4		T4	2		T7	3
all_values[1]	auto[1]	auto[1]	2541	1			T4	4		T7	2		T36	2
all_values[2]	auto[0]	auto[0]	57228	1			T4	2		T5	1		T7	5
all_values[2]	auto[0]	auto[1]	2694	1			T3	1		T4	3		T7	1
all_values[2]	auto[1]	auto[0]	62722	1			T3	1		T4	2		T36	1
all_values[2]	auto[1]	auto[1]	2310	1			T3	3		T4	1		T7	2
all_values[3]	auto[0]	auto[0]	67578	1			T3	3		T4	5		T5	1
all_values[3]	auto[0]	auto[1]	230	1			T4	2		T7	2		T36	1
all_values[3]	auto[1]	auto[0]	56916	1			T3	2		T7	2		T36	2
all_values[3]	auto[1]	auto[1]	230	1			T4	1		T7	1		T36	2
all_values[4]	auto[0]	auto[0]	61811	1			T3	1		T4	1		T5	1
all_values[4]	auto[0]	auto[1]	490	1			T4	1		T7	1		T36	3
all_values[4]	auto[1]	auto[0]	62192	1			T3	4		T4	3		T7	5
all_values[4]	auto[1]	auto[1]	461	1			T4	3		T51	2		T110	5
all_values[5]	auto[0]	auto[0]	66445	1			T3	3		T4	2		T5	1
all_values[5]	auto[0]	auto[1]	184	1			T7	1		T36	1		T51	3
all_values[5]	auto[1]	auto[0]	58132	1			T4	5		T7	3		T36	1
all_values[5]	auto[1]	auto[1]	193	1			T3	2		T4	1		T36	2
all_values[6]	auto[0]	auto[0]	65332	1			T3	2		T4	2		T5	1
all_values[6]	auto[0]	auto[1]	187	1			T4	4		T7	1		T36	1
all_values[6]	auto[1]	auto[0]	59257	1			T3	3		T7	3		T36	2
all_values[6]	auto[1]	auto[1]	178	1			T4	2		T7	1		T36	2
all_values[7]	auto[0]	auto[0]	62110	1			T3	2		T4	2		T5	1
all_values[7]	auto[0]	auto[1]	329	1			T3	2		T4	1		T7	2
all_values[7]	auto[1]	auto[0]	62155	1			T3	1		T4	4		T7	3
all_values[7]	auto[1]	auto[1]	360	1			T4	1		T7	1		T36	2