Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2535

1

T1

1

T2

1

T3

1

auto[UartRx]

2535

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4484	1			T1	2		T2	2		T3	2
values[1]	56	1			T13	2		T30	1		T79	1
values[2]	45	1			T13	1		T30	1		T263	3
values[3]	57	1			T13	1		T30	1		T79	1
values[4]	61	1			T13	1		T30	2		T79	1
values[5]	50	1			T79	1		T80	1		T263	1
values[6]	41	1			T13	1		T304	1		T133	2
values[7]	59	1			T30	1		T82	1		T59	1
values[8]	43	1			T263	1		T304	1		T133	1
values[9]	67	1			T79	3		T401	1		T304	1
values[10]	69	1			T30	1		T401	1		T304	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2326	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	18	1			T79	1		T322	1		T426	1
auto[UartTx]	values[2]	17	1			T13	1		T263	1		T437	1
auto[UartTx]	values[3]	20	1			T263	1		T332	1		T438	1
auto[UartTx]	values[4]	28	1			T13	1		T30	2		T263	1
auto[UartTx]	values[5]	19	1			T133	1		T186	1		T437	1
auto[UartTx]	values[6]	13	1			T133	1		T426	1		T292	1
auto[UartTx]	values[7]	24	1			T59	1		T142	2		T138	1
auto[UartTx]	values[8]	5	1			T138	1		T439	1		T440	1
auto[UartTx]	values[9]	29	1			T79	1		T304	1		T59	1
auto[UartTx]	values[10]	27	1			T59	1		T186	1		T426	2
auto[UartRx]	values[0]	2158	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	38	1			T13	2		T30	1		T416	1
auto[UartRx]	values[2]	28	1			T30	1		T263	2		T133	1
auto[UartRx]	values[3]	37	1			T13	1		T30	1		T79	1
auto[UartRx]	values[4]	33	1			T79	1		T263	1		T59	1
auto[UartRx]	values[5]	31	1			T79	1		T80	1		T263	1
auto[UartRx]	values[6]	28	1			T13	1		T304	1		T133	1
auto[UartRx]	values[7]	35	1			T30	1		T82	1		T138	1
auto[UartRx]	values[8]	38	1			T263	1		T304	1		T133	1
auto[UartRx]	values[9]	38	1			T79	2		T401	1		T59	1
auto[UartRx]	values[10]	42	1			T30	1		T401	1		T304	1