Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1991	1			T13	1		T17	7		T18	3
auto[BaudRate115200]	2136	1			T11	3		T12	2		T13	5
auto[BaudRate230400]	1914	1			T11	3		T13	1		T17	16
auto[BaudRate128Kbps]	1861	1			T11	6		T12	1		T13	1
auto[BaudRate256Kbps]	2194	1			T11	15		T12	3		T13	3
auto[BaudRate1Mbps]	1716	1			T11	9		T12	3		T13	3
auto[BaudRate1p5Mbps]	1263	1			T11	6		T13	5		T14	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1385	1			T12	9		T17	62		T18	10
freqs[25]	1057	1			T28	7		T15	52		T114	7
freqs[48]	448	1			T13	19		T154	10		T433	2
freqs[50]	781	1			T435	5		T98	7		T99	2
freqs[100]	1091	1			T104	7		T23	5		T403	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	238	1			T17	7		T18	3		T16	3
auto[BaudRate9600]	freqs[25]	177	1			T15	10		T114	1		T165	2
auto[BaudRate9600]	freqs[48]	65	1			T13	1		T154	1		T119	1
auto[BaudRate9600]	freqs[50]	104	1			T435	2		T99	1		T441	4
auto[BaudRate9600]	freqs[100]	152	1			T104	3		T23	1		T403	2
auto[BaudRate115200]	freqs[24]	191	1			T12	2		T17	5		T18	1
auto[BaudRate115200]	freqs[25]	183	1			T28	2		T15	9		T114	3
auto[BaudRate115200]	freqs[48]	91	1			T13	5		T154	2		T433	1
auto[BaudRate115200]	freqs[50]	95	1			T435	1		T98	2		T441	3
auto[BaudRate115200]	freqs[100]	162	1			T104	1		T23	1		T403	3
auto[BaudRate230400]	freqs[24]	197	1			T17	16		T18	1		T120	1
auto[BaudRate230400]	freqs[25]	172	1			T28	1		T15	9		T114	1
auto[BaudRate230400]	freqs[48]	58	1			T13	1		T119	1		T148	2
auto[BaudRate230400]	freqs[50]	116	1			T98	1		T442	3		T443	15
auto[BaudRate230400]	freqs[100]	133	1			T403	1		T143	1		T444	1
auto[BaudRate128Kbps]	freqs[24]	193	1			T12	1		T17	14		T18	2
auto[BaudRate128Kbps]	freqs[25]	143	1			T28	2		T15	3		T165	3
auto[BaudRate128Kbps]	freqs[48]	51	1			T13	1		T154	1		T433	1
auto[BaudRate128Kbps]	freqs[50]	114	1			T98	1		T442	1		T443	15
auto[BaudRate128Kbps]	freqs[100]	140	1			T104	1		T23	3		T403	1
auto[BaudRate256Kbps]	freqs[24]	220	1			T12	3		T17	12		T18	1
auto[BaudRate256Kbps]	freqs[25]	142	1			T28	1		T15	10		T114	2
auto[BaudRate256Kbps]	freqs[48]	81	1			T13	3		T154	4		T119	2
auto[BaudRate256Kbps]	freqs[50]	115	1			T435	1		T98	1		T443	6
auto[BaudRate256Kbps]	freqs[100]	165	1			T143	1		T444	5		T324	4
auto[BaudRate1Mbps]	freqs[24]	237	1			T12	3		T17	8		T18	1
auto[BaudRate1Mbps]	freqs[25]	143	1			T28	1		T15	5		T165	4
auto[BaudRate1Mbps]	freqs[48]	51	1			T13	3		T154	1		T119	1
auto[BaudRate1Mbps]	freqs[50]	110	1			T98	2		T442	2		T443	9
auto[BaudRate1Mbps]	freqs[100]	165	1			T104	1		T403	2		T143	1
auto[BaudRate1p5Mbps]	freqs[25]	97	1			T15	6		T165	1		T445	1
auto[BaudRate1p5Mbps]	freqs[48]	51	1			T13	5		T154	1		T446	1
auto[BaudRate1p5Mbps]	freqs[50]	127	1			T435	1		T99	1		T442	3
auto[BaudRate1p5Mbps]	freqs[100]	174	1			T104	1		T403	1		T143	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded